2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/delay.h>
18 #include <linux/kernel.h>
19 #include <linux/string.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
30 #include <pcie_core.h>
41 #include <sbsdpcmdev.h>
46 /* this file now contains only definitions for sb functions, only necessary
47 *for devices using Sonics backplanes (bcm4329)
50 /* if an amba SDIO device is supported, please further restrict the inclusion
54 #include "siutils_priv.h"
57 /* local prototypes */
58 static si_info_t
*si_doattach(si_info_t
*sii
, uint devid
, struct osl_info
*osh
,
59 void *regs
, uint bustype
, void *sdh
, char **vars
,
61 static bool si_buscore_prep(si_info_t
*sii
, uint bustype
, uint devid
,
63 static bool si_buscore_setup(si_info_t
*sii
, chipcregs_t
*cc
, uint bustype
,
64 u32 savewin
, uint
*origidx
, void *regs
);
65 static void si_nvram_process(si_info_t
*sii
, char *pvars
);
67 /* dev path concatenation util */
68 static char *si_devpathvar(si_t
*sih
, char *var
, int len
, const char *name
);
69 static bool _si_clkctl_cc(si_info_t
*sii
, uint mode
);
70 static bool si_ispcie(si_info_t
*sii
);
71 static uint
socram_banksize(si_info_t
*sii
, sbsocramregs_t
*r
,
74 /* global variable to indicate reservation/release of gpio's */
75 static u32 si_gpioreservation
;
78 * Allocate a si handle.
79 * devid - pci device id (used to determine chip#)
80 * osh - opaque OS handle
81 * regs - virtual address of initial core registers
82 * bustype - pci/sb/sdio/etc
83 * vars - pointer to a pointer area for "environment" variables
84 * varsz - pointer to int to return the size of the vars
86 si_t
*si_attach(uint devid
, struct osl_info
*osh
, void *regs
, uint bustype
,
87 void *sdh
, char **vars
, uint
*varsz
)
92 sii
= kmalloc(sizeof(si_info_t
), GFP_ATOMIC
);
94 SI_ERROR(("si_attach: malloc failed!\n"));
98 if (si_doattach(sii
, devid
, osh
, regs
, bustype
, sdh
, vars
, varsz
) ==
103 sii
->vars
= vars
? *vars
: NULL
;
104 sii
->varsz
= varsz
? *varsz
: 0;
109 /* global kernel resource */
110 static si_info_t ksii
;
112 static bool si_buscore_prep(si_info_t
*sii
, uint bustype
, uint devid
,
117 /* kludge to enable the clock on the 4306 which lacks a slowclock */
118 if (bustype
== PCI_BUS
&& !si_ispcie(sii
))
119 si_clkctl_xtal(&sii
->pub
, XTAL
| PLL
, ON
);
123 if (bustype
== SDIO_BUS
) {
127 /* Try forcing SDIO core to do ALPAvail request only */
128 clkset
= SBSDIO_FORCE_HW_CLKREQ_OFF
| SBSDIO_ALP_AVAIL_REQ
;
129 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_CHIPCLKCSR
,
134 /* If register supported, wait for ALPAvail and then force ALP */
136 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
137 SBSDIO_FUNC1_CHIPCLKCSR
, NULL
);
138 if ((clkval
& ~SBSDIO_AVBITS
) == clkset
) {
140 bcmsdh_cfg_read(sdh
, SDIO_FUNC_1
,
141 SBSDIO_FUNC1_CHIPCLKCSR
,
143 !SBSDIO_ALPAV(clkval
)),
144 PMU_MAX_TRANSITION_DLY
);
145 if (!SBSDIO_ALPAV(clkval
)) {
146 SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", clkval
));
150 SBSDIO_FORCE_HW_CLKREQ_OFF
|
152 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
,
153 SBSDIO_FUNC1_CHIPCLKCSR
,
159 /* Also, disable the extra SDIO pull-ups */
160 bcmsdh_cfg_write(sdh
, SDIO_FUNC_1
, SBSDIO_FUNC1_SDIOPULLUP
, 0,
163 #endif /* defined(BCMSDIO) */
168 static bool si_buscore_setup(si_info_t
*sii
, chipcregs_t
*cc
, uint bustype
,
169 u32 savewin
, uint
*origidx
, void *regs
)
173 uint pciidx
, pcieidx
, pcirev
, pcierev
;
175 cc
= si_setcoreidx(&sii
->pub
, SI_CC_IDX
);
178 /* get chipcommon rev */
179 sii
->pub
.ccrev
= (int)si_corerev(&sii
->pub
);
181 /* get chipcommon chipstatus */
182 if (sii
->pub
.ccrev
>= 11)
183 sii
->pub
.chipst
= R_REG(&cc
->chipstatus
);
185 /* get chipcommon capabilites */
186 sii
->pub
.cccaps
= R_REG(&cc
->capabilities
);
187 /* get chipcommon extended capabilities */
190 if (sii
->pub
.ccrev
>= 35)
191 sii
->pub
.cccaps_ext
= R_REG(&cc
->capabilities_ext
);
193 /* get pmu rev and caps */
194 if (sii
->pub
.cccaps
& CC_CAP_PMU
) {
195 sii
->pub
.pmucaps
= R_REG(&cc
->pmucapabilities
);
196 sii
->pub
.pmurev
= sii
->pub
.pmucaps
& PCAP_REV_MASK
;
200 SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n",
201 sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
205 /* figure out bus/orignal core idx */
206 sii
->pub
.buscoretype
= NODEV_CORE_ID
;
207 sii
->pub
.buscorerev
= NOREV
;
208 sii
->pub
.buscoreidx
= BADIDX
;
211 pcirev
= pcierev
= NOREV
;
212 pciidx
= pcieidx
= BADIDX
;
214 for (i
= 0; i
< sii
->numcores
; i
++) {
217 si_setcoreidx(&sii
->pub
, i
);
218 cid
= si_coreid(&sii
->pub
);
219 crev
= si_corerev(&sii
->pub
);
221 /* Display cores found */
222 SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
223 i
, cid
, crev
, sii
->coresba
[i
], sii
->regs
[i
]));
225 if (bustype
== PCI_BUS
) {
226 if (cid
== PCI_CORE_ID
) {
230 } else if (cid
== PCIE_CORE_ID
) {
237 else if (((bustype
== SDIO_BUS
) ||
238 (bustype
== SPI_BUS
)) &&
239 ((cid
== PCMCIA_CORE_ID
) || (cid
== SDIOD_CORE_ID
))) {
240 sii
->pub
.buscorerev
= crev
;
241 sii
->pub
.buscoretype
= cid
;
242 sii
->pub
.buscoreidx
= i
;
246 /* find the core idx before entering this func. */
247 if ((savewin
&& (savewin
== sii
->coresba
[i
])) ||
248 (regs
== sii
->regs
[i
]))
253 SI_MSG(("Buscore id/type/rev %d/0x%x/%d\n", sii
->pub
.buscoreidx
,
254 sii
->pub
.buscoretype
, sii
->pub
.buscorerev
));
256 /* Make sure any on-chip ARM is off (in case strapping is wrong),
257 * or downloaded code was
260 if ((bustype
== SDIO_BUS
) || (bustype
== SPI_BUS
)) {
261 if (si_setcore(&sii
->pub
, ARM7S_CORE_ID
, 0) ||
262 si_setcore(&sii
->pub
, ARMCM3_CORE_ID
, 0))
263 si_core_disable(&sii
->pub
, 0);
273 sii
->pub
.buscoretype
= PCI_CORE_ID
;
274 sii
->pub
.buscorerev
= pcirev
;
275 sii
->pub
.buscoreidx
= pciidx
;
277 sii
->pub
.buscoretype
= PCIE_CORE_ID
;
278 sii
->pub
.buscorerev
= pcierev
;
279 sii
->pub
.buscoreidx
= pcieidx
;
282 SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii
->pub
.buscoreidx
,
283 sii
->pub
.buscoretype
, sii
->pub
.buscorerev
));
285 /* fixup necessary chip/core configurations */
286 if (sii
->pub
.bustype
== PCI_BUS
) {
289 sii
->pch
= (void *)pcicore_init(
291 (void *)PCIEREGS(sii
));
292 if (sii
->pch
== NULL
)
296 if (si_pci_fixcfg(&sii
->pub
)) {
297 SI_ERROR(("si_doattach: sb_pci_fixcfg failed\n"));
302 /* return to the original core */
303 si_setcoreidx(&sii
->pub
, *origidx
);
308 static __used
void si_nvram_process(si_info_t
*sii
, char *pvars
)
312 /* get boardtype and boardrev */
313 switch (sii
->pub
.bustype
) {
315 /* do a pci config read to get subsystem id and subvendor id */
316 pci_read_config_dword(sii
->pbus
, PCI_CFG_SVID
, &w
);
317 /* Let nvram variables override subsystem Vend/ID */
318 sii
->pub
.boardvendor
= (u16
)si_getdevpathintvar(&sii
->pub
,
320 if (sii
->pub
.boardvendor
== 0)
321 sii
->pub
.boardvendor
= w
& 0xffff;
323 SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii
->pub
.boardvendor
, w
& 0xffff));
324 sii
->pub
.boardtype
= (u16
)si_getdevpathintvar(&sii
->pub
,
326 if (sii
->pub
.boardtype
== 0)
327 sii
->pub
.boardtype
= (w
>> 16) & 0xffff;
329 SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", sii
->pub
.boardtype
, (w
>> 16) & 0xffff));
335 sii
->pub
.boardvendor
= getintvar(pvars
, "manfid");
336 sii
->pub
.boardtype
= getintvar(pvars
, "prodid");
341 sii
->pub
.boardvendor
= VENDOR_BROADCOM
;
342 sii
->pub
.boardtype
= SPI_BOARD
;
348 sii
->pub
.boardvendor
= VENDOR_BROADCOM
;
349 sii
->pub
.boardtype
= getintvar(pvars
, "prodid");
350 if (pvars
== NULL
|| (sii
->pub
.boardtype
== 0)) {
351 sii
->pub
.boardtype
= getintvar(NULL
, "boardtype");
352 if (sii
->pub
.boardtype
== 0)
353 sii
->pub
.boardtype
= 0xffff;
358 if (sii
->pub
.boardtype
== 0) {
359 SI_ERROR(("si_doattach: unknown board type\n"));
360 ASSERT(sii
->pub
.boardtype
);
363 sii
->pub
.boardflags
= getintvar(pvars
, "boardflags");
366 /* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */
367 /* this has been customized for the bcm 4329 ONLY */
369 static si_info_t
*si_doattach(si_info_t
*sii
, uint devid
, struct osl_info
*osh
,
370 void *regs
, uint bustype
, void *pbus
,
371 char **vars
, uint
*varsz
)
373 struct si_pub
*sih
= &sii
->pub
;
379 ASSERT(GOODREGS(regs
));
381 memset((unsigned char *) sii
, 0, sizeof(si_info_t
));
385 sih
->buscoreidx
= BADIDX
;
391 /* find Chipcommon address */
392 cc
= (chipcregs_t
*) sii
->curmap
;
393 sih
->bustype
= bustype
;
395 /* bus/core/clk setup for register access */
396 if (!si_buscore_prep(sii
, bustype
, devid
, pbus
)) {
397 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
402 /* ChipID recognition.
403 * We assume we can read chipid at offset 0 from the regs arg.
404 * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
405 * some way of recognizing them needs to be added here.
407 w
= R_REG(&cc
->chipid
);
408 sih
->socitype
= (w
& CID_TYPE_MASK
) >> CID_TYPE_SHIFT
;
409 /* Might as wll fill in chip id rev & pkg */
410 sih
->chip
= w
& CID_ID_MASK
;
411 sih
->chiprev
= (w
& CID_REV_MASK
) >> CID_REV_SHIFT
;
412 sih
->chippkg
= (w
& CID_PKG_MASK
) >> CID_PKG_SHIFT
;
414 if ((sih
->chip
== BCM4329_CHIP_ID
) &&
415 (sih
->chippkg
!= BCM4329_289PIN_PKG_ID
))
416 sih
->chippkg
= BCM4329_182PIN_PKG_ID
;
418 sih
->issim
= IS_SIM(sih
->chippkg
);
421 /* SI_MSG(("Found chip type SB (0x%08x)\n", w)); */
422 sb_scan(&sii
->pub
, regs
, devid
);
424 /* no cores found, bail out */
425 if (sii
->numcores
== 0) {
426 SI_ERROR(("si_doattach: could not find any cores\n"));
429 /* bus/core/clk setup */
431 if (!si_buscore_setup(sii
, cc
, bustype
, savewin
, &origidx
, regs
)) {
432 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
439 /* Init nvram from flash if it exists */
440 nvram_init((void *)&(sii
->pub
));
442 /* Init nvram from sprom/otp if they exist */
444 (&sii
->pub
, bustype
, regs
, sii
->osh
, vars
, varsz
)) {
445 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
448 pvars
= vars
? *vars
: NULL
;
449 si_nvram_process(sii
, pvars
);
452 /* === NVRAM, clock is ready === */
455 if (sii
->pub
.ccrev
>= 20) {
457 cc
= (chipcregs_t
*) si_setcore(sih
, CC_CORE_ID
, 0);
458 W_REG(&cc
->gpiopullup
, 0);
459 W_REG(&cc
->gpiopulldown
, 0);
460 sb_setcoreidx(sih
, origidx
);
466 /* PMU specific initializations */
467 if (PMUCTL_ENAB(sih
)) {
469 si_pmu_init(sih
, sii
->osh
);
470 si_pmu_chip_init(sih
, sii
->osh
);
471 xtalfreq
= getintvar(pvars
, "xtalfreq");
472 /* If xtalfreq var not available, try to measure it */
474 xtalfreq
= si_pmu_measure_alpclk(sih
, sii
->osh
);
475 si_pmu_pll_init(sih
, sii
->osh
, xtalfreq
);
476 si_pmu_res_init(sih
, sii
->osh
);
477 si_pmu_swreg_init(sih
, sii
->osh
);
480 /* setup the GPIO based LED powersave register */
481 w
= getintvar(pvars
, "leddc");
483 w
= DEFAULT_GPIOTIMERVAL
;
484 sb_corereg(sih
, SI_CC_IDX
, offsetof(chipcregs_t
, gpiotimerval
), ~0, w
);
487 /* clear any previous epidiag-induced target abort */
488 sb_taclear(sih
, false);
499 static si_info_t
*si_doattach(si_info_t
*sii
, uint devid
, struct osl_info
*osh
,
500 void *regs
, uint bustype
, void *pbus
,
501 char **vars
, uint
*varsz
)
503 struct si_pub
*sih
= &sii
->pub
;
509 ASSERT(GOODREGS(regs
));
511 memset((unsigned char *) sii
, 0, sizeof(si_info_t
));
515 sih
->buscoreidx
= BADIDX
;
521 /* check to see if we are a si core mimic'ing a pci core */
522 if (bustype
== PCI_BUS
) {
523 pci_read_config_dword(sii
->pbus
, PCI_SPROM_CONTROL
, &w
);
524 if (w
== 0xffffffff) {
525 SI_ERROR(("%s: incoming bus is PCI but it's a lie, "
526 " switching to SI devid:0x%x\n",
532 /* find Chipcommon address */
533 if (bustype
== PCI_BUS
) {
534 pci_read_config_dword(sii
->pbus
, PCI_BAR0_WIN
, &savewin
);
535 if (!GOODCOREADDR(savewin
, SI_ENUM_BASE
))
536 savewin
= SI_ENUM_BASE
;
537 pci_write_config_dword(sii
->pbus
, PCI_BAR0_WIN
,
539 cc
= (chipcregs_t
*) regs
;
541 cc
= (chipcregs_t
*) REG_MAP(SI_ENUM_BASE
, SI_CORE_SIZE
);
544 sih
->bustype
= bustype
;
546 /* bus/core/clk setup for register access */
547 if (!si_buscore_prep(sii
, bustype
, devid
, pbus
)) {
548 SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
553 /* ChipID recognition.
554 * We assume we can read chipid at offset 0 from the regs arg.
555 * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
556 * some way of recognizing them needs to be added here.
558 w
= R_REG(&cc
->chipid
);
559 sih
->socitype
= (w
& CID_TYPE_MASK
) >> CID_TYPE_SHIFT
;
560 /* Might as wll fill in chip id rev & pkg */
561 sih
->chip
= w
& CID_ID_MASK
;
562 sih
->chiprev
= (w
& CID_REV_MASK
) >> CID_REV_SHIFT
;
563 sih
->chippkg
= (w
& CID_PKG_MASK
) >> CID_PKG_SHIFT
;
565 sih
->issim
= IS_SIM(sih
->chippkg
);
568 if (sii
->pub
.socitype
== SOCI_AI
) {
569 SI_MSG(("Found chip type AI (0x%08x)\n", w
));
570 /* pass chipc address instead of original core base */
571 ai_scan(&sii
->pub
, (void *)cc
, devid
);
573 SI_ERROR(("Found chip of unknown type (0x%08x)\n", w
));
576 /* no cores found, bail out */
577 if (sii
->numcores
== 0) {
578 SI_ERROR(("si_doattach: could not find any cores\n"));
581 /* bus/core/clk setup */
583 if (!si_buscore_setup(sii
, cc
, bustype
, savewin
, &origidx
, regs
)) {
584 SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
588 /* assume current core is CC */
589 if ((sii
->pub
.ccrev
== 0x25)
591 ((sih
->chip
== BCM43236_CHIP_ID
592 || sih
->chip
== BCM43235_CHIP_ID
593 || sih
->chip
== BCM43238_CHIP_ID
)
594 && (sii
->pub
.chiprev
<= 2))) {
596 if ((cc
->chipstatus
& CST43236_BP_CLK
) != 0) {
598 clkdiv
= R_REG(&cc
->clkdiv
);
599 /* otp_clk_div is even number, 120/14 < 9mhz */
600 clkdiv
= (clkdiv
& ~CLKD_OTP
) | (14 << CLKD_OTP_SHIFT
);
601 W_REG(&cc
->clkdiv
, clkdiv
);
602 SI_ERROR(("%s: set clkdiv to %x\n", __func__
, clkdiv
));
607 /* Init nvram from flash if it exists */
608 nvram_init((void *)&(sii
->pub
));
610 /* Init nvram from sprom/otp if they exist */
612 (&sii
->pub
, bustype
, regs
, sii
->osh
, vars
, varsz
)) {
613 SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
616 pvars
= vars
? *vars
: NULL
;
617 si_nvram_process(sii
, pvars
);
619 /* === NVRAM, clock is ready === */
620 cc
= (chipcregs_t
*) si_setcore(sih
, CC_CORE_ID
, 0);
621 W_REG(&cc
->gpiopullup
, 0);
622 W_REG(&cc
->gpiopulldown
, 0);
623 si_setcoreidx(sih
, origidx
);
625 /* PMU specific initializations */
626 if (PMUCTL_ENAB(sih
)) {
628 si_pmu_init(sih
, sii
->osh
);
629 si_pmu_chip_init(sih
, sii
->osh
);
630 xtalfreq
= getintvar(pvars
, "xtalfreq");
631 /* If xtalfreq var not available, try to measure it */
633 xtalfreq
= si_pmu_measure_alpclk(sih
, sii
->osh
);
634 si_pmu_pll_init(sih
, sii
->osh
, xtalfreq
);
635 si_pmu_res_init(sih
, sii
->osh
);
636 si_pmu_swreg_init(sih
, sii
->osh
);
639 /* setup the GPIO based LED powersave register */
640 w
= getintvar(pvars
, "leddc");
642 w
= DEFAULT_GPIOTIMERVAL
;
643 si_corereg(sih
, SI_CC_IDX
, offsetof(chipcregs_t
, gpiotimerval
), ~0, w
);
646 ASSERT(sii
->pch
!= NULL
);
647 pcicore_attach(sii
->pch
, pvars
, SI_DOATTACH
);
650 if ((sih
->chip
== BCM43224_CHIP_ID
) ||
651 (sih
->chip
== BCM43421_CHIP_ID
)) {
652 /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */
653 if (sih
->chiprev
== 0) {
654 SI_MSG(("Applying 43224A0 WARs\n"));
655 si_corereg(sih
, SI_CC_IDX
,
656 offsetof(chipcregs_t
, chipcontrol
),
657 CCTRL43224_GPIO_TOGGLE
,
658 CCTRL43224_GPIO_TOGGLE
);
659 si_pmu_chipcontrol(sih
, 0, CCTRL_43224A0_12MA_LED_DRIVE
,
660 CCTRL_43224A0_12MA_LED_DRIVE
);
662 if (sih
->chiprev
>= 1) {
663 SI_MSG(("Applying 43224B0+ WARs\n"));
664 si_pmu_chipcontrol(sih
, 0, CCTRL_43224B0_12MA_LED_DRIVE
,
665 CCTRL_43224B0_12MA_LED_DRIVE
);
669 if (sih
->chip
== BCM4313_CHIP_ID
) {
670 /* enable 12 mA drive strenth for 4313 and set chipControl register bit 1 */
671 SI_MSG(("Applying 4313 WARs\n"));
672 si_pmu_chipcontrol(sih
, 0, CCTRL_4313_12MA_LED_DRIVE
,
673 CCTRL_4313_12MA_LED_DRIVE
);
676 if (sih
->chip
== BCM4331_CHIP_ID
) {
677 /* Enable Ext PA lines depending on chip package option */
678 si_chipcontrl_epa4331(sih
, true);
683 if (sih
->bustype
== PCI_BUS
) {
685 pcicore_deinit(sii
->pch
);
693 /* may be called with core in reset */
694 void si_detach(si_t
*sih
)
699 struct si_pub
*si_local
= NULL
;
700 memcpy(&si_local
, &sih
, sizeof(si_t
**));
707 if (sih
->bustype
== SI_BUS
)
708 for (idx
= 0; idx
< SI_MAXCORES
; idx
++)
709 if (sii
->regs
[idx
]) {
710 iounmap(sii
->regs
[idx
]);
711 sii
->regs
[idx
] = NULL
;
715 nvram_exit((void *)si_local
); /* free up nvram buffers */
717 if (sih
->bustype
== PCI_BUS
) {
719 pcicore_deinit(sii
->pch
);
723 #if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)
725 #endif /* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */
729 struct osl_info
*si_osh(si_t
*sih
)
737 /* register driver interrupt disabling and restoring callback functions */
739 si_register_intr_callback(si_t
*sih
, void *intrsoff_fn
, void *intrsrestore_fn
,
740 void *intrsenabled_fn
, void *intr_arg
)
745 sii
->intr_arg
= intr_arg
;
746 sii
->intrsoff_fn
= (si_intrsoff_t
) intrsoff_fn
;
747 sii
->intrsrestore_fn
= (si_intrsrestore_t
) intrsrestore_fn
;
748 sii
->intrsenabled_fn
= (si_intrsenabled_t
) intrsenabled_fn
;
749 /* save current core id. when this function called, the current core
750 * must be the core which provides driver functions(il, et, wl, etc.)
752 sii
->dev_coreid
= sii
->coreid
[sii
->curidx
];
755 void si_deregister_intr_callback(si_t
*sih
)
760 sii
->intrsoff_fn
= NULL
;
763 uint
si_flag(si_t
*sih
)
765 if (sih
->socitype
== SOCI_AI
)
773 void si_setint(si_t
*sih
, int siflag
)
775 if (sih
->socitype
== SOCI_AI
)
776 ai_setint(sih
, siflag
);
782 uint
si_coreid(si_t
*sih
)
787 return sii
->coreid
[sii
->curidx
];
791 uint
si_coreidx(si_t
*sih
)
799 bool si_backplane64(si_t
*sih
)
801 return (sih
->cccaps
& CC_CAP_BKPLN64
) != 0;
805 uint
si_corerev(si_t
*sih
)
807 if (sih
->socitype
== SOCI_AI
)
808 return ai_corerev(sih
);
816 /* return index of coreid or BADIDX if not found */
817 uint
si_findcoreidx(si_t
*sih
, uint coreid
, uint coreunit
)
827 for (i
= 0; i
< sii
->numcores
; i
++)
828 if (sii
->coreid
[i
] == coreid
) {
829 if (found
== coreunit
)
838 * This function changes logical "focus" to the indicated core;
839 * must be called with interrupts off.
840 * Moreover, callers should keep interrupts off during switching out of and back to d11 core
842 void *si_setcore(si_t
*sih
, uint coreid
, uint coreunit
)
846 idx
= si_findcoreidx(sih
, coreid
, coreunit
);
850 if (sih
->socitype
== SOCI_AI
)
851 return ai_setcoreidx(sih
, idx
);
854 return sb_setcoreidx(sih
, idx
);
863 void *si_setcoreidx(si_t
*sih
, uint coreidx
)
865 if (sih
->socitype
== SOCI_AI
)
866 return ai_setcoreidx(sih
, coreidx
);
874 /* Turn off interrupt as required by sb_setcore, before switch core */
875 void *si_switch_core(si_t
*sih
, uint coreid
, uint
*origidx
, uint
*intr_val
)
883 /* Overloading the origidx variable to remember the coreid,
884 * this works because the core ids cannot be confused with
888 if (coreid
== CC_CORE_ID
)
889 return (void *)CCREGS_FAST(sii
);
890 else if (coreid
== sih
->buscoretype
)
891 return (void *)PCIEREGS(sii
);
893 INTR_OFF(sii
, *intr_val
);
894 *origidx
= sii
->curidx
;
895 cc
= si_setcore(sih
, coreid
, 0);
901 /* restore coreidx and restore interrupt */
902 void si_restore_core(si_t
*sih
, uint coreid
, uint intr_val
)
908 && ((coreid
== CC_CORE_ID
) || (coreid
== sih
->buscoretype
)))
911 si_setcoreidx(sih
, coreid
);
912 INTR_RESTORE(sii
, intr_val
);
915 u32
si_core_cflags(si_t
*sih
, u32 mask
, u32 val
)
917 if (sih
->socitype
== SOCI_AI
)
918 return ai_core_cflags(sih
, mask
, val
);
925 u32
si_core_sflags(si_t
*sih
, u32 mask
, u32 val
)
927 if (sih
->socitype
== SOCI_AI
)
928 return ai_core_sflags(sih
, mask
, val
);
935 bool si_iscoreup(si_t
*sih
)
937 if (sih
->socitype
== SOCI_AI
)
938 return ai_iscoreup(sih
);
941 return sb_iscoreup(sih
);
949 void si_write_wrapperreg(si_t
*sih
, u32 offset
, u32 val
)
951 /* only for 4319, no requirement for SOCI_SB */
952 if (sih
->socitype
== SOCI_AI
) {
953 ai_write_wrap_reg(sih
, offset
, val
);
957 uint
si_corereg(si_t
*sih
, uint coreidx
, uint regoff
, uint mask
, uint val
)
960 if (sih
->socitype
== SOCI_AI
)
961 return ai_corereg(sih
, coreidx
, regoff
, mask
, val
);
964 return sb_corereg(sih
, coreidx
, regoff
, mask
, val
);
972 void si_core_disable(si_t
*sih
, u32 bits
)
975 if (sih
->socitype
== SOCI_AI
)
976 ai_core_disable(sih
, bits
);
979 sb_core_disable(sih
, bits
);
983 void si_core_reset(si_t
*sih
, u32 bits
, u32 resetbits
)
985 if (sih
->socitype
== SOCI_AI
)
986 ai_core_reset(sih
, bits
, resetbits
);
989 sb_core_reset(sih
, bits
, resetbits
);
993 u32
si_alp_clock(si_t
*sih
)
995 if (PMUCTL_ENAB(sih
))
996 return si_pmu_alp_clock(sih
, si_osh(sih
));
1001 u32
si_ilp_clock(si_t
*sih
)
1003 if (PMUCTL_ENAB(sih
))
1004 return si_pmu_ilp_clock(sih
, si_osh(sih
));
1009 /* set chip watchdog reset timer to fire in 'ticks' */
1012 si_watchdog(si_t
*sih
, uint ticks
)
1014 if (PMUCTL_ENAB(sih
)) {
1016 if ((sih
->chip
== BCM4319_CHIP_ID
) && (sih
->chiprev
== 0) &&
1018 si_corereg(sih
, SI_CC_IDX
, offsetof(chipcregs_t
,
1019 clk_ctl_st
), ~0, 0x2);
1020 si_setcore(sih
, USB20D_CORE_ID
, 0);
1021 si_core_disable(sih
, 1);
1022 si_setcore(sih
, CC_CORE_ID
, 0);
1027 si_corereg(sih
, SI_CC_IDX
, offsetof(chipcregs_t
, pmuwatchdog
),
1031 si_corereg(sih
, SI_CC_IDX
, offsetof(chipcregs_t
, watchdog
),
1036 void si_watchdog(si_t
*sih
, uint ticks
)
1040 if (PMUCTL_ENAB(sih
)) {
1042 if ((sih
->chip
== BCM4319_CHIP_ID
) &&
1043 (sih
->chiprev
== 0) && (ticks
!= 0)) {
1044 si_corereg(sih
, SI_CC_IDX
,
1045 offsetof(chipcregs_t
, clk_ctl_st
), ~0, 0x2);
1046 si_setcore(sih
, USB20D_CORE_ID
, 0);
1047 si_core_disable(sih
, 1);
1048 si_setcore(sih
, CC_CORE_ID
, 0);
1051 nb
= (sih
->ccrev
< 26) ? 16 : ((sih
->ccrev
>= 37) ? 32 : 24);
1052 /* The mips compiler uses the sllv instruction,
1053 * so we specially handle the 32-bit case.
1058 maxt
= ((1 << nb
) - 1);
1062 else if (ticks
> maxt
)
1065 si_corereg(sih
, SI_CC_IDX
, offsetof(chipcregs_t
, pmuwatchdog
),
1068 /* make sure we come up in fast clock mode; or if clearing, clear clock */
1069 si_clkctl_cc(sih
, ticks
? CLK_FAST
: CLK_DYNAMIC
);
1070 maxt
= (1 << 28) - 1;
1074 si_corereg(sih
, SI_CC_IDX
, offsetof(chipcregs_t
, watchdog
), ~0,
1080 /* return the slow clock source - LPO, XTAL, or PCI */
1081 static uint
si_slowclk_src(si_info_t
*sii
)
1086 ASSERT(SI_FAST(sii
) || si_coreid(&sii
->pub
) == CC_CORE_ID
);
1088 if (sii
->pub
.ccrev
< 6) {
1089 if (sii
->pub
.bustype
== PCI_BUS
) {
1090 pci_read_config_dword(sii
->pbus
, PCI_GPIO_OUT
,
1092 if (val
& PCI_CFG_GPIO_SCS
)
1096 } else if (sii
->pub
.ccrev
< 10) {
1097 cc
= (chipcregs_t
*) si_setcoreidx(&sii
->pub
, sii
->curidx
);
1098 return R_REG(&cc
->slow_clk_ctl
) & SCC_SS_MASK
;
1099 } else /* Insta-clock */
1103 /* return the ILP (slowclock) min or max frequency */
1104 static uint
si_slowclk_freq(si_info_t
*sii
, bool max_freq
, chipcregs_t
*cc
)
1109 ASSERT(SI_FAST(sii
) || si_coreid(&sii
->pub
) == CC_CORE_ID
);
1111 /* shouldn't be here unless we've established the chip has dynamic clk control */
1112 ASSERT(R_REG(&cc
->capabilities
) & CC_CAP_PWR_CTL
);
1114 slowclk
= si_slowclk_src(sii
);
1115 if (sii
->pub
.ccrev
< 6) {
1116 if (slowclk
== SCC_SS_PCI
)
1117 return max_freq
? (PCIMAXFREQ
/ 64)
1118 : (PCIMINFREQ
/ 64);
1120 return max_freq
? (XTALMAXFREQ
/ 32)
1121 : (XTALMINFREQ
/ 32);
1122 } else if (sii
->pub
.ccrev
< 10) {
1124 (((R_REG(&cc
->slow_clk_ctl
) & SCC_CD_MASK
) >>
1126 if (slowclk
== SCC_SS_LPO
)
1127 return max_freq
? LPOMAXFREQ
: LPOMINFREQ
;
1128 else if (slowclk
== SCC_SS_XTAL
)
1129 return max_freq
? (XTALMAXFREQ
/ div
)
1130 : (XTALMINFREQ
/ div
);
1131 else if (slowclk
== SCC_SS_PCI
)
1132 return max_freq
? (PCIMAXFREQ
/ div
)
1133 : (PCIMINFREQ
/ div
);
1137 /* Chipc rev 10 is InstaClock */
1138 div
= R_REG(&cc
->system_clk_ctl
) >> SYCC_CD_SHIFT
;
1139 div
= 4 * (div
+ 1);
1140 return max_freq
? XTALMAXFREQ
: (XTALMINFREQ
/ div
);
1145 static void si_clkctl_setdelay(si_info_t
*sii
, void *chipcregs
)
1147 chipcregs_t
*cc
= (chipcregs_t
*) chipcregs
;
1148 uint slowmaxfreq
, pll_delay
, slowclk
;
1149 uint pll_on_delay
, fref_sel_delay
;
1151 pll_delay
= PLL_DELAY
;
1153 /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
1154 * since the xtal will also be powered down by dynamic clk control logic.
1157 slowclk
= si_slowclk_src(sii
);
1158 if (slowclk
!= SCC_SS_XTAL
)
1159 pll_delay
+= XTAL_ON_DELAY
;
1161 /* Starting with 4318 it is ILP that is used for the delays */
1163 si_slowclk_freq(sii
, (sii
->pub
.ccrev
>= 10) ? false : true, cc
);
1165 pll_on_delay
= ((slowmaxfreq
* pll_delay
) + 999999) / 1000000;
1166 fref_sel_delay
= ((slowmaxfreq
* FREF_DELAY
) + 999999) / 1000000;
1168 W_REG(&cc
->pll_on_delay
, pll_on_delay
);
1169 W_REG(&cc
->fref_sel_delay
, fref_sel_delay
);
1172 /* initialize power control delay registers */
1173 void si_clkctl_init(si_t
*sih
)
1180 if (!CCCTL_ENAB(sih
))
1184 fast
= SI_FAST(sii
);
1186 origidx
= sii
->curidx
;
1187 cc
= (chipcregs_t
*) si_setcore(sih
, CC_CORE_ID
, 0);
1191 cc
= (chipcregs_t
*) CCREGS_FAST(sii
);
1197 /* set all Instaclk chip ILP to 1 MHz */
1198 if (sih
->ccrev
>= 10)
1199 SET_REG(&cc
->system_clk_ctl
, SYCC_CD_MASK
,
1200 (ILP_DIV_1MHZ
<< SYCC_CD_SHIFT
));
1202 si_clkctl_setdelay(sii
, (void *)cc
);
1205 si_setcoreidx(sih
, origidx
);
1208 /* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
1209 u16
si_clkctl_fast_pwrup_delay(si_t
*sih
)
1220 if (PMUCTL_ENAB(sih
)) {
1221 INTR_OFF(sii
, intr_val
);
1222 fpdelay
= si_pmu_fast_pwrup_delay(sih
, sii
->osh
);
1223 INTR_RESTORE(sii
, intr_val
);
1227 if (!CCCTL_ENAB(sih
))
1230 fast
= SI_FAST(sii
);
1233 origidx
= sii
->curidx
;
1234 INTR_OFF(sii
, intr_val
);
1235 cc
= (chipcregs_t
*) si_setcore(sih
, CC_CORE_ID
, 0);
1239 cc
= (chipcregs_t
*) CCREGS_FAST(sii
);
1245 slowminfreq
= si_slowclk_freq(sii
, false, cc
);
1246 fpdelay
= (((R_REG(&cc
->pll_on_delay
) + 2) * 1000000) +
1247 (slowminfreq
- 1)) / slowminfreq
;
1251 si_setcoreidx(sih
, origidx
);
1252 INTR_RESTORE(sii
, intr_val
);
1257 /* turn primary xtal and/or pll off/on */
1258 int si_clkctl_xtal(si_t
*sih
, uint what
, bool on
)
1265 switch (sih
->bustype
) {
1270 #endif /* BCMSDIO */
1273 /* pcie core doesn't have any mapping to control the xtal pu */
1277 pci_read_config_dword(sii
->pbus
, PCI_GPIO_IN
, &in
);
1278 pci_read_config_dword(sii
->pbus
, PCI_GPIO_OUT
, &out
);
1279 pci_read_config_dword(sii
->pbus
, PCI_GPIO_OUTEN
, &outen
);
1282 * Avoid glitching the clock if GPRS is already using it.
1283 * We can't actually read the state of the PLLPD so we infer it
1284 * by the value of XTAL_PU which *is* readable via gpioin.
1286 if (on
&& (in
& PCI_CFG_GPIO_XTAL
))
1290 outen
|= PCI_CFG_GPIO_XTAL
;
1292 outen
|= PCI_CFG_GPIO_PLL
;
1295 /* turn primary xtal on */
1297 out
|= PCI_CFG_GPIO_XTAL
;
1299 out
|= PCI_CFG_GPIO_PLL
;
1300 pci_write_config_dword(sii
->pbus
,
1302 pci_write_config_dword(sii
->pbus
,
1303 PCI_GPIO_OUTEN
, outen
);
1304 udelay(XTAL_ON_DELAY
);
1309 out
&= ~PCI_CFG_GPIO_PLL
;
1310 pci_write_config_dword(sii
->pbus
,
1316 out
&= ~PCI_CFG_GPIO_XTAL
;
1318 out
|= PCI_CFG_GPIO_PLL
;
1319 pci_write_config_dword(sii
->pbus
,
1321 pci_write_config_dword(sii
->pbus
,
1322 PCI_GPIO_OUTEN
, outen
);
1333 * clock control policy function throught chipcommon
1335 * set dynamic clk control mode (forceslow, forcefast, dynamic)
1336 * returns true if we are forcing fast clock
1337 * this is a wrapper over the next internal function
1338 * to allow flexible policy settings for outside caller
1340 bool si_clkctl_cc(si_t
*sih
, uint mode
)
1346 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1350 if (PCI_FORCEHT(sii
))
1351 return mode
== CLK_FAST
;
1353 return _si_clkctl_cc(sii
, mode
);
1356 /* clk control mechanism through chipcommon, no policy checking */
1357 static bool _si_clkctl_cc(si_info_t
*sii
, uint mode
)
1363 bool fast
= SI_FAST(sii
);
1365 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1366 if (sii
->pub
.ccrev
< 6)
1369 /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
1370 ASSERT(sii
->pub
.ccrev
!= 10);
1373 INTR_OFF(sii
, intr_val
);
1374 origidx
= sii
->curidx
;
1376 if ((sii
->pub
.bustype
== SI_BUS
) &&
1377 si_setcore(&sii
->pub
, MIPS33_CORE_ID
, 0) &&
1378 (si_corerev(&sii
->pub
) <= 7) && (sii
->pub
.ccrev
>= 10))
1381 cc
= (chipcregs_t
*) si_setcore(&sii
->pub
, CC_CORE_ID
, 0);
1383 cc
= (chipcregs_t
*) CCREGS_FAST(sii
);
1389 if (!CCCTL_ENAB(&sii
->pub
) && (sii
->pub
.ccrev
< 20))
1393 case CLK_FAST
: /* FORCEHT, fast (pll) clock */
1394 if (sii
->pub
.ccrev
< 10) {
1395 /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
1396 si_clkctl_xtal(&sii
->pub
, XTAL
, ON
);
1397 SET_REG(&cc
->slow_clk_ctl
,
1398 (SCC_XC
| SCC_FS
| SCC_IP
), SCC_IP
);
1399 } else if (sii
->pub
.ccrev
< 20) {
1400 OR_REG(&cc
->system_clk_ctl
, SYCC_HR
);
1402 OR_REG(&cc
->clk_ctl_st
, CCS_FORCEHT
);
1405 /* wait for the PLL */
1406 if (PMUCTL_ENAB(&sii
->pub
)) {
1407 u32 htavail
= CCS_HTAVAIL
;
1408 SPINWAIT(((R_REG(&cc
->clk_ctl_st
) & htavail
)
1409 == 0), PMU_MAX_TRANSITION_DLY
);
1410 ASSERT(R_REG(&cc
->clk_ctl_st
) & htavail
);
1416 case CLK_DYNAMIC
: /* enable dynamic clock control */
1417 if (sii
->pub
.ccrev
< 10) {
1418 scc
= R_REG(&cc
->slow_clk_ctl
);
1419 scc
&= ~(SCC_FS
| SCC_IP
| SCC_XC
);
1420 if ((scc
& SCC_SS_MASK
) != SCC_SS_XTAL
)
1422 W_REG(&cc
->slow_clk_ctl
, scc
);
1424 /* for dynamic control, we have to release our xtal_pu "force on" */
1426 si_clkctl_xtal(&sii
->pub
, XTAL
, OFF
);
1427 } else if (sii
->pub
.ccrev
< 20) {
1429 AND_REG(&cc
->system_clk_ctl
, ~SYCC_HR
);
1431 AND_REG(&cc
->clk_ctl_st
, ~CCS_FORCEHT
);
1441 si_setcoreidx(&sii
->pub
, origidx
);
1442 INTR_RESTORE(sii
, intr_val
);
1444 return mode
== CLK_FAST
;
1447 /* Build device path. Support SI, PCI, and JTAG for now. */
1448 int si_devpath(si_t
*sih
, char *path
, int size
)
1452 ASSERT(path
!= NULL
);
1453 ASSERT(size
>= SI_DEVPATH_BUFSZ
);
1455 if (!path
|| size
<= 0)
1458 switch (sih
->bustype
) {
1461 slen
= snprintf(path
, (size_t) size
, "sb/%u/", si_coreidx(sih
));
1464 ASSERT((SI_INFO(sih
))->osh
!= NULL
);
1465 slen
= snprintf(path
, (size_t) size
, "pci/%u/%u/",
1466 ((struct pci_dev
*)((SI_INFO(sih
))->pbus
))->bus
->number
,
1468 ((struct pci_dev
*)((SI_INFO(sih
))->pbus
))->devfn
));
1473 SI_ERROR(("si_devpath: device 0 assumed\n"));
1474 slen
= snprintf(path
, (size_t) size
, "sd/%u/", si_coreidx(sih
));
1483 if (slen
< 0 || slen
>= size
) {
1491 /* Get a variable, but only if it has a devpath prefix */
1492 char *si_getdevpathvar(si_t
*sih
, const char *name
)
1494 char varname
[SI_DEVPATH_BUFSZ
+ 32];
1496 si_devpathvar(sih
, varname
, sizeof(varname
), name
);
1498 return getvar(NULL
, varname
);
1501 /* Get a variable, but only if it has a devpath prefix */
1502 int si_getdevpathintvar(si_t
*sih
, const char *name
)
1504 #if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
1505 return getintvar(NULL
, name
);
1507 char varname
[SI_DEVPATH_BUFSZ
+ 32];
1509 si_devpathvar(sih
, varname
, sizeof(varname
), name
);
1511 return getintvar(NULL
, varname
);
1515 char *si_getnvramflvar(si_t
*sih
, const char *name
)
1517 return getvar(NULL
, name
);
1520 /* Concatenate the dev path with a varname into the given 'var' buffer
1521 * and return the 'var' pointer.
1522 * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned.
1523 * On overflow, the first char will be set to '\0'.
1525 static char *si_devpathvar(si_t
*sih
, char *var
, int len
, const char *name
)
1529 if (!var
|| len
<= 0)
1532 if (si_devpath(sih
, var
, len
) == 0) {
1533 path_len
= strlen(var
);
1535 if (strlen(name
) + 1 > (uint
) (len
- path_len
))
1538 strncpy(var
+ path_len
, name
, len
- path_len
- 1);
1544 /* return true if PCIE capability exists in the pci config space */
1545 static __used
bool si_ispcie(si_info_t
*sii
)
1549 if (sii
->pub
.bustype
!= PCI_BUS
)
1553 pcicore_find_pci_capability(sii
->pbus
, PCI_CAP_PCIECAP_ID
, NULL
,
1562 /* initialize the sdio core */
1563 void si_sdio_init(si_t
*sih
)
1565 si_info_t
*sii
= SI_INFO(sih
);
1567 if (((sih
->buscoretype
== PCMCIA_CORE_ID
) && (sih
->buscorerev
>= 8)) ||
1568 (sih
->buscoretype
== SDIOD_CORE_ID
)) {
1570 sdpcmd_regs_t
*sdpregs
;
1572 /* get the current core index */
1574 ASSERT(idx
== si_findcoreidx(sih
, D11_CORE_ID
, 0));
1576 /* switch to sdio core */
1577 sdpregs
= (sdpcmd_regs_t
*) si_setcore(sih
, PCMCIA_CORE_ID
, 0);
1580 (sdpcmd_regs_t
*) si_setcore(sih
, SDIOD_CORE_ID
, 0);
1583 SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih
->buscorerev
, idx
, sii
->curidx
, sdpregs
));
1585 /* enable backplane error and core interrupts */
1586 W_REG(&sdpregs
->hostintmask
, I_SBINT
);
1587 W_REG(&sdpregs
->sbintmask
,
1588 (I_SB_SERR
| I_SB_RESPERR
| (1 << idx
)));
1590 /* switch back to previous core */
1591 si_setcoreidx(sih
, idx
);
1594 /* enable interrupts */
1595 bcmsdh_intr_enable(sii
->pbus
);
1598 #endif /* BCMSDIO */
1600 bool si_pci_war16165(si_t
*sih
)
1606 return PCI(sii
) && (sih
->buscorerev
<= 10);
1609 void si_pci_up(si_t
*sih
)
1615 /* if not pci bus, we're done */
1616 if (sih
->bustype
!= PCI_BUS
)
1619 if (PCI_FORCEHT(sii
))
1620 _si_clkctl_cc(sii
, CLK_FAST
);
1623 pcicore_up(sii
->pch
, SI_PCIUP
);
1627 /* Unconfigure and/or apply various WARs when system is going to sleep mode */
1628 void si_pci_sleep(si_t
*sih
)
1634 pcicore_sleep(sii
->pch
);
1637 /* Unconfigure and/or apply various WARs when going down */
1638 void si_pci_down(si_t
*sih
)
1644 /* if not pci bus, we're done */
1645 if (sih
->bustype
!= PCI_BUS
)
1648 /* release FORCEHT since chip is going to "down" state */
1649 if (PCI_FORCEHT(sii
))
1650 _si_clkctl_cc(sii
, CLK_DYNAMIC
);
1652 pcicore_down(sii
->pch
, SI_PCIDOWN
);
1656 * Configure the pci core for pci client (NIC) action
1657 * coremask is the bitvec of cores by index to be enabled.
1659 void si_pci_setup(si_t
*sih
, uint coremask
)
1662 struct sbpciregs
*pciregs
= NULL
;
1668 if (sii
->pub
.bustype
!= PCI_BUS
)
1671 ASSERT(PCI(sii
) || PCIE(sii
));
1672 ASSERT(sii
->pub
.buscoreidx
!= BADIDX
);
1675 /* get current core index */
1678 /* we interrupt on this backplane flag number */
1679 siflag
= si_flag(sih
);
1681 /* switch over to pci core */
1682 pciregs
= (struct sbpciregs
*)si_setcoreidx(sih
, sii
->pub
.buscoreidx
);
1686 * Enable sb->pci interrupts. Assume
1687 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
1689 if (PCIE(sii
) || (PCI(sii
) && ((sii
->pub
.buscorerev
) >= 6))) {
1690 /* pci config write to set this core bit in PCIIntMask */
1691 pci_read_config_dword(sii
->pbus
, PCI_INT_MASK
, &w
);
1692 w
|= (coremask
<< PCI_SBIM_SHIFT
);
1693 pci_write_config_dword(sii
->pbus
, PCI_INT_MASK
, w
);
1695 /* set sbintvec bit for our flag number */
1696 si_setint(sih
, siflag
);
1700 OR_REG(&pciregs
->sbtopci2
,
1701 (SBTOPCI_PREF
| SBTOPCI_BURST
));
1702 if (sii
->pub
.buscorerev
>= 11) {
1703 OR_REG(&pciregs
->sbtopci2
,
1704 SBTOPCI_RC_READMULTI
);
1705 w
= R_REG(&pciregs
->clkrun
);
1706 W_REG(&pciregs
->clkrun
,
1707 (w
| PCI_CLKRUN_DSBL
));
1708 w
= R_REG(&pciregs
->clkrun
);
1711 /* switch back to previous core */
1712 si_setcoreidx(sih
, idx
);
1717 * Fixup SROMless PCI device's configuration.
1718 * The current core may be changed upon return.
1720 int si_pci_fixcfg(si_t
*sih
)
1722 uint origidx
, pciidx
;
1723 struct sbpciregs
*pciregs
= NULL
;
1724 sbpcieregs_t
*pcieregs
= NULL
;
1726 u16 val16
, *reg16
= NULL
;
1728 si_info_t
*sii
= SI_INFO(sih
);
1730 ASSERT(sii
->pub
.bustype
== PCI_BUS
);
1732 /* Fixup PI in SROM shadow area to enable the correct PCI core access */
1733 /* save the current index */
1734 origidx
= si_coreidx(&sii
->pub
);
1736 /* check 'pi' is correct and fix it if not */
1737 if (sii
->pub
.buscoretype
== PCIE_CORE_ID
) {
1739 (sbpcieregs_t
*) si_setcore(&sii
->pub
, PCIE_CORE_ID
, 0);
1741 ASSERT(pcieregs
!= NULL
);
1742 reg16
= &pcieregs
->sprom
[SRSH_PI_OFFSET
];
1743 } else if (sii
->pub
.buscoretype
== PCI_CORE_ID
) {
1744 pciregs
= (struct sbpciregs
*)si_setcore(&sii
->pub
, PCI_CORE_ID
, 0);
1746 ASSERT(pciregs
!= NULL
);
1747 reg16
= &pciregs
->sprom
[SRSH_PI_OFFSET
];
1749 pciidx
= si_coreidx(&sii
->pub
);
1750 val16
= R_REG(reg16
);
1751 if (((val16
& SRSH_PI_MASK
) >> SRSH_PI_SHIFT
) != (u16
) pciidx
) {
1753 (u16
) (pciidx
<< SRSH_PI_SHIFT
) | (val16
&
1755 W_REG(reg16
, val16
);
1758 /* restore the original index */
1759 si_setcoreidx(&sii
->pub
, origidx
);
1761 pcicore_hwup(sii
->pch
);
1765 /* mask&set gpiocontrol bits */
1766 u32
si_gpiocontrol(si_t
*sih
, u32 mask
, u32 val
, u8 priority
)
1772 /* gpios could be shared on router platforms
1773 * ignore reservation if it's high priority (e.g., test apps)
1775 if ((priority
!= GPIO_HI_PRIORITY
) &&
1776 (sih
->bustype
== SI_BUS
) && (val
|| mask
)) {
1777 mask
= priority
? (si_gpioreservation
& mask
) :
1778 ((si_gpioreservation
| mask
) & ~(si_gpioreservation
));
1782 regoff
= offsetof(chipcregs_t
, gpiocontrol
);
1783 return si_corereg(sih
, SI_CC_IDX
, regoff
, mask
, val
);
1786 /* Return the size of the specified SOCRAM bank */
1788 socram_banksize(si_info_t
*sii
, sbsocramregs_t
*regs
, u8 index
,
1791 uint banksize
, bankinfo
;
1792 uint bankidx
= index
| (mem_type
<< SOCRAM_BANKIDX_MEMTYPE_SHIFT
);
1794 ASSERT(mem_type
<= SOCRAM_MEMTYPE_DEVRAM
);
1796 W_REG(®s
->bankidx
, bankidx
);
1797 bankinfo
= R_REG(®s
->bankinfo
);
1799 SOCRAM_BANKINFO_SZBASE
* ((bankinfo
& SOCRAM_BANKINFO_SZMASK
) + 1);
1803 /* Return the RAM size of the SOCRAM core */
1804 u32
si_socram_size(si_t
*sih
)
1810 sbsocramregs_t
*regs
;
1818 /* Block ints and save current core */
1819 INTR_OFF(sii
, intr_val
);
1820 origidx
= si_coreidx(sih
);
1822 /* Switch to SOCRAM core */
1823 regs
= si_setcore(sih
, SOCRAM_CORE_ID
, 0);
1827 /* Get info for determining size */
1828 wasup
= si_iscoreup(sih
);
1830 si_core_reset(sih
, 0, 0);
1831 corerev
= si_corerev(sih
);
1832 coreinfo
= R_REG(®s
->coreinfo
);
1834 /* Calculate size from coreinfo based on rev */
1836 memsize
= 1 << (16 + (coreinfo
& SRCI_MS0_MASK
));
1837 else if (corerev
< 3) {
1838 memsize
= 1 << (SR_BSZ_BASE
+ (coreinfo
& SRCI_SRBSZ_MASK
));
1839 memsize
*= (coreinfo
& SRCI_SRNB_MASK
) >> SRCI_SRNB_SHIFT
;
1840 } else if ((corerev
<= 7) || (corerev
== 12)) {
1841 uint nb
= (coreinfo
& SRCI_SRNB_MASK
) >> SRCI_SRNB_SHIFT
;
1842 uint bsz
= (coreinfo
& SRCI_SRBSZ_MASK
);
1843 uint lss
= (coreinfo
& SRCI_LSS_MASK
) >> SRCI_LSS_SHIFT
;
1846 memsize
= nb
* (1 << (bsz
+ SR_BSZ_BASE
));
1848 memsize
+= (1 << ((lss
- 1) + SR_BSZ_BASE
));
1851 uint nb
= (coreinfo
& SRCI_SRNB_MASK
) >> SRCI_SRNB_SHIFT
;
1852 for (i
= 0; i
< nb
; i
++)
1854 socram_banksize(sii
, regs
, i
, SOCRAM_MEMTYPE_RAM
);
1857 /* Return to previous state and core */
1859 si_core_disable(sih
, 0);
1860 si_setcoreidx(sih
, origidx
);
1863 INTR_RESTORE(sii
, intr_val
);
1868 void si_chipcontrl_epa4331(si_t
*sih
, bool on
)
1876 origidx
= si_coreidx(sih
);
1878 cc
= (chipcregs_t
*) si_setcore(sih
, CC_CORE_ID
, 0);
1880 val
= R_REG(&cc
->chipcontrol
);
1883 if (sih
->chippkg
== 9 || sih
->chippkg
== 0xb) {
1884 /* Ext PA Controls for 4331 12x9 Package */
1885 W_REG(&cc
->chipcontrol
, val
|
1886 (CCTRL4331_EXTPA_EN
|
1887 CCTRL4331_EXTPA_ON_GPIO2_5
));
1889 /* Ext PA Controls for 4331 12x12 Package */
1890 W_REG(&cc
->chipcontrol
,
1891 val
| (CCTRL4331_EXTPA_EN
));
1894 val
&= ~(CCTRL4331_EXTPA_EN
| CCTRL4331_EXTPA_ON_GPIO2_5
);
1895 W_REG(&cc
->chipcontrol
, val
);
1898 si_setcoreidx(sih
, origidx
);
1901 /* Enable BT-COEX & Ex-PA for 4313 */
1902 void si_epa_4313war(si_t
*sih
)
1909 origidx
= si_coreidx(sih
);
1911 cc
= (chipcregs_t
*) si_setcore(sih
, CC_CORE_ID
, 0);
1914 W_REG(&cc
->gpiocontrol
,
1915 R_REG(&cc
->gpiocontrol
) | GPIO_CTRL_EPA_EN_MASK
);
1917 si_setcoreidx(sih
, origidx
);
1920 /* check if the device is removed */
1921 bool si_deviceremoved(si_t
*sih
)
1928 switch (sih
->bustype
) {
1930 ASSERT(sii
->osh
!= NULL
);
1931 pci_read_config_dword(sii
->pbus
, PCI_CFG_VID
, &w
);
1932 if ((w
& 0xFFFF) != VENDOR_BROADCOM
)
1939 bool si_is_sprom_available(si_t
*sih
)
1941 if (sih
->ccrev
>= 31) {
1947 if ((sih
->cccaps
& CC_CAP_SROM
) == 0)
1951 origidx
= sii
->curidx
;
1952 cc
= si_setcoreidx(sih
, SI_CC_IDX
);
1953 sromctrl
= R_REG(&cc
->sromcontrol
);
1954 si_setcoreidx(sih
, origidx
);
1955 return sromctrl
& SRC_PRESENT
;
1958 switch (sih
->chip
) {
1959 case BCM4329_CHIP_ID
:
1960 return (sih
->chipst
& CST4329_SPROM_SEL
) != 0;
1961 case BCM4319_CHIP_ID
:
1962 return (sih
->chipst
& CST4319_SPROM_SEL
) != 0;
1963 case BCM4336_CHIP_ID
:
1964 return (sih
->chipst
& CST4336_SPROM_PRESENT
) != 0;
1965 case BCM4330_CHIP_ID
:
1966 return (sih
->chipst
& CST4330_SPROM_PRESENT
) != 0;
1967 case BCM4313_CHIP_ID
:
1968 return (sih
->chipst
& CST4313_SPROM_PRESENT
) != 0;
1969 case BCM4331_CHIP_ID
:
1970 return (sih
->chipst
& CST4331_SPROM_PRESENT
) != 0;
1976 bool si_is_otp_disabled(si_t
*sih
)
1978 switch (sih
->chip
) {
1979 case BCM4329_CHIP_ID
:
1980 return (sih
->chipst
& CST4329_SPROM_OTP_SEL_MASK
) ==
1982 case BCM4319_CHIP_ID
:
1983 return (sih
->chipst
& CST4319_SPROM_OTP_SEL_MASK
) ==
1985 case BCM4336_CHIP_ID
:
1986 return (sih
->chipst
& CST4336_OTP_PRESENT
) == 0;
1987 case BCM4330_CHIP_ID
:
1988 return (sih
->chipst
& CST4330_OTP_PRESENT
) == 0;
1989 case BCM4313_CHIP_ID
:
1990 return (sih
->chipst
& CST4313_OTP_PRESENT
) == 0;
1991 /* These chips always have their OTP on */
1992 case BCM43224_CHIP_ID
:
1993 case BCM43225_CHIP_ID
:
1994 case BCM43421_CHIP_ID
:
1995 case BCM43235_CHIP_ID
:
1996 case BCM43236_CHIP_ID
:
1997 case BCM43238_CHIP_ID
:
1998 case BCM4331_CHIP_ID
:
2004 bool si_is_otp_powered(si_t
*sih
)
2006 if (PMUCTL_ENAB(sih
))
2007 return si_pmu_is_otp_powered(sih
, si_osh(sih
));
2011 void si_otp_power(si_t
*sih
, bool on
)
2013 if (PMUCTL_ENAB(sih
))
2014 si_pmu_otp_power(sih
, si_osh(sih
), on
);