drivers/staging/comedi/comedi.h

   1 /*
   2     include/comedi.h (installed as /usr/include/comedi.h)
   3     header file for comedi
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU Lesser General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22 */
  23
  24 #ifndef _COMEDI_H
  25 #define _COMEDI_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #define COMEDI_MAJORVERSION     0
  32 #define COMEDI_MINORVERSION     7
  33 #define COMEDI_MICROVERSION     76
  34 #define VERSION "0.7.76"
  35
  36 /* comedi's major device number */
  37 #define COMEDI_MAJOR 98
  38
  39 /*
  40    maximum number of minor devices.  This can be increased, although
  41    kernel structures are currently statically allocated, thus you
  42    don't want this to be much more than you actually use.
  43  */
  44 #define COMEDI_NDEVICES 16
  45
  46 /* number of config options in the config structure */
  47 #define COMEDI_NDEVCONFOPTS 32
  48 /*length of nth chunk of firmware data*/
  49 #define COMEDI_DEVCONF_AUX_DATA3_LENGTH         25
  50 #define COMEDI_DEVCONF_AUX_DATA2_LENGTH         26
  51 #define COMEDI_DEVCONF_AUX_DATA1_LENGTH         27
  52 #define COMEDI_DEVCONF_AUX_DATA0_LENGTH         28
  53 #define COMEDI_DEVCONF_AUX_DATA_HI              29      /* most significant 32 bits of pointer address (if needed) */
  54 #define COMEDI_DEVCONF_AUX_DATA_LO              30      /* least significant 32 bits of pointer address */
  55 #define COMEDI_DEVCONF_AUX_DATA_LENGTH          31      /* total data length */
  56
  57 /* max length of device and driver names */
  58 #define COMEDI_NAMELEN 20
  59
  60 /* packs and unpacks a channel/range number */
  61
  62 #define CR_PACK(chan, rng, aref)                ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
  63 #define CR_PACK_FLAGS(chan, range, aref, flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
  64
  65 #define CR_CHAN(a)      ((a)&0xffff)
  66 #define CR_RANGE(a)     (((a)>>16)&0xff)
  67 #define CR_AREF(a)      (((a)>>24)&0x03)
  68
  69 #define CR_FLAGS_MASK   0xfc000000
  70 #define CR_ALT_FILTER   (1<<26)
  71 #define CR_DITHER       CR_ALT_FILTER
  72 #define CR_DEGLITCH     CR_ALT_FILTER
  73 #define CR_ALT_SOURCE   (1<<27)
  74 #define CR_EDGE         (1<<30)
  75 #define CR_INVERT       (1<<31)
  76
  77 #define AREF_GROUND     0x00    /* analog ref = analog ground */
  78 #define AREF_COMMON     0x01    /* analog ref = analog common */
  79 #define AREF_DIFF       0x02    /* analog ref = differential */
  80 #define AREF_OTHER      0x03    /* analog ref = other (undefined) */
  81
  82 /* counters -- these are arbitrary values */
  83 #define GPCT_RESET              0x0001
  84 #define GPCT_SET_SOURCE         0x0002
  85 #define GPCT_SET_GATE           0x0004
  86 #define GPCT_SET_DIRECTION      0x0008
  87 #define GPCT_SET_OPERATION      0x0010
  88 #define GPCT_ARM                0x0020
  89 #define GPCT_DISARM             0x0040
  90 #define GPCT_GET_INT_CLK_FRQ    0x0080
  91
  92 #define GPCT_INT_CLOCK          0x0001
  93 #define GPCT_EXT_PIN            0x0002
  94 #define GPCT_NO_GATE            0x0004
  95 #define GPCT_UP                 0x0008
  96 #define GPCT_DOWN               0x0010
  97 #define GPCT_HWUD               0x0020
  98 #define GPCT_SIMPLE_EVENT       0x0040
  99 #define GPCT_SINGLE_PERIOD      0x0080
 100 #define GPCT_SINGLE_PW          0x0100
 101 #define GPCT_CONT_PULSE_OUT     0x0200
 102 #define GPCT_SINGLE_PULSE_OUT   0x0400
 103
 104 /* instructions */
 105
 106 #define INSN_MASK_WRITE         0x8000000
 107 #define INSN_MASK_READ          0x4000000
 108 #define INSN_MASK_SPECIAL       0x2000000
 109
 110 #define INSN_READ               (0 | INSN_MASK_READ)
 111 #define INSN_WRITE              (1 | INSN_MASK_WRITE)
 112 #define INSN_BITS               (2 | INSN_MASK_READ|INSN_MASK_WRITE)
 113 #define INSN_CONFIG             (3 | INSN_MASK_READ|INSN_MASK_WRITE)
 114 #define INSN_GTOD               (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
 115 #define INSN_WAIT               (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 116 #define INSN_INTTRIG            (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 117
 118 /* trigger flags */
 119 /* These flags are used in comedi_trig structures */
 120
 121 #define TRIG_BOGUS      0x0001  /* do the motions */
 122 #define TRIG_DITHER     0x0002  /* enable dithering */
 123 #define TRIG_DEGLITCH   0x0004  /* enable deglitching */
 124 /*#define TRIG_RT       0x0008 */       /* perform op in real time */
 125 #define TRIG_CONFIG     0x0010  /* perform configuration, not triggering */
 126 #define TRIG_WAKE_EOS   0x0020  /* wake up on end-of-scan events */
 127 /*#define TRIG_WRITE    0x0040*/        /* write to bidirectional devices */
 128
 129 /* command flags */
 130 /* These flags are used in comedi_cmd structures */
 131
 132 #define CMDF_PRIORITY           0x00000008      /* try to use a real-time interrupt while performing command */
 133
 134 #define TRIG_RT         CMDF_PRIORITY   /* compatibility definition */
 135
 136 #define CMDF_WRITE              0x00000040
 137 #define TRIG_WRITE      CMDF_WRITE      /* compatibility definition */
 138
 139 #define CMDF_RAWDATA            0x00000080
 140
 141 #define COMEDI_EV_START         0x00040000
 142 #define COMEDI_EV_SCAN_BEGIN    0x00080000
 143 #define COMEDI_EV_CONVERT       0x00100000
 144 #define COMEDI_EV_SCAN_END      0x00200000
 145 #define COMEDI_EV_STOP          0x00400000
 146
 147 #define TRIG_ROUND_MASK         0x00030000
 148 #define TRIG_ROUND_NEAREST      0x00000000
 149 #define TRIG_ROUND_DOWN         0x00010000
 150 #define TRIG_ROUND_UP           0x00020000
 151 #define TRIG_ROUND_UP_NEXT      0x00030000
 152
 153 /* trigger sources */
 154
 155 #define TRIG_ANY        0xffffffff
 156 #define TRIG_INVALID    0x00000000
 157
 158 #define TRIG_NONE       0x00000001      /* never trigger */
 159 #define TRIG_NOW        0x00000002      /* trigger now + N ns */
 160 #define TRIG_FOLLOW     0x00000004      /* trigger on next lower level trig */
 161 #define TRIG_TIME       0x00000008      /* trigger at time N ns */
 162 #define TRIG_TIMER      0x00000010      /* trigger at rate N ns */
 163 #define TRIG_COUNT      0x00000020      /* trigger when count reaches N */
 164 #define TRIG_EXT        0x00000040      /* trigger on external signal N */
 165 #define TRIG_INT        0x00000080      /* trigger on comedi-internal signal N */
 166 #define TRIG_OTHER      0x00000100      /* driver defined */
 167
 168 /* subdevice flags */
 169
 170 #define SDF_BUSY        0x0001  /* device is busy */
 171 #define SDF_BUSY_OWNER  0x0002  /* device is busy with your job */
 172 #define SDF_LOCKED      0x0004  /* subdevice is locked */
 173 #define SDF_LOCK_OWNER  0x0008  /* you own lock */
 174 #define SDF_MAXDATA     0x0010  /* maxdata depends on channel */
 175 #define SDF_FLAGS       0x0020  /* flags depend on channel */
 176 #define SDF_RANGETYPE   0x0040  /* range type depends on channel */
 177 #define SDF_MODE0       0x0080  /* can do mode 0 */
 178 #define SDF_MODE1       0x0100  /* can do mode 1 */
 179 #define SDF_MODE2       0x0200  /* can do mode 2 */
 180 #define SDF_MODE3       0x0400  /* can do mode 3 */
 181 #define SDF_MODE4       0x0800  /* can do mode 4 */
 182 #define SDF_CMD         0x1000  /* can do commands (deprecated) */
 183 #define SDF_SOFT_CALIBRATED     0x2000  /* subdevice uses software calibration */
 184 #define SDF_CMD_WRITE           0x4000  /* can do output commands */
 185 #define SDF_CMD_READ            0x8000  /* can do input commands */
 186
 187 #define SDF_READABLE    0x00010000      /* subdevice can be read (e.g. analog input) */
 188 #define SDF_WRITABLE    0x00020000      /* subdevice can be written (e.g. analog output) */
 189 #define SDF_WRITEABLE   SDF_WRITABLE    /* spelling error in API */
 190 #define SDF_INTERNAL    0x00040000      /* subdevice does not have externally visible lines */
 191 #define SDF_RT          0x00080000      /* DEPRECATED: subdevice is RT capable */
 192 #define SDF_GROUND      0x00100000      /* can do aref=ground */
 193 #define SDF_COMMON      0x00200000      /* can do aref=common */
 194 #define SDF_DIFF        0x00400000      /* can do aref=diff */
 195 #define SDF_OTHER       0x00800000      /* can do aref=other */
 196 #define SDF_DITHER      0x01000000      /* can do dithering */
 197 #define SDF_DEGLITCH    0x02000000      /* can do deglitching */
 198 #define SDF_MMAP        0x04000000      /* can do mmap() */
 199 #define SDF_RUNNING     0x08000000      /* subdevice is acquiring data */
 200 #define SDF_LSAMPL      0x10000000      /* subdevice uses 32-bit samples */
 201 #define SDF_PACKED      0x20000000      /* subdevice can do packed DIO */
 202 /* re recyle these flags for PWM */
 203 #define SDF_PWM_COUNTER SDF_MODE0       /* PWM can automatically switch off */
 204 #define SDF_PWM_HBRIDGE SDF_MODE1       /* PWM is signed (H-bridge) */
 205
 206
 207
 208 /* subdevice types */
 209
 210 enum comedi_subdevice_type {
 211         COMEDI_SUBD_UNUSED,     /* unused by driver */
 212         COMEDI_SUBD_AI, /* analog input */
 213         COMEDI_SUBD_AO, /* analog output */
 214         COMEDI_SUBD_DI, /* digital input */
 215         COMEDI_SUBD_DO, /* digital output */
 216         COMEDI_SUBD_DIO,        /* digital input/output */
 217         COMEDI_SUBD_COUNTER,    /* counter */
 218         COMEDI_SUBD_TIMER,      /* timer */
 219         COMEDI_SUBD_MEMORY,     /* memory, EEPROM, DPRAM */
 220         COMEDI_SUBD_CALIB,      /* calibration DACs */
 221         COMEDI_SUBD_PROC,       /* processor, DSP */
 222         COMEDI_SUBD_SERIAL,     /* serial IO */
 223         COMEDI_SUBD_PWM         /* PWM */
 224 };
 225
 226 /* configuration instructions */
 227
 228 enum configuration_ids {
 229         INSN_CONFIG_DIO_INPUT = 0,
 230         INSN_CONFIG_DIO_OUTPUT = 1,
 231         INSN_CONFIG_DIO_OPENDRAIN = 2,
 232         INSN_CONFIG_ANALOG_TRIG = 16,
 233 /*      INSN_CONFIG_WAVEFORM = 17, */
 234 /*      INSN_CONFIG_TRIG = 18, */
 235 /*      INSN_CONFIG_COUNTER = 19, */
 236         INSN_CONFIG_ALT_SOURCE = 20,
 237         INSN_CONFIG_DIGITAL_TRIG = 21,
 238         INSN_CONFIG_BLOCK_SIZE = 22,
 239         INSN_CONFIG_TIMER_1 = 23,
 240         INSN_CONFIG_FILTER = 24,
 241         INSN_CONFIG_CHANGE_NOTIFY = 25,
 242
 243          /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26,
 244         INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
 245         INSN_CONFIG_DIO_QUERY = 28,
 246         INSN_CONFIG_PWM_OUTPUT = 29,
 247         INSN_CONFIG_GET_PWM_OUTPUT = 30,
 248         INSN_CONFIG_ARM = 31,
 249         INSN_CONFIG_DISARM = 32,
 250         INSN_CONFIG_GET_COUNTER_STATUS = 33,
 251         INSN_CONFIG_RESET = 34,
 252         INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, /* Use CTR as single pulsegenerator */
 253         INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002,  /* Use CTR as pulsetraingenerator */
 254         INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003,     /* Use the counter as encoder */
 255         INSN_CONFIG_SET_GATE_SRC = 2001,        /* Set gate source */
 256         INSN_CONFIG_GET_GATE_SRC = 2002,        /* Get gate source */
 257         INSN_CONFIG_SET_CLOCK_SRC = 2003,       /* Set master clock source */
 258         INSN_CONFIG_GET_CLOCK_SRC = 2004,       /* Get master clock source */
 259         INSN_CONFIG_SET_OTHER_SRC = 2005,       /* Set other source */
 260 /*      INSN_CONFIG_GET_OTHER_SRC = 2006,*/     /* Get other source */
 261         INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006,    /* Get size in bytes of
 262                                                            subdevice's on-board
 263                                                            fifos used during
 264                                                            streaming
 265                                                            input/output */
 266         INSN_CONFIG_SET_COUNTER_MODE = 4097,
 267         INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE,       /* deprecated */
 268         INSN_CONFIG_8254_READ_STATUS = 4098,
 269         INSN_CONFIG_SET_ROUTING = 4099,
 270         INSN_CONFIG_GET_ROUTING = 4109,
 271 /* PWM */
 272         INSN_CONFIG_PWM_SET_PERIOD = 5000,   /* sets frequency */
 273         INSN_CONFIG_PWM_GET_PERIOD = 5001,   /* gets frequency */
 274         INSN_CONFIG_GET_PWM_STATUS = 5002,          /* is it running? */
 275         INSN_CONFIG_PWM_SET_H_BRIDGE = 5003, /* sets H bridge: duty cycle and sign bit for a relay  at the same time*/
 276         INSN_CONFIG_PWM_GET_H_BRIDGE = 5004  /* gets H bridge data: duty cycle and the sign bit */
 277 };
 278
 279 enum comedi_io_direction {
 280         COMEDI_INPUT = 0,
 281         COMEDI_OUTPUT = 1,
 282         COMEDI_OPENDRAIN = 2
 283 };
 284
 285 enum comedi_support_level {
 286         COMEDI_UNKNOWN_SUPPORT = 0,
 287         COMEDI_SUPPORTED,
 288         COMEDI_UNSUPPORTED
 289 };
 290
 291 /* ioctls */
 292
 293 #define CIO 'd'
 294 #define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig)
 295 #define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo)
 296 #define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo)
 297 #define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo)
 298 #define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
 299 #define COMEDI_LOCK _IO(CIO, 5)
 300 #define COMEDI_UNLOCK _IO(CIO, 6)
 301 #define COMEDI_CANCEL _IO(CIO, 7)
 302 #define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo)
 303 #define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd)
 304 #define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd)
 305 #define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist)
 306 #define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn)
 307 #define COMEDI_BUFCONFIG _IOR(CIO, 13, comedi_bufconfig)
 308 #define COMEDI_BUFINFO _IOWR(CIO, 14, comedi_bufinfo)
 309 #define COMEDI_POLL _IO(CIO, 15)
 310
 311 /* structures */
 312
 313 typedef struct comedi_bufconfig_struct comedi_bufconfig;
 314 typedef struct comedi_bufinfo_struct comedi_bufinfo;
 315
 316 struct comedi_trig {
 317         unsigned int subdev;    /* subdevice */
 318         unsigned int mode;      /* mode */
 319         unsigned int flags;
 320         unsigned int n_chan;    /* number of channels */
 321         unsigned int *chanlist; /* channel/range list */
 322         short *data;    /* data list, size depends on subd flags */
 323         unsigned int n; /* number of scans */
 324         unsigned int trigsrc;
 325         unsigned int trigvar;
 326         unsigned int trigvar1;
 327         unsigned int data_len;
 328         unsigned int unused[3];
 329 };
 330
 331 struct comedi_insn {
 332         unsigned int insn;
 333         unsigned int n;
 334         unsigned int *data;
 335         unsigned int subdev;
 336         unsigned int chanspec;
 337         unsigned int unused[3];
 338 };
 339
 340 struct comedi_insnlist {
 341         unsigned int n_insns;
 342         struct comedi_insn *insns;
 343 };
 344
 345 struct comedi_cmd {
 346         unsigned int subdev;
 347         unsigned int flags;
 348
 349         unsigned int start_src;
 350         unsigned int start_arg;
 351
 352         unsigned int scan_begin_src;
 353         unsigned int scan_begin_arg;
 354
 355         unsigned int convert_src;
 356         unsigned int convert_arg;
 357
 358         unsigned int scan_end_src;
 359         unsigned int scan_end_arg;
 360
 361         unsigned int stop_src;
 362         unsigned int stop_arg;
 363
 364         unsigned int *chanlist; /* channel/range list */
 365         unsigned int chanlist_len;
 366
 367         short *data;    /* data list, size depends on subd flags */
 368         unsigned int data_len;
 369 };
 370
 371 struct comedi_chaninfo {
 372         unsigned int subdev;
 373         unsigned int *maxdata_list;
 374         unsigned int *flaglist;
 375         unsigned int *rangelist;
 376         unsigned int unused[4];
 377 };
 378
 379 struct comedi_rangeinfo {
 380         unsigned int range_type;
 381         void *range_ptr;
 382 };
 383
 384 struct comedi_krange {
 385         int min;        /* fixed point, multiply by 1e-6 */
 386         int max;        /* fixed point, multiply by 1e-6 */
 387         unsigned int flags;
 388 };
 389
 390
 391 struct comedi_subdinfo {
 392         unsigned int type;
 393         unsigned int n_chan;
 394         unsigned int subd_flags;
 395         unsigned int timer_type;
 396         unsigned int len_chanlist;
 397         unsigned int maxdata;
 398         unsigned int flags;     /* channel flags */
 399         unsigned int range_type;        /* lookup in kernel */
 400         unsigned int settling_time_0;
 401         unsigned insn_bits_support;     /* see support_level enum for values*/
 402         unsigned int unused[8];
 403 };
 404
 405 struct comedi_devinfo {
 406         unsigned int version_code;
 407         unsigned int n_subdevs;
 408         char driver_name[COMEDI_NAMELEN];
 409         char board_name[COMEDI_NAMELEN];
 410         int read_subdevice;
 411         int write_subdevice;
 412         int unused[30];
 413 };
 414
 415 struct comedi_devconfig {
 416         char board_name[COMEDI_NAMELEN];
 417         int options[COMEDI_NDEVCONFOPTS];
 418 };
 419
 420 struct comedi_bufconfig_struct {
 421         unsigned int subdevice;
 422         unsigned int flags;
 423
 424         unsigned int maximum_size;
 425         unsigned int size;
 426
 427         unsigned int unused[4];
 428 };
 429
 430 struct comedi_bufinfo_struct {
 431         unsigned int subdevice;
 432         unsigned int bytes_read;
 433
 434         unsigned int buf_write_ptr;
 435         unsigned int buf_read_ptr;
 436         unsigned int buf_write_count;
 437         unsigned int buf_read_count;
 438
 439         unsigned int bytes_written;
 440
 441         unsigned int unused[4];
 442 };
 443
 444 /* range stuff */
 445
 446 #define __RANGE(a, b)   ((((a)&0xffff)<<16)|((b)&0xffff))
 447
 448 #define RANGE_OFFSET(a)         (((a)>>16)&0xffff)
 449 #define RANGE_LENGTH(b)         ((b)&0xffff)
 450
 451 #define RF_UNIT(flags)          ((flags)&0xff)
 452 #define RF_EXTERNAL             (1<<8)
 453
 454 #define UNIT_volt               0
 455 #define UNIT_mA                 1
 456 #define UNIT_none               2
 457
 458 #define COMEDI_MIN_SPEED        ((unsigned int)0xffffffff)
 459
 460 /* callback stuff */
 461 /* only relevant to kernel modules. */
 462
 463 #define COMEDI_CB_EOS           1       /* end of scan */
 464 #define COMEDI_CB_EOA           2       /* end of acquisition */
 465 #define COMEDI_CB_BLOCK         4       /* DEPRECATED: convenient block size */
 466 #define COMEDI_CB_EOBUF         8       /* DEPRECATED: end of buffer */
 467 #define COMEDI_CB_ERROR         16      /* card error during acquisition */
 468 #define COMEDI_CB_OVERFLOW      32      /* buffer overflow/underflow */
 469
 470 /**********************************************************/
 471 /* everything after this line is ALPHA */
 472 /**********************************************************/
 473
 474 /*
 475   8254 specific configuration.
 476
 477   It supports two config commands:
 478
 479   0 ID: INSN_CONFIG_SET_COUNTER_MODE
 480   1 8254 Mode
 481     I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
 482     OR'ed with:
 483     I8254_BCD, I8254_BINARY
 484
 485   0 ID: INSN_CONFIG_8254_READ_STATUS
 486   1 <-- Status byte returned here.
 487     B7 = Output
 488     B6 = NULL Count
 489     B5 - B0 Current mode.
 490
 491 */
 492
 493 enum i8254_mode {
 494         I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
 495         I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
 496         I8254_MODE2 = (2 << 1), /* Rate generator */
 497         I8254_MODE3 = (3 << 1), /* Square wave mode */
 498         I8254_MODE4 = (4 << 1), /* Software triggered strobe */
 499         I8254_MODE5 = (5 << 1), /* Hardware triggered strobe (retriggerable) */
 500         I8254_BCD = 1,  /* use binary-coded decimal instead of binary (pretty useless) */
 501         I8254_BINARY = 0
 502 };
 503
 504 static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel)
 505 {
 506         if (pfi_channel < 10)
 507                 return 0x1 + pfi_channel;
 508         else
 509                 return 0xb + pfi_channel;
 510 }
 511 static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel)
 512 {
 513         if (rtsi_channel < 7)
 514                 return 0xb + rtsi_channel;
 515         else
 516                 return 0x1b;
 517 }
 518 /* mode bits for NI general-purpose counters, set with
 519  * INSN_CONFIG_SET_COUNTER_MODE */
 520 #define NI_GPCT_COUNTING_MODE_SHIFT 16
 521 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20
 522 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
 523 enum ni_gpct_mode_bits {
 524         NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
 525         NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
 526         NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
 527         NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
 528         NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
 529         NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
 530         NI_GPCT_STOP_MODE_MASK = 0x60,
 531         NI_GPCT_STOP_ON_GATE_BITS = 0x00,
 532         NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
 533         NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
 534         NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
 535         NI_GPCT_OUTPUT_MODE_MASK = 0x300,
 536         NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
 537         NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
 538         NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
 539         NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
 540         NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
 541         NI_GPCT_DISARM_AT_TC_BITS = 0x400,
 542         NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
 543         NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
 544         NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
 545         NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
 546         NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
 547         NI_GPCT_COUNTING_MODE_NORMAL_BITS =
 548                 0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
 549         NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
 550                 0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
 551         NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
 552                 0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
 553         NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
 554                 0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
 555         NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
 556                 0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
 557         NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
 558                 0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
 559         NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 560         NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
 561                 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 562         NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
 563                 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 564         NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
 565                 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 566         NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
 567                 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 568         NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
 569         NI_GPCT_COUNTING_DIRECTION_MASK =
 570                 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 571         NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
 572                 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 573         NI_GPCT_COUNTING_DIRECTION_UP_BITS =
 574                 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 575         NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
 576                 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 577         NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
 578                 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 579         NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
 580         NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
 581         NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
 582         NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
 583         NI_GPCT_OR_GATE_BIT = 0x10000000,
 584         NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
 585 };
 586
 587 /* Bits for setting a clock source with
 588  * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
 589 enum ni_gpct_clock_source_bits {
 590         NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
 591         NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
 592         NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
 593         NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
 594         NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
 595         NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
 596         NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
 597         NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6,      /* NI 660x-specific */
 598         NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
 599         NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
 600         NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
 601         NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
 602         NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
 603         NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000, /* divide source by 2 */
 604         NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000, /* divide source by 8 */
 605         NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
 606 };
 607 static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n)
 608 {
 609         /* NI 660x-specific */
 610         return 0x10 + n;
 611 }
 612 static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n)
 613 {
 614         return 0x18 + n;
 615 }
 616 static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n)
 617 {
 618         /* no pfi on NI 660x */
 619         return 0x20 + n;
 620 }
 621
 622 /* Possibilities for setting a gate source with
 623 INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
 624 May be bitwise-or'd with CR_EDGE or CR_INVERT. */
 625 enum ni_gpct_gate_select {
 626         /* m-series gates */
 627         NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
 628         NI_GPCT_AI_START2_GATE_SELECT = 0x12,
 629         NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
 630         NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
 631         NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
 632         NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
 633         NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
 634         NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
 635         /* more gates for 660x */
 636         NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
 637         NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
 638         /* more gates for 660x "second gate" */
 639         NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
 640         NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
 641         /* m-series "second gate" sources are unknown,
 642            we should add them here with an offset of 0x300 when known. */
 643         NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
 644 };
 645 static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n)
 646 {
 647         return 0x102 + n;
 648 }
 649 static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n)
 650 {
 651         return NI_USUAL_RTSI_SELECT(n);
 652 }
 653 static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n)
 654 {
 655         return NI_USUAL_PFI_SELECT(n);
 656 }
 657 static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n)
 658 {
 659         return 0x202 + n;
 660 }
 661
 662 /* Possibilities for setting a source with
 663 INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
 664 enum ni_gpct_other_index {
 665         NI_GPCT_SOURCE_ENCODER_A,
 666         NI_GPCT_SOURCE_ENCODER_B,
 667         NI_GPCT_SOURCE_ENCODER_Z
 668 };
 669 enum ni_gpct_other_select {
 670         /* m-series gates */
 671         /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
 672         NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
 673 };
 674 static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n)
 675 {
 676         return NI_USUAL_PFI_SELECT(n);
 677 }
 678
 679 /* start sources for ni general-purpose counters for use with
 680 INSN_CONFIG_ARM */
 681 enum ni_gpct_arm_source {
 682         NI_GPCT_ARM_IMMEDIATE = 0x0,
 683         NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1,     /* Start both the counter and
 684                                                    the adjacent paired counter
 685                                                    simultaneously */
 686         /* NI doesn't document bits for selecting hardware arm triggers.  If
 687          * the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
 688          * significant bits (3 bits for 660x or 5 bits for m-series) through to
 689          * the hardware.  This will at least allow someone to figure out what
 690          * the bits do later. */
 691         NI_GPCT_ARM_UNKNOWN = 0x1000,
 692 };
 693
 694 /* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
 695 enum ni_gpct_filter_select {
 696         NI_GPCT_FILTER_OFF = 0x0,
 697         NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
 698         NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
 699         NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
 700         NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
 701         NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
 702         NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
 703 };
 704
 705 /* PFI digital filtering options for ni m-series for use with
 706  * INSN_CONFIG_FILTER. */
 707 enum ni_pfi_filter_select {
 708         NI_PFI_FILTER_OFF = 0x0,
 709         NI_PFI_FILTER_125ns = 0x1,
 710         NI_PFI_FILTER_6425ns = 0x2,
 711         NI_PFI_FILTER_2550us = 0x3
 712 };
 713
 714 /* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
 715 enum ni_mio_clock_source {
 716         NI_MIO_INTERNAL_CLOCK = 0,
 717         NI_MIO_RTSI_CLOCK = 1,  /* doesn't work for m-series, use
 718                                    NI_MIO_PLL_RTSI_CLOCK() */
 719         /* the NI_MIO_PLL_* sources are m-series only */
 720         NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
 721         NI_MIO_PLL_PXI10_CLOCK = 3,
 722         NI_MIO_PLL_RTSI0_CLOCK = 4
 723 };
 724 static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel)
 725 {
 726         return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
 727 }
 728
 729 /* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
 730  The numbers assigned are not arbitrary, they correspond to the bits required
 731  to program the board. */
 732 enum ni_rtsi_routing {
 733         NI_RTSI_OUTPUT_ADR_START1 = 0,
 734         NI_RTSI_OUTPUT_ADR_START2 = 1,
 735         NI_RTSI_OUTPUT_SCLKG = 2,
 736         NI_RTSI_OUTPUT_DACUPDN = 3,
 737         NI_RTSI_OUTPUT_DA_START1 = 4,
 738         NI_RTSI_OUTPUT_G_SRC0 = 5,
 739         NI_RTSI_OUTPUT_G_GATE0 = 6,
 740         NI_RTSI_OUTPUT_RGOUT0 = 7,
 741         NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
 742         NI_RTSI_OUTPUT_RTSI_OSC = 12    /* pre-m-series always have RTSI clock
 743                                            on line 7 */
 744 };
 745 static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n)
 746 {
 747         return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
 748 }
 749
 750 /* Signals which can be routed to an NI PFI pin on an m-series board with
 751  * INSN_CONFIG_SET_ROUTING.  These numbers are also returned by
 752  * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
 753  * cannot be changed.  The numbers assigned are not arbitrary, they correspond
 754  * to the bits required to program the board. */
 755 enum ni_pfi_routing {
 756         NI_PFI_OUTPUT_PFI_DEFAULT = 0,
 757         NI_PFI_OUTPUT_AI_START1 = 1,
 758         NI_PFI_OUTPUT_AI_START2 = 2,
 759         NI_PFI_OUTPUT_AI_CONVERT = 3,
 760         NI_PFI_OUTPUT_G_SRC1 = 4,
 761         NI_PFI_OUTPUT_G_GATE1 = 5,
 762         NI_PFI_OUTPUT_AO_UPDATE_N = 6,
 763         NI_PFI_OUTPUT_AO_START1 = 7,
 764         NI_PFI_OUTPUT_AI_START_PULSE = 8,
 765         NI_PFI_OUTPUT_G_SRC0 = 9,
 766         NI_PFI_OUTPUT_G_GATE0 = 10,
 767         NI_PFI_OUTPUT_EXT_STROBE = 11,
 768         NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
 769         NI_PFI_OUTPUT_GOUT0 = 13,
 770         NI_PFI_OUTPUT_GOUT1 = 14,
 771         NI_PFI_OUTPUT_FREQ_OUT = 15,
 772         NI_PFI_OUTPUT_PFI_DO = 16,
 773         NI_PFI_OUTPUT_I_ATRIG = 17,
 774         NI_PFI_OUTPUT_RTSI0 = 18,
 775         NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
 776         NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
 777         NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
 778         NI_PFI_OUTPUT_CDI_SAMPLE = 29,
 779         NI_PFI_OUTPUT_CDO_UPDATE = 30
 780 };
 781 static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel)
 782 {
 783         return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
 784 }
 785
 786 /* Signals which can be routed to output on a NI PFI pin on a 660x board
 787  with INSN_CONFIG_SET_ROUTING.  The numbers assigned are
 788  not arbitrary, they correspond to the bits required
 789  to program the board.  Lines 0 to 7 can only be set to
 790  NI_660X_PFI_OUTPUT_DIO.  Lines 32 to 39 can only be set to
 791  NI_660X_PFI_OUTPUT_COUNTER. */
 792 enum ni_660x_pfi_routing {
 793         NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
 794         NI_660X_PFI_OUTPUT_DIO = 2,     /* static digital output */
 795 };
 796
 797 /* NI External Trigger lines.  These values are not arbitrary, but are related
 798  * to the bits required to program the board (offset by 1 for historical
 799  * reasons). */
 800 static inline unsigned NI_EXT_PFI(unsigned pfi_channel)
 801 {
 802         return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
 803 }
 804 static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel)
 805 {
 806         return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
 807 }
 808
 809 /* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
 810 enum comedi_counter_status_flags {
 811         COMEDI_COUNTER_ARMED = 0x1,
 812         COMEDI_COUNTER_COUNTING = 0x2,
 813         COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
 814 };
 815
 816 /* Clock sources for CDIO subdevice on NI m-series boards.  Used as the
 817  * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
 818  * with CR_INVERT to change polarity. */
 819 enum ni_m_series_cdio_scan_begin_src {
 820         NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
 821         NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
 822         NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
 823         NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
 824         NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
 825         NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
 826         NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
 827         NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
 828         NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
 829         NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
 830 };
 831 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
 832 {
 833         return NI_USUAL_PFI_SELECT(pfi_channel);
 834 }
 835 static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
 836 {
 837         return NI_USUAL_RTSI_SELECT(rtsi_channel);
 838 }
 839
 840 /* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
 841  * boards.  These scan begin sources can also be bitwise-or'd with CR_INVERT to
 842  * change polarity. */
 843 static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel)
 844 {
 845         return NI_USUAL_PFI_SELECT(pfi_channel);
 846 }
 847 static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel)
 848 {
 849         return NI_USUAL_RTSI_SELECT(rtsi_channel);
 850 }
 851
 852 /* Bits for setting a clock source with
 853  * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
 854 enum ni_freq_out_clock_source_bits {
 855         NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
 856         NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC        /* 100 KHz */
 857 };
 858
 859 /* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
 860  * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 861         enum amplc_dio_clock_source {
 862                 AMPLC_DIO_CLK_CLKN,     /* per channel external clock
 863                                            input/output pin (pin is only an
 864                                            input when clock source set to this
 865                                            value, otherwise it is an output) */
 866                 AMPLC_DIO_CLK_10MHZ,    /* 10 MHz internal clock */
 867                 AMPLC_DIO_CLK_1MHZ,     /* 1 MHz internal clock */
 868                 AMPLC_DIO_CLK_100KHZ,   /* 100 kHz internal clock */
 869                 AMPLC_DIO_CLK_10KHZ,    /* 10 kHz internal clock */
 870                 AMPLC_DIO_CLK_1KHZ,     /* 1 kHz internal clock */
 871                 AMPLC_DIO_CLK_OUTNM1,   /* output of preceding counter channel
 872                                            (for channel 0, preceding counter
 873                                            channel is channel 2 on preceding
 874                                            counter subdevice, for first counter
 875                                            subdevice, preceding counter
 876                                            subdevice is the last counter
 877                                            subdevice) */
 878                 AMPLC_DIO_CLK_EXT       /* per chip external input pin */
 879         };
 880
 881 /* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
 882  * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 883         enum amplc_dio_gate_source {
 884                 AMPLC_DIO_GAT_VCC,      /* internal high logic level */
 885                 AMPLC_DIO_GAT_GND,      /* internal low logic level */
 886                 AMPLC_DIO_GAT_GATN,     /* per channel external gate input */
 887                 AMPLC_DIO_GAT_NOUTNM2,  /* negated output of counter channel
 888                                            minus 2 (for channels 0 or 1,
 889                                            channel minus 2 is channel 1 or 2 on
 890                                            the preceding counter subdevice, for
 891                                            the first counter subdevice the
 892                                            preceding counter subdevice is the
 893                                            last counter subdevice) */
 894                 AMPLC_DIO_GAT_RESERVED4,
 895                 AMPLC_DIO_GAT_RESERVED5,
 896                 AMPLC_DIO_GAT_RESERVED6,
 897                 AMPLC_DIO_GAT_RESERVED7
 898         };
 899
 900 #ifdef __cplusplus
 901 }
 902 #endif
 903
 904 #endif /* _COMEDI_H */