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Staging: comedi: remove comedi-specific wrappers
[deliverable/linux.git] / drivers / staging / comedi / drivers / cb_pcidas64.c
1 /*
2 comedi/drivers/cb_pcidas64.c
3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4 64xx, 60xx, and 4020 cards.
5
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2001, 2002 Frank Mori Hess
8
9 Thanks also go to the following people:
10
11 Steve Rosenbluth, for providing the source code for
12 his pci-das6402 driver, and source code for working QNX pci-6402
13 drivers by Greg Laird and Mariusz Bogacz. None of the code was
14 used directly here, but it was useful as an additional source of
15 documentation on how to program the boards.
16
17 John Sims, for much testing and feedback on pcidas-4020 support.
18
19 COMEDI - Linux Control and Measurement Device Interface
20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
21
22 This program is free software; you can redistribute it and/or modify
23 it under the terms of the GNU General Public License as published by
24 the Free Software Foundation; either version 2 of the License, or
25 (at your option) any later version.
26
27 This program is distributed in the hope that it will be useful,
28 but WITHOUT ANY WARRANTY; without even the implied warranty of
29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 GNU General Public License for more details.
31
32 You should have received a copy of the GNU General Public License
33 along with this program; if not, write to the Free Software
34 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35
36 ************************************************************************/
37
38 /*
39
40 Driver: cb_pcidas64
41 Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller
42 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
43 Status: works
44 Updated: 2002-10-09
45 Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
46 PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
47 PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
48 PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
49 PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
50 PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
51 PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
52 PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
53 PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
54
55 Configuration options:
56 [0] - PCI bus of device (optional)
57 [1] - PCI slot of device (optional)
58
59 These boards may be autocalibrated with the comedi_calibrate utility.
60
61 To select the bnc trigger input on the 4020 (instead of the dio input),
62 specify a nonzero channel in the chanspec. If you wish to use an external
63 master clock on the 4020, you may do so by setting the scan_begin_src
64 to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
65 to configure the divisor to use for the external clock.
66
67 Some devices are not identified because the PCI device IDs are not yet
68 known. If you have such a board, please file a bug report at
69 https://bugs.comedi.org.
70
71 */
72
73 /*
74
75 TODO:
76 make it return error if user attempts an ai command that uses the
77 external queue, and an ao command simultaneously
78 user counter subdevice
79 there are a number of boards this driver will support when they are
80 fully released, but does not yet since the pci device id numbers
81 are not yet available.
82 support prescaled 100khz clock for slow pacing (not available on 6000 series?)
83 make ao fifo size adjustable like ai fifo
84 */
85
86 #include "../comedidev.h"
87 #include <linux/delay.h>
88 #include <linux/interrupt.h>
89 #include <asm/system.h>
90
91 #include "comedi_pci.h"
92 #include "8253.h"
93 #include "8255.h"
94 #include "plx9080.h"
95 #include "comedi_fc.h"
96
97 #undef PCIDAS64_DEBUG /* disable debugging code */
98 /* #define PCIDAS64_DEBUG enable debugging code */
99
100 #ifdef PCIDAS64_DEBUG
101 #define DEBUG_PRINT(format, args...) printk(format , ## args)
102 #else
103 #define DEBUG_PRINT(format, args...)
104 #endif
105
106 #define TIMER_BASE 25 /* 40MHz master clock */
107 #define PRESCALED_TIMER_BASE 10000 /* 100kHz 'prescaled' clock for slow aquisition, maybe I'll support this someday */
108 #define DMA_BUFFER_SIZE 0x1000
109
110 /* maximum value that can be loaded into board's 24-bit counters*/
111 static const int max_counter_value = 0xffffff;
112
113 /* PCI-DAS64xxx base addresses */
114
115 /* indices of base address regions */
116 enum base_address_regions {
117 PLX9080_BADDRINDEX = 0,
118 MAIN_BADDRINDEX = 2,
119 DIO_COUNTER_BADDRINDEX = 3,
120 };
121
122 /* priv(dev)->main_iobase registers */
123 enum write_only_registers {
124 INTR_ENABLE_REG = 0x0, /* interrupt enable register */
125 HW_CONFIG_REG = 0x2, /* hardware config register */
126 DAQ_SYNC_REG = 0xc,
127 DAQ_ATRIG_LOW_4020_REG = 0xc,
128 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */
129 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */
130 CALIBRATION_REG = 0x14,
131 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16, /* lower 16 bits of adc sample interval counter */
132 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18, /* upper 8 bits of adc sample interval counter */
133 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a, /* lower 16 bits of delay interval counter */
134 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, /* upper 8 bits of delay interval counter */
135 ADC_COUNT_LOWER_REG = 0x1e, /* lower 16 bits of hardware conversion/scan counter */
136 ADC_COUNT_UPPER_REG = 0x20, /* upper 8 bits of hardware conversion/scan counter */
137 ADC_START_REG = 0x22, /* software trigger to start aquisition */
138 ADC_CONVERT_REG = 0x24, /* initiates single conversion */
139 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */
140 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */
141 ADC_BUFFER_CLEAR_REG = 0x2a,
142 ADC_QUEUE_HIGH_REG = 0x2c, /* high channel for internal queue, use adc_chan_bits() inline above */
143 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */
144 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */
145 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54, /* lower 16 bits of dac sample interval counter */
146 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56, /* upper 8 bits of dac sample interval counter */
147 DAC_SELECT_REG = 0x60,
148 DAC_START_REG = 0x64,
149 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */
150 };
151 static inline unsigned int dac_convert_reg(unsigned int channel)
152 {
153 return 0x70 + (2 * (channel & 0x1));
154 }
155 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
156 {
157 return 0x70 + (4 * (channel & 0x1));
158 }
159 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
160 {
161 return 0x72 + (4 * (channel & 0x1));
162 }
163
164 enum read_only_registers {
165 HW_STATUS_REG = 0x0, /* hardware status register, reading this apparently clears pending interrupts as well */
166 PIPE1_READ_REG = 0x4,
167 ADC_READ_PNTR_REG = 0x8,
168 LOWER_XFER_REG = 0x10,
169 ADC_WRITE_PNTR_REG = 0xc,
170 PREPOST_REG = 0x14,
171 };
172
173 enum read_write_registers {
174 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */
175 ADC_QUEUE_FIFO_REG = 0x100, /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
176 ADC_FIFO_REG = 0x200, /* adc data fifo */
177 DAC_FIFO_REG = 0x300, /* dac data fifo, has weird interactions with external channel queue */
178 };
179
180 /* priv(dev)->dio_counter_iobase registers */
181 enum dio_counter_registers {
182 DIO_8255_OFFSET = 0x0,
183 DO_REG = 0x20,
184 DI_REG = 0x28,
185 DIO_DIRECTION_60XX_REG = 0x40,
186 DIO_DATA_60XX_REG = 0x48,
187 };
188
189 /* bit definitions for write-only registers */
190
191 enum intr_enable_contents {
192 ADC_INTR_SRC_MASK = 0x3, /* bits that set adc interrupt source */
193 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quater full */
194 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */
195 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */
196 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence (probably wont use this it's pretty fancy) */
197 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */
198 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc aquisition done interrupt */
199 DAC_INTR_SRC_MASK = 0x30,
200 DAC_INTR_QEMPTY_BITS = 0x0,
201 DAC_INTR_HIGH_CHAN_BITS = 0x10,
202 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */
203 EN_DAC_DONE_INTR_BIT = 0x80,
204 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
205 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */
206 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
207 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */
208 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */
209 };
210
211 enum hw_config_contents {
212 MASTER_CLOCK_4020_MASK = 0x3, /* bits that specify master clock source for 4020 */
213 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock for 4020 */
214 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */
215 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */
216 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue (more versatile than internal queue) */
217 SLOW_DAC_BIT = 0x400, /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
218 HW_CONFIG_DUMMY_BITS = 0x2000, /* bit with unknown function yet given as default value in pci-das64 manual */
219 DMA_CH_SELECT_BIT = 0x8000, /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
220 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */
221 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */
222 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
223 };
224 #define DAC_FIFO_SIZE 0x2000
225
226 enum daq_atrig_low_4020_contents {
227 EXT_AGATE_BNC_BIT = 0x8000, /* use trig/ext clk bnc input for analog gate signal */
228 EXT_STOP_TRIG_BNC_BIT = 0x4000, /* use trig/ext clk bnc input for external stop trigger signal */
229 EXT_START_TRIG_BNC_BIT = 0x2000, /* use trig/ext clk bnc input for external start trigger signal */
230 };
231 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
232 {
233 return threshold & 0xfff;
234 }
235
236 enum adc_control0_contents {
237 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */
238 ADC_SOFT_GATE_BITS = 0x1, /* software gate */
239 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */
240 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */
241 ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */
242 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */
243 ADC_START_TRIG_SOFT_BITS = 0x10,
244 ADC_START_TRIG_EXT_BITS = 0x20,
245 ADC_START_TRIG_ANALOG_BITS = 0x30,
246 ADC_START_TRIG_MASK = 0x30,
247 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */
248 ADC_EXT_CONV_FALLING_BIT = 0x800, /* external pacing uses falling edge */
249 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000, /* enable hardware scan counter */
250 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */
251 ADC_ENABLE_BIT = 0x8000, /* master adc enable */
252 };
253
254 enum adc_control1_contents {
255 ADC_QUEUE_CONFIG_BIT = 0x1, /* should be set for boards with > 16 channels */
256 CONVERT_POLARITY_BIT = 0x10,
257 EOC_POLARITY_BIT = 0x20,
258 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */
259 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */
260 RETRIGGER_BIT = 0x800,
261 ADC_LO_CHANNEL_4020_MASK = 0x300,
262 ADC_HI_CHANNEL_4020_MASK = 0xc00,
263 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */
264 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */
265 CHANNEL_MODE_4020_MASK = 0x3000,
266 ADC_MODE_MASK = 0xf000,
267 };
268 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
269 {
270 return (channel & 0x3) << 8;
271 };
272 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
273 {
274 return (channel & 0x3) << 10;
275 };
276 static inline uint16_t adc_mode_bits(unsigned int mode)
277 {
278 return (mode & 0xf) << 12;
279 };
280
281 enum calibration_contents {
282 SELECT_8800_BIT = 0x1,
283 SELECT_8402_64XX_BIT = 0x2,
284 SELECT_1590_60XX_BIT = 0x2,
285 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */
286 SERIAL_DATA_IN_BIT = 0x80,
287 SERIAL_CLOCK_BIT = 0x100,
288 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */
289 CAL_GAIN_BIT = 0x800,
290 };
291 /* calibration sources for 6025 are:
292 * 0 : ground
293 * 1 : 10V
294 * 2 : 5V
295 * 3 : 0.5V
296 * 4 : 0.05V
297 * 5 : ground
298 * 6 : dac channel 0
299 * 7 : dac channel 1
300 */
301 static inline uint16_t adc_src_bits(unsigned int source)
302 {
303 return (source & 0xf) << 3;
304 };
305
306 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
307 {
308 return (channel & 0x3) << 8;
309 };
310
311 enum adc_queue_load_contents {
312 UNIP_BIT = 0x800, /* unipolar/bipolar bit */
313 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */
314 ADC_COMMON_BIT = 0x2000, /* non-referenced single-ended (common-mode input) */
315 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */
316 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */
317 };
318 static inline uint16_t adc_chan_bits(unsigned int channel)
319 {
320 return channel & 0x3f;
321 };
322
323 enum dac_control0_contents {
324 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */
325 DAC_CYCLIC_STOP_BIT = 0x4000,
326 DAC_WAVEFORM_MODE_BIT = 0x100,
327 DAC_EXT_UPDATE_FALLING_BIT = 0x80,
328 DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
329 WAVEFORM_TRIG_MASK = 0x30,
330 WAVEFORM_TRIG_DISABLED_BITS = 0x0,
331 WAVEFORM_TRIG_SOFT_BITS = 0x10,
332 WAVEFORM_TRIG_EXT_BITS = 0x20,
333 WAVEFORM_TRIG_ADC1_BITS = 0x30,
334 WAVEFORM_TRIG_FALLING_BIT = 0x8,
335 WAVEFORM_GATE_LEVEL_BIT = 0x4,
336 WAVEFORM_GATE_ENABLE_BIT = 0x2,
337 WAVEFORM_GATE_SELECT_BIT = 0x1,
338 };
339
340 enum dac_control1_contents {
341 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
342 DAC1_EXT_REF_BIT = 0x200,
343 DAC0_EXT_REF_BIT = 0x100,
344 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */
345 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
346 DAC_SW_GATE_BIT = 0x20,
347 DAC1_UNIPOLAR_BIT = 0x8,
348 DAC0_UNIPOLAR_BIT = 0x2,
349 };
350
351 /* bit definitions for read-only registers */
352 enum hw_status_contents {
353 DAC_UNDERRUN_BIT = 0x1,
354 ADC_OVERRUN_BIT = 0x2,
355 DAC_ACTIVE_BIT = 0x4,
356 ADC_ACTIVE_BIT = 0x8,
357 DAC_INTR_PENDING_BIT = 0x10,
358 ADC_INTR_PENDING_BIT = 0x20,
359 DAC_DONE_BIT = 0x40,
360 ADC_DONE_BIT = 0x80,
361 EXT_INTR_PENDING_BIT = 0x100,
362 ADC_STOP_BIT = 0x200,
363 };
364 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
365 {
366 return (hw_status_bits >> 10) & 0x3;
367 };
368
369 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
370 {
371 return (prepost_bits >> 6) & 0x3;
372 }
373 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
374 {
375 return (prepost_bits >> 12) & 0x3;
376 }
377 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
378 {
379 return (prepost_bits >> 14) & 0x3;
380 }
381
382 /* I2C addresses for 4020 */
383 enum i2c_addresses {
384 RANGE_CAL_I2C_ADDR = 0x20,
385 CALDAC0_I2C_ADDR = 0xc,
386 CALDAC1_I2C_ADDR = 0xd,
387 };
388
389 enum range_cal_i2c_contents {
390 ADC_SRC_4020_MASK = 0x70, /* bits that set what source the adc converter measures */
391 BNC_TRIG_THRESHOLD_0V_BIT = 0x80, /* make bnc trig/ext clock threshold 0V instead of 2.5V */
392 };
393 static inline uint8_t adc_src_4020_bits(unsigned int source)
394 {
395 return (source << 4) & ADC_SRC_4020_MASK;
396 };
397 static inline uint8_t attenuate_bit(unsigned int channel)
398 {
399 /* attenuate channel (+-5V input range) */
400 return 1 << (channel & 0x3);
401 };
402
403 /* analog input ranges for 64xx boards */
404 static const struct comedi_lrange ai_ranges_64xx = {
405 8,
406 {
407 BIP_RANGE(10),
408 BIP_RANGE(5),
409 BIP_RANGE(2.5),
410 BIP_RANGE(1.25),
411 UNI_RANGE(10),
412 UNI_RANGE(5),
413 UNI_RANGE(2.5),
414 UNI_RANGE(1.25)
415 }
416 };
417
418 /* analog input ranges for 60xx boards */
419 static const struct comedi_lrange ai_ranges_60xx = {
420 4,
421 {
422 BIP_RANGE(10),
423 BIP_RANGE(5),
424 BIP_RANGE(0.5),
425 BIP_RANGE(0.05),
426 }
427 };
428
429 /* analog input ranges for 6030, etc boards */
430 static const struct comedi_lrange ai_ranges_6030 = {
431 14,
432 {
433 BIP_RANGE(10),
434 BIP_RANGE(5),
435 BIP_RANGE(2),
436 BIP_RANGE(1),
437 BIP_RANGE(0.5),
438 BIP_RANGE(0.2),
439 BIP_RANGE(0.1),
440 UNI_RANGE(10),
441 UNI_RANGE(5),
442 UNI_RANGE(2),
443 UNI_RANGE(1),
444 UNI_RANGE(0.5),
445 UNI_RANGE(0.2),
446 UNI_RANGE(0.1),
447 }
448 };
449
450 /* analog input ranges for 6052, etc boards */
451 static const struct comedi_lrange ai_ranges_6052 = {
452 15,
453 {
454 BIP_RANGE(10),
455 BIP_RANGE(5),
456 BIP_RANGE(2.5),
457 BIP_RANGE(1),
458 BIP_RANGE(0.5),
459 BIP_RANGE(0.25),
460 BIP_RANGE(0.1),
461 BIP_RANGE(0.05),
462 UNI_RANGE(10),
463 UNI_RANGE(5),
464 UNI_RANGE(2),
465 UNI_RANGE(1),
466 UNI_RANGE(0.5),
467 UNI_RANGE(0.2),
468 UNI_RANGE(0.1),
469 }
470 };
471
472 /* analog input ranges for 4020 board */
473 static const struct comedi_lrange ai_ranges_4020 = {
474 2,
475 {
476 BIP_RANGE(5),
477 BIP_RANGE(1),
478 }
479 };
480
481 /* analog output ranges */
482 static const struct comedi_lrange ao_ranges_64xx = {
483 4,
484 {
485 BIP_RANGE(5),
486 BIP_RANGE(10),
487 UNI_RANGE(5),
488 UNI_RANGE(10),
489 }
490 };
491 static const int ao_range_code_64xx[] = {
492 0x0,
493 0x1,
494 0x2,
495 0x3,
496 };
497
498 static const struct comedi_lrange ao_ranges_60xx = {
499 1,
500 {
501 BIP_RANGE(10),
502 }
503 };
504 static const int ao_range_code_60xx[] = {
505 0x0,
506 };
507
508 static const struct comedi_lrange ao_ranges_6030 = {
509 2,
510 {
511 BIP_RANGE(10),
512 UNI_RANGE(10),
513 }
514 };
515 static const int ao_range_code_6030[] = {
516 0x0,
517 0x2,
518 };
519
520 static const struct comedi_lrange ao_ranges_4020 = {
521 2,
522 {
523 BIP_RANGE(5),
524 BIP_RANGE(10),
525 }
526 };
527 static const int ao_range_code_4020[] = {
528 0x1,
529 0x0,
530 };
531
532 enum register_layout {
533 LAYOUT_60XX,
534 LAYOUT_64XX,
535 LAYOUT_4020,
536 };
537
538 struct hw_fifo_info {
539 unsigned int num_segments;
540 unsigned int max_segment_length;
541 unsigned int sample_packing_ratio;
542 uint16_t fifo_size_reg_mask;
543 };
544
545 struct pcidas64_board {
546 const char *name;
547 int device_id; /* pci device id */
548 int ai_se_chans; /* number of ai inputs in single-ended mode */
549 int ai_bits; /* analog input resolution */
550 int ai_speed; /* fastest conversion period in ns */
551 const struct comedi_lrange *ai_range_table;
552 int ao_nchan; /* number of analog out channels */
553 int ao_bits; /* analog output resolution */
554 int ao_scan_speed; /* analog output speed (for a scan, not conversion) */
555 const struct comedi_lrange *ao_range_table;
556 const int *ao_range_code;
557 const struct hw_fifo_info *const ai_fifo;
558 enum register_layout layout; /* different board families have slightly different registers */
559 unsigned has_8255:1;
560 };
561
562 static const struct hw_fifo_info ai_fifo_4020 = {
563 .num_segments = 2,
564 .max_segment_length = 0x8000,
565 .sample_packing_ratio = 2,
566 .fifo_size_reg_mask = 0x7f,
567 };
568
569 static const struct hw_fifo_info ai_fifo_64xx = {
570 .num_segments = 4,
571 .max_segment_length = 0x800,
572 .sample_packing_ratio = 1,
573 .fifo_size_reg_mask = 0x3f,
574 };
575
576 static const struct hw_fifo_info ai_fifo_60xx = {
577 .num_segments = 4,
578 .max_segment_length = 0x800,
579 .sample_packing_ratio = 1,
580 .fifo_size_reg_mask = 0x7f,
581 };
582
583 /* maximum number of dma transfers we will chain together into a ring
584 * (and the maximum number of dma buffers we maintain) */
585 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
586 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
587 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
588 static inline unsigned int ai_dma_ring_count(struct pcidas64_board *board)
589 {
590 if (board->layout == LAYOUT_4020)
591 return MAX_AI_DMA_RING_COUNT;
592 else
593 return MIN_AI_DMA_RING_COUNT;
594 }
595
596 static const int bytes_in_sample = 2;
597
598 static const struct pcidas64_board pcidas64_boards[] = {
599 {
600 .name = "pci-das6402/16",
601 .device_id = 0x1d,
602 .ai_se_chans = 64,
603 .ai_bits = 16,
604 .ai_speed = 5000,
605 .ao_nchan = 2,
606 .ao_bits = 16,
607 .ao_scan_speed = 10000,
608 .layout = LAYOUT_64XX,
609 .ai_range_table = &ai_ranges_64xx,
610 .ao_range_table = &ao_ranges_64xx,
611 .ao_range_code = ao_range_code_64xx,
612 .ai_fifo = &ai_fifo_64xx,
613 .has_8255 = 1,
614 },
615 {
616 .name = "pci-das6402/12", /* XXX check */
617 .device_id = 0x1e,
618 .ai_se_chans = 64,
619 .ai_bits = 12,
620 .ai_speed = 5000,
621 .ao_nchan = 2,
622 .ao_bits = 12,
623 .ao_scan_speed = 10000,
624 .layout = LAYOUT_64XX,
625 .ai_range_table = &ai_ranges_64xx,
626 .ao_range_table = &ao_ranges_64xx,
627 .ao_range_code = ao_range_code_64xx,
628 .ai_fifo = &ai_fifo_64xx,
629 .has_8255 = 1,
630 },
631 {
632 .name = "pci-das64/m1/16",
633 .device_id = 0x35,
634 .ai_se_chans = 64,
635 .ai_bits = 16,
636 .ai_speed = 1000,
637 .ao_nchan = 2,
638 .ao_bits = 16,
639 .ao_scan_speed = 10000,
640 .layout = LAYOUT_64XX,
641 .ai_range_table = &ai_ranges_64xx,
642 .ao_range_table = &ao_ranges_64xx,
643 .ao_range_code = ao_range_code_64xx,
644 .ai_fifo = &ai_fifo_64xx,
645 .has_8255 = 1,
646 },
647 {
648 .name = "pci-das64/m2/16",
649 .device_id = 0x36,
650 .ai_se_chans = 64,
651 .ai_bits = 16,
652 .ai_speed = 500,
653 .ao_nchan = 2,
654 .ao_bits = 16,
655 .ao_scan_speed = 10000,
656 .layout = LAYOUT_64XX,
657 .ai_range_table = &ai_ranges_64xx,
658 .ao_range_table = &ao_ranges_64xx,
659 .ao_range_code = ao_range_code_64xx,
660 .ai_fifo = &ai_fifo_64xx,
661 .has_8255 = 1,
662 },
663 {
664 .name = "pci-das64/m3/16",
665 .device_id = 0x37,
666 .ai_se_chans = 64,
667 .ai_bits = 16,
668 .ai_speed = 333,
669 .ao_nchan = 2,
670 .ao_bits = 16,
671 .ao_scan_speed = 10000,
672 .layout = LAYOUT_64XX,
673 .ai_range_table = &ai_ranges_64xx,
674 .ao_range_table = &ao_ranges_64xx,
675 .ao_range_code = ao_range_code_64xx,
676 .ai_fifo = &ai_fifo_64xx,
677 .has_8255 = 1,
678 },
679 {
680 .name = "pci-das6013",
681 .device_id = 0x78,
682 .ai_se_chans = 16,
683 .ai_bits = 16,
684 .ai_speed = 5000,
685 .ao_nchan = 0,
686 .ao_bits = 16,
687 .layout = LAYOUT_60XX,
688 .ai_range_table = &ai_ranges_60xx,
689 .ao_range_table = &ao_ranges_60xx,
690 .ao_range_code = ao_range_code_60xx,
691 .ai_fifo = &ai_fifo_60xx,
692 .has_8255 = 0,
693 },
694 {
695 .name = "pci-das6014",
696 .device_id = 0x79,
697 .ai_se_chans = 16,
698 .ai_bits = 16,
699 .ai_speed = 5000,
700 .ao_nchan = 2,
701 .ao_bits = 16,
702 .ao_scan_speed = 100000,
703 .layout = LAYOUT_60XX,
704 .ai_range_table = &ai_ranges_60xx,
705 .ao_range_table = &ao_ranges_60xx,
706 .ao_range_code = ao_range_code_60xx,
707 .ai_fifo = &ai_fifo_60xx,
708 .has_8255 = 0,
709 },
710 {
711 .name = "pci-das6023",
712 .device_id = 0x5d,
713 .ai_se_chans = 16,
714 .ai_bits = 12,
715 .ai_speed = 5000,
716 .ao_nchan = 0,
717 .ao_scan_speed = 100000,
718 .layout = LAYOUT_60XX,
719 .ai_range_table = &ai_ranges_60xx,
720 .ao_range_table = &ao_ranges_60xx,
721 .ao_range_code = ao_range_code_60xx,
722 .ai_fifo = &ai_fifo_60xx,
723 .has_8255 = 1,
724 },
725 {
726 .name = "pci-das6025",
727 .device_id = 0x5e,
728 .ai_se_chans = 16,
729 .ai_bits = 12,
730 .ai_speed = 5000,
731 .ao_nchan = 2,
732 .ao_bits = 12,
733 .ao_scan_speed = 100000,
734 .layout = LAYOUT_60XX,
735 .ai_range_table = &ai_ranges_60xx,
736 .ao_range_table = &ao_ranges_60xx,
737 .ao_range_code = ao_range_code_60xx,
738 .ai_fifo = &ai_fifo_60xx,
739 .has_8255 = 1,
740 },
741 {
742 .name = "pci-das6030",
743 .device_id = 0x5f,
744 .ai_se_chans = 16,
745 .ai_bits = 16,
746 .ai_speed = 10000,
747 .ao_nchan = 2,
748 .ao_bits = 16,
749 .ao_scan_speed = 10000,
750 .layout = LAYOUT_60XX,
751 .ai_range_table = &ai_ranges_6030,
752 .ao_range_table = &ao_ranges_6030,
753 .ao_range_code = ao_range_code_6030,
754 .ai_fifo = &ai_fifo_60xx,
755 .has_8255 = 0,
756 },
757 {
758 .name = "pci-das6031",
759 .device_id = 0x60,
760 .ai_se_chans = 64,
761 .ai_bits = 16,
762 .ai_speed = 10000,
763 .ao_nchan = 2,
764 .ao_bits = 16,
765 .ao_scan_speed = 10000,
766 .layout = LAYOUT_60XX,
767 .ai_range_table = &ai_ranges_6030,
768 .ao_range_table = &ao_ranges_6030,
769 .ao_range_code = ao_range_code_6030,
770 .ai_fifo = &ai_fifo_60xx,
771 .has_8255 = 0,
772 },
773 {
774 .name = "pci-das6032",
775 .device_id = 0x61,
776 .ai_se_chans = 16,
777 .ai_bits = 16,
778 .ai_speed = 10000,
779 .ao_nchan = 0,
780 .layout = LAYOUT_60XX,
781 .ai_range_table = &ai_ranges_6030,
782 .ai_fifo = &ai_fifo_60xx,
783 .has_8255 = 0,
784 },
785 {
786 .name = "pci-das6033",
787 .device_id = 0x62,
788 .ai_se_chans = 64,
789 .ai_bits = 16,
790 .ai_speed = 10000,
791 .ao_nchan = 0,
792 .layout = LAYOUT_60XX,
793 .ai_range_table = &ai_ranges_6030,
794 .ai_fifo = &ai_fifo_60xx,
795 .has_8255 = 0,
796 },
797 {
798 .name = "pci-das6034",
799 .device_id = 0x63,
800 .ai_se_chans = 16,
801 .ai_bits = 16,
802 .ai_speed = 5000,
803 .ao_nchan = 0,
804 .ao_scan_speed = 0,
805 .layout = LAYOUT_60XX,
806 .ai_range_table = &ai_ranges_60xx,
807 .ai_fifo = &ai_fifo_60xx,
808 .has_8255 = 0,
809 },
810 {
811 .name = "pci-das6035",
812 .device_id = 0x64,
813 .ai_se_chans = 16,
814 .ai_bits = 16,
815 .ai_speed = 5000,
816 .ao_nchan = 2,
817 .ao_bits = 12,
818 .ao_scan_speed = 100000,
819 .layout = LAYOUT_60XX,
820 .ai_range_table = &ai_ranges_60xx,
821 .ao_range_table = &ao_ranges_60xx,
822 .ao_range_code = ao_range_code_60xx,
823 .ai_fifo = &ai_fifo_60xx,
824 .has_8255 = 0,
825 },
826 {
827 .name = "pci-das6036",
828 .device_id = 0x6f,
829 .ai_se_chans = 16,
830 .ai_bits = 16,
831 .ai_speed = 5000,
832 .ao_nchan = 2,
833 .ao_bits = 16,
834 .ao_scan_speed = 100000,
835 .layout = LAYOUT_60XX,
836 .ai_range_table = &ai_ranges_60xx,
837 .ao_range_table = &ao_ranges_60xx,
838 .ao_range_code = ao_range_code_60xx,
839 .ai_fifo = &ai_fifo_60xx,
840 .has_8255 = 0,
841 },
842 {
843 .name = "pci-das6040",
844 .device_id = 0x65,
845 .ai_se_chans = 16,
846 .ai_bits = 12,
847 .ai_speed = 2000,
848 .ao_nchan = 2,
849 .ao_bits = 12,
850 .ao_scan_speed = 1000,
851 .layout = LAYOUT_60XX,
852 .ai_range_table = &ai_ranges_6052,
853 .ao_range_table = &ao_ranges_6030,
854 .ao_range_code = ao_range_code_6030,
855 .ai_fifo = &ai_fifo_60xx,
856 .has_8255 = 0,
857 },
858 {
859 .name = "pci-das6052",
860 .device_id = 0x66,
861 .ai_se_chans = 16,
862 .ai_bits = 16,
863 .ai_speed = 3333,
864 .ao_nchan = 2,
865 .ao_bits = 16,
866 .ao_scan_speed = 3333,
867 .layout = LAYOUT_60XX,
868 .ai_range_table = &ai_ranges_6052,
869 .ao_range_table = &ao_ranges_6030,
870 .ao_range_code = ao_range_code_6030,
871 .ai_fifo = &ai_fifo_60xx,
872 .has_8255 = 0,
873 },
874 {
875 .name = "pci-das6070",
876 .device_id = 0x67,
877 .ai_se_chans = 16,
878 .ai_bits = 12,
879 .ai_speed = 800,
880 .ao_nchan = 2,
881 .ao_bits = 12,
882 .ao_scan_speed = 1000,
883 .layout = LAYOUT_60XX,
884 .ai_range_table = &ai_ranges_6052,
885 .ao_range_table = &ao_ranges_6030,
886 .ao_range_code = ao_range_code_6030,
887 .ai_fifo = &ai_fifo_60xx,
888 .has_8255 = 0,
889 },
890 {
891 .name = "pci-das6071",
892 .device_id = 0x68,
893 .ai_se_chans = 64,
894 .ai_bits = 12,
895 .ai_speed = 800,
896 .ao_nchan = 2,
897 .ao_bits = 12,
898 .ao_scan_speed = 1000,
899 .layout = LAYOUT_60XX,
900 .ai_range_table = &ai_ranges_6052,
901 .ao_range_table = &ao_ranges_6030,
902 .ao_range_code = ao_range_code_6030,
903 .ai_fifo = &ai_fifo_60xx,
904 .has_8255 = 0,
905 },
906 {
907 .name = "pci-das4020/12",
908 .device_id = 0x52,
909 .ai_se_chans = 4,
910 .ai_bits = 12,
911 .ai_speed = 50,
912 .ao_bits = 12,
913 .ao_nchan = 2,
914 .ao_scan_speed = 0, /* no hardware pacing on ao */
915 .layout = LAYOUT_4020,
916 .ai_range_table = &ai_ranges_4020,
917 .ao_range_table = &ao_ranges_4020,
918 .ao_range_code = ao_range_code_4020,
919 .ai_fifo = &ai_fifo_4020,
920 .has_8255 = 1,
921 },
922 #if 0
923 {
924 .name = "pci-das6402/16/jr",
925 .device_id = 0 /* XXX, */
926 .ai_se_chans = 64,
927 .ai_bits = 16,
928 .ai_speed = 5000,
929 .ao_nchan = 0,
930 .ao_scan_speed = 10000,
931 .layout = LAYOUT_64XX,
932 .ai_range_table = &ai_ranges_64xx,
933 .ai_fifo = ai_fifo_64xx,
934 .has_8255 = 1,
935 },
936 {
937 .name = "pci-das64/m1/16/jr",
938 .device_id = 0 /* XXX, */
939 .ai_se_chans = 64,
940 .ai_bits = 16,
941 .ai_speed = 1000,
942 .ao_nchan = 0,
943 .ao_scan_speed = 10000,
944 .layout = LAYOUT_64XX,
945 .ai_range_table = &ai_ranges_64xx,
946 .ai_fifo = ai_fifo_64xx,
947 .has_8255 = 1,
948 },
949 {
950 .name = "pci-das64/m2/16/jr",
951 .device_id = 0 /* XXX, */
952 .ai_se_chans = 64,
953 .ai_bits = 16,
954 .ai_speed = 500,
955 .ao_nchan = 0,
956 .ao_scan_speed = 10000,
957 .layout = LAYOUT_64XX,
958 .ai_range_table = &ai_ranges_64xx,
959 .ai_fifo = ai_fifo_64xx,
960 .has_8255 = 1,
961 },
962 {
963 .name = "pci-das64/m3/16/jr",
964 .device_id = 0 /* XXX, */
965 .ai_se_chans = 64,
966 .ai_bits = 16,
967 .ai_speed = 333,
968 .ao_nchan = 0,
969 .ao_scan_speed = 10000,
970 .layout = LAYOUT_64XX,
971 .ai_range_table = &ai_ranges_64xx,
972 .ai_fifo = ai_fifo_64xx,
973 .has_8255 = 1,
974 },
975 {
976 .name = "pci-das64/m1/14",
977 .device_id = 0, /* XXX */
978 .ai_se_chans = 64,
979 .ai_bits = 14,
980 .ai_speed = 1000,
981 .ao_nchan = 2,
982 .ao_scan_speed = 10000,
983 .layout = LAYOUT_64XX,
984 .ai_range_table = &ai_ranges_64xx,
985 .ai_fifo = ai_fifo_64xx,
986 .has_8255 = 1,
987 },
988 {
989 .name = "pci-das64/m2/14",
990 .device_id = 0, /* XXX */
991 .ai_se_chans = 64,
992 .ai_bits = 14,
993 .ai_speed = 500,
994 .ao_nchan = 2,
995 .ao_scan_speed = 10000,
996 .layout = LAYOUT_64XX,
997 .ai_range_table = &ai_ranges_64xx,
998 .ai_fifo = ai_fifo_64xx,
999 .has_8255 = 1,
1000 },
1001 {
1002 .name = "pci-das64/m3/14",
1003 .device_id = 0, /* XXX */
1004 .ai_se_chans = 64,
1005 .ai_bits = 14,
1006 .ai_speed = 333,
1007 .ao_nchan = 2,
1008 .ao_scan_speed = 10000,
1009 .layout = LAYOUT_64XX,
1010 .ai_range_table = &ai_ranges_64xx,
1011 .ai_fifo = ai_fifo_64xx,
1012 .has_8255 = 1,
1013 },
1014 #endif
1015 };
1016
1017 static DEFINE_PCI_DEVICE_TABLE(pcidas64_pci_table) = {
1018 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x001d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1019 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x001e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1020 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0035, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1021 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0036, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1022 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0037, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1023 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0052, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1024 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x005d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1025 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x005e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1026 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x005f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1027 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0061, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1028 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0062, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1029 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0063, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1030 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0064, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1031 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0066, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1032 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0067, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1033 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0068, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1034 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x006f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1035 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0078, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1036 {PCI_VENDOR_ID_COMPUTERBOARDS, 0x0079, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1037 {0}
1038 };
1039
1040 MODULE_DEVICE_TABLE(pci, pcidas64_pci_table);
1041
1042 static inline struct pcidas64_board *board(const struct comedi_device * dev)
1043 {
1044 return (struct pcidas64_board *) dev->board_ptr;
1045 }
1046
1047 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1048 int use_differential)
1049 {
1050 if ((board(dev)->layout == LAYOUT_64XX && !use_differential) ||
1051 (board(dev)->layout == LAYOUT_60XX && use_differential))
1052 return ADC_SE_DIFF_BIT;
1053 else
1054 return 0;
1055 };
1056
1057 struct ext_clock_info {
1058 unsigned int divisor; /* master clock divisor to use for scans with external master clock */
1059 unsigned int chanspec; /* chanspec for master clock input when used as scan begin src */
1060 };
1061
1062 /* this structure is for data unique to this hardware driver. */
1063 struct pcidas64_private {
1064
1065 struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */
1066 /* base addresses (physical) */
1067 resource_size_t plx9080_phys_iobase;
1068 resource_size_t main_phys_iobase;
1069 resource_size_t dio_counter_phys_iobase;
1070 /* base addresses (ioremapped) */
1071 void *plx9080_iobase;
1072 void *main_iobase;
1073 void *dio_counter_iobase;
1074 /* local address (used by dma controller) */
1075 uint32_t local0_iobase;
1076 uint32_t local1_iobase;
1077 volatile unsigned int ai_count; /* number of analog input samples remaining */
1078 uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT]; /* dma buffers for analog input */
1079 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT]; /* physical addresses of ai dma buffers */
1080 struct plx_dma_desc *ai_dma_desc; /* array of ai dma descriptors read by plx9080, allocated to get proper alignment */
1081 dma_addr_t ai_dma_desc_bus_addr; /* physical address of ai dma descriptor array */
1082 volatile unsigned int ai_dma_index; /* index of the ai dma descriptor/buffer that is currently being used */
1083 uint16_t *ao_buffer[AO_DMA_RING_COUNT]; /* dma buffers for analog output */
1084 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT]; /* physical addresses of ao dma buffers */
1085 struct plx_dma_desc *ao_dma_desc;
1086 dma_addr_t ao_dma_desc_bus_addr;
1087 volatile unsigned int ao_dma_index; /* keeps track of buffer where the next ao sample should go */
1088 volatile unsigned long ao_count; /* number of analog output samples remaining */
1089 volatile unsigned int ao_value[2]; /* remember what the analog outputs are set to, to allow readback */
1090 unsigned int hw_revision; /* stc chip hardware revision number */
1091 volatile unsigned int intr_enable_bits; /* last bits sent to INTR_ENABLE_REG register */
1092 volatile uint16_t adc_control1_bits; /* last bits sent to ADC_CONTROL1_REG register */
1093 volatile uint16_t fifo_size_bits; /* last bits sent to FIFO_SIZE_REG register */
1094 volatile uint16_t hw_config_bits; /* last bits sent to HW_CONFIG_REG register */
1095 volatile uint16_t dac_control1_bits;
1096 volatile uint32_t plx_control_bits; /* last bits written to plx9080 control register */
1097 volatile uint32_t plx_intcsr_bits; /* last bits written to plx interrupt control and status register */
1098 volatile int calibration_source; /* index of calibration source readable through ai ch0 */
1099 volatile uint8_t i2c_cal_range_bits; /* bits written to i2c calibration/range register */
1100 volatile unsigned int ext_trig_falling; /* configure digital triggers to trigger on falling edge */
1101 /* states of various devices stored to enable read-back */
1102 unsigned int ad8402_state[2];
1103 unsigned int caldac_state[8];
1104 volatile short ai_cmd_running;
1105 unsigned int ai_fifo_segment_length;
1106 struct ext_clock_info ext_clock;
1107 short ao_bounce_buffer[DAC_FIFO_SIZE];
1108 };
1109
1110
1111 /* inline function that makes it easier to
1112 * access the private structure.
1113 */
1114 static inline struct pcidas64_private *priv(struct comedi_device * dev)
1115 {
1116 return dev->private;
1117 }
1118
1119 /*
1120 * The comedi_driver structure tells the Comedi core module
1121 * which functions to call to configure/deconfigure (attach/detach)
1122 * the board, and also about the kernel module that contains
1123 * the device code.
1124 */
1125 static int attach(struct comedi_device *dev, struct comedi_devconfig *it);
1126 static int detach(struct comedi_device *dev);
1127 static struct comedi_driver driver_cb_pcidas = {
1128 .driver_name = "cb_pcidas64",
1129 .module = THIS_MODULE,
1130 .attach = attach,
1131 .detach = detach,
1132 };
1133
1134 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1135 struct comedi_insn *insn, unsigned int *data);
1136 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1137 struct comedi_insn *insn, unsigned int *data);
1138 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1139 struct comedi_insn *insn, unsigned int *data);
1140 static int ao_readback_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1141 struct comedi_insn *insn, unsigned int *data);
1142 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1143 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1144 struct comedi_cmd *cmd);
1145 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1146 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *subdev,
1147 unsigned int trig_num);
1148 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1149 struct comedi_cmd *cmd);
1150 static irqreturn_t handle_interrupt(int irq, void *d);
1151 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1152 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1153 static int dio_callback(int dir, int port, int data, unsigned long arg);
1154 static int dio_callback_4020(int dir, int port, int data, unsigned long arg);
1155 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
1156 struct comedi_insn *insn, unsigned int *data);
1157 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1158 struct comedi_insn *insn, unsigned int *data);
1159 static int dio_60xx_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1160 struct comedi_insn *insn, unsigned int *data);
1161 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1162 struct comedi_insn *insn, unsigned int *data);
1163 static int calib_read_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1164 struct comedi_insn *insn, unsigned int *data);
1165 static int calib_write_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1166 struct comedi_insn *insn, unsigned int *data);
1167 static int ad8402_read_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1168 struct comedi_insn *insn, unsigned int *data);
1169 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
1170 unsigned int value);
1171 static int ad8402_write_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1172 struct comedi_insn *insn, unsigned int *data);
1173 static int eeprom_read_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1174 struct comedi_insn *insn, unsigned int *data);
1175 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
1176 static unsigned int get_divisor(unsigned int ns, unsigned int flags);
1177 static void i2c_write(struct comedi_device *dev, unsigned int address,
1178 const uint8_t *data, unsigned int length);
1179 static void caldac_write(struct comedi_device *dev, unsigned int channel,
1180 unsigned int value);
1181 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
1182 uint8_t value);
1183 /* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */
1184 static int caldac_i2c_write(struct comedi_device *dev, unsigned int caldac_channel,
1185 unsigned int value);
1186 static void abort_dma(struct comedi_device *dev, unsigned int channel);
1187 static void disable_plx_interrupts(struct comedi_device *dev);
1188 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples);
1189 static unsigned int ai_fifo_size(struct comedi_device *dev);
1190 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1191 unsigned int num_entries);
1192 static void disable_ai_pacing(struct comedi_device *dev);
1193 static void disable_ai_interrupts(struct comedi_device *dev);
1194 static void enable_ai_interrupts(struct comedi_device *dev, const struct comedi_cmd *cmd);
1195 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags);
1196 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd);
1197
1198 COMEDI_PCI_INITCLEANUP(driver_cb_pcidas, pcidas64_pci_table);
1199
1200 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1201 unsigned int range_index)
1202 {
1203 const struct comedi_krange *range =
1204 &board(dev)->ai_range_table->range[range_index];
1205 unsigned int bits = 0;
1206
1207 switch (range->max) {
1208 case 10000000:
1209 bits = 0x000;
1210 break;
1211 case 5000000:
1212 bits = 0x100;
1213 break;
1214 case 2000000:
1215 case 2500000:
1216 bits = 0x200;
1217 break;
1218 case 1000000:
1219 case 1250000:
1220 bits = 0x300;
1221 break;
1222 case 500000:
1223 bits = 0x400;
1224 break;
1225 case 200000:
1226 case 250000:
1227 bits = 0x500;
1228 break;
1229 case 100000:
1230 bits = 0x600;
1231 break;
1232 case 50000:
1233 bits = 0x700;
1234 break;
1235 default:
1236 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1237 break;
1238 }
1239 if (range->min == 0)
1240 bits += 0x900;
1241 return bits;
1242 }
1243
1244 static unsigned int hw_revision(const struct comedi_device *dev,
1245 uint16_t hw_status_bits)
1246 {
1247 if (board(dev)->layout == LAYOUT_4020)
1248 return (hw_status_bits >> 13) & 0x7;
1249
1250 return (hw_status_bits >> 12) & 0xf;
1251 }
1252
1253 static void set_dac_range_bits(struct comedi_device *dev, volatile uint16_t *bits,
1254 unsigned int channel, unsigned int range)
1255 {
1256 unsigned int code = board(dev)->ao_range_code[range];
1257
1258 if (channel > 1)
1259 comedi_error(dev, "bug! bad channel?");
1260 if (code & ~0x3)
1261 comedi_error(dev, "bug! bad range code?");
1262
1263 *bits &= ~(0x3 << (2 * channel));
1264 *bits |= code << (2 * channel);
1265 };
1266
1267 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1268 {
1269 return board->ao_nchan && board->layout != LAYOUT_4020;
1270 }
1271
1272 /* initialize plx9080 chip */
1273 static void init_plx9080(struct comedi_device *dev)
1274 {
1275 uint32_t bits;
1276 void *plx_iobase = priv(dev)->plx9080_iobase;
1277
1278 priv(dev)->plx_control_bits =
1279 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG);
1280
1281 /* plx9080 dump */
1282 DEBUG_PRINT(" plx interrupt status 0x%x\n",
1283 readl(plx_iobase + PLX_INTRCS_REG));
1284 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1285 DEBUG_PRINT(" plx control reg 0x%x\n", priv(dev)->plx_control_bits);
1286 DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1287 readl(plx_iobase + PLX_MARB_REG));
1288 DEBUG_PRINT(" plx region0 reg 0x%x\n",
1289 readl(plx_iobase + PLX_REGION0_REG));
1290 DEBUG_PRINT(" plx region1 reg 0x%x\n",
1291 readl(plx_iobase + PLX_REGION1_REG));
1292
1293 DEBUG_PRINT(" plx revision 0x%x\n",
1294 readl(plx_iobase + PLX_REVISION_REG));
1295 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1296 readl(plx_iobase + PLX_DMA0_MODE_REG));
1297 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1298 readl(plx_iobase + PLX_DMA1_MODE_REG));
1299 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1300 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1301 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1302 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1303 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1304 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1305 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1306 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1307 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1308 readb(plx_iobase + PLX_DMA0_CS_REG));
1309 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1310 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1311 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1312
1313 #ifdef __BIG_ENDIAN
1314 bits = BIGEND_DMA0 | BIGEND_DMA1;
1315 #else
1316 bits = 0;
1317 #endif
1318 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
1319
1320 disable_plx_interrupts(dev);
1321
1322 abort_dma(dev, 0);
1323 abort_dma(dev, 1);
1324
1325 /* configure dma0 mode */
1326 bits = 0;
1327 /* enable ready input, not sure if this is necessary */
1328 bits |= PLX_DMA_EN_READYIN_BIT;
1329 /* enable bterm, not sure if this is necessary */
1330 bits |= PLX_EN_BTERM_BIT;
1331 /* enable dma chaining */
1332 bits |= PLX_EN_CHAIN_BIT;
1333 /* enable interrupt on dma done (probably don't need this, since chain never finishes) */
1334 bits |= PLX_EN_DMA_DONE_INTR_BIT;
1335 /* don't increment local address during transfers (we are transferring from a fixed fifo register) */
1336 bits |= PLX_LOCAL_ADDR_CONST_BIT;
1337 /* route dma interrupt to pci bus */
1338 bits |= PLX_DMA_INTR_PCI_BIT;
1339 /* enable demand mode */
1340 bits |= PLX_DEMAND_MODE_BIT;
1341 /* enable local burst mode */
1342 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1343 /* 4020 uses 32 bit dma */
1344 if (board(dev)->layout == LAYOUT_4020) {
1345 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1346 } else { /* localspace0 bus is 16 bits wide */
1347 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1348 }
1349 writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1350 if (ao_cmd_is_supported(board(dev)))
1351 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1352
1353 /* enable interrupts on plx 9080 */
1354 priv(dev)->plx_intcsr_bits |=
1355 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1356 ICS_DMA0_E | ICS_DMA1_E;
1357 writel(priv(dev)->plx_intcsr_bits,
1358 priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1359 }
1360
1361 /* Allocate and initialize the subdevice structures.
1362 */
1363 static int setup_subdevices(struct comedi_device *dev)
1364 {
1365 struct comedi_subdevice *s;
1366 void *dio_8255_iobase;
1367 int i;
1368
1369 if (alloc_subdevices(dev, 10) < 0)
1370 return -ENOMEM;
1371
1372 s = dev->subdevices + 0;
1373 /* analog input subdevice */
1374 dev->read_subdev = s;
1375 s->type = COMEDI_SUBD_AI;
1376 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
1377 if (board(dev)->layout == LAYOUT_60XX)
1378 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
1379 else if (board(dev)->layout == LAYOUT_64XX)
1380 s->subdev_flags |= SDF_DIFF;
1381 /* XXX Number of inputs in differential mode is ignored */
1382 s->n_chan = board(dev)->ai_se_chans;
1383 s->len_chanlist = 0x2000;
1384 s->maxdata = (1 << board(dev)->ai_bits) - 1;
1385 s->range_table = board(dev)->ai_range_table;
1386 s->insn_read = ai_rinsn;
1387 s->insn_config = ai_config_insn;
1388 s->do_cmd = ai_cmd;
1389 s->do_cmdtest = ai_cmdtest;
1390 s->cancel = ai_cancel;
1391 if (board(dev)->layout == LAYOUT_4020) {
1392 unsigned int i;
1393 uint8_t data;
1394 /* set adc to read from inputs (not internal calibration sources) */
1395 priv(dev)->i2c_cal_range_bits = adc_src_4020_bits(4);
1396 /* set channels to +-5 volt input ranges */
1397 for (i = 0; i < s->n_chan; i++)
1398 priv(dev)->i2c_cal_range_bits |= attenuate_bit(i);
1399 data = priv(dev)->i2c_cal_range_bits;
1400 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
1401 }
1402
1403 /* analog output subdevice */
1404 s = dev->subdevices + 1;
1405 if (board(dev)->ao_nchan) {
1406 s->type = COMEDI_SUBD_AO;
1407 s->subdev_flags =
1408 SDF_READABLE | SDF_WRITABLE | SDF_GROUND |
1409 SDF_CMD_WRITE;
1410 s->n_chan = board(dev)->ao_nchan;
1411 s->maxdata = (1 << board(dev)->ao_bits) - 1;
1412 s->range_table = board(dev)->ao_range_table;
1413 s->insn_read = ao_readback_insn;
1414 s->insn_write = ao_winsn;
1415 if (ao_cmd_is_supported(board(dev))) {
1416 dev->write_subdev = s;
1417 s->do_cmdtest = ao_cmdtest;
1418 s->do_cmd = ao_cmd;
1419 s->len_chanlist = board(dev)->ao_nchan;
1420 s->cancel = ao_cancel;
1421 }
1422 } else {
1423 s->type = COMEDI_SUBD_UNUSED;
1424 }
1425
1426 /* digital input */
1427 s = dev->subdevices + 2;
1428 if (board(dev)->layout == LAYOUT_64XX) {
1429 s->type = COMEDI_SUBD_DI;
1430 s->subdev_flags = SDF_READABLE;
1431 s->n_chan = 4;
1432 s->maxdata = 1;
1433 s->range_table = &range_digital;
1434 s->insn_bits = di_rbits;
1435 } else
1436 s->type = COMEDI_SUBD_UNUSED;
1437
1438 /* digital output */
1439 if (board(dev)->layout == LAYOUT_64XX) {
1440 s = dev->subdevices + 3;
1441 s->type = COMEDI_SUBD_DO;
1442 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1443 s->n_chan = 4;
1444 s->maxdata = 1;
1445 s->range_table = &range_digital;
1446 s->insn_bits = do_wbits;
1447 } else
1448 s->type = COMEDI_SUBD_UNUSED;
1449
1450 /* 8255 */
1451 s = dev->subdevices + 4;
1452 if (board(dev)->has_8255) {
1453 if (board(dev)->layout == LAYOUT_4020) {
1454 dio_8255_iobase =
1455 priv(dev)->main_iobase + I8255_4020_REG;
1456 subdev_8255_init(dev, s, dio_callback_4020,
1457 (unsigned long)dio_8255_iobase);
1458 } else {
1459 dio_8255_iobase =
1460 priv(dev)->dio_counter_iobase + DIO_8255_OFFSET;
1461 subdev_8255_init(dev, s, dio_callback,
1462 (unsigned long)dio_8255_iobase);
1463 }
1464 } else
1465 s->type = COMEDI_SUBD_UNUSED;
1466
1467 /* 8 channel dio for 60xx */
1468 s = dev->subdevices + 5;
1469 if (board(dev)->layout == LAYOUT_60XX) {
1470 s->type = COMEDI_SUBD_DIO;
1471 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1472 s->n_chan = 8;
1473 s->maxdata = 1;
1474 s->range_table = &range_digital;
1475 s->insn_config = dio_60xx_config_insn;
1476 s->insn_bits = dio_60xx_wbits;
1477 } else
1478 s->type = COMEDI_SUBD_UNUSED;
1479
1480 /* caldac */
1481 s = dev->subdevices + 6;
1482 s->type = COMEDI_SUBD_CALIB;
1483 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1484 s->n_chan = 8;
1485 if (board(dev)->layout == LAYOUT_4020)
1486 s->maxdata = 0xfff;
1487 else
1488 s->maxdata = 0xff;
1489 s->insn_read = calib_read_insn;
1490 s->insn_write = calib_write_insn;
1491 for (i = 0; i < s->n_chan; i++)
1492 caldac_write(dev, i, s->maxdata / 2);
1493
1494 /* 2 channel ad8402 potentiometer */
1495 s = dev->subdevices + 7;
1496 if (board(dev)->layout == LAYOUT_64XX) {
1497 s->type = COMEDI_SUBD_CALIB;
1498 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1499 s->n_chan = 2;
1500 s->insn_read = ad8402_read_insn;
1501 s->insn_write = ad8402_write_insn;
1502 s->maxdata = 0xff;
1503 for (i = 0; i < s->n_chan; i++)
1504 ad8402_write(dev, i, s->maxdata / 2);
1505 } else
1506 s->type = COMEDI_SUBD_UNUSED;
1507
1508 /* serial EEPROM, if present */
1509 s = dev->subdevices + 8;
1510 if (readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
1511 s->type = COMEDI_SUBD_MEMORY;
1512 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
1513 s->n_chan = 128;
1514 s->maxdata = 0xffff;
1515 s->insn_read = eeprom_read_insn;
1516 } else
1517 s->type = COMEDI_SUBD_UNUSED;
1518
1519 /* user counter subd XXX */
1520 s = dev->subdevices + 9;
1521 s->type = COMEDI_SUBD_UNUSED;
1522
1523 return 0;
1524 }
1525
1526 static void disable_plx_interrupts(struct comedi_device *dev)
1527 {
1528 priv(dev)->plx_intcsr_bits = 0;
1529 writel(priv(dev)->plx_intcsr_bits,
1530 priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1531 }
1532
1533 static void init_stc_registers(struct comedi_device *dev)
1534 {
1535 uint16_t bits;
1536 unsigned long flags;
1537
1538 spin_lock_irqsave(&dev->spinlock, flags);
1539
1540 /* bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */
1541 if (1)
1542 priv(dev)->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1543 writew(priv(dev)->adc_control1_bits,
1544 priv(dev)->main_iobase + ADC_CONTROL1_REG);
1545
1546 /* 6402/16 manual says this register must be initialized to 0xff? */
1547 writew(0xff, priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1548
1549 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1550 if (board(dev)->layout == LAYOUT_4020)
1551 bits |= INTERNAL_CLOCK_4020_BITS;
1552 priv(dev)->hw_config_bits |= bits;
1553 writew(priv(dev)->hw_config_bits,
1554 priv(dev)->main_iobase + HW_CONFIG_REG);
1555
1556 writew(0, priv(dev)->main_iobase + DAQ_SYNC_REG);
1557 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1558
1559 spin_unlock_irqrestore(&dev->spinlock, flags);
1560
1561 /* set fifos to maximum size */
1562 priv(dev)->fifo_size_bits |= DAC_FIFO_BITS;
1563 set_ai_fifo_segment_length(dev,
1564 board(dev)->ai_fifo->max_segment_length);
1565
1566 priv(dev)->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1567 priv(dev)->intr_enable_bits = /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1568 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1569 writew(priv(dev)->intr_enable_bits,
1570 priv(dev)->main_iobase + INTR_ENABLE_REG);
1571
1572 disable_ai_pacing(dev);
1573 };
1574
1575 int alloc_and_init_dma_members(struct comedi_device *dev)
1576 {
1577 int i;
1578
1579 /* alocate pci dma buffers */
1580 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1581 priv(dev)->ai_buffer[i] =
1582 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
1583 &priv(dev)->ai_buffer_bus_addr[i]);
1584 if (priv(dev)->ai_buffer[i] == NULL) {
1585 return -ENOMEM;
1586 }
1587 }
1588 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1589 if (ao_cmd_is_supported(board(dev))) {
1590 priv(dev)->ao_buffer[i] =
1591 pci_alloc_consistent(priv(dev)->hw_dev,
1592 DMA_BUFFER_SIZE,
1593 &priv(dev)->ao_buffer_bus_addr[i]);
1594 if (priv(dev)->ao_buffer[i] == NULL) {
1595 return -ENOMEM;
1596 }
1597 }
1598 }
1599 /* allocate dma descriptors */
1600 priv(dev)->ai_dma_desc =
1601 pci_alloc_consistent(priv(dev)->hw_dev,
1602 sizeof(struct plx_dma_desc) * ai_dma_ring_count(board(dev)),
1603 &priv(dev)->ai_dma_desc_bus_addr);
1604 if (priv(dev)->ai_dma_desc == NULL) {
1605 return -ENOMEM;
1606 }
1607 DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n",
1608 priv(dev)->ai_dma_desc_bus_addr);
1609 if (ao_cmd_is_supported(board(dev))) {
1610 priv(dev)->ao_dma_desc =
1611 pci_alloc_consistent(priv(dev)->hw_dev,
1612 sizeof(struct plx_dma_desc) * AO_DMA_RING_COUNT,
1613 &priv(dev)->ao_dma_desc_bus_addr);
1614 if (priv(dev)->ao_dma_desc == NULL) {
1615 return -ENOMEM;
1616 }
1617 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n",
1618 priv(dev)->ao_dma_desc_bus_addr);
1619 }
1620 /* initialize dma descriptors */
1621 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1622 priv(dev)->ai_dma_desc[i].pci_start_addr =
1623 cpu_to_le32(priv(dev)->ai_buffer_bus_addr[i]);
1624 if (board(dev)->layout == LAYOUT_4020)
1625 priv(dev)->ai_dma_desc[i].local_start_addr =
1626 cpu_to_le32(priv(dev)->local1_iobase +
1627 ADC_FIFO_REG);
1628 else
1629 priv(dev)->ai_dma_desc[i].local_start_addr =
1630 cpu_to_le32(priv(dev)->local0_iobase +
1631 ADC_FIFO_REG);
1632 priv(dev)->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1633 priv(dev)->ai_dma_desc[i].next =
1634 cpu_to_le32((priv(dev)->ai_dma_desc_bus_addr + ((i +
1635 1) %
1636 ai_dma_ring_count(board(dev))) *
1637 sizeof(priv(dev)->
1638 ai_dma_desc[0])) | PLX_DESC_IN_PCI_BIT |
1639 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI);
1640 }
1641 if (ao_cmd_is_supported(board(dev))) {
1642 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1643 priv(dev)->ao_dma_desc[i].pci_start_addr =
1644 cpu_to_le32(priv(dev)->ao_buffer_bus_addr[i]);
1645 priv(dev)->ao_dma_desc[i].local_start_addr =
1646 cpu_to_le32(priv(dev)->local0_iobase +
1647 DAC_FIFO_REG);
1648 priv(dev)->ao_dma_desc[i].transfer_size =
1649 cpu_to_le32(0);
1650 priv(dev)->ao_dma_desc[i].next =
1651 cpu_to_le32((priv(dev)->ao_dma_desc_bus_addr +
1652 ((i + 1) % (AO_DMA_RING_COUNT)) *
1653 sizeof(priv(dev)->
1654 ao_dma_desc[0])) |
1655 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
1656 }
1657 }
1658 return 0;
1659 }
1660
1661 static inline void warn_external_queue(struct comedi_device *dev)
1662 {
1663 comedi_error(dev,
1664 "AO command and AI external channel queue cannot be used simultaneously.");
1665 comedi_error(dev,
1666 "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1667 }
1668
1669 /*
1670 * Attach is called by the Comedi core to configure the driver
1671 * for a particular board.
1672 */
1673 static int attach(struct comedi_device *dev, struct comedi_devconfig *it)
1674 {
1675 struct pci_dev *pcidev;
1676 int index;
1677 uint32_t local_range, local_decode;
1678 int retval;
1679
1680 printk("comedi%d: cb_pcidas64\n", dev->minor);
1681
1682 /*
1683 * Allocate the private structure area.
1684 */
1685 if (alloc_private(dev, sizeof(struct pcidas64_private)) < 0)
1686 return -ENOMEM;
1687
1688 /*
1689 * Probe the device to determine what device in the series it is.
1690 */
1691
1692 for (pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, NULL);
1693 pcidev != NULL;
1694 pcidev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pcidev)) {
1695 /* is it not a computer boards card? */
1696 if (pcidev->vendor != PCI_VENDOR_ID_COMPUTERBOARDS)
1697 continue;
1698 /* loop through cards supported by this driver */
1699 for (index = 0; index < ARRAY_SIZE(pcidas64_boards); index++) {
1700 if (pcidas64_boards[index].device_id != pcidev->device)
1701 continue;
1702 /* was a particular bus/slot requested? */
1703 if (it->options[0] || it->options[1]) {
1704 /* are we on the wrong bus/slot? */
1705 if (pcidev->bus->number != it->options[0] ||
1706 PCI_SLOT(pcidev->devfn) !=
1707 it->options[1]) {
1708 continue;
1709 }
1710 }
1711 priv(dev)->hw_dev = pcidev;
1712 dev->board_ptr = pcidas64_boards + index;
1713 break;
1714 }
1715 if (dev->board_ptr)
1716 break;
1717 }
1718
1719 if (dev->board_ptr == NULL) {
1720 printk("No supported ComputerBoards/MeasurementComputing card found\n");
1721 return -EIO;
1722 }
1723
1724 printk("Found %s on bus %i, slot %i\n", board(dev)->name,
1725 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
1726
1727 if (comedi_pci_enable(pcidev, driver_cb_pcidas.driver_name)) {
1728 printk(KERN_WARNING
1729 " failed to enable PCI device and request regions\n");
1730 return -EIO;
1731 }
1732 pci_set_master(pcidev);
1733
1734 /* Initialize dev->board_name */
1735 dev->board_name = board(dev)->name;
1736
1737 priv(dev)->plx9080_phys_iobase =
1738 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
1739 priv(dev)->main_phys_iobase =
1740 pci_resource_start(pcidev, MAIN_BADDRINDEX);
1741 priv(dev)->dio_counter_phys_iobase =
1742 pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
1743
1744 /* remap, won't work with 2.0 kernels but who cares */
1745 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
1746 pci_resource_len(pcidev, PLX9080_BADDRINDEX));
1747 priv(dev)->main_iobase = ioremap(priv(dev)->main_phys_iobase,
1748 pci_resource_len(pcidev, MAIN_BADDRINDEX));
1749 priv(dev)->dio_counter_iobase =
1750 ioremap(priv(dev)->dio_counter_phys_iobase,
1751 pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
1752
1753 if (!priv(dev)->plx9080_iobase || !priv(dev)->main_iobase
1754 || !priv(dev)->dio_counter_iobase) {
1755 printk(" failed to remap io memory\n");
1756 return -ENOMEM;
1757 }
1758
1759 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
1760 DEBUG_PRINT(" main remapped to 0x%p\n", priv(dev)->main_iobase);
1761 DEBUG_PRINT(" diocounter remapped to 0x%p\n",
1762 priv(dev)->dio_counter_iobase);
1763
1764 /* figure out what local addresses are */
1765 local_range =
1766 readl(priv(dev)->plx9080_iobase +
1767 PLX_LAS0RNG_REG) & LRNG_MEM_MASK;
1768 local_decode =
1769 readl(priv(dev)->plx9080_iobase +
1770 PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK;
1771 priv(dev)->local0_iobase =
1772 ((uint32_t) priv(dev)->
1773 main_phys_iobase & ~local_range) | local_decode;
1774 local_range =
1775 readl(priv(dev)->plx9080_iobase +
1776 PLX_LAS1RNG_REG) & LRNG_MEM_MASK;
1777 local_decode =
1778 readl(priv(dev)->plx9080_iobase +
1779 PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK;
1780 priv(dev)->local1_iobase =
1781 ((uint32_t) priv(dev)->
1782 dio_counter_phys_iobase & ~local_range) | local_decode;
1783
1784 DEBUG_PRINT(" local 0 io addr 0x%x\n", priv(dev)->local0_iobase);
1785 DEBUG_PRINT(" local 1 io addr 0x%x\n", priv(dev)->local1_iobase);
1786
1787 retval = alloc_and_init_dma_members(dev);
1788 if (retval < 0)
1789 return retval;
1790
1791 priv(dev)->hw_revision =
1792 hw_revision(dev, readw(priv(dev)->main_iobase + HW_STATUS_REG));
1793 printk(" stc hardware revision %i\n", priv(dev)->hw_revision);
1794 init_plx9080(dev);
1795 init_stc_registers(dev);
1796 /* get irq */
1797 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
1798 "cb_pcidas64", dev)) {
1799 printk(" unable to allocate irq %u\n", pcidev->irq);
1800 return -EINVAL;
1801 }
1802 dev->irq = pcidev->irq;
1803 printk(" irq %u\n", dev->irq);
1804
1805 retval = setup_subdevices(dev);
1806 if (retval < 0) {
1807 return retval;
1808 }
1809
1810 return 0;
1811 }
1812
1813 /*
1814 * _detach is called to deconfigure a device. It should deallocate
1815 * resources.
1816 * This function is also called when _attach() fails, so it should be
1817 * careful not to release resources that were not necessarily
1818 * allocated by _attach(). dev->private and dev->subdevices are
1819 * deallocated automatically by the core.
1820 */
1821 static int detach(struct comedi_device *dev)
1822 {
1823 unsigned int i;
1824
1825 printk("comedi%d: cb_pcidas: remove\n", dev->minor);
1826
1827 if (dev->irq)
1828 free_irq(dev->irq, dev);
1829 if (priv(dev)) {
1830 if (priv(dev)->hw_dev) {
1831 if (priv(dev)->plx9080_iobase) {
1832 disable_plx_interrupts(dev);
1833 iounmap((void *)priv(dev)->plx9080_iobase);
1834 }
1835 if (priv(dev)->main_iobase)
1836 iounmap((void *)priv(dev)->main_iobase);
1837 if (priv(dev)->dio_counter_iobase)
1838 iounmap((void *)priv(dev)->dio_counter_iobase);
1839 /* free pci dma buffers */
1840 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1841 if (priv(dev)->ai_buffer[i])
1842 pci_free_consistent(priv(dev)->hw_dev,
1843 DMA_BUFFER_SIZE,
1844 priv(dev)->ai_buffer[i],
1845 priv(dev)->
1846 ai_buffer_bus_addr[i]);
1847 }
1848 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1849 if (priv(dev)->ao_buffer[i])
1850 pci_free_consistent(priv(dev)->hw_dev,
1851 DMA_BUFFER_SIZE,
1852 priv(dev)->ao_buffer[i],
1853 priv(dev)->
1854 ao_buffer_bus_addr[i]);
1855 }
1856 /* free dma descriptors */
1857 if (priv(dev)->ai_dma_desc)
1858 pci_free_consistent(priv(dev)->hw_dev,
1859 sizeof(struct plx_dma_desc) *
1860 ai_dma_ring_count(board(dev)),
1861 priv(dev)->ai_dma_desc,
1862 priv(dev)->ai_dma_desc_bus_addr);
1863 if (priv(dev)->ao_dma_desc)
1864 pci_free_consistent(priv(dev)->hw_dev,
1865 sizeof(struct plx_dma_desc) *
1866 AO_DMA_RING_COUNT,
1867 priv(dev)->ao_dma_desc,
1868 priv(dev)->ao_dma_desc_bus_addr);
1869 if (priv(dev)->main_phys_iobase) {
1870 comedi_pci_disable(priv(dev)->hw_dev);
1871 }
1872 pci_dev_put(priv(dev)->hw_dev);
1873 }
1874 }
1875 if (dev->subdevices)
1876 subdev_8255_cleanup(dev, dev->subdevices + 4);
1877
1878 return 0;
1879 }
1880
1881 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1882 struct comedi_insn *insn, unsigned int *data)
1883 {
1884 unsigned int bits = 0, n, i;
1885 unsigned int channel, range, aref;
1886 unsigned long flags;
1887 static const int timeout = 100;
1888
1889 DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1890 channel = CR_CHAN(insn->chanspec);
1891 range = CR_RANGE(insn->chanspec);
1892 aref = CR_AREF(insn->chanspec);
1893
1894 /* disable card's analog input interrupt sources and pacing */
1895 /* 4020 generates dac done interrupts even though they are disabled */
1896 disable_ai_pacing(dev);
1897
1898 spin_lock_irqsave(&dev->spinlock, flags);
1899 if (insn->chanspec & CR_ALT_FILTER)
1900 priv(dev)->adc_control1_bits |= ADC_DITHER_BIT;
1901 else
1902 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
1903 writew(priv(dev)->adc_control1_bits,
1904 priv(dev)->main_iobase + ADC_CONTROL1_REG);
1905 spin_unlock_irqrestore(&dev->spinlock, flags);
1906
1907 if (board(dev)->layout != LAYOUT_4020) {
1908 /* use internal queue */
1909 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
1910 writew(priv(dev)->hw_config_bits,
1911 priv(dev)->main_iobase + HW_CONFIG_REG);
1912
1913 /* ALT_SOURCE is internal calibration reference */
1914 if (insn->chanspec & CR_ALT_SOURCE) {
1915 unsigned int cal_en_bit;
1916
1917 DEBUG_PRINT("reading calibration source\n");
1918 if (board(dev)->layout == LAYOUT_60XX)
1919 cal_en_bit = CAL_EN_60XX_BIT;
1920 else
1921 cal_en_bit = CAL_EN_64XX_BIT;
1922 /* select internal reference source to connect to channel 0 */
1923 writew(cal_en_bit | adc_src_bits(priv(dev)->
1924 calibration_source),
1925 priv(dev)->main_iobase + CALIBRATION_REG);
1926 } else {
1927 /* make sure internal calibration source is turned off */
1928 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1929 }
1930 /* load internal queue */
1931 bits = 0;
1932 /* set gain */
1933 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1934 /* set single-ended / differential */
1935 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1936 if (aref == AREF_COMMON)
1937 bits |= ADC_COMMON_BIT;
1938 bits |= adc_chan_bits(channel);
1939 /* set stop channel */
1940 writew(adc_chan_bits(channel),
1941 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
1942 /* set start channel, and rest of settings */
1943 writew(bits, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
1944 } else {
1945 uint8_t old_cal_range_bits = priv(dev)->i2c_cal_range_bits;
1946
1947 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1948 if (insn->chanspec & CR_ALT_SOURCE) {
1949 DEBUG_PRINT("reading calibration source\n");
1950 priv(dev)->i2c_cal_range_bits |=
1951 adc_src_4020_bits(priv(dev)->
1952 calibration_source);
1953 } else { /* select BNC inputs */
1954 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
1955 }
1956 /* select range */
1957 if (range == 0)
1958 priv(dev)->i2c_cal_range_bits |= attenuate_bit(channel);
1959 else
1960 priv(dev)->i2c_cal_range_bits &=
1961 ~attenuate_bit(channel);
1962 /* update calibration/range i2c register only if necessary, as it is very slow */
1963 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
1964 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
1965 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1966 sizeof(i2c_data));
1967 }
1968
1969 /* 4020 manual asks that sample interval register to be set before writing to convert register.
1970 * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */
1971 writew(0,
1972 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1973 writew(2,
1974 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1975 }
1976
1977 for (n = 0; n < insn->n; n++) {
1978
1979 /* clear adc buffer (inside loop for 4020 sake) */
1980 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
1981
1982 /* trigger conversion, bits sent only matter for 4020 */
1983 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1984 priv(dev)->main_iobase + ADC_CONVERT_REG);
1985
1986 /* wait for data */
1987 for (i = 0; i < timeout; i++) {
1988 bits = readw(priv(dev)->main_iobase + HW_STATUS_REG);
1989 DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
1990 if (board(dev)->layout == LAYOUT_4020) {
1991 if (readw(priv(dev)->main_iobase +
1992 ADC_WRITE_PNTR_REG))
1993 break;
1994 } else {
1995 if (pipe_full_bits(bits))
1996 break;
1997 }
1998 udelay(1);
1999 }
2000 DEBUG_PRINT(" looped %i times waiting for data\n", i);
2001 if (i == timeout) {
2002 comedi_error(dev, " analog input read insn timed out");
2003 printk(" status 0x%x\n", bits);
2004 return -ETIME;
2005 }
2006 if (board(dev)->layout == LAYOUT_4020)
2007 data[n] =
2008 readl(priv(dev)->dio_counter_iobase +
2009 ADC_FIFO_REG) & 0xffff;
2010 else
2011 data[n] =
2012 readw(priv(dev)->main_iobase + PIPE1_READ_REG);
2013 }
2014
2015 return n;
2016 }
2017
2018 static int ai_config_calibration_source(struct comedi_device *dev, unsigned int *data)
2019 {
2020 unsigned int source = data[1];
2021 int num_calibration_sources;
2022
2023 if (board(dev)->layout == LAYOUT_60XX)
2024 num_calibration_sources = 16;
2025 else
2026 num_calibration_sources = 8;
2027 if (source >= num_calibration_sources) {
2028 printk("invalid calibration source: %i\n", source);
2029 return -EINVAL;
2030 }
2031
2032 DEBUG_PRINT("setting calibration source to %i\n", source);
2033 priv(dev)->calibration_source = source;
2034
2035 return 2;
2036 }
2037
2038 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
2039 {
2040 int fifo_size;
2041 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
2042 unsigned int block_size, requested_block_size;
2043 int retval;
2044
2045 requested_block_size = data[1];
2046
2047 if (requested_block_size) {
2048 fifo_size =
2049 requested_block_size * fifo->num_segments /
2050 bytes_in_sample;
2051
2052 retval = set_ai_fifo_size(dev, fifo_size);
2053 if (retval < 0)
2054 return retval;
2055
2056 }
2057
2058 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
2059
2060 data[1] = block_size;
2061
2062 return 2;
2063 }
2064
2065 static int ai_config_master_clock_4020(struct comedi_device *dev, unsigned int *data)
2066 {
2067 unsigned int divisor = data[4];
2068 int retval = 0;
2069
2070 if (divisor < 2) {
2071 divisor = 2;
2072 retval = -EAGAIN;
2073 }
2074
2075 switch (data[1]) {
2076 case COMEDI_EV_SCAN_BEGIN:
2077 priv(dev)->ext_clock.divisor = divisor;
2078 priv(dev)->ext_clock.chanspec = data[2];
2079 break;
2080 default:
2081 return -EINVAL;
2082 break;
2083 }
2084
2085 data[4] = divisor;
2086
2087 return retval ? retval : 5;
2088 }
2089
2090 /* XXX could add support for 60xx series */
2091 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
2092 {
2093
2094 switch (board(dev)->layout) {
2095 case LAYOUT_4020:
2096 return ai_config_master_clock_4020(dev, data);
2097 break;
2098 default:
2099 return -EINVAL;
2100 break;
2101 }
2102
2103 return -EINVAL;
2104 }
2105
2106 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
2107 struct comedi_insn *insn, unsigned int *data)
2108 {
2109 int id = data[0];
2110
2111 switch (id) {
2112 case INSN_CONFIG_ALT_SOURCE:
2113 return ai_config_calibration_source(dev, data);
2114 break;
2115 case INSN_CONFIG_BLOCK_SIZE:
2116 return ai_config_block_size(dev, data);
2117 break;
2118 case INSN_CONFIG_TIMER_1:
2119 return ai_config_master_clock(dev, data);
2120 break;
2121 default:
2122 return -EINVAL;
2123 break;
2124 }
2125 return -EINVAL;
2126 }
2127
2128 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2129 struct comedi_cmd *cmd)
2130 {
2131 int err = 0;
2132 int tmp;
2133 unsigned int tmp_arg, tmp_arg2;
2134 int i;
2135 int aref;
2136 unsigned int triggers;
2137
2138 /* step 1: make sure trigger sources are trivially valid */
2139
2140 tmp = cmd->start_src;
2141 cmd->start_src &= TRIG_NOW | TRIG_EXT;
2142 if (!cmd->start_src || tmp != cmd->start_src)
2143 err++;
2144
2145 tmp = cmd->scan_begin_src;
2146 triggers = TRIG_TIMER;
2147 if (board(dev)->layout == LAYOUT_4020)
2148 triggers |= TRIG_OTHER;
2149 else
2150 triggers |= TRIG_FOLLOW;
2151 cmd->scan_begin_src &= triggers;
2152 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2153 err++;
2154
2155 tmp = cmd->convert_src;
2156 triggers = TRIG_TIMER;
2157 if (board(dev)->layout == LAYOUT_4020)
2158 triggers |= TRIG_NOW;
2159 else
2160 triggers |= TRIG_EXT;
2161 cmd->convert_src &= triggers;
2162 if (!cmd->convert_src || tmp != cmd->convert_src)
2163 err++;
2164
2165 tmp = cmd->scan_end_src;
2166 cmd->scan_end_src &= TRIG_COUNT;
2167 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2168 err++;
2169
2170 tmp = cmd->stop_src;
2171 cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE;
2172 if (!cmd->stop_src || tmp != cmd->stop_src)
2173 err++;
2174
2175 if (err)
2176 return 1;
2177
2178 /* step 2: make sure trigger sources are unique and mutually compatible */
2179
2180 /* uniqueness check */
2181 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
2182 err++;
2183 if (cmd->scan_begin_src != TRIG_TIMER &&
2184 cmd->scan_begin_src != TRIG_OTHER &&
2185 cmd->scan_begin_src != TRIG_FOLLOW)
2186 err++;
2187 if (cmd->convert_src != TRIG_TIMER &&
2188 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2189 err++;
2190 if (cmd->stop_src != TRIG_COUNT &&
2191 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2192 err++;
2193
2194 /* compatibility check */
2195 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2196 err++;
2197 if (cmd->stop_src != TRIG_COUNT &&
2198 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2199 err++;
2200
2201 if (err)
2202 return 2;
2203
2204 /* step 3: make sure arguments are trivially compatible */
2205
2206 if (cmd->convert_src == TRIG_TIMER) {
2207 if (board(dev)->layout == LAYOUT_4020) {
2208 if (cmd->convert_arg) {
2209 cmd->convert_arg = 0;
2210 err++;
2211 }
2212 } else {
2213 if (cmd->convert_arg < board(dev)->ai_speed) {
2214 cmd->convert_arg = board(dev)->ai_speed;
2215 err++;
2216 }
2217 if (cmd->scan_begin_src == TRIG_TIMER) {
2218 /* if scans are timed faster than conversion rate allows */
2219 if (cmd->convert_arg * cmd->chanlist_len >
2220 cmd->scan_begin_arg) {
2221 cmd->scan_begin_arg =
2222 cmd->convert_arg *
2223 cmd->chanlist_len;
2224 err++;
2225 }
2226 }
2227 }
2228 }
2229
2230 if (!cmd->chanlist_len) {
2231 cmd->chanlist_len = 1;
2232 err++;
2233 }
2234 if (cmd->scan_end_arg != cmd->chanlist_len) {
2235 cmd->scan_end_arg = cmd->chanlist_len;
2236 err++;
2237 }
2238
2239 switch (cmd->stop_src) {
2240 case TRIG_EXT:
2241 break;
2242 case TRIG_COUNT:
2243 if (!cmd->stop_arg) {
2244 cmd->stop_arg = 1;
2245 err++;
2246 }
2247 break;
2248 case TRIG_NONE:
2249 if (cmd->stop_arg != 0) {
2250 cmd->stop_arg = 0;
2251 err++;
2252 }
2253 break;
2254 default:
2255 break;
2256 }
2257
2258 if (err)
2259 return 3;
2260
2261 /* step 4: fix up any arguments */
2262
2263 if (cmd->convert_src == TRIG_TIMER) {
2264 tmp_arg = cmd->convert_arg;
2265 tmp_arg2 = cmd->scan_begin_arg;
2266 check_adc_timing(dev, cmd);
2267 if (tmp_arg != cmd->convert_arg)
2268 err++;
2269 if (tmp_arg2 != cmd->scan_begin_arg)
2270 err++;
2271 }
2272
2273 if (err)
2274 return 4;
2275
2276 /* make sure user is doesn't change analog reference mid chanlist */
2277 if (cmd->chanlist) {
2278 aref = CR_AREF(cmd->chanlist[0]);
2279 for (i = 1; i < cmd->chanlist_len; i++) {
2280 if (aref != CR_AREF(cmd->chanlist[i])) {
2281 comedi_error(dev,
2282 "all elements in chanlist must use the same analog reference");
2283 err++;
2284 break;
2285 }
2286 }
2287 /* check 4020 chanlist */
2288 if (board(dev)->layout == LAYOUT_4020) {
2289 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2290 for (i = 1; i < cmd->chanlist_len; i++) {
2291 if (CR_CHAN(cmd->chanlist[i]) !=
2292 first_channel + i) {
2293 comedi_error(dev,
2294 "chanlist must use consecutive channels");
2295 err++;
2296 break;
2297 }
2298 }
2299 if (cmd->chanlist_len == 3) {
2300 comedi_error(dev,
2301 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2302 err++;
2303 }
2304 }
2305 }
2306
2307 if (err)
2308 return 5;
2309
2310 return 0;
2311 }
2312
2313 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2314 {
2315 /* disable for now until I work out a race */
2316 return 0;
2317
2318 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2319 return 1;
2320 else
2321 return 0;
2322 }
2323
2324 static void setup_sample_counters(struct comedi_device *dev, struct comedi_cmd *cmd)
2325 {
2326 if (cmd->stop_src == TRIG_COUNT) {
2327 /* set software count */
2328 priv(dev)->ai_count = cmd->stop_arg * cmd->chanlist_len;
2329 }
2330 /* load hardware conversion counter */
2331 if (use_hw_sample_counter(cmd)) {
2332 writew(cmd->stop_arg & 0xffff,
2333 priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2334 writew((cmd->stop_arg >> 16) & 0xff,
2335 priv(dev)->main_iobase + ADC_COUNT_UPPER_REG);
2336 } else {
2337 writew(1, priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2338 }
2339 }
2340
2341 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2342 {
2343 unsigned int num_samples;
2344
2345 num_samples =
2346 priv(dev)->ai_fifo_segment_length *
2347 board(dev)->ai_fifo->sample_packing_ratio;
2348 if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2349 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2350
2351 return num_samples;
2352 }
2353
2354 static void disable_ai_pacing(struct comedi_device *dev)
2355 {
2356 unsigned long flags;
2357
2358 disable_ai_interrupts(dev);
2359
2360 spin_lock_irqsave(&dev->spinlock, flags);
2361 priv(dev)->adc_control1_bits &= ~ADC_SW_GATE_BIT;
2362 writew(priv(dev)->adc_control1_bits,
2363 priv(dev)->main_iobase + ADC_CONTROL1_REG);
2364 spin_unlock_irqrestore(&dev->spinlock, flags);
2365
2366 /* disable pacing, triggering, etc */
2367 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
2368 priv(dev)->main_iobase + ADC_CONTROL0_REG);
2369 }
2370
2371 static void disable_ai_interrupts(struct comedi_device *dev)
2372 {
2373 unsigned long flags;
2374
2375 spin_lock_irqsave(&dev->spinlock, flags);
2376 priv(dev)->intr_enable_bits &=
2377 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
2378 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
2379 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
2380 writew(priv(dev)->intr_enable_bits,
2381 priv(dev)->main_iobase + INTR_ENABLE_REG);
2382 spin_unlock_irqrestore(&dev->spinlock, flags);
2383
2384 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2385 }
2386
2387 static void enable_ai_interrupts(struct comedi_device *dev, const struct comedi_cmd *cmd)
2388 {
2389 uint32_t bits;
2390 unsigned long flags;
2391
2392 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
2393 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
2394 /* Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */
2395 if (cmd->flags & TRIG_WAKE_EOS) {
2396 /* 4020 doesn't support pio transfers except for fifo dregs */
2397 if (board(dev)->layout != LAYOUT_4020)
2398 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
2399 }
2400 spin_lock_irqsave(&dev->spinlock, flags);
2401 priv(dev)->intr_enable_bits |= bits;
2402 writew(priv(dev)->intr_enable_bits,
2403 priv(dev)->main_iobase + INTR_ENABLE_REG);
2404 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2405 spin_unlock_irqrestore(&dev->spinlock, flags);
2406 }
2407
2408 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2409 const struct comedi_cmd *cmd)
2410 {
2411 /* supposed to load counter with desired divisor minus 3 */
2412 return cmd->convert_arg / TIMER_BASE - 3;
2413 }
2414
2415 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev, struct comedi_cmd *cmd)
2416 {
2417 uint32_t count;
2418 /* figure out how long we need to delay at end of scan */
2419 switch (cmd->scan_begin_src) {
2420 case TRIG_TIMER:
2421 count = (cmd->scan_begin_arg -
2422 (cmd->convert_arg * (cmd->chanlist_len - 1)))
2423 / TIMER_BASE;
2424 break;
2425 case TRIG_FOLLOW:
2426 count = cmd->convert_arg / TIMER_BASE;
2427 break;
2428 default:
2429 return 0;
2430 break;
2431 }
2432 return count - 3;
2433 }
2434
2435 static uint32_t ai_convert_counter_4020(struct comedi_device *dev, struct comedi_cmd *cmd)
2436 {
2437 unsigned int divisor;
2438
2439 switch (cmd->scan_begin_src) {
2440 case TRIG_TIMER:
2441 divisor = cmd->scan_begin_arg / TIMER_BASE;
2442 break;
2443 case TRIG_OTHER:
2444 divisor = priv(dev)->ext_clock.divisor;
2445 break;
2446 default: /* should never happen */
2447 comedi_error(dev, "bug! failed to set ai pacing!");
2448 divisor = 1000;
2449 break;
2450 }
2451
2452 /* supposed to load counter with desired divisor minus 2 for 4020 */
2453 return divisor - 2;
2454 }
2455
2456 static void select_master_clock_4020(struct comedi_device *dev,
2457 const struct comedi_cmd *cmd)
2458 {
2459 /* select internal/external master clock */
2460 priv(dev)->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2461 if (cmd->scan_begin_src == TRIG_OTHER) {
2462 int chanspec = priv(dev)->ext_clock.chanspec;
2463
2464 if (CR_CHAN(chanspec))
2465 priv(dev)->hw_config_bits |= BNC_CLOCK_4020_BITS;
2466 else
2467 priv(dev)->hw_config_bits |= EXT_CLOCK_4020_BITS;
2468 } else {
2469 priv(dev)->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2470 }
2471 writew(priv(dev)->hw_config_bits,
2472 priv(dev)->main_iobase + HW_CONFIG_REG);
2473 }
2474
2475 static void select_master_clock(struct comedi_device *dev, const struct comedi_cmd *cmd)
2476 {
2477 switch (board(dev)->layout) {
2478 case LAYOUT_4020:
2479 select_master_clock_4020(dev, cmd);
2480 break;
2481 default:
2482 break;
2483 }
2484 }
2485
2486 static inline void dma_start_sync(struct comedi_device *dev, unsigned int channel)
2487 {
2488 unsigned long flags;
2489
2490 /* spinlock for plx dma control/status reg */
2491 spin_lock_irqsave(&dev->spinlock, flags);
2492 if (channel)
2493 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2494 PLX_CLEAR_DMA_INTR_BIT,
2495 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2496 else
2497 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2498 PLX_CLEAR_DMA_INTR_BIT,
2499 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
2500 spin_unlock_irqrestore(&dev->spinlock, flags);
2501 }
2502
2503 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2504 {
2505 uint32_t convert_counter = 0, scan_counter = 0;
2506
2507 check_adc_timing(dev, cmd);
2508
2509 select_master_clock(dev, cmd);
2510
2511 if (board(dev)->layout == LAYOUT_4020) {
2512 convert_counter = ai_convert_counter_4020(dev, cmd);
2513 } else {
2514 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2515 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2516 }
2517
2518 /* load lower 16 bits of convert interval */
2519 writew(convert_counter & 0xffff,
2520 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2521 DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2522 /* load upper 8 bits of convert interval */
2523 writew((convert_counter >> 16) & 0xff,
2524 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2525 /* load lower 16 bits of scan delay */
2526 writew(scan_counter & 0xffff,
2527 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2528 /* load upper 8 bits of scan delay */
2529 writew((scan_counter >> 16) & 0xff,
2530 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2531 DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2532 }
2533
2534 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2535 {
2536 int i;
2537 for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2538 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2539 CR_CHAN(cmd->chanlist[i]) + 1)
2540 return 0;
2541 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2542 CR_RANGE(cmd->chanlist[i]))
2543 return 0;
2544 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2545 return 0;
2546 }
2547 return 1;
2548 }
2549
2550 static int setup_channel_queue(struct comedi_device *dev, const struct comedi_cmd *cmd)
2551 {
2552 unsigned short bits;
2553 int i;
2554
2555 if (board(dev)->layout != LAYOUT_4020) {
2556 if (use_internal_queue_6xxx(cmd)) {
2557 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
2558 writew(priv(dev)->hw_config_bits,
2559 priv(dev)->main_iobase + HW_CONFIG_REG);
2560 bits = 0;
2561 /* set channel */
2562 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2563 /* set gain */
2564 bits |= ai_range_bits_6xxx(dev,
2565 CR_RANGE(cmd->chanlist[0]));
2566 /* set single-ended / differential */
2567 bits |= se_diff_bit_6xxx(dev,
2568 CR_AREF(cmd->chanlist[0]) == AREF_DIFF);
2569 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2570 bits |= ADC_COMMON_BIT;
2571 /* set stop channel */
2572 writew(adc_chan_bits(CR_CHAN(cmd->chanlist[cmd->
2573 chanlist_len - 1])),
2574 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
2575 /* set start channel, and rest of settings */
2576 writew(bits,
2577 priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2578 } else {
2579 /* use external queue */
2580 if (dev->write_subdev && dev->write_subdev->busy) {
2581 warn_external_queue(dev);
2582 return -EBUSY;
2583 }
2584 priv(dev)->hw_config_bits |= EXT_QUEUE_BIT;
2585 writew(priv(dev)->hw_config_bits,
2586 priv(dev)->main_iobase + HW_CONFIG_REG);
2587 /* clear DAC buffer to prevent weird interactions */
2588 writew(0,
2589 priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
2590 /* clear queue pointer */
2591 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2592 /* load external queue */
2593 for (i = 0; i < cmd->chanlist_len; i++) {
2594 bits = 0;
2595 /* set channel */
2596 bits |= adc_chan_bits(CR_CHAN(cmd->
2597 chanlist[i]));
2598 /* set gain */
2599 bits |= ai_range_bits_6xxx(dev,
2600 CR_RANGE(cmd->chanlist[i]));
2601 /* set single-ended / differential */
2602 bits |= se_diff_bit_6xxx(dev,
2603 CR_AREF(cmd->chanlist[i]) == AREF_DIFF);
2604 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2605 bits |= ADC_COMMON_BIT;
2606 /* mark end of queue */
2607 if (i == cmd->chanlist_len - 1)
2608 bits |= QUEUE_EOSCAN_BIT |
2609 QUEUE_EOSEQ_BIT;
2610 writew(bits,
2611 priv(dev)->main_iobase +
2612 ADC_QUEUE_FIFO_REG);
2613 DEBUG_PRINT
2614 ("wrote 0x%x to external channel queue\n",
2615 bits);
2616 }
2617 /* doing a queue clear is not specified in board docs,
2618 * but required for reliable operation */
2619 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2620 /* prime queue holding register */
2621 writew(0, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2622 }
2623 } else {
2624 unsigned short old_cal_range_bits =
2625 priv(dev)->i2c_cal_range_bits;
2626
2627 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2628 /* select BNC inputs */
2629 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
2630 /* select ranges */
2631 for (i = 0; i < cmd->chanlist_len; i++) {
2632 unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2633 unsigned int range = CR_RANGE(cmd->chanlist[i]);
2634
2635 if (range == 0)
2636 priv(dev)->i2c_cal_range_bits |=
2637 attenuate_bit(channel);
2638 else
2639 priv(dev)->i2c_cal_range_bits &=
2640 ~attenuate_bit(channel);
2641 }
2642 /* update calibration/range i2c register only if necessary, as it is very slow */
2643 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
2644 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
2645 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2646 sizeof(i2c_data));
2647 }
2648 }
2649 return 0;
2650 }
2651
2652 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2653 unsigned int dma_channel, unsigned int descriptor_bits)
2654 {
2655 /* The transfer size, pci address, and local address registers
2656 * are supposedly unused during chained dma,
2657 * but I have found that left over values from last operation
2658 * occasionally cause problems with transfer of first dma
2659 * block. Initializing them to zero seems to fix the problem. */
2660 if (dma_channel) {
2661 writel(0,
2662 priv(dev)->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2663 writel(0, priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2664 writel(0,
2665 priv(dev)->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2666 writel(descriptor_bits,
2667 priv(dev)->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2668 } else {
2669 writel(0,
2670 priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2671 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2672 writel(0,
2673 priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2674 writel(descriptor_bits,
2675 priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2676 }
2677 }
2678
2679 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2680 {
2681 struct comedi_async *async = s->async;
2682 struct comedi_cmd *cmd = &async->cmd;
2683 uint32_t bits;
2684 unsigned int i;
2685 unsigned long flags;
2686 int retval;
2687
2688 disable_ai_pacing(dev);
2689 abort_dma(dev, 1);
2690
2691 retval = setup_channel_queue(dev, cmd);
2692 if (retval < 0)
2693 return retval;
2694
2695 /* make sure internal calibration source is turned off */
2696 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
2697
2698 set_ai_pacing(dev, cmd);
2699
2700 setup_sample_counters(dev, cmd);
2701
2702 enable_ai_interrupts(dev, cmd);
2703
2704 spin_lock_irqsave(&dev->spinlock, flags);
2705 /* set mode, allow conversions through software gate */
2706 priv(dev)->adc_control1_bits |= ADC_SW_GATE_BIT;
2707 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
2708 if (board(dev)->layout != LAYOUT_4020) {
2709 priv(dev)->adc_control1_bits &= ~ADC_MODE_MASK;
2710 if (cmd->convert_src == TRIG_EXT)
2711 priv(dev)->adc_control1_bits |= adc_mode_bits(13); /* good old mode 13 */
2712 else
2713 priv(dev)->adc_control1_bits |= adc_mode_bits(8); /* mode 8. What else could you need? */
2714 } else {
2715 priv(dev)->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2716 if (cmd->chanlist_len == 4)
2717 priv(dev)->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2718 else if (cmd->chanlist_len == 2)
2719 priv(dev)->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2720 priv(dev)->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2721 priv(dev)->adc_control1_bits |=
2722 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2723 priv(dev)->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2724 priv(dev)->adc_control1_bits |=
2725 adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist[cmd->
2726 chanlist_len - 1]));
2727 }
2728 writew(priv(dev)->adc_control1_bits,
2729 priv(dev)->main_iobase + ADC_CONTROL1_REG);
2730 DEBUG_PRINT("control1 bits 0x%x\n", priv(dev)->adc_control1_bits);
2731 spin_unlock_irqrestore(&dev->spinlock, flags);
2732
2733 /* clear adc buffer */
2734 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
2735
2736 if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2737 board(dev)->layout == LAYOUT_4020) {
2738 priv(dev)->ai_dma_index = 0;
2739
2740 /* set dma transfer size */
2741 for (i = 0; i < ai_dma_ring_count(board(dev)); i++)
2742 priv(dev)->ai_dma_desc[i].transfer_size =
2743 cpu_to_le32(dma_transfer_size(dev) *
2744 sizeof(uint16_t));
2745
2746 /* give location of first dma descriptor */
2747 load_first_dma_descriptor(dev, 1,
2748 priv(dev)->
2749 ai_dma_desc_bus_addr | PLX_DESC_IN_PCI_BIT |
2750 PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI);
2751
2752 dma_start_sync(dev, 1);
2753 }
2754
2755 if (board(dev)->layout == LAYOUT_4020) {
2756 /* set source for external triggers */
2757 bits = 0;
2758 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2759 bits |= EXT_START_TRIG_BNC_BIT;
2760 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2761 bits |= EXT_STOP_TRIG_BNC_BIT;
2762 writew(bits, priv(dev)->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2763 }
2764
2765 spin_lock_irqsave(&dev->spinlock, flags);
2766
2767 /* enable pacing, triggering, etc */
2768 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2769 if (cmd->flags & TRIG_WAKE_EOS)
2770 bits |= ADC_DMA_DISABLE_BIT;
2771 /* set start trigger */
2772 if (cmd->start_src == TRIG_EXT) {
2773 bits |= ADC_START_TRIG_EXT_BITS;
2774 if (cmd->start_arg & CR_INVERT)
2775 bits |= ADC_START_TRIG_FALLING_BIT;
2776 } else if (cmd->start_src == TRIG_NOW)
2777 bits |= ADC_START_TRIG_SOFT_BITS;
2778 if (use_hw_sample_counter(cmd))
2779 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2780 writew(bits, priv(dev)->main_iobase + ADC_CONTROL0_REG);
2781 DEBUG_PRINT("control0 bits 0x%x\n", bits);
2782
2783 priv(dev)->ai_cmd_running = 1;
2784
2785 spin_unlock_irqrestore(&dev->spinlock, flags);
2786
2787 /* start aquisition */
2788 if (cmd->start_src == TRIG_NOW) {
2789 writew(0, priv(dev)->main_iobase + ADC_START_REG);
2790 DEBUG_PRINT("soft trig\n");
2791 }
2792
2793 return 0;
2794 }
2795
2796 /* read num_samples from 16 bit wide ai fifo */
2797 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2798 {
2799 struct comedi_subdevice *s = dev->read_subdev;
2800 struct comedi_async *async = s->async;
2801 struct comedi_cmd *cmd = &async->cmd;
2802 unsigned int i;
2803 uint16_t prepost_bits;
2804 int read_segment, read_index, write_segment, write_index;
2805 int num_samples;
2806
2807 do {
2808 /* get least significant 15 bits */
2809 read_index =
2810 readw(priv(dev)->main_iobase +
2811 ADC_READ_PNTR_REG) & 0x7fff;
2812 write_index =
2813 readw(priv(dev)->main_iobase +
2814 ADC_WRITE_PNTR_REG) & 0x7fff;
2815 /* Get most significant bits (grey code). Different boards use different code
2816 * so use a scheme that doesn't depend on encoding. This read must
2817 * occur after reading least significant 15 bits to avoid race
2818 * with fifo switching to next segment. */
2819 prepost_bits = readw(priv(dev)->main_iobase + PREPOST_REG);
2820
2821 /* if read and write pointers are not on the same fifo segment, read to the
2822 * end of the read segment */
2823 read_segment = adc_upper_read_ptr_code(prepost_bits);
2824 write_segment = adc_upper_write_ptr_code(prepost_bits);
2825
2826 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2827 read_segment, write_segment, read_index, write_index);
2828
2829 if (read_segment != write_segment)
2830 num_samples =
2831 priv(dev)->ai_fifo_segment_length - read_index;
2832 else
2833 num_samples = write_index - read_index;
2834
2835 if (cmd->stop_src == TRIG_COUNT) {
2836 if (priv(dev)->ai_count == 0)
2837 break;
2838 if (num_samples > priv(dev)->ai_count) {
2839 num_samples = priv(dev)->ai_count;
2840 }
2841 priv(dev)->ai_count -= num_samples;
2842 }
2843
2844 if (num_samples < 0) {
2845 printk(" cb_pcidas64: bug! num_samples < 0\n");
2846 break;
2847 }
2848
2849 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2850
2851 for (i = 0; i < num_samples; i++) {
2852 cfc_write_to_buffer(s,
2853 readw(priv(dev)->main_iobase + ADC_FIFO_REG));
2854 }
2855
2856 } while (read_segment != write_segment);
2857 }
2858
2859 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
2860 * The pci-4020 hardware only supports
2861 * dma transfers (it only supports the use of pio for draining the last remaining
2862 * points from the fifo when a data aquisition operation has completed).
2863 */
2864 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2865 {
2866 struct comedi_subdevice *s = dev->read_subdev;
2867 struct comedi_async *async = s->async;
2868 struct comedi_cmd *cmd = &async->cmd;
2869 unsigned int i;
2870 unsigned int max_transfer = 100000;
2871 uint32_t fifo_data;
2872 int write_code =
2873 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2874 int read_code =
2875 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2876
2877 if (cmd->stop_src == TRIG_COUNT) {
2878 if (max_transfer > priv(dev)->ai_count) {
2879 max_transfer = priv(dev)->ai_count;
2880 }
2881 }
2882 for (i = 0; read_code != write_code && i < max_transfer;) {
2883 fifo_data = readl(priv(dev)->dio_counter_iobase + ADC_FIFO_REG);
2884 cfc_write_to_buffer(s, fifo_data & 0xffff);
2885 i++;
2886 if (i < max_transfer) {
2887 cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2888 i++;
2889 }
2890 read_code =
2891 readw(priv(dev)->main_iobase +
2892 ADC_READ_PNTR_REG) & 0x7fff;
2893 }
2894 priv(dev)->ai_count -= i;
2895 }
2896
2897 /* empty fifo */
2898 static void pio_drain_ai_fifo(struct comedi_device *dev)
2899 {
2900 if (board(dev)->layout == LAYOUT_4020) {
2901 pio_drain_ai_fifo_32(dev);
2902 } else
2903 pio_drain_ai_fifo_16(dev);
2904 }
2905
2906 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2907 {
2908 struct comedi_async *async = dev->read_subdev->async;
2909 uint32_t next_transfer_addr;
2910 int j;
2911 int num_samples = 0;
2912 void *pci_addr_reg;
2913
2914 if (channel)
2915 pci_addr_reg =
2916 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2917 else
2918 pci_addr_reg =
2919 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2920
2921 /* loop until we have read all the full buffers */
2922 for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2923 (next_transfer_addr <
2924 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index]
2925 || next_transfer_addr >=
2926 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] +
2927 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev));
2928 j++) {
2929 /* transfer data from dma buffer to comedi buffer */
2930 num_samples = dma_transfer_size(dev);
2931 if (async->cmd.stop_src == TRIG_COUNT) {
2932 if (num_samples > priv(dev)->ai_count)
2933 num_samples = priv(dev)->ai_count;
2934 priv(dev)->ai_count -= num_samples;
2935 }
2936 cfc_write_array_to_buffer(dev->read_subdev,
2937 priv(dev)->ai_buffer[priv(dev)->ai_dma_index],
2938 num_samples * sizeof(uint16_t));
2939 priv(dev)->ai_dma_index =
2940 (priv(dev)->ai_dma_index +
2941 1) % ai_dma_ring_count(board(dev));
2942
2943 DEBUG_PRINT("next buffer addr 0x%lx\n",
2944 (unsigned long)priv(dev)->ai_buffer_bus_addr[priv(dev)->
2945 ai_dma_index]);
2946 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
2947 }
2948 /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last
2949 * unused buffer) */
2950 }
2951
2952 void handle_ai_interrupt(struct comedi_device *dev, unsigned short status,
2953 unsigned int plx_status)
2954 {
2955 struct comedi_subdevice *s = dev->read_subdev;
2956 struct comedi_async *async = s->async;
2957 struct comedi_cmd *cmd = &async->cmd;
2958 uint8_t dma1_status;
2959 unsigned long flags;
2960
2961 /* check for fifo overrun */
2962 if (status & ADC_OVERRUN_BIT) {
2963 comedi_error(dev, "fifo overrun");
2964 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2965 }
2966 /* spin lock makes sure noone else changes plx dma control reg */
2967 spin_lock_irqsave(&dev->spinlock, flags);
2968 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2969 if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
2970 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2971 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2972 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
2973
2974 if (dma1_status & PLX_DMA_EN_BIT) {
2975 drain_dma_buffers(dev, 1);
2976 }
2977 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
2978 }
2979 spin_unlock_irqrestore(&dev->spinlock, flags);
2980
2981 if (status & ADC_DONE_BIT)
2982 DEBUG_PRINT("adc done interrupt\n");
2983
2984 /* drain fifo with pio */
2985 if ((status & ADC_DONE_BIT) ||
2986 ((cmd->flags & TRIG_WAKE_EOS) &&
2987 (status & ADC_INTR_PENDING_BIT) &&
2988 (board(dev)->layout != LAYOUT_4020))) {
2989 DEBUG_PRINT("pio fifo drain\n");
2990 spin_lock_irqsave(&dev->spinlock, flags);
2991 if (priv(dev)->ai_cmd_running) {
2992 spin_unlock_irqrestore(&dev->spinlock, flags);
2993 pio_drain_ai_fifo(dev);
2994 } else
2995 spin_unlock_irqrestore(&dev->spinlock, flags);
2996 }
2997 /* if we are have all the data, then quit */
2998 if ((cmd->stop_src == TRIG_COUNT && priv(dev)->ai_count <= 0) ||
2999 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
3000 async->events |= COMEDI_CB_EOA;
3001 }
3002
3003 cfc_handle_events(dev, s);
3004 }
3005
3006 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
3007 {
3008 unsigned int buffer_index;
3009
3010 if (priv(dev)->ao_dma_index == 0)
3011 buffer_index = AO_DMA_RING_COUNT - 1;
3012 else
3013 buffer_index = priv(dev)->ao_dma_index - 1;
3014 return buffer_index;
3015 }
3016
3017 static int last_ao_dma_load_completed(struct comedi_device *dev)
3018 {
3019 unsigned int buffer_index;
3020 unsigned int transfer_address;
3021 unsigned short dma_status;
3022
3023 buffer_index = prev_ao_dma_index(dev);
3024 dma_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3025 if ((dma_status & PLX_DMA_DONE_BIT) == 0)
3026 return 0;
3027
3028 transfer_address =
3029 readl(priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
3030 if (transfer_address != priv(dev)->ao_buffer_bus_addr[buffer_index])
3031 return 0;
3032
3033 return 1;
3034 }
3035
3036 static int ao_stopped_by_error(struct comedi_device *dev, const struct comedi_cmd *cmd)
3037 {
3038 if (cmd->stop_src == TRIG_NONE)
3039 return 1;
3040 if (cmd->stop_src == TRIG_COUNT) {
3041 if (priv(dev)->ao_count)
3042 return 1;
3043 if (last_ao_dma_load_completed(dev) == 0)
3044 return 1;
3045 }
3046 return 0;
3047 }
3048
3049 static inline int ao_dma_needs_restart(struct comedi_device *dev,
3050 unsigned short dma_status)
3051 {
3052 if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
3053 (dma_status & PLX_DMA_EN_BIT) == 0)
3054 return 0;
3055 if (last_ao_dma_load_completed(dev))
3056 return 0;
3057
3058 return 1;
3059 }
3060
3061 static void restart_ao_dma(struct comedi_device *dev)
3062 {
3063 unsigned int dma_desc_bits;
3064
3065 dma_desc_bits =
3066 readl(priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
3067 dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
3068 DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
3069 load_first_dma_descriptor(dev, 0, dma_desc_bits);
3070
3071 dma_start_sync(dev, 0);
3072 }
3073
3074 static void handle_ao_interrupt(struct comedi_device *dev, unsigned short status,
3075 unsigned int plx_status)
3076 {
3077 struct comedi_subdevice *s = dev->write_subdev;
3078 struct comedi_async *async;
3079 struct comedi_cmd *cmd;
3080 uint8_t dma0_status;
3081 unsigned long flags;
3082
3083 /* board might not support ao, in which case write_subdev is NULL */
3084 if (s == NULL)
3085 return;
3086 async = s->async;
3087 cmd = &async->cmd;
3088
3089 /* spin lock makes sure noone else changes plx dma control reg */
3090 spin_lock_irqsave(&dev->spinlock, flags);
3091 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3092 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
3093 if ((dma0_status & PLX_DMA_EN_BIT)
3094 && !(dma0_status & PLX_DMA_DONE_BIT))
3095 writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3096 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3097 else
3098 writeb(PLX_CLEAR_DMA_INTR_BIT,
3099 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3100 spin_unlock_irqrestore(&dev->spinlock, flags);
3101 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3102 if (dma0_status & PLX_DMA_EN_BIT) {
3103 load_ao_dma(dev, cmd);
3104 /* try to recover from dma end-of-chain event */
3105 if (ao_dma_needs_restart(dev, dma0_status))
3106 restart_ao_dma(dev);
3107 }
3108 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3109 } else
3110 spin_unlock_irqrestore(&dev->spinlock, flags);
3111
3112 if ((status & DAC_DONE_BIT)) {
3113 async->events |= COMEDI_CB_EOA;
3114 if (ao_stopped_by_error(dev, cmd))
3115 async->events |= COMEDI_CB_ERROR;
3116 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3117 readl(priv(dev)->plx9080_iobase +
3118 PLX_DMA0_DESCRIPTOR_REG));
3119 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3120 readl(priv(dev)->plx9080_iobase +
3121 PLX_DMA0_PCI_ADDRESS_REG));
3122 }
3123 cfc_handle_events(dev, s);
3124 }
3125
3126 static irqreturn_t handle_interrupt(int irq, void *d)
3127 {
3128 struct comedi_device *dev = d;
3129 unsigned short status;
3130 uint32_t plx_status;
3131 uint32_t plx_bits;
3132
3133 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
3134 status = readw(priv(dev)->main_iobase + HW_STATUS_REG);
3135
3136 DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status);
3137 DEBUG_PRINT("plx status 0x%x\n", plx_status);
3138
3139 /* an interrupt before all the postconfig stuff gets done could
3140 * cause a NULL dereference if we continue through the
3141 * interrupt handler */
3142 if (dev->attached == 0) {
3143 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring",
3144 status);
3145 return IRQ_HANDLED;
3146 }
3147 handle_ai_interrupt(dev, status, plx_status);
3148 handle_ao_interrupt(dev, status, plx_status);
3149
3150 /* clear possible plx9080 interrupt sources */
3151 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
3152 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3153 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3154 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3155 }
3156
3157 DEBUG_PRINT("exiting handler\n");
3158
3159 return IRQ_HANDLED;
3160 }
3161
3162 void abort_dma(struct comedi_device *dev, unsigned int channel)
3163 {
3164 unsigned long flags;
3165
3166 /* spinlock for plx dma control/status reg */
3167 spin_lock_irqsave(&dev->spinlock, flags);
3168
3169 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
3170
3171 spin_unlock_irqrestore(&dev->spinlock, flags);
3172 }
3173
3174 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3175 {
3176 unsigned long flags;
3177
3178 spin_lock_irqsave(&dev->spinlock, flags);
3179 if (priv(dev)->ai_cmd_running == 0) {
3180 spin_unlock_irqrestore(&dev->spinlock, flags);
3181 return 0;
3182 }
3183 priv(dev)->ai_cmd_running = 0;
3184 spin_unlock_irqrestore(&dev->spinlock, flags);
3185
3186 disable_ai_pacing(dev);
3187
3188 abort_dma(dev, 1);
3189
3190 DEBUG_PRINT("ai canceled\n");
3191 return 0;
3192 }
3193
3194 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3195 struct comedi_insn *insn, unsigned int *data)
3196 {
3197 int chan = CR_CHAN(insn->chanspec);
3198 int range = CR_RANGE(insn->chanspec);
3199
3200 /* do some initializing */
3201 writew(0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3202
3203 /* set range */
3204 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, chan, range);
3205 writew(priv(dev)->dac_control1_bits,
3206 priv(dev)->main_iobase + DAC_CONTROL1_REG);
3207
3208 /* write to channel */
3209 if (board(dev)->layout == LAYOUT_4020) {
3210 writew(data[0] & 0xff,
3211 priv(dev)->main_iobase + dac_lsb_4020_reg(chan));
3212 writew((data[0] >> 8) & 0xf,
3213 priv(dev)->main_iobase + dac_msb_4020_reg(chan));
3214 } else {
3215 writew(data[0], priv(dev)->main_iobase + dac_convert_reg(chan));
3216 }
3217
3218 /* remember output value */
3219 priv(dev)->ao_value[chan] = data[0];
3220
3221 return 1;
3222 }
3223
3224 static int ao_readback_insn(struct comedi_device *dev, struct comedi_subdevice *s,
3225 struct comedi_insn *insn, unsigned int *data)
3226 {
3227 data[0] = priv(dev)->ao_value[CR_CHAN(insn->chanspec)];
3228
3229 return 1;
3230 }
3231
3232 static void set_dac_control0_reg(struct comedi_device *dev, const struct comedi_cmd *cmd)
3233 {
3234 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3235 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3236
3237 if (cmd->start_src == TRIG_EXT) {
3238 bits |= WAVEFORM_TRIG_EXT_BITS;
3239 if (cmd->start_arg & CR_INVERT)
3240 bits |= WAVEFORM_TRIG_FALLING_BIT;
3241 } else {
3242 bits |= WAVEFORM_TRIG_SOFT_BITS;
3243 }
3244 if (cmd->scan_begin_src == TRIG_EXT) {
3245 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3246 if (cmd->scan_begin_arg & CR_INVERT)
3247 bits |= DAC_EXT_UPDATE_FALLING_BIT;
3248 }
3249 writew(bits, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3250 }
3251
3252 static void set_dac_control1_reg(struct comedi_device *dev, const struct comedi_cmd *cmd)
3253 {
3254 int i;
3255
3256 for (i = 0; i < cmd->chanlist_len; i++) {
3257 int channel, range;
3258
3259 channel = CR_CHAN(cmd->chanlist[i]);
3260 range = CR_RANGE(cmd->chanlist[i]);
3261 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, channel,
3262 range);
3263 }
3264 priv(dev)->dac_control1_bits |= DAC_SW_GATE_BIT;
3265 writew(priv(dev)->dac_control1_bits,
3266 priv(dev)->main_iobase + DAC_CONTROL1_REG);
3267 }
3268
3269 static void set_dac_select_reg(struct comedi_device *dev, const struct comedi_cmd *cmd)
3270 {
3271 uint16_t bits;
3272 unsigned int first_channel, last_channel;
3273
3274 first_channel = CR_CHAN(cmd->chanlist[0]);
3275 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3276 if (last_channel < first_channel)
3277 comedi_error(dev, "bug! last ao channel < first ao channel");
3278
3279 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3280
3281 writew(bits, priv(dev)->main_iobase + DAC_SELECT_REG);
3282 }
3283
3284 static void set_dac_interval_regs(struct comedi_device *dev, const struct comedi_cmd *cmd)
3285 {
3286 unsigned int divisor;
3287
3288 if (cmd->scan_begin_src != TRIG_TIMER)
3289 return;
3290
3291 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3292 if (divisor > max_counter_value) {
3293 comedi_error(dev, "bug! ao divisor too big");
3294 divisor = max_counter_value;
3295 }
3296 writew(divisor & 0xffff,
3297 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3298 writew((divisor >> 16) & 0xff,
3299 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3300 }
3301
3302 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
3303 const struct comedi_cmd *cmd)
3304 {
3305 unsigned int num_bytes, buffer_index, prev_buffer_index;
3306 unsigned int next_bits;
3307
3308 buffer_index = priv(dev)->ao_dma_index;
3309 prev_buffer_index = prev_ao_dma_index(dev);
3310
3311 DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index,
3312 priv(dev)->ao_buffer_bus_addr[buffer_index]);
3313
3314 num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
3315 if (num_bytes > DMA_BUFFER_SIZE)
3316 num_bytes = DMA_BUFFER_SIZE;
3317 if (cmd->stop_src == TRIG_COUNT && num_bytes > priv(dev)->ao_count)
3318 num_bytes = priv(dev)->ao_count;
3319 num_bytes -= num_bytes % bytes_in_sample;
3320
3321 if (num_bytes == 0)
3322 return 0;
3323
3324 DEBUG_PRINT("loading %i bytes\n", num_bytes);
3325
3326 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3327 priv(dev)->ao_buffer[buffer_index], num_bytes);
3328 priv(dev)->ao_dma_desc[buffer_index].transfer_size =
3329 cpu_to_le32(num_bytes);
3330 /* set end of chain bit so we catch underruns */
3331 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[buffer_index].next);
3332 next_bits |= PLX_END_OF_CHAIN_BIT;
3333 priv(dev)->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3334 /* clear end of chain bit on previous buffer now that we have set it
3335 * for the last buffer */
3336 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[prev_buffer_index].next);
3337 next_bits &= ~PLX_END_OF_CHAIN_BIT;
3338 priv(dev)->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3339
3340 priv(dev)->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3341 priv(dev)->ao_count -= num_bytes;
3342
3343 return num_bytes;
3344 }
3345
3346 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3347 {
3348 unsigned int num_bytes;
3349 unsigned int next_transfer_addr;
3350 void *pci_addr_reg =
3351 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3352 unsigned int buffer_index;
3353
3354 do {
3355 buffer_index = priv(dev)->ao_dma_index;
3356 /* don't overwrite data that hasn't been transferred yet */
3357 next_transfer_addr = readl(pci_addr_reg);
3358 if (next_transfer_addr >=
3359 priv(dev)->ao_buffer_bus_addr[buffer_index]
3360 && next_transfer_addr <
3361 priv(dev)->ao_buffer_bus_addr[buffer_index] +
3362 DMA_BUFFER_SIZE)
3363 return;
3364 num_bytes = load_ao_dma_buffer(dev, cmd);
3365 } while (num_bytes >= DMA_BUFFER_SIZE);
3366 }
3367
3368 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3369 {
3370 unsigned int num_bytes;
3371 int i;
3372
3373 /* clear queue pointer too, since external queue has
3374 * weird interactions with ao fifo */
3375 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
3376 writew(0, priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
3377
3378 num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3379 if (cmd->stop_src == TRIG_COUNT &&
3380 num_bytes / bytes_in_sample > priv(dev)->ao_count)
3381 num_bytes = priv(dev)->ao_count * bytes_in_sample;
3382 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3383 priv(dev)->ao_bounce_buffer, num_bytes);
3384 for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3385 writew(priv(dev)->ao_bounce_buffer[i],
3386 priv(dev)->main_iobase + DAC_FIFO_REG);
3387 }
3388 priv(dev)->ao_count -= num_bytes / bytes_in_sample;
3389 if (cmd->stop_src == TRIG_COUNT && priv(dev)->ao_count == 0)
3390 return 0;
3391 num_bytes = load_ao_dma_buffer(dev, cmd);
3392 if (num_bytes == 0)
3393 return -1;
3394 if (num_bytes >= DMA_BUFFER_SIZE) ;
3395 load_ao_dma(dev, cmd);
3396
3397 dma_start_sync(dev, 0);
3398
3399 return 0;
3400 }
3401
3402 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3403 {
3404 if (dev->read_subdev->busy)
3405 return 0;
3406 if (board(dev)->layout == LAYOUT_4020)
3407 return 0;
3408 else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3409 return 0;
3410 return 1;
3411 }
3412
3413 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3414 {
3415 struct comedi_cmd *cmd = &s->async->cmd;
3416
3417 if (external_ai_queue_in_use(dev)) {
3418 warn_external_queue(dev);
3419 return -EBUSY;
3420 }
3421 /* disable analog output system during setup */
3422 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3423
3424 priv(dev)->ao_dma_index = 0;
3425 priv(dev)->ao_count = cmd->stop_arg * cmd->chanlist_len;
3426
3427 set_dac_select_reg(dev, cmd);
3428 set_dac_interval_regs(dev, cmd);
3429 load_first_dma_descriptor(dev, 0, priv(dev)->ao_dma_desc_bus_addr |
3430 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3431
3432 set_dac_control1_reg(dev, cmd);
3433 s->async->inttrig = ao_inttrig;
3434
3435 return 0;
3436 }
3437
3438 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3439 unsigned int trig_num)
3440 {
3441 struct comedi_cmd *cmd = &s->async->cmd;
3442 int retval;
3443
3444 if (trig_num != 0)
3445 return -EINVAL;
3446
3447 retval = prep_ao_dma(dev, cmd);
3448 if (retval < 0)
3449 return -EPIPE;
3450
3451 set_dac_control0_reg(dev, cmd);
3452
3453 if (cmd->start_src == TRIG_INT)
3454 writew(0, priv(dev)->main_iobase + DAC_START_REG);
3455
3456 s->async->inttrig = NULL;
3457
3458 return 0;
3459 }
3460
3461 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3462 struct comedi_cmd *cmd)
3463 {
3464 int err = 0;
3465 int tmp;
3466 unsigned int tmp_arg;
3467 int i;
3468
3469 /* step 1: make sure trigger sources are trivially valid */
3470
3471 tmp = cmd->start_src;
3472 cmd->start_src &= TRIG_INT | TRIG_EXT;
3473 if (!cmd->start_src || tmp != cmd->start_src)
3474 err++;
3475
3476 tmp = cmd->scan_begin_src;
3477 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3478 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3479 err++;
3480
3481 tmp = cmd->convert_src;
3482 cmd->convert_src &= TRIG_NOW;
3483 if (!cmd->convert_src || tmp != cmd->convert_src)
3484 err++;
3485
3486 tmp = cmd->scan_end_src;
3487 cmd->scan_end_src &= TRIG_COUNT;
3488 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3489 err++;
3490
3491 tmp = cmd->stop_src;
3492 cmd->stop_src &= TRIG_NONE;
3493 if (!cmd->stop_src || tmp != cmd->stop_src)
3494 err++;
3495
3496 if (err)
3497 return 1;
3498
3499 /* step 2: make sure trigger sources are unique and mutually compatible */
3500
3501 /* uniqueness check */
3502 if (cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
3503 err++;
3504 if (cmd->scan_begin_src != TRIG_TIMER &&
3505 cmd->scan_begin_src != TRIG_EXT)
3506 err++;
3507
3508 /* compatibility check */
3509 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3510 err++;
3511 if (cmd->stop_src != TRIG_COUNT &&
3512 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3513 err++;
3514
3515 if (err)
3516 return 2;
3517
3518 /* step 3: make sure arguments are trivially compatible */
3519
3520 if (cmd->scan_begin_src == TRIG_TIMER) {
3521 if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) {
3522 cmd->scan_begin_arg = board(dev)->ao_scan_speed;
3523 err++;
3524 }
3525 if (get_ao_divisor(cmd->scan_begin_arg,
3526 cmd->flags) > max_counter_value) {
3527 cmd->scan_begin_arg =
3528 (max_counter_value + 2) * TIMER_BASE;
3529 err++;
3530 }
3531 }
3532
3533 if (!cmd->chanlist_len) {
3534 cmd->chanlist_len = 1;
3535 err++;
3536 }
3537 if (cmd->scan_end_arg != cmd->chanlist_len) {
3538 cmd->scan_end_arg = cmd->chanlist_len;
3539 err++;
3540 }
3541
3542 if (err)
3543 return 3;
3544
3545 /* step 4: fix up any arguments */
3546
3547 if (cmd->scan_begin_src == TRIG_TIMER) {
3548 tmp_arg = cmd->scan_begin_arg;
3549 cmd->scan_begin_arg =
3550 get_divisor(cmd->scan_begin_arg,
3551 cmd->flags) * TIMER_BASE;
3552 if (tmp_arg != cmd->scan_begin_arg)
3553 err++;
3554 }
3555
3556 if (err)
3557 return 4;
3558
3559 if (cmd->chanlist) {
3560 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3561 for (i = 1; i < cmd->chanlist_len; i++) {
3562 if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3563 comedi_error(dev,
3564 "chanlist must use consecutive channels");
3565 err++;
3566 break;
3567 }
3568 }
3569 }
3570
3571 if (err)
3572 return 5;
3573
3574 return 0;
3575 }
3576
3577 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3578 {
3579 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3580 abort_dma(dev, 0);
3581 return 0;
3582 }
3583
3584 static int dio_callback(int dir, int port, int data, unsigned long iobase)
3585 {
3586 if (dir) {
3587 writeb(data, (void *)(iobase + port));
3588 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3589 return 0;
3590 } else {
3591 return readb((void *)(iobase + port));
3592 }
3593 }
3594
3595 static int dio_callback_4020(int dir, int port, int data, unsigned long iobase)
3596 {
3597 if (dir) {
3598 writew(data, (void *)(iobase + 2 * port));
3599 return 0;
3600 } else {
3601 return readw((void *)(iobase + 2 * port));
3602 }
3603 }
3604
3605 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3606 struct comedi_insn *insn, unsigned int *data)
3607 {
3608 unsigned int bits;
3609
3610 bits = readb(priv(dev)->dio_counter_iobase + DI_REG);
3611 bits &= 0xf;
3612 data[1] = bits;
3613 data[0] = 0;
3614
3615 return 2;
3616 }
3617
3618 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3619 struct comedi_insn *insn, unsigned int *data)
3620 {
3621 data[0] &= 0xf;
3622 /* zero bits we are going to change */
3623 s->state &= ~data[0];
3624 /* set new bits */
3625 s->state |= data[0] & data[1];
3626
3627 writeb(s->state, priv(dev)->dio_counter_iobase + DO_REG);
3628
3629 data[1] = s->state;
3630
3631 return 2;
3632 }
3633
3634 static int dio_60xx_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
3635 struct comedi_insn *insn, unsigned int *data)
3636 {
3637 unsigned int mask;
3638
3639 mask = 1 << CR_CHAN(insn->chanspec);
3640
3641 switch (data[0]) {
3642 case INSN_CONFIG_DIO_INPUT:
3643 s->io_bits &= ~mask;
3644 break;
3645 case INSN_CONFIG_DIO_OUTPUT:
3646 s->io_bits |= mask;
3647 break;
3648 case INSN_CONFIG_DIO_QUERY:
3649 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3650 return 2;
3651 default:
3652 return -EINVAL;
3653 }
3654
3655 writeb(s->io_bits,
3656 priv(dev)->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3657
3658 return 1;
3659 }
3660
3661 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3662 struct comedi_insn *insn, unsigned int *data)
3663 {
3664 if (data[0]) {
3665 s->state &= ~data[0];
3666 s->state |= (data[0] & data[1]);
3667 writeb(s->state,
3668 priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3669 }
3670
3671 data[1] = readb(priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3672
3673 return 2;
3674 }
3675
3676 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3677 unsigned int value)
3678 {
3679 priv(dev)->caldac_state[channel] = value;
3680
3681 switch (board(dev)->layout) {
3682 case LAYOUT_60XX:
3683 case LAYOUT_64XX:
3684 caldac_8800_write(dev, channel, value);
3685 break;
3686 case LAYOUT_4020:
3687 caldac_i2c_write(dev, channel, value);
3688 break;
3689 default:
3690 break;
3691 }
3692 }
3693
3694 static int calib_write_insn(struct comedi_device *dev, struct comedi_subdevice *s,
3695 struct comedi_insn *insn, unsigned int *data)
3696 {
3697 int channel = CR_CHAN(insn->chanspec);
3698
3699 /* return immediately if setting hasn't changed, since
3700 * programming these things is slow */
3701 if (priv(dev)->caldac_state[channel] == data[0])
3702 return 1;
3703
3704 caldac_write(dev, channel, data[0]);
3705
3706 return 1;
3707 }
3708
3709 static int calib_read_insn(struct comedi_device *dev, struct comedi_subdevice *s,
3710 struct comedi_insn *insn, unsigned int *data)
3711 {
3712 unsigned int channel = CR_CHAN(insn->chanspec);
3713
3714 data[0] = priv(dev)->caldac_state[channel];
3715
3716 return 1;
3717 }
3718
3719 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3720 unsigned int value)
3721 {
3722 static const int bitstream_length = 10;
3723 unsigned int bit, register_bits;
3724 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3725 static const int ad8402_udelay = 1;
3726
3727 priv(dev)->ad8402_state[channel] = value;
3728
3729 register_bits = SELECT_8402_64XX_BIT;
3730 udelay(ad8402_udelay);
3731 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3732
3733 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3734 if (bitstream & bit)
3735 register_bits |= SERIAL_DATA_IN_BIT;
3736 else
3737 register_bits &= ~SERIAL_DATA_IN_BIT;
3738 udelay(ad8402_udelay);
3739 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3740 udelay(ad8402_udelay);
3741 writew(register_bits | SERIAL_CLOCK_BIT,
3742 priv(dev)->main_iobase + CALIBRATION_REG);
3743 }
3744
3745 udelay(ad8402_udelay);
3746 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
3747 }
3748
3749 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3750 static int ad8402_write_insn(struct comedi_device *dev, struct comedi_subdevice *s,
3751 struct comedi_insn *insn, unsigned int *data)
3752 {
3753 int channel = CR_CHAN(insn->chanspec);
3754
3755 /* return immediately if setting hasn't changed, since
3756 * programming these things is slow */
3757 if (priv(dev)->ad8402_state[channel] == data[0])
3758 return 1;
3759
3760 priv(dev)->ad8402_state[channel] = data[0];
3761
3762 ad8402_write(dev, channel, data[0]);
3763
3764 return 1;
3765 }
3766
3767 static int ad8402_read_insn(struct comedi_device *dev, struct comedi_subdevice *s,
3768 struct comedi_insn *insn, unsigned int *data)
3769 {
3770 unsigned int channel = CR_CHAN(insn->chanspec);
3771
3772 data[0] = priv(dev)->ad8402_state[channel];
3773
3774 return 1;
3775 }
3776
3777 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3778 {
3779 static const int bitstream_length = 11;
3780 static const int read_command = 0x6;
3781 unsigned int bitstream = (read_command << 8) | address;
3782 unsigned int bit;
3783 void *const plx_control_addr =
3784 priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
3785 uint16_t value;
3786 static const int value_length = 16;
3787 static const int eeprom_udelay = 1;
3788
3789 udelay(eeprom_udelay);
3790 priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3791 /* make sure we don't send anything to the i2c bus on 4020 */
3792 priv(dev)->plx_control_bits |= CTL_USERO;
3793 writel(priv(dev)->plx_control_bits, plx_control_addr);
3794 /* activate serial eeprom */
3795 udelay(eeprom_udelay);
3796 priv(dev)->plx_control_bits |= CTL_EE_CS;
3797 writel(priv(dev)->plx_control_bits, plx_control_addr);
3798
3799 /* write read command and desired memory address */
3800 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3801 /* set bit to be written */
3802 udelay(eeprom_udelay);
3803 if (bitstream & bit)
3804 priv(dev)->plx_control_bits |= CTL_EE_W;
3805 else
3806 priv(dev)->plx_control_bits &= ~CTL_EE_W;
3807 writel(priv(dev)->plx_control_bits, plx_control_addr);
3808 /* clock in bit */
3809 udelay(eeprom_udelay);
3810 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3811 writel(priv(dev)->plx_control_bits, plx_control_addr);
3812 udelay(eeprom_udelay);
3813 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3814 writel(priv(dev)->plx_control_bits, plx_control_addr);
3815 }
3816 /* read back value from eeprom memory location */
3817 value = 0;
3818 for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3819 /* clock out bit */
3820 udelay(eeprom_udelay);
3821 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3822 writel(priv(dev)->plx_control_bits, plx_control_addr);
3823 udelay(eeprom_udelay);
3824 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3825 writel(priv(dev)->plx_control_bits, plx_control_addr);
3826 udelay(eeprom_udelay);
3827 if (readl(plx_control_addr) & CTL_EE_R)
3828 value |= bit;
3829 }
3830
3831 /* deactivate eeprom serial input */
3832 udelay(eeprom_udelay);
3833 priv(dev)->plx_control_bits &= ~CTL_EE_CS;
3834 writel(priv(dev)->plx_control_bits, plx_control_addr);
3835
3836 return value;
3837 }
3838
3839 static int eeprom_read_insn(struct comedi_device *dev, struct comedi_subdevice *s,
3840 struct comedi_insn *insn, unsigned int *data)
3841 {
3842 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3843
3844 return 1;
3845 }
3846
3847 /* utility function that rounds desired timing to an achievable time, and
3848 * sets cmd members appropriately.
3849 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
3850 */
3851 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
3852 {
3853 unsigned int convert_divisor = 0, scan_divisor;
3854 static const int min_convert_divisor = 3;
3855 static const int max_convert_divisor =
3856 max_counter_value + min_convert_divisor;
3857 static const int min_scan_divisor_4020 = 2;
3858 unsigned long long max_scan_divisor, min_scan_divisor;
3859
3860 if (cmd->convert_src == TRIG_TIMER) {
3861 if (board(dev)->layout == LAYOUT_4020) {
3862 cmd->convert_arg = 0;
3863 } else {
3864 convert_divisor =
3865 get_divisor(cmd->convert_arg, cmd->flags);
3866 if (convert_divisor > max_convert_divisor)
3867 convert_divisor = max_convert_divisor;
3868 if (convert_divisor < min_convert_divisor)
3869 convert_divisor = min_convert_divisor;
3870 cmd->convert_arg = convert_divisor * TIMER_BASE;
3871 }
3872 } else if (cmd->convert_src == TRIG_NOW)
3873 cmd->convert_arg = 0;
3874
3875 if (cmd->scan_begin_src == TRIG_TIMER) {
3876 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
3877 if (cmd->convert_src == TRIG_TIMER) {
3878 /* XXX check for integer overflows */
3879 min_scan_divisor = convert_divisor * cmd->chanlist_len;
3880 max_scan_divisor =
3881 (convert_divisor * cmd->chanlist_len - 1) +
3882 max_counter_value;
3883 } else {
3884 min_scan_divisor = min_scan_divisor_4020;
3885 max_scan_divisor = max_counter_value + min_scan_divisor;
3886 }
3887 if (scan_divisor > max_scan_divisor)
3888 scan_divisor = max_scan_divisor;
3889 if (scan_divisor < min_scan_divisor)
3890 scan_divisor = min_scan_divisor;
3891 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
3892 }
3893
3894 return;
3895 }
3896
3897 /* Gets nearest achievable timing given master clock speed, does not
3898 * take into account possible minimum/maximum divisor values. Used
3899 * by other timing checking functions. */
3900 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
3901 {
3902 unsigned int divisor;
3903
3904 switch (flags & TRIG_ROUND_MASK) {
3905 case TRIG_ROUND_UP:
3906 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
3907 break;
3908 case TRIG_ROUND_DOWN:
3909 divisor = ns / TIMER_BASE;
3910 break;
3911 case TRIG_ROUND_NEAREST:
3912 default:
3913 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
3914 break;
3915 }
3916 return divisor;
3917 }
3918
3919 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3920 {
3921 return get_divisor(ns, flags) - 2;
3922 }
3923
3924 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
3925 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
3926 {
3927 unsigned int num_fifo_entries;
3928 int retval;
3929 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3930
3931 num_fifo_entries = num_samples / fifo->sample_packing_ratio;
3932
3933 retval = set_ai_fifo_segment_length(dev,
3934 num_fifo_entries / fifo->num_segments);
3935 if (retval < 0)
3936 return retval;
3937
3938 num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
3939
3940 DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
3941
3942 return num_samples;
3943 }
3944
3945 /* query length of fifo */
3946 static unsigned int ai_fifo_size(struct comedi_device *dev)
3947 {
3948 return priv(dev)->ai_fifo_segment_length *
3949 board(dev)->ai_fifo->num_segments *
3950 board(dev)->ai_fifo->sample_packing_ratio;
3951 }
3952
3953 static int set_ai_fifo_segment_length(struct comedi_device *dev,
3954 unsigned int num_entries)
3955 {
3956 static const int increment_size = 0x100;
3957 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
3958 unsigned int num_increments;
3959 uint16_t bits;
3960
3961 if (num_entries < increment_size)
3962 num_entries = increment_size;
3963 if (num_entries > fifo->max_segment_length)
3964 num_entries = fifo->max_segment_length;
3965
3966 /* 1 == 256 entries, 2 == 512 entries, etc */
3967 num_increments = (num_entries + increment_size / 2) / increment_size;
3968
3969 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
3970 priv(dev)->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
3971 priv(dev)->fifo_size_bits |= bits;
3972 writew(priv(dev)->fifo_size_bits,
3973 priv(dev)->main_iobase + FIFO_SIZE_REG);
3974
3975 priv(dev)->ai_fifo_segment_length = num_increments * increment_size;
3976
3977 DEBUG_PRINT("set hardware fifo segment length to %i\n",
3978 priv(dev)->ai_fifo_segment_length);
3979
3980 return priv(dev)->ai_fifo_segment_length;
3981 }
3982
3983 /* pci-6025 8800 caldac:
3984 * address 0 == dac channel 0 offset
3985 * address 1 == dac channel 0 gain
3986 * address 2 == dac channel 1 offset
3987 * address 3 == dac channel 1 gain
3988 * address 4 == fine adc offset
3989 * address 5 == coarse adc offset
3990 * address 6 == coarse adc gain
3991 * address 7 == fine adc gain
3992 */
3993 /* pci-6402/16 uses all 8 channels for dac:
3994 * address 0 == dac channel 0 fine gain
3995 * address 1 == dac channel 0 coarse gain
3996 * address 2 == dac channel 0 coarse offset
3997 * address 3 == dac channel 1 coarse offset
3998 * address 4 == dac channel 1 fine gain
3999 * address 5 == dac channel 1 coarse gain
4000 * address 6 == dac channel 0 fine offset
4001 * address 7 == dac channel 1 fine offset
4002 */
4003
4004 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
4005 uint8_t value)
4006 {
4007 static const int num_caldac_channels = 8;
4008 static const int bitstream_length = 11;
4009 unsigned int bitstream = ((address & 0x7) << 8) | value;
4010 unsigned int bit, register_bits;
4011 static const int caldac_8800_udelay = 1;
4012
4013 if (address >= num_caldac_channels) {
4014 comedi_error(dev, "illegal caldac channel");
4015 return -1;
4016 }
4017 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
4018 register_bits = 0;
4019 if (bitstream & bit)
4020 register_bits |= SERIAL_DATA_IN_BIT;
4021 udelay(caldac_8800_udelay);
4022 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4023 register_bits |= SERIAL_CLOCK_BIT;
4024 udelay(caldac_8800_udelay);
4025 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4026 }
4027 udelay(caldac_8800_udelay);
4028 writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG);
4029 udelay(caldac_8800_udelay);
4030 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
4031 udelay(caldac_8800_udelay);
4032 return 0;
4033 }
4034
4035 /* 4020 caldacs */
4036 static int caldac_i2c_write(struct comedi_device *dev, unsigned int caldac_channel,
4037 unsigned int value)
4038 {
4039 uint8_t serial_bytes[3];
4040 uint8_t i2c_addr;
4041 enum pointer_bits {
4042 /* manual has gain and offset bits switched */
4043 OFFSET_0_2 = 0x1,
4044 GAIN_0_2 = 0x2,
4045 OFFSET_1_3 = 0x4,
4046 GAIN_1_3 = 0x8,
4047 };
4048 enum data_bits {
4049 NOT_CLEAR_REGISTERS = 0x20,
4050 };
4051
4052 switch (caldac_channel) {
4053 case 0: /* chan 0 offset */
4054 i2c_addr = CALDAC0_I2C_ADDR;
4055 serial_bytes[0] = OFFSET_0_2;
4056 break;
4057 case 1: /* chan 1 offset */
4058 i2c_addr = CALDAC0_I2C_ADDR;
4059 serial_bytes[0] = OFFSET_1_3;
4060 break;
4061 case 2: /* chan 2 offset */
4062 i2c_addr = CALDAC1_I2C_ADDR;
4063 serial_bytes[0] = OFFSET_0_2;
4064 break;
4065 case 3: /* chan 3 offset */
4066 i2c_addr = CALDAC1_I2C_ADDR;
4067 serial_bytes[0] = OFFSET_1_3;
4068 break;
4069 case 4: /* chan 0 gain */
4070 i2c_addr = CALDAC0_I2C_ADDR;
4071 serial_bytes[0] = GAIN_0_2;
4072 break;
4073 case 5: /* chan 1 gain */
4074 i2c_addr = CALDAC0_I2C_ADDR;
4075 serial_bytes[0] = GAIN_1_3;
4076 break;
4077 case 6: /* chan 2 gain */
4078 i2c_addr = CALDAC1_I2C_ADDR;
4079 serial_bytes[0] = GAIN_0_2;
4080 break;
4081 case 7: /* chan 3 gain */
4082 i2c_addr = CALDAC1_I2C_ADDR;
4083 serial_bytes[0] = GAIN_1_3;
4084 break;
4085 default:
4086 comedi_error(dev, "invalid caldac channel\n");
4087 return -1;
4088 break;
4089 }
4090 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
4091 serial_bytes[2] = value & 0xff;
4092 i2c_write(dev, i2c_addr, serial_bytes, 3);
4093 return 0;
4094 }
4095
4096 /* Their i2c requires a huge delay on setting clock or data high for some reason */
4097 static const int i2c_high_udelay = 1000;
4098 static const int i2c_low_udelay = 10;
4099
4100 /* set i2c data line high or low */
4101 static void i2c_set_sda(struct comedi_device *dev, int state)
4102 {
4103 static const int data_bit = CTL_EE_W;
4104 void *plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
4105
4106 if (state) {
4107 /* set data line high */
4108 priv(dev)->plx_control_bits &= ~data_bit;
4109 writel(priv(dev)->plx_control_bits, plx_control_addr);
4110 udelay(i2c_high_udelay);
4111 } else /* set data line low */
4112 {
4113 priv(dev)->plx_control_bits |= data_bit;
4114 writel(priv(dev)->plx_control_bits, plx_control_addr);
4115 udelay(i2c_low_udelay);
4116 }
4117 }
4118
4119 /* set i2c clock line high or low */
4120 static void i2c_set_scl(struct comedi_device *dev, int state)
4121 {
4122 static const int clock_bit = CTL_USERO;
4123 void *plx_control_addr = priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
4124
4125 if (state) {
4126 /* set clock line high */
4127 priv(dev)->plx_control_bits &= ~clock_bit;
4128 writel(priv(dev)->plx_control_bits, plx_control_addr);
4129 udelay(i2c_high_udelay);
4130 } else /* set clock line low */
4131 {
4132 priv(dev)->plx_control_bits |= clock_bit;
4133 writel(priv(dev)->plx_control_bits, plx_control_addr);
4134 udelay(i2c_low_udelay);
4135 }
4136 }
4137
4138 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
4139 {
4140 uint8_t bit;
4141 unsigned int num_bits = 8;
4142
4143 DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
4144
4145 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
4146 i2c_set_scl(dev, 0);
4147 if ((byte & bit))
4148 i2c_set_sda(dev, 1);
4149 else
4150 i2c_set_sda(dev, 0);
4151 i2c_set_scl(dev, 1);
4152 }
4153 }
4154
4155 /* we can't really read the lines, so fake it */
4156 static int i2c_read_ack(struct comedi_device *dev)
4157 {
4158 i2c_set_scl(dev, 0);
4159 i2c_set_sda(dev, 1);
4160 i2c_set_scl(dev, 1);
4161
4162 return 0; /* return fake acknowledge bit */
4163 }
4164
4165 /* send start bit */
4166 static void i2c_start(struct comedi_device *dev)
4167 {
4168 i2c_set_scl(dev, 1);
4169 i2c_set_sda(dev, 1);
4170 i2c_set_sda(dev, 0);
4171 }
4172
4173 /* send stop bit */
4174 static void i2c_stop(struct comedi_device *dev)
4175 {
4176 i2c_set_scl(dev, 0);
4177 i2c_set_sda(dev, 0);
4178 i2c_set_scl(dev, 1);
4179 i2c_set_sda(dev, 1);
4180 }
4181
4182 static void i2c_write(struct comedi_device *dev, unsigned int address,
4183 const uint8_t *data, unsigned int length)
4184 {
4185 unsigned int i;
4186 uint8_t bitstream;
4187 static const int read_bit = 0x1;
4188
4189 /* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */
4190
4191 /* make sure we dont send anything to eeprom */
4192 priv(dev)->plx_control_bits &= ~CTL_EE_CS;
4193
4194 i2c_stop(dev);
4195 i2c_start(dev);
4196
4197 /* send address and write bit */
4198 bitstream = (address << 1) & ~read_bit;
4199 i2c_write_byte(dev, bitstream);
4200
4201 /* get acknowledge */
4202 if (i2c_read_ack(dev) != 0) {
4203 comedi_error(dev, "i2c write failed: no acknowledge");
4204 i2c_stop(dev);
4205 return;
4206 }
4207 /* write data bytes */
4208 for (i = 0; i < length; i++) {
4209 i2c_write_byte(dev, data[i]);
4210 if (i2c_read_ack(dev) != 0) {
4211 comedi_error(dev, "i2c write failed: no acknowledge");
4212 i2c_stop(dev);
4213 return;
4214 }
4215 }
4216 i2c_stop(dev);
4217 }
Linux kernel - Deliverables
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