drivers/staging/comedi/drivers/gsc_hpdi.c

   1 /*
   2  * gsc_hpdi.c
   3  * Comedi driver the General Standards Corporation
   4  * High Speed Parallel Digital Interface rs485 boards.
   5  *
   6  * Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7  * Copyright (C) 2003 Coherent Imaging Systems
   8  *
   9  * COMEDI - Linux Control and Measurement Device Interface
  10  * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  */
  22
  23 /*
  24  * Driver: gsc_hpdi
  25  * Description: General Standards Corporation High
  26  *    Speed Parallel Digital Interface rs485 boards
  27  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  28  * Status: only receive mode works, transmit not supported
  29  * Updated: Thu, 01 Nov 2012 16:17:38 +0000
  30  * Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
  31  *   PMC-HPDI32
  32  *
  33  * Configuration options:
  34  *    None.
  35  *
  36  * Manual configuration of supported devices is not supported; they are
  37  * configured automatically.
  38  *
  39  * There are some additional hpdi models available from GSC for which
  40  * support could be added to this driver.
  41  */
  42
  43 #include <linux/module.h>
  44 #include <linux/delay.h>
  45 #include <linux/interrupt.h>
  46
  47 #include "../comedi_pci.h"
  48
  49 #include "plx9080.h"
  50
  51 /*
  52  * PCI BAR2 Register map (dev->mmio)
  53  */
  54 #define FIRMWARE_REV_REG                        0x00
  55 #define FEATURES_REG_PRESENT_BIT                (1 << 15)
  56 #define BOARD_CONTROL_REG                       0x04
  57 #define BOARD_RESET_BIT                         (1 << 0)
  58 #define TX_FIFO_RESET_BIT                       (1 << 1)
  59 #define RX_FIFO_RESET_BIT                       (1 << 2)
  60 #define TX_ENABLE_BIT                           (1 << 4)
  61 #define RX_ENABLE_BIT                           (1 << 5)
  62 #define DEMAND_DMA_DIRECTION_TX_BIT             (1 << 6)  /* ch 0 only */
  63 #define LINE_VALID_ON_STATUS_VALID_BIT          (1 << 7)
  64 #define START_TX_BIT                            (1 << 8)
  65 #define CABLE_THROTTLE_ENABLE_BIT               (1 << 9)
  66 #define TEST_MODE_ENABLE_BIT                    (1 << 31)
  67 #define BOARD_STATUS_REG                        0x08
  68 #define COMMAND_LINE_STATUS_MASK                (0x7f << 0)
  69 #define TX_IN_PROGRESS_BIT                      (1 << 7)
  70 #define TX_NOT_EMPTY_BIT                        (1 << 8)
  71 #define TX_NOT_ALMOST_EMPTY_BIT                 (1 << 9)
  72 #define TX_NOT_ALMOST_FULL_BIT                  (1 << 10)
  73 #define TX_NOT_FULL_BIT                         (1 << 11)
  74 #define RX_NOT_EMPTY_BIT                        (1 << 12)
  75 #define RX_NOT_ALMOST_EMPTY_BIT                 (1 << 13)
  76 #define RX_NOT_ALMOST_FULL_BIT                  (1 << 14)
  77 #define RX_NOT_FULL_BIT                         (1 << 15)
  78 #define BOARD_JUMPER0_INSTALLED_BIT             (1 << 16)
  79 #define BOARD_JUMPER1_INSTALLED_BIT             (1 << 17)
  80 #define TX_OVERRUN_BIT                          (1 << 21)
  81 #define RX_UNDERRUN_BIT                         (1 << 22)
  82 #define RX_OVERRUN_BIT                          (1 << 23)
  83 #define TX_PROG_ALMOST_REG                      0x0c
  84 #define RX_PROG_ALMOST_REG                      0x10
  85 #define ALMOST_EMPTY_BITS(x)                    (((x) & 0xffff) << 0)
  86 #define ALMOST_FULL_BITS(x)                     (((x) & 0xff) << 16)
  87 #define FEATURES_REG                            0x14
  88 #define FIFO_SIZE_PRESENT_BIT                   (1 << 0)
  89 #define FIFO_WORDS_PRESENT_BIT                  (1 << 1)
  90 #define LEVEL_EDGE_INTERRUPTS_PRESENT_BIT       (1 << 2)
  91 #define GPIO_SUPPORTED_BIT                      (1 << 3)
  92 #define PLX_DMA_CH1_SUPPORTED_BIT               (1 << 4)
  93 #define OVERRUN_UNDERRUN_SUPPORTED_BIT          (1 << 5)
  94 #define FIFO_REG                                0x18
  95 #define TX_STATUS_COUNT_REG                     0x1c
  96 #define TX_LINE_VALID_COUNT_REG                 0x20,
  97 #define TX_LINE_INVALID_COUNT_REG               0x24
  98 #define RX_STATUS_COUNT_REG                     0x28
  99 #define RX_LINE_COUNT_REG                       0x2c
 100 #define INTERRUPT_CONTROL_REG                   0x30
 101 #define FRAME_VALID_START_INTR                  (1 << 0)
 102 #define FRAME_VALID_END_INTR                    (1 << 1)
 103 #define TX_FIFO_EMPTY_INTR                      (1 << 8)
 104 #define TX_FIFO_ALMOST_EMPTY_INTR               (1 << 9)
 105 #define TX_FIFO_ALMOST_FULL_INTR                (1 << 10)
 106 #define TX_FIFO_FULL_INTR                       (1 << 11)
 107 #define RX_EMPTY_INTR                           (1 << 12)
 108 #define RX_ALMOST_EMPTY_INTR                    (1 << 13)
 109 #define RX_ALMOST_FULL_INTR                     (1 << 14)
 110 #define RX_FULL_INTR                            (1 << 15)
 111 #define INTERRUPT_STATUS_REG                    0x34
 112 #define TX_CLOCK_DIVIDER_REG                    0x38
 113 #define TX_FIFO_SIZE_REG                        0x40
 114 #define RX_FIFO_SIZE_REG                        0x44
 115 #define FIFO_SIZE_MASK                          (0xfffff << 0)
 116 #define TX_FIFO_WORDS_REG                       0x48
 117 #define RX_FIFO_WORDS_REG                       0x4c
 118 #define INTERRUPT_EDGE_LEVEL_REG                0x50
 119 #define INTERRUPT_POLARITY_REG                  0x54
 120
 121 #define TIMER_BASE                              50      /* 20MHz master clock */
 122 #define DMA_BUFFER_SIZE                         0x10000
 123 #define NUM_DMA_BUFFERS                         4
 124 #define NUM_DMA_DESCRIPTORS                     256
 125
 126 struct hpdi_board {
 127         const char *name;
 128         int device_id;
 129         int subdevice_id;
 130 };
 131
 132 static const struct hpdi_board hpdi_boards[] = {
 133         {
 134                 .name           = "pci-hpdi32",
 135                 .device_id      = PCI_DEVICE_ID_PLX_9080,
 136                 .subdevice_id   = 0x2400,
 137          },
 138 };
 139
 140 struct hpdi_private {
 141         void __iomem *plx9080_mmio;
 142         uint32_t *dio_buffer[NUM_DMA_BUFFERS];  /* dma buffers */
 143         /* physical addresses of dma buffers */
 144         dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS];
 145         /*
 146          * array of dma descriptors read by plx9080, allocated to get proper
 147          * alignment
 148          */
 149         struct plx_dma_desc *dma_desc;
 150         /* physical address of dma descriptor array */
 151         dma_addr_t dma_desc_phys_addr;
 152         unsigned int num_dma_descriptors;
 153         /* pointer to start of buffers indexed by descriptor */
 154         uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS];
 155         /* index of the dma descriptor that is currently being used */
 156         unsigned int dma_desc_index;
 157         unsigned int tx_fifo_size;
 158         unsigned int rx_fifo_size;
 159         unsigned long dio_count;
 160         /* number of bytes at which to generate COMEDI_CB_BLOCK events */
 161         unsigned int block_size;
 162 };
 163
 164 static void gsc_hpdi_drain_dma(struct comedi_device *dev, unsigned int channel)
 165 {
 166         struct hpdi_private *devpriv = dev->private;
 167         struct comedi_subdevice *s = dev->read_subdev;
 168         struct comedi_cmd *cmd = &s->async->cmd;
 169         unsigned int idx;
 170         unsigned int start;
 171         unsigned int desc;
 172         unsigned int size;
 173         unsigned int next;
 174
 175         if (channel)
 176                 next = readl(devpriv->plx9080_mmio + PLX_DMA1_PCI_ADDRESS_REG);
 177         else
 178                 next = readl(devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
 179
 180         idx = devpriv->dma_desc_index;
 181         start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
 182         /* loop until we have read all the full buffers */
 183         for (desc = 0; (next < start || next >= start + devpriv->block_size) &&
 184              desc < devpriv->num_dma_descriptors; desc++) {
 185                 /* transfer data from dma buffer to comedi buffer */
 186                 size = devpriv->block_size / sizeof(uint32_t);
 187                 if (cmd->stop_src == TRIG_COUNT) {
 188                         if (size > devpriv->dio_count)
 189                                 size = devpriv->dio_count;
 190                         devpriv->dio_count -= size;
 191                 }
 192                 comedi_buf_write_samples(s, devpriv->desc_dio_buffer[idx],
 193                                          size);
 194                 idx++;
 195                 idx %= devpriv->num_dma_descriptors;
 196                 start = le32_to_cpu(devpriv->dma_desc[idx].pci_start_addr);
 197
 198                 devpriv->dma_desc_index = idx;
 199         }
 200         /* XXX check for buffer overrun somehow */
 201 }
 202
 203 static irqreturn_t gsc_hpdi_interrupt(int irq, void *d)
 204 {
 205         struct comedi_device *dev = d;
 206         struct hpdi_private *devpriv = dev->private;
 207         struct comedi_subdevice *s = dev->read_subdev;
 208         struct comedi_async *async = s->async;
 209         uint32_t hpdi_intr_status, hpdi_board_status;
 210         uint32_t plx_status;
 211         uint32_t plx_bits;
 212         uint8_t dma0_status, dma1_status;
 213         unsigned long flags;
 214
 215         if (!dev->attached)
 216                 return IRQ_NONE;
 217
 218         plx_status = readl(devpriv->plx9080_mmio + PLX_INTRCS_REG);
 219         if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0)
 220                 return IRQ_NONE;
 221
 222         hpdi_intr_status = readl(dev->mmio + INTERRUPT_STATUS_REG);
 223         hpdi_board_status = readl(dev->mmio + BOARD_STATUS_REG);
 224
 225         if (hpdi_intr_status)
 226                 writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG);
 227
 228         /* spin lock makes sure no one else changes plx dma control reg */
 229         spin_lock_irqsave(&dev->spinlock, flags);
 230         dma0_status = readb(devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
 231         if (plx_status & ICS_DMA0_A) {
 232                 /* dma chan 0 interrupt */
 233                 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
 234                        devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
 235
 236                 if (dma0_status & PLX_DMA_EN_BIT)
 237                         gsc_hpdi_drain_dma(dev, 0);
 238         }
 239         spin_unlock_irqrestore(&dev->spinlock, flags);
 240
 241         /* spin lock makes sure no one else changes plx dma control reg */
 242         spin_lock_irqsave(&dev->spinlock, flags);
 243         dma1_status = readb(devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
 244         if (plx_status & ICS_DMA1_A) {
 245                 /* XXX */ /* dma chan 1 interrupt */
 246                 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
 247                        devpriv->plx9080_mmio + PLX_DMA1_CS_REG);
 248         }
 249         spin_unlock_irqrestore(&dev->spinlock, flags);
 250
 251         /* clear possible plx9080 interrupt sources */
 252         if (plx_status & ICS_LDIA) {
 253                 /* clear local doorbell interrupt */
 254                 plx_bits = readl(devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
 255                 writel(plx_bits, devpriv->plx9080_mmio + PLX_DBR_OUT_REG);
 256         }
 257
 258         if (hpdi_board_status & RX_OVERRUN_BIT) {
 259                 dev_err(dev->class_dev, "rx fifo overrun\n");
 260                 async->events |= COMEDI_CB_ERROR;
 261         }
 262
 263         if (hpdi_board_status & RX_UNDERRUN_BIT) {
 264                 dev_err(dev->class_dev, "rx fifo underrun\n");
 265                 async->events |= COMEDI_CB_ERROR;
 266         }
 267
 268         if (devpriv->dio_count == 0)
 269                 async->events |= COMEDI_CB_EOA;
 270
 271         comedi_handle_events(dev, s);
 272
 273         return IRQ_HANDLED;
 274 }
 275
 276 static void gsc_hpdi_abort_dma(struct comedi_device *dev, unsigned int channel)
 277 {
 278         struct hpdi_private *devpriv = dev->private;
 279         unsigned long flags;
 280
 281         /* spinlock for plx dma control/status reg */
 282         spin_lock_irqsave(&dev->spinlock, flags);
 283
 284         plx9080_abort_dma(devpriv->plx9080_mmio, channel);
 285
 286         spin_unlock_irqrestore(&dev->spinlock, flags);
 287 }
 288
 289 static int gsc_hpdi_cancel(struct comedi_device *dev,
 290                            struct comedi_subdevice *s)
 291 {
 292         writel(0, dev->mmio + BOARD_CONTROL_REG);
 293         writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
 294
 295         gsc_hpdi_abort_dma(dev, 0);
 296
 297         return 0;
 298 }
 299
 300 static int gsc_hpdi_cmd(struct comedi_device *dev,
 301                         struct comedi_subdevice *s)
 302 {
 303         struct hpdi_private *devpriv = dev->private;
 304         struct comedi_async *async = s->async;
 305         struct comedi_cmd *cmd = &async->cmd;
 306         unsigned long flags;
 307         uint32_t bits;
 308
 309         if (s->io_bits)
 310                 return -EINVAL;
 311
 312         writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
 313
 314         gsc_hpdi_abort_dma(dev, 0);
 315
 316         devpriv->dma_desc_index = 0;
 317
 318         /*
 319          * These register are supposedly unused during chained dma,
 320          * but I have found that left over values from last operation
 321          * occasionally cause problems with transfer of first dma
 322          * block.  Initializing them to zero seems to fix the problem.
 323          */
 324         writel(0, devpriv->plx9080_mmio + PLX_DMA0_TRANSFER_SIZE_REG);
 325         writel(0, devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG);
 326         writel(0, devpriv->plx9080_mmio + PLX_DMA0_LOCAL_ADDRESS_REG);
 327
 328         /* give location of first dma descriptor */
 329         bits = devpriv->dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT |
 330                PLX_INTR_TERM_COUNT | PLX_XFER_LOCAL_TO_PCI;
 331         writel(bits, devpriv->plx9080_mmio + PLX_DMA0_DESCRIPTOR_REG);
 332
 333         /* enable dma transfer */
 334         spin_lock_irqsave(&dev->spinlock, flags);
 335         writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
 336                devpriv->plx9080_mmio + PLX_DMA0_CS_REG);
 337         spin_unlock_irqrestore(&dev->spinlock, flags);
 338
 339         if (cmd->stop_src == TRIG_COUNT)
 340                 devpriv->dio_count = cmd->stop_arg;
 341         else
 342                 devpriv->dio_count = 1;
 343
 344         /* clear over/under run status flags */
 345         writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG);
 346
 347         /* enable interrupts */
 348         writel(RX_FULL_INTR, dev->mmio + INTERRUPT_CONTROL_REG);
 349
 350         writel(RX_ENABLE_BIT, dev->mmio + BOARD_CONTROL_REG);
 351
 352         return 0;
 353 }
 354
 355 static int gsc_hpdi_check_chanlist(struct comedi_device *dev,
 356                                    struct comedi_subdevice *s,
 357                                    struct comedi_cmd *cmd)
 358 {
 359         int i;
 360
 361         for (i = 0; i < cmd->chanlist_len; i++) {
 362                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
 363
 364                 if (chan != i) {
 365                         dev_dbg(dev->class_dev,
 366                                 "chanlist must be ch 0 to 31 in order\n");
 367                         return -EINVAL;
 368                 }
 369         }
 370
 371         return 0;
 372 }
 373
 374 static int gsc_hpdi_cmd_test(struct comedi_device *dev,
 375                              struct comedi_subdevice *s,
 376                              struct comedi_cmd *cmd)
 377 {
 378         int err = 0;
 379
 380         if (s->io_bits)
 381                 return -EINVAL;
 382
 383         /* Step 1 : check if triggers are trivially valid */
 384
 385         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
 386         err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
 387         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
 388         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 389         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
 390
 391         if (err)
 392                 return 1;
 393
 394         /* Step 2a : make sure trigger sources are unique */
 395
 396         err |= comedi_check_trigger_is_unique(cmd->stop_src);
 397
 398         /* Step 2b : and mutually compatible */
 399
 400         if (err)
 401                 return 2;
 402
 403         /* Step 3: check if arguments are trivially valid */
 404
 405         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
 406
 407         if (!cmd->chanlist_len || !cmd->chanlist) {
 408                 cmd->chanlist_len = 32;
 409                 err |= -EINVAL;
 410         }
 411         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 412                                            cmd->chanlist_len);
 413
 414         if (cmd->stop_src == TRIG_COUNT)
 415                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
 416         else    /* TRIG_NONE */
 417                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 418
 419         if (err)
 420                 return 3;
 421
 422         /* Step 4: fix up any arguments */
 423
 424         /* Step 5: check channel list if it exists */
 425
 426         if (cmd->chanlist && cmd->chanlist_len > 0)
 427                 err |= gsc_hpdi_check_chanlist(dev, s, cmd);
 428
 429         if (err)
 430                 return 5;
 431
 432         return 0;
 433 }
 434
 435 /* setup dma descriptors so a link completes every 'len' bytes */
 436 static int gsc_hpdi_setup_dma_descriptors(struct comedi_device *dev,
 437                                           unsigned int len)
 438 {
 439         struct hpdi_private *devpriv = dev->private;
 440         dma_addr_t phys_addr = devpriv->dma_desc_phys_addr;
 441         uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
 442                              PLX_XFER_LOCAL_TO_PCI;
 443         unsigned int offset = 0;
 444         unsigned int idx = 0;
 445         unsigned int i;
 446
 447         if (len > DMA_BUFFER_SIZE)
 448                 len = DMA_BUFFER_SIZE;
 449         len -= len % sizeof(uint32_t);
 450         if (len == 0)
 451                 return -EINVAL;
 452
 453         for (i = 0; i < NUM_DMA_DESCRIPTORS && idx < NUM_DMA_BUFFERS; i++) {
 454                 devpriv->dma_desc[i].pci_start_addr =
 455                     cpu_to_le32(devpriv->dio_buffer_phys_addr[idx] + offset);
 456                 devpriv->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
 457                 devpriv->dma_desc[i].transfer_size = cpu_to_le32(len);
 458                 devpriv->dma_desc[i].next = cpu_to_le32((phys_addr +
 459                         (i + 1) * sizeof(devpriv->dma_desc[0])) | next_bits);
 460
 461                 devpriv->desc_dio_buffer[i] = devpriv->dio_buffer[idx] +
 462                                               (offset / sizeof(uint32_t));
 463
 464                 offset += len;
 465                 if (len + offset > DMA_BUFFER_SIZE) {
 466                         offset = 0;
 467                         idx++;
 468                 }
 469         }
 470         devpriv->num_dma_descriptors = i;
 471         /* fix last descriptor to point back to first */
 472         devpriv->dma_desc[i - 1].next = cpu_to_le32(phys_addr | next_bits);
 473
 474         devpriv->block_size = len;
 475
 476         return len;
 477 }
 478
 479 static int gsc_hpdi_dio_insn_config(struct comedi_device *dev,
 480                                     struct comedi_subdevice *s,
 481                                     struct comedi_insn *insn,
 482                                     unsigned int *data)
 483 {
 484         int ret;
 485
 486         switch (data[0]) {
 487         case INSN_CONFIG_BLOCK_SIZE:
 488                 ret = gsc_hpdi_setup_dma_descriptors(dev, data[1]);
 489                 if (ret)
 490                         return ret;
 491
 492                 data[1] = ret;
 493                 break;
 494         default:
 495                 ret = comedi_dio_insn_config(dev, s, insn, data, 0xffffffff);
 496                 if (ret)
 497                         return ret;
 498                 break;
 499         }
 500
 501         return insn->n;
 502 }
 503
 504 static void gsc_hpdi_free_dma(struct comedi_device *dev)
 505 {
 506         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 507         struct hpdi_private *devpriv = dev->private;
 508         int i;
 509
 510         if (!devpriv)
 511                 return;
 512
 513         /* free pci dma buffers */
 514         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
 515                 if (devpriv->dio_buffer[i])
 516                         pci_free_consistent(pcidev,
 517                                             DMA_BUFFER_SIZE,
 518                                             devpriv->dio_buffer[i],
 519                                             devpriv->dio_buffer_phys_addr[i]);
 520         }
 521         /* free dma descriptors */
 522         if (devpriv->dma_desc)
 523                 pci_free_consistent(pcidev,
 524                                     sizeof(struct plx_dma_desc) *
 525                                     NUM_DMA_DESCRIPTORS,
 526                                     devpriv->dma_desc,
 527                                     devpriv->dma_desc_phys_addr);
 528 }
 529
 530 static int gsc_hpdi_init(struct comedi_device *dev)
 531 {
 532         struct hpdi_private *devpriv = dev->private;
 533         uint32_t plx_intcsr_bits;
 534
 535         /* wait 10usec after reset before accessing fifos */
 536         writel(BOARD_RESET_BIT, dev->mmio + BOARD_CONTROL_REG);
 537         udelay(10);
 538
 539         writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
 540                dev->mmio + RX_PROG_ALMOST_REG);
 541         writel(ALMOST_EMPTY_BITS(32) | ALMOST_FULL_BITS(32),
 542                dev->mmio + TX_PROG_ALMOST_REG);
 543
 544         devpriv->tx_fifo_size = readl(dev->mmio + TX_FIFO_SIZE_REG) &
 545                                 FIFO_SIZE_MASK;
 546         devpriv->rx_fifo_size = readl(dev->mmio + RX_FIFO_SIZE_REG) &
 547                                 FIFO_SIZE_MASK;
 548
 549         writel(0, dev->mmio + INTERRUPT_CONTROL_REG);
 550
 551         /* enable interrupts */
 552         plx_intcsr_bits =
 553             ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
 554             ICS_DMA0_E;
 555         writel(plx_intcsr_bits, devpriv->plx9080_mmio + PLX_INTRCS_REG);
 556
 557         return 0;
 558 }
 559
 560 static void gsc_hpdi_init_plx9080(struct comedi_device *dev)
 561 {
 562         struct hpdi_private *devpriv = dev->private;
 563         uint32_t bits;
 564         void __iomem *plx_iobase = devpriv->plx9080_mmio;
 565
 566 #ifdef __BIG_ENDIAN
 567         bits = BIGEND_DMA0 | BIGEND_DMA1;
 568 #else
 569         bits = 0;
 570 #endif
 571         writel(bits, devpriv->plx9080_mmio + PLX_BIGEND_REG);
 572
 573         writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
 574
 575         gsc_hpdi_abort_dma(dev, 0);
 576         gsc_hpdi_abort_dma(dev, 1);
 577
 578         /* configure dma0 mode */
 579         bits = 0;
 580         /* enable ready input */
 581         bits |= PLX_DMA_EN_READYIN_BIT;
 582         /* enable dma chaining */
 583         bits |= PLX_EN_CHAIN_BIT;
 584         /*
 585          * enable interrupt on dma done
 586          * (probably don't need this, since chain never finishes)
 587          */
 588         bits |= PLX_EN_DMA_DONE_INTR_BIT;
 589         /*
 590          * don't increment local address during transfers
 591          * (we are transferring from a fixed fifo register)
 592          */
 593         bits |= PLX_LOCAL_ADDR_CONST_BIT;
 594         /* route dma interrupt to pci bus */
 595         bits |= PLX_DMA_INTR_PCI_BIT;
 596         /* enable demand mode */
 597         bits |= PLX_DEMAND_MODE_BIT;
 598         /* enable local burst mode */
 599         bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
 600         bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
 601         writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
 602 }
 603
 604 static const struct hpdi_board *gsc_hpdi_find_board(struct pci_dev *pcidev)
 605 {
 606         unsigned int i;
 607
 608         for (i = 0; i < ARRAY_SIZE(hpdi_boards); i++)
 609                 if (pcidev->device == hpdi_boards[i].device_id &&
 610                     pcidev->subsystem_device == hpdi_boards[i].subdevice_id)
 611                         return &hpdi_boards[i];
 612         return NULL;
 613 }
 614
 615 static int gsc_hpdi_auto_attach(struct comedi_device *dev,
 616                                 unsigned long context_unused)
 617 {
 618         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 619         const struct hpdi_board *thisboard;
 620         struct hpdi_private *devpriv;
 621         struct comedi_subdevice *s;
 622         int i;
 623         int retval;
 624
 625         thisboard = gsc_hpdi_find_board(pcidev);
 626         if (!thisboard) {
 627                 dev_err(dev->class_dev, "gsc_hpdi: pci %s not supported\n",
 628                         pci_name(pcidev));
 629                 return -EINVAL;
 630         }
 631         dev->board_ptr = thisboard;
 632         dev->board_name = thisboard->name;
 633
 634         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 635         if (!devpriv)
 636                 return -ENOMEM;
 637
 638         retval = comedi_pci_enable(dev);
 639         if (retval)
 640                 return retval;
 641         pci_set_master(pcidev);
 642
 643         devpriv->plx9080_mmio = pci_ioremap_bar(pcidev, 0);
 644         dev->mmio = pci_ioremap_bar(pcidev, 2);
 645         if (!devpriv->plx9080_mmio || !dev->mmio) {
 646                 dev_warn(dev->class_dev, "failed to remap io memory\n");
 647                 return -ENOMEM;
 648         }
 649
 650         gsc_hpdi_init_plx9080(dev);
 651
 652         /* get irq */
 653         if (request_irq(pcidev->irq, gsc_hpdi_interrupt, IRQF_SHARED,
 654                         dev->board_name, dev)) {
 655                 dev_warn(dev->class_dev,
 656                          "unable to allocate irq %u\n", pcidev->irq);
 657                 return -EINVAL;
 658         }
 659         dev->irq = pcidev->irq;
 660
 661         dev_dbg(dev->class_dev, " irq %u\n", dev->irq);
 662
 663         /* allocate pci dma buffers */
 664         for (i = 0; i < NUM_DMA_BUFFERS; i++) {
 665                 devpriv->dio_buffer[i] =
 666                     pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
 667                                          &devpriv->dio_buffer_phys_addr[i]);
 668         }
 669         /* allocate dma descriptors */
 670         devpriv->dma_desc = pci_alloc_consistent(pcidev,
 671                                                  sizeof(struct plx_dma_desc) *
 672                                                  NUM_DMA_DESCRIPTORS,
 673                                                  &devpriv->dma_desc_phys_addr);
 674         if (devpriv->dma_desc_phys_addr & 0xf) {
 675                 dev_warn(dev->class_dev,
 676                          " dma descriptors not quad-word aligned (bug)\n");
 677                 return -EIO;
 678         }
 679
 680         retval = gsc_hpdi_setup_dma_descriptors(dev, 0x1000);
 681         if (retval < 0)
 682                 return retval;
 683
 684         retval = comedi_alloc_subdevices(dev, 1);
 685         if (retval)
 686                 return retval;
 687
 688         /* Digital I/O subdevice */
 689         s = &dev->subdevices[0];
 690         dev->read_subdev = s;
 691         s->type         = COMEDI_SUBD_DIO;
 692         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
 693                           SDF_CMD_READ;
 694         s->n_chan       = 32;
 695         s->len_chanlist = 32;
 696         s->maxdata      = 1;
 697         s->range_table  = &range_digital;
 698         s->insn_config  = gsc_hpdi_dio_insn_config;
 699         s->do_cmd       = gsc_hpdi_cmd;
 700         s->do_cmdtest   = gsc_hpdi_cmd_test;
 701         s->cancel       = gsc_hpdi_cancel;
 702
 703         return gsc_hpdi_init(dev);
 704 }
 705
 706 static void gsc_hpdi_detach(struct comedi_device *dev)
 707 {
 708         struct hpdi_private *devpriv = dev->private;
 709
 710         if (dev->irq)
 711                 free_irq(dev->irq, dev);
 712         if (devpriv) {
 713                 if (devpriv->plx9080_mmio) {
 714                         writel(0, devpriv->plx9080_mmio + PLX_INTRCS_REG);
 715                         iounmap(devpriv->plx9080_mmio);
 716                 }
 717                 if (dev->mmio)
 718                         iounmap(dev->mmio);
 719         }
 720         comedi_pci_disable(dev);
 721         gsc_hpdi_free_dma(dev);
 722 }
 723
 724 static struct comedi_driver gsc_hpdi_driver = {
 725         .driver_name    = "gsc_hpdi",
 726         .module         = THIS_MODULE,
 727         .auto_attach    = gsc_hpdi_auto_attach,
 728         .detach         = gsc_hpdi_detach,
 729 };
 730
 731 static int gsc_hpdi_pci_probe(struct pci_dev *dev,
 732                               const struct pci_device_id *id)
 733 {
 734         return comedi_pci_auto_config(dev, &gsc_hpdi_driver, id->driver_data);
 735 }
 736
 737 static const struct pci_device_id gsc_hpdi_pci_table[] = {
 738         { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX,
 739                     0x2400, 0, 0, 0},
 740         { 0 }
 741 };
 742 MODULE_DEVICE_TABLE(pci, gsc_hpdi_pci_table);
 743
 744 static struct pci_driver gsc_hpdi_pci_driver = {
 745         .name           = "gsc_hpdi",
 746         .id_table       = gsc_hpdi_pci_table,
 747         .probe          = gsc_hpdi_pci_probe,
 748         .remove         = comedi_pci_auto_unconfig,
 749 };
 750 module_comedi_pci_driver(gsc_hpdi_driver, gsc_hpdi_pci_driver);
 751
 752 MODULE_AUTHOR("Comedi http://www.comedi.org");
 753 MODULE_DESCRIPTION("Comedi low-level driver");
 754 MODULE_LICENSE("GPL");