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staging: comedi: drivers: use comedi_dio_update_state() for simple cases
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_atmio16d.c
1 /*
2 comedi/drivers/ni_atmio16d.c
3 Hardware driver for National Instruments AT-MIO16D board
4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15 */
16 /*
17 Driver: ni_atmio16d
18 Description: National Instruments AT-MIO-16D
19 Author: Chris R. Baugher <baugher@enteract.com>
20 Status: unknown
21 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
22 */
23 /*
24 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
25 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
26 * handling code from his driver as an example for this one.
27 *
28 * Chris Baugher
29 * 5/1/2000
30 *
31 */
32
33 #include <linux/module.h>
34 #include <linux/interrupt.h>
35 #include "../comedidev.h"
36
37 #include "comedi_fc.h"
38 #include "8255.h"
39
40 /* Configuration and Status Registers */
41 #define COM_REG_1 0x00 /* wo 16 */
42 #define STAT_REG 0x00 /* ro 16 */
43 #define COM_REG_2 0x02 /* wo 16 */
44 /* Event Strobe Registers */
45 #define START_CONVERT_REG 0x08 /* wo 16 */
46 #define START_DAQ_REG 0x0A /* wo 16 */
47 #define AD_CLEAR_REG 0x0C /* wo 16 */
48 #define EXT_STROBE_REG 0x0E /* wo 16 */
49 /* Analog Output Registers */
50 #define DAC0_REG 0x10 /* wo 16 */
51 #define DAC1_REG 0x12 /* wo 16 */
52 #define INT2CLR_REG 0x14 /* wo 16 */
53 /* Analog Input Registers */
54 #define MUX_CNTR_REG 0x04 /* wo 16 */
55 #define MUX_GAIN_REG 0x06 /* wo 16 */
56 #define AD_FIFO_REG 0x16 /* ro 16 */
57 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
58 /* AM9513A Counter/Timer Registers */
59 #define AM9513A_DATA_REG 0x18 /* rw 16 */
60 #define AM9513A_COM_REG 0x1A /* wo 16 */
61 #define AM9513A_STAT_REG 0x1A /* ro 16 */
62 /* MIO-16 Digital I/O Registers */
63 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
64 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
65 /* RTSI Switch Registers */
66 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
67 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
68 /* DIO-24 Registers */
69 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
70 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
71 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
72 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
73
74 /* Command Register bits */
75 #define COMREG1_2SCADC 0x0001
76 #define COMREG1_1632CNT 0x0002
77 #define COMREG1_SCANEN 0x0008
78 #define COMREG1_DAQEN 0x0010
79 #define COMREG1_DMAEN 0x0020
80 #define COMREG1_CONVINTEN 0x0080
81 #define COMREG2_SCN2 0x0010
82 #define COMREG2_INTEN 0x0080
83 #define COMREG2_DOUTEN0 0x0100
84 #define COMREG2_DOUTEN1 0x0200
85 /* Status Register bits */
86 #define STAT_AD_OVERRUN 0x0100
87 #define STAT_AD_OVERFLOW 0x0200
88 #define STAT_AD_DAQPROG 0x0800
89 #define STAT_AD_CONVAVAIL 0x2000
90 #define STAT_AD_DAQSTOPINT 0x4000
91 /* AM9513A Counter/Timer defines */
92 #define CLOCK_1_MHZ 0x8B25
93 #define CLOCK_100_KHZ 0x8C25
94 #define CLOCK_10_KHZ 0x8D25
95 #define CLOCK_1_KHZ 0x8E25
96 #define CLOCK_100_HZ 0x8F25
97 /* Other miscellaneous defines */
98 #define ATMIO16D_SIZE 32 /* bus address range */
99 #define ATMIO16D_TIMEOUT 10
100
101 struct atmio16_board_t {
102
103 const char *name;
104 int has_8255;
105 };
106
107 /* range structs */
108 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = { 4, {
109 BIP_RANGE
110 (10),
111 BIP_RANGE
112 (1),
113 BIP_RANGE
114 (0.1),
115 BIP_RANGE
116 (0.02)
117 }
118 };
119
120 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = { 4, {
121 BIP_RANGE
122 (5),
123 BIP_RANGE
124 (0.5),
125 BIP_RANGE
126 (0.05),
127 BIP_RANGE
128 (0.01)
129 }
130 };
131
132 static const struct comedi_lrange range_atmio16d_ai_unipolar = { 4, {
133 UNI_RANGE
134 (10),
135 UNI_RANGE
136 (1),
137 UNI_RANGE
138 (0.1),
139 UNI_RANGE
140 (0.02)
141 }
142 };
143
144 /* private data struct */
145 struct atmio16d_private {
146 enum { adc_diff, adc_singleended } adc_mux;
147 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
148 enum { adc_2comp, adc_straight } adc_coding;
149 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
150 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
151 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
152 const struct comedi_lrange *ao_range_type_list[2];
153 unsigned int ao_readback[2];
154 unsigned int com_reg_1_state; /* current state of command register 1 */
155 unsigned int com_reg_2_state; /* current state of command register 2 */
156 };
157
158 static void reset_counters(struct comedi_device *dev)
159 {
160 /* Counter 2 */
161 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
162 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
163 outw(0x4, dev->iobase + AM9513A_DATA_REG);
164 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
165 outw(0x3, dev->iobase + AM9513A_DATA_REG);
166 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
167 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
168 /* Counter 3 */
169 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
170 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
171 outw(0x4, dev->iobase + AM9513A_DATA_REG);
172 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
173 outw(0x3, dev->iobase + AM9513A_DATA_REG);
174 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
175 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
176 /* Counter 4 */
177 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
178 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
179 outw(0x4, dev->iobase + AM9513A_DATA_REG);
180 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
181 outw(0x3, dev->iobase + AM9513A_DATA_REG);
182 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
183 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
184 /* Counter 5 */
185 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
186 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
187 outw(0x4, dev->iobase + AM9513A_DATA_REG);
188 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
189 outw(0x3, dev->iobase + AM9513A_DATA_REG);
190 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
191 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
192
193 outw(0, dev->iobase + AD_CLEAR_REG);
194 }
195
196 static void reset_atmio16d(struct comedi_device *dev)
197 {
198 struct atmio16d_private *devpriv = dev->private;
199 int i;
200
201 /* now we need to initialize the board */
202 outw(0, dev->iobase + COM_REG_1);
203 outw(0, dev->iobase + COM_REG_2);
204 outw(0, dev->iobase + MUX_GAIN_REG);
205 /* init AM9513A timer */
206 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
207 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
208 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
209 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
210 for (i = 1; i <= 5; ++i) {
211 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
212 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
213 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
214 outw(0x3, dev->iobase + AM9513A_DATA_REG);
215 }
216 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
217 /* timer init done */
218 outw(0, dev->iobase + AD_CLEAR_REG);
219 outw(0, dev->iobase + INT2CLR_REG);
220 /* select straight binary mode for Analog Input */
221 devpriv->com_reg_1_state |= 1;
222 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
223 devpriv->adc_coding = adc_straight;
224 /* zero the analog outputs */
225 outw(2048, dev->iobase + DAC0_REG);
226 outw(2048, dev->iobase + DAC1_REG);
227 }
228
229 static irqreturn_t atmio16d_interrupt(int irq, void *d)
230 {
231 struct comedi_device *dev = d;
232 struct comedi_subdevice *s = &dev->subdevices[0];
233
234 comedi_buf_put(s->async, inw(dev->iobase + AD_FIFO_REG));
235
236 comedi_event(dev, s);
237 return IRQ_HANDLED;
238 }
239
240 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
241 struct comedi_subdevice *s,
242 struct comedi_cmd *cmd)
243 {
244 int err = 0;
245
246 /* Step 1 : check if triggers are trivially valid */
247
248 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
249 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
250 TRIG_FOLLOW | TRIG_TIMER);
251 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
252 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
253 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
254
255 if (err)
256 return 1;
257
258 /* Step 2a : make sure trigger sources are unique */
259
260 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
261 err |= cfc_check_trigger_is_unique(cmd->stop_src);
262
263 /* Step 2b : and mutually compatible */
264
265 if (err)
266 return 2;
267
268 /* Step 3: check if arguments are trivially valid */
269
270 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
271
272 if (cmd->scan_begin_src == TRIG_FOLLOW) {
273 /* internal trigger */
274 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
275 } else {
276 #if 0
277 /* external trigger */
278 /* should be level/edge, hi/lo specification here */
279 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
280 #endif
281 }
282
283 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 10000);
284 #if 0
285 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, SLOWEST_TIMER);
286 #endif
287
288 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
289
290 if (cmd->stop_src == TRIG_COUNT) {
291 /* any count is allowed */
292 } else { /* TRIG_NONE */
293 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
294 }
295
296 if (err)
297 return 3;
298
299 return 0;
300 }
301
302 static int atmio16d_ai_cmd(struct comedi_device *dev,
303 struct comedi_subdevice *s)
304 {
305 struct atmio16d_private *devpriv = dev->private;
306 struct comedi_cmd *cmd = &s->async->cmd;
307 unsigned int timer, base_clock;
308 unsigned int sample_count, tmp, chan, gain;
309 int i;
310
311 /* This is slowly becoming a working command interface. *
312 * It is still uber-experimental */
313
314 reset_counters(dev);
315 s->async->cur_chan = 0;
316
317 /* check if scanning multiple channels */
318 if (cmd->chanlist_len < 2) {
319 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
320 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
321 } else {
322 devpriv->com_reg_1_state |= COMREG1_SCANEN;
323 devpriv->com_reg_2_state |= COMREG2_SCN2;
324 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
325 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
326 }
327
328 /* Setup the Mux-Gain Counter */
329 for (i = 0; i < cmd->chanlist_len; ++i) {
330 chan = CR_CHAN(cmd->chanlist[i]);
331 gain = CR_RANGE(cmd->chanlist[i]);
332 outw(i, dev->iobase + MUX_CNTR_REG);
333 tmp = chan | (gain << 6);
334 if (i == cmd->scan_end_arg - 1)
335 tmp |= 0x0010; /* set LASTONE bit */
336 outw(tmp, dev->iobase + MUX_GAIN_REG);
337 }
338
339 /* Now program the sample interval timer */
340 /* Figure out which clock to use then get an
341 * appropriate timer value */
342 if (cmd->convert_arg < 65536000) {
343 base_clock = CLOCK_1_MHZ;
344 timer = cmd->convert_arg / 1000;
345 } else if (cmd->convert_arg < 655360000) {
346 base_clock = CLOCK_100_KHZ;
347 timer = cmd->convert_arg / 10000;
348 } else if (cmd->convert_arg <= 0xffffffff /* 6553600000 */) {
349 base_clock = CLOCK_10_KHZ;
350 timer = cmd->convert_arg / 100000;
351 } else if (cmd->convert_arg <= 0xffffffff /* 65536000000 */) {
352 base_clock = CLOCK_1_KHZ;
353 timer = cmd->convert_arg / 1000000;
354 }
355 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
356 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
357 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
358 outw(0x2, dev->iobase + AM9513A_DATA_REG);
359 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
360 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
361 outw(timer, dev->iobase + AM9513A_DATA_REG);
362 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
363
364 /* Now figure out how many samples to get */
365 /* and program the sample counter */
366 sample_count = cmd->stop_arg * cmd->scan_end_arg;
367 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
368 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
369 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
370 if (sample_count < 65536) {
371 /* use only Counter 4 */
372 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
373 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
374 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
375 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
376 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
377 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
378 } else {
379 /* Counter 4 and 5 are needed */
380
381 tmp = sample_count & 0xFFFF;
382 if (tmp)
383 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
384 else
385 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
386
387 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
388 outw(0, dev->iobase + AM9513A_DATA_REG);
389 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
390 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
391 outw(0x25, dev->iobase + AM9513A_DATA_REG);
392 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
393 tmp = sample_count & 0xFFFF;
394 if ((tmp == 0) || (tmp == 1)) {
395 outw((sample_count >> 16) & 0xFFFF,
396 dev->iobase + AM9513A_DATA_REG);
397 } else {
398 outw(((sample_count >> 16) & 0xFFFF) + 1,
399 dev->iobase + AM9513A_DATA_REG);
400 }
401 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
402 devpriv->com_reg_1_state |= COMREG1_1632CNT;
403 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
404 }
405
406 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
407 /* Figure out which clock to use then get an
408 * appropriate timer value */
409 if (cmd->chanlist_len > 1) {
410 if (cmd->scan_begin_arg < 65536000) {
411 base_clock = CLOCK_1_MHZ;
412 timer = cmd->scan_begin_arg / 1000;
413 } else if (cmd->scan_begin_arg < 655360000) {
414 base_clock = CLOCK_100_KHZ;
415 timer = cmd->scan_begin_arg / 10000;
416 } else if (cmd->scan_begin_arg < 0xffffffff /* 6553600000 */) {
417 base_clock = CLOCK_10_KHZ;
418 timer = cmd->scan_begin_arg / 100000;
419 } else if (cmd->scan_begin_arg < 0xffffffff /* 65536000000 */) {
420 base_clock = CLOCK_1_KHZ;
421 timer = cmd->scan_begin_arg / 1000000;
422 }
423 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
424 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
425 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
426 outw(0x2, dev->iobase + AM9513A_DATA_REG);
427 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
428 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
429 outw(timer, dev->iobase + AM9513A_DATA_REG);
430 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
431 }
432
433 /* Clear the A/D FIFO and reset the MUX counter */
434 outw(0, dev->iobase + AD_CLEAR_REG);
435 outw(0, dev->iobase + MUX_CNTR_REG);
436 outw(0, dev->iobase + INT2CLR_REG);
437 /* enable this acquisition operation */
438 devpriv->com_reg_1_state |= COMREG1_DAQEN;
439 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
440 /* enable interrupts for conversion completion */
441 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
442 devpriv->com_reg_2_state |= COMREG2_INTEN;
443 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
444 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
445 /* apply a trigger. this starts the counters! */
446 outw(0, dev->iobase + START_DAQ_REG);
447
448 return 0;
449 }
450
451 /* This will cancel a running acquisition operation */
452 static int atmio16d_ai_cancel(struct comedi_device *dev,
453 struct comedi_subdevice *s)
454 {
455 reset_atmio16d(dev);
456
457 return 0;
458 }
459
460 /* Mode 0 is used to get a single conversion on demand */
461 static int atmio16d_ai_insn_read(struct comedi_device *dev,
462 struct comedi_subdevice *s,
463 struct comedi_insn *insn, unsigned int *data)
464 {
465 struct atmio16d_private *devpriv = dev->private;
466 int i, t;
467 int chan;
468 int gain;
469 int status;
470
471 chan = CR_CHAN(insn->chanspec);
472 gain = CR_RANGE(insn->chanspec);
473
474 /* reset the Analog input circuitry */
475 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
476 /* reset the Analog Input MUX Counter to 0 */
477 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
478
479 /* set the Input MUX gain */
480 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
481
482 for (i = 0; i < insn->n; i++) {
483 /* start the conversion */
484 outw(0, dev->iobase + START_CONVERT_REG);
485 /* wait for it to finish */
486 for (t = 0; t < ATMIO16D_TIMEOUT; t++) {
487 /* check conversion status */
488 status = inw(dev->iobase + STAT_REG);
489 if (status & STAT_AD_CONVAVAIL) {
490 /* read the data now */
491 data[i] = inw(dev->iobase + AD_FIFO_REG);
492 /* change to two's complement if need be */
493 if (devpriv->adc_coding == adc_2comp)
494 data[i] ^= 0x800;
495 break;
496 }
497 if (status & STAT_AD_OVERFLOW) {
498 printk(KERN_INFO "atmio16d: a/d FIFO overflow\n");
499 outw(0, dev->iobase + AD_CLEAR_REG);
500
501 return -ETIME;
502 }
503 }
504 /* end waiting, now check if it timed out */
505 if (t == ATMIO16D_TIMEOUT) {
506 printk(KERN_INFO "atmio16d: timeout\n");
507
508 return -ETIME;
509 }
510 }
511
512 return i;
513 }
514
515 static int atmio16d_ao_insn_read(struct comedi_device *dev,
516 struct comedi_subdevice *s,
517 struct comedi_insn *insn, unsigned int *data)
518 {
519 struct atmio16d_private *devpriv = dev->private;
520 int i;
521
522 for (i = 0; i < insn->n; i++)
523 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
524 return i;
525 }
526
527 static int atmio16d_ao_insn_write(struct comedi_device *dev,
528 struct comedi_subdevice *s,
529 struct comedi_insn *insn, unsigned int *data)
530 {
531 struct atmio16d_private *devpriv = dev->private;
532 int i;
533 int chan;
534 int d;
535
536 chan = CR_CHAN(insn->chanspec);
537
538 for (i = 0; i < insn->n; i++) {
539 d = data[i];
540 switch (chan) {
541 case 0:
542 if (devpriv->dac0_coding == dac_2comp)
543 d ^= 0x800;
544 outw(d, dev->iobase + DAC0_REG);
545 break;
546 case 1:
547 if (devpriv->dac1_coding == dac_2comp)
548 d ^= 0x800;
549 outw(d, dev->iobase + DAC1_REG);
550 break;
551 default:
552 return -EINVAL;
553 }
554 devpriv->ao_readback[chan] = data[i];
555 }
556 return i;
557 }
558
559 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
560 struct comedi_subdevice *s,
561 struct comedi_insn *insn,
562 unsigned int *data)
563 {
564 if (comedi_dio_update_state(s, data))
565 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
566
567 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
568
569 return insn->n;
570 }
571
572 static int atmio16d_dio_insn_config(struct comedi_device *dev,
573 struct comedi_subdevice *s,
574 struct comedi_insn *insn,
575 unsigned int *data)
576 {
577 struct atmio16d_private *devpriv = dev->private;
578 unsigned int chan = CR_CHAN(insn->chanspec);
579 unsigned int mask;
580 int ret;
581
582 if (chan < 4)
583 mask = 0x0f;
584 else
585 mask = 0xf0;
586
587 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
588 if (ret)
589 return ret;
590
591 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
592 if (s->io_bits & 0x0f)
593 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
594 if (s->io_bits & 0xf0)
595 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
596 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
597
598 return insn->n;
599 }
600
601 /*
602 options[0] - I/O port
603 options[1] - MIO irq
604 0 == no irq
605 N == irq N {3,4,5,6,7,9,10,11,12,14,15}
606 options[2] - DIO irq
607 0 == no irq
608 N == irq N {3,4,5,6,7,9}
609 options[3] - DMA1 channel
610 0 == no DMA
611 N == DMA N {5,6,7}
612 options[4] - DMA2 channel
613 0 == no DMA
614 N == DMA N {5,6,7}
615
616 options[5] - a/d mux
617 0=differential, 1=single
618 options[6] - a/d range
619 0=bipolar10, 1=bipolar5, 2=unipolar10
620
621 options[7] - dac0 range
622 0=bipolar, 1=unipolar
623 options[8] - dac0 reference
624 0=internal, 1=external
625 options[9] - dac0 coding
626 0=2's comp, 1=straight binary
627
628 options[10] - dac1 range
629 options[11] - dac1 reference
630 options[12] - dac1 coding
631 */
632
633 static int atmio16d_attach(struct comedi_device *dev,
634 struct comedi_devconfig *it)
635 {
636 const struct atmio16_board_t *board = comedi_board(dev);
637 struct atmio16d_private *devpriv;
638 struct comedi_subdevice *s;
639 unsigned int irq;
640 int ret;
641
642 ret = comedi_request_region(dev, it->options[0], ATMIO16D_SIZE);
643 if (ret)
644 return ret;
645
646 ret = comedi_alloc_subdevices(dev, 4);
647 if (ret)
648 return ret;
649
650 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
651 if (!devpriv)
652 return -ENOMEM;
653
654 /* reset the atmio16d hardware */
655 reset_atmio16d(dev);
656
657 /* check if our interrupt is available and get it */
658 irq = it->options[1];
659 if (irq) {
660
661 ret = request_irq(irq, atmio16d_interrupt, 0, "atmio16d", dev);
662 if (ret < 0) {
663 printk(KERN_INFO "failed to allocate irq %u\n", irq);
664 return ret;
665 }
666 dev->irq = irq;
667 printk(KERN_INFO "( irq = %u )\n", irq);
668 } else {
669 printk(KERN_INFO "( no irq )");
670 }
671
672 /* set device options */
673 devpriv->adc_mux = it->options[5];
674 devpriv->adc_range = it->options[6];
675
676 devpriv->dac0_range = it->options[7];
677 devpriv->dac0_reference = it->options[8];
678 devpriv->dac0_coding = it->options[9];
679 devpriv->dac1_range = it->options[10];
680 devpriv->dac1_reference = it->options[11];
681 devpriv->dac1_coding = it->options[12];
682
683 /* setup sub-devices */
684 s = &dev->subdevices[0];
685 dev->read_subdev = s;
686 /* ai subdevice */
687 s->type = COMEDI_SUBD_AI;
688 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_CMD_READ;
689 s->n_chan = (devpriv->adc_mux ? 16 : 8);
690 s->len_chanlist = 16;
691 s->insn_read = atmio16d_ai_insn_read;
692 s->do_cmdtest = atmio16d_ai_cmdtest;
693 s->do_cmd = atmio16d_ai_cmd;
694 s->cancel = atmio16d_ai_cancel;
695 s->maxdata = 0xfff; /* 4095 decimal */
696 switch (devpriv->adc_range) {
697 case adc_bipolar10:
698 s->range_table = &range_atmio16d_ai_10_bipolar;
699 break;
700 case adc_bipolar5:
701 s->range_table = &range_atmio16d_ai_5_bipolar;
702 break;
703 case adc_unipolar10:
704 s->range_table = &range_atmio16d_ai_unipolar;
705 break;
706 }
707
708 /* ao subdevice */
709 s = &dev->subdevices[1];
710 s->type = COMEDI_SUBD_AO;
711 s->subdev_flags = SDF_WRITABLE;
712 s->n_chan = 2;
713 s->insn_read = atmio16d_ao_insn_read;
714 s->insn_write = atmio16d_ao_insn_write;
715 s->maxdata = 0xfff; /* 4095 decimal */
716 s->range_table_list = devpriv->ao_range_type_list;
717 switch (devpriv->dac0_range) {
718 case dac_bipolar:
719 devpriv->ao_range_type_list[0] = &range_bipolar10;
720 break;
721 case dac_unipolar:
722 devpriv->ao_range_type_list[0] = &range_unipolar10;
723 break;
724 }
725 switch (devpriv->dac1_range) {
726 case dac_bipolar:
727 devpriv->ao_range_type_list[1] = &range_bipolar10;
728 break;
729 case dac_unipolar:
730 devpriv->ao_range_type_list[1] = &range_unipolar10;
731 break;
732 }
733
734 /* Digital I/O */
735 s = &dev->subdevices[2];
736 s->type = COMEDI_SUBD_DIO;
737 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
738 s->n_chan = 8;
739 s->insn_bits = atmio16d_dio_insn_bits;
740 s->insn_config = atmio16d_dio_insn_config;
741 s->maxdata = 1;
742 s->range_table = &range_digital;
743
744 /* 8255 subdevice */
745 s = &dev->subdevices[3];
746 if (board->has_8255)
747 subdev_8255_init(dev, s, NULL, dev->iobase);
748 else
749 s->type = COMEDI_SUBD_UNUSED;
750
751 /* don't yet know how to deal with counter/timers */
752 #if 0
753 s = &dev->subdevices[4];
754 /* do */
755 s->type = COMEDI_SUBD_TIMER;
756 s->n_chan = 0;
757 s->maxdata = 0
758 #endif
759 printk("\n");
760
761 return 0;
762 }
763
764 static void atmio16d_detach(struct comedi_device *dev)
765 {
766 reset_atmio16d(dev);
767 comedi_legacy_detach(dev);
768 }
769
770 static const struct atmio16_board_t atmio16_boards[] = {
771 {
772 .name = "atmio16",
773 .has_8255 = 0,
774 }, {
775 .name = "atmio16d",
776 .has_8255 = 1,
777 },
778 };
779
780 static struct comedi_driver atmio16d_driver = {
781 .driver_name = "atmio16",
782 .module = THIS_MODULE,
783 .attach = atmio16d_attach,
784 .detach = atmio16d_detach,
785 .board_name = &atmio16_boards[0].name,
786 .num_names = ARRAY_SIZE(atmio16_boards),
787 .offset = sizeof(struct atmio16_board_t),
788 };
789 module_comedi_driver(atmio16d_driver);
790
791 MODULE_AUTHOR("Comedi http://www.comedi.org");
792 MODULE_DESCRIPTION("Comedi low-level driver");
793 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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