drivers/staging/comedi/drivers/plx9080.h

   1 /*
   2  * plx9080.h
   3  *
   4  * Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net>
   5  *
   6  * I modified this file from the plx9060.h header for the
   7  * wanXL device driver in the linux kernel,
   8  * for the register offsets and bit definitions.  Made minor modifications,
   9  * added plx9080 registers and
  10  * stripped out stuff that was specifically for the wanXL driver.
  11  * Note: I've only made sure the definitions are correct as far
  12  * as I make use of them.  There are still various plx9060-isms
  13  * left in this header file.
  14  *
  15  ********************************************************************
  16  *
  17  * Copyright (C) 1999 RG Studio s.c.
  18  * Written by Krzysztof Halasa <khc@rgstudio.com.pl>
  19  *
  20  * Portions (C) SBE Inc., used by permission.
  21  *
  22  * This program is free software; you can redistribute it and/or
  23  * modify it under the terms of the GNU General Public License
  24  * as published by the Free Software Foundation; either version
  25  * 2 of the License, or (at your option) any later version.
  26  */
  27
  28 #ifndef __COMEDI_PLX9080_H
  29 #define __COMEDI_PLX9080_H
  30
  31 /*  descriptor block used for chained dma transfers */
  32 struct plx_dma_desc {
  33         __le32 pci_start_addr;
  34         __le32 local_start_addr;
  35         /* transfer_size is in bytes, only first 23 bits of register are used */
  36         __le32 transfer_size;
  37         /*
  38          * address of next descriptor (quad word aligned), plus some
  39          * additional bits (see PLX_DMA0_DESCRIPTOR_REG)
  40          */
  41         __le32 next;
  42 };
  43
  44 /**********************************************************************
  45 **            Register Offsets and Bit Definitions
  46 **
  47 ** Note: All offsets zero relative.  IE. Some standard base address
  48 ** must be added to the Register Number to properly access the register.
  49 **
  50 **********************************************************************/
  51
  52 /* L, Local Addr Space 0 Range Register */
  53 #define PLX_LAS0RNG_REG         0x0000
  54 /* L, Local Addr Space 1 Range Register */
  55 #define PLX_LAS1RNG_REG         0x00f0
  56 #define  LRNG_IO           0x00000001   /* Map to: 1=I/O, 0=Mem */
  57 #define  LRNG_ANY32        0x00000000   /* Locate anywhere in 32 bit */
  58 #define  LRNG_LT1MB        0x00000002   /* Locate in 1st meg */
  59 #define  LRNG_ANY64        0x00000004   /* Locate anywhere in 64 bit */
  60 /*  bits that specify range for memory io */
  61 #define  LRNG_MEM_MASK     0xfffffff0
  62 /*  bits that specify range for normal io */
  63 #define  LRNG_IO_MASK     0xfffffffa
  64 /* L, Local Addr Space 0 Remap Register */
  65 #define PLX_LAS0MAP_REG         0x0004
  66 /* L, Local Addr Space 1 Remap Register */
  67 #define PLX_LAS1MAP_REG         0x00f4
  68 #define  LMAP_EN           0x00000001   /* Enable slave decode */
  69 /*  bits that specify decode for memory io */
  70 #define  LMAP_MEM_MASK     0xfffffff0
  71 /*  bits that specify decode bits for normal io */
  72 #define  LMAP_IO_MASK     0xfffffffa
  73
  74 /*
  75  * Mode/Arbitration Register.
  76  */
  77 #define PLX_MARB_REG         0x8        /* L, Local Arbitration Register */
  78 #define PLX_DMAARB_REG      0xac
  79 enum marb_bits {
  80         MARB_LLT_MASK = 0x000000ff,     /* Local Bus Latency Timer */
  81         MARB_LPT_MASK = 0x0000ff00,     /* Local Bus Pause Timer */
  82         MARB_LTEN = 0x00010000, /* Latency Timer Enable */
  83         MARB_LPEN = 0x00020000, /* Pause Timer Enable */
  84         MARB_BREQ = 0x00040000, /* Local Bus BREQ Enable */
  85         MARB_DMA_PRIORITY_MASK = 0x00180000,
  86         /* local bus direct slave give up bus mode */
  87         MARB_LBDS_GIVE_UP_BUS_MODE = 0x00200000,
  88         /* direct slave LLOCKo# enable */
  89         MARB_DS_LLOCK_ENABLE = 0x00400000,
  90         MARB_PCI_REQUEST_MODE = 0x00800000,
  91         MARB_PCIv21_MODE = 0x01000000,  /* pci specification v2.1 mode */
  92         MARB_PCI_READ_NO_WRITE_MODE = 0x02000000,
  93         MARB_PCI_READ_WITH_WRITE_FLUSH_MODE = 0x04000000,
  94         /* gate local bus latency timer with BREQ */
  95         MARB_GATE_TIMER_WITH_BREQ = 0x08000000,
  96         MARB_PCI_READ_NO_FLUSH_MODE = 0x10000000,
  97         MARB_USE_SUBSYSTEM_IDS = 0x20000000,
  98 };
  99
 100 #define PLX_BIGEND_REG 0xc
 101 enum bigend_bits {
 102         /* use big endian ordering for configuration register accesses */
 103         BIGEND_CONFIG = 0x1,
 104         BIGEND_DIRECT_MASTER = 0x2,
 105         BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4,
 106         BIGEND_ROM = 0x8,
 107         /*
 108          * use byte lane consisting of most significant bits instead of
 109          * least significant
 110          */
 111         BIGEND_BYTE_LANE = 0x10,
 112         BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20,
 113         BIGEND_DMA1 = 0x40,
 114         BIGEND_DMA0 = 0x80,
 115 };
 116
 117 /*
 118 ** Note: The Expansion ROM  stuff is only relevant to the PC environment.
 119 **       This expansion ROM code is executed by the host CPU at boot time.
 120 **       For this reason no bit definitions are provided here.
 121  */
 122 #define PLX_ROMRNG_REG         0x0010   /* L, Expn ROM Space Range Register */
 123 /* L, Local Addr Space Range Register */
 124 #define PLX_ROMMAP_REG         0x0014
 125
 126 #define PLX_REGION0_REG         0x0018  /* L, Local Bus Region 0 Descriptor */
 127 #define  RGN_WIDTH         0x00000002   /* Local bus width bits */
 128 #define  RGN_8BITS         0x00000000   /* 08 bit Local Bus */
 129 #define  RGN_16BITS        0x00000001   /* 16 bit Local Bus */
 130 #define  RGN_32BITS        0x00000002   /* 32 bit Local Bus */
 131 #define  RGN_MWS           0x0000003C   /* Memory Access Wait States */
 132 #define  RGN_0MWS          0x00000000
 133 #define  RGN_1MWS          0x00000004
 134 #define  RGN_2MWS          0x00000008
 135 #define  RGN_3MWS          0x0000000C
 136 #define  RGN_4MWS          0x00000010
 137 #define  RGN_6MWS          0x00000018
 138 #define  RGN_8MWS          0x00000020
 139 #define  RGN_MRE           0x00000040   /* Memory Space Ready Input Enable */
 140 #define  RGN_MBE           0x00000080   /* Memory Space Bterm Input Enable */
 141 #define  RGN_READ_PREFETCH_DISABLE 0x00000100
 142 #define  RGN_ROM_PREFETCH_DISABLE 0x00000200
 143 #define  RGN_READ_PREFETCH_COUNT_ENABLE 0x00000400
 144 #define  RGN_RWS           0x003C0000   /* Expn ROM Wait States */
 145 #define  RGN_RRE           0x00400000   /* ROM Space Ready Input Enable */
 146 #define  RGN_RBE           0x00800000   /* ROM Space Bterm Input Enable */
 147 #define  RGN_MBEN          0x01000000   /* Memory Space Burst Enable */
 148 #define  RGN_RBEN          0x04000000   /* ROM Space Burst Enable */
 149 #define  RGN_THROT         0x08000000   /* De-assert TRDY when FIFO full */
 150 #define  RGN_TRD           0xF0000000   /* Target Ready Delay /8 */
 151
 152 #define PLX_REGION1_REG         0x00f8  /* L, Local Bus Region 1 Descriptor */
 153
 154 #define PLX_DMRNG_REG          0x001C   /* L, Direct Master Range Register */
 155
 156 #define PLX_LBAPMEM_REG        0x0020   /* L, Lcl Base Addr for PCI mem space */
 157
 158 #define PLX_LBAPIO_REG         0x0024   /* L, Lcl Base Addr for PCI I/O space */
 159
 160 #define PLX_DMMAP_REG          0x0028   /* L, Direct Master Remap Register */
 161 #define  DMM_MAE           0x00000001   /* Direct Mstr Memory Acc Enable */
 162 #define  DMM_IAE           0x00000002   /* Direct Mstr I/O Acc Enable */
 163 #define  DMM_LCK           0x00000004   /* LOCK Input Enable */
 164 #define  DMM_PF4           0x00000008   /* Prefetch 4 Mode Enable */
 165 #define  DMM_THROT         0x00000010   /* Assert IRDY when read FIFO full */
 166 #define  DMM_PAF0          0x00000000   /* Programmable Almost fill level */
 167 #define  DMM_PAF1          0x00000020   /* Programmable Almost fill level */
 168 #define  DMM_PAF2          0x00000040   /* Programmable Almost fill level */
 169 #define  DMM_PAF3          0x00000060   /* Programmable Almost fill level */
 170 #define  DMM_PAF4          0x00000080   /* Programmable Almost fill level */
 171 #define  DMM_PAF5          0x000000A0   /* Programmable Almost fill level */
 172 #define  DMM_PAF6          0x000000C0   /* Programmable Almost fill level */
 173 #define  DMM_PAF7          0x000000D0   /* Programmable Almost fill level */
 174 #define  DMM_MAP           0xFFFF0000   /* Remap Address Bits */
 175
 176 #define PLX_CAR_REG            0x002C   /* L, Configuration Address Register */
 177 #define  CAR_CT0           0x00000000   /* Config Type 0 */
 178 #define  CAR_CT1           0x00000001   /* Config Type 1 */
 179 #define  CAR_REG           0x000000FC   /* Register Number Bits */
 180 #define  CAR_FUN           0x00000700   /* Function Number Bits */
 181 #define  CAR_DEV           0x0000F800   /* Device Number Bits */
 182 #define  CAR_BUS           0x00FF0000   /* Bus Number Bits */
 183 #define  CAR_CFG           0x80000000   /* Config Spc Access Enable */
 184
 185 #define PLX_DBR_IN_REG         0x0060   /* L, PCI to Local Doorbell Register */
 186
 187 #define PLX_DBR_OUT_REG        0x0064   /* L, Local to PCI Doorbell Register */
 188
 189 #define PLX_INTRCS_REG         0x0068   /* L, Interrupt Control/Status Reg */
 190 #define  ICS_AERR          0x00000001   /* Assert LSERR on ABORT */
 191 #define  ICS_PERR          0x00000002   /* Assert LSERR on Parity Error */
 192 #define  ICS_SERR          0x00000004   /* Generate PCI SERR# */
 193 #define  ICS_MBIE          0x00000008   /*  mailbox interrupt enable */
 194 #define  ICS_PIE           0x00000100   /* PCI Interrupt Enable */
 195 #define  ICS_PDIE          0x00000200   /* PCI Doorbell Interrupt Enable */
 196 #define  ICS_PAIE          0x00000400   /* PCI Abort Interrupt Enable */
 197 #define  ICS_PLIE          0x00000800   /* PCI Local Int Enable */
 198 #define  ICS_RAE           0x00001000   /* Retry Abort Enable */
 199 #define  ICS_PDIA          0x00002000   /* PCI Doorbell Interrupt Active */
 200 #define  ICS_PAIA          0x00004000   /* PCI Abort Interrupt Active */
 201 #define  ICS_LIA           0x00008000   /* Local Interrupt Active */
 202 #define  ICS_LIE           0x00010000   /* Local Interrupt Enable */
 203 #define  ICS_LDIE          0x00020000   /* Local Doorbell Int Enable */
 204 #define  ICS_DMA0_E        0x00040000   /* DMA #0 Interrupt Enable */
 205 #define  ICS_DMA1_E        0x00080000   /* DMA #1 Interrupt Enable */
 206 #define  ICS_LDIA          0x00100000   /* Local Doorbell Int Active */
 207 #define  ICS_DMA0_A        0x00200000   /* DMA #0 Interrupt Active */
 208 #define  ICS_DMA1_A        0x00400000   /* DMA #1 Interrupt Active */
 209 #define  ICS_BIA           0x00800000   /* BIST Interrupt Active */
 210 #define  ICS_TA_DM         0x01000000   /* Target Abort - Direct Master */
 211 #define  ICS_TA_DMA0       0x02000000   /* Target Abort - DMA #0 */
 212 #define  ICS_TA_DMA1       0x04000000   /* Target Abort - DMA #1 */
 213 #define  ICS_TA_RA         0x08000000   /* Target Abort - Retry Timeout */
 214 /*  mailbox x is active */
 215 #define  ICS_MBIA(x)       (0x10000000 << ((x) & 0x3))
 216
 217 #define PLX_CONTROL_REG        0x006C   /* L, EEPROM Cntl & PCI Cmd Codes */
 218 #define  CTL_RDMA          0x0000000E   /* DMA Read Command */
 219 #define  CTL_WDMA          0x00000070   /* DMA Write Command */
 220 #define  CTL_RMEM          0x00000600   /* Memory Read Command */
 221 #define  CTL_WMEM          0x00007000   /* Memory Write Command */
 222 #define  CTL_USERO         0x00010000   /* USERO output pin control bit */
 223 #define  CTL_USERI         0x00020000   /* USERI input pin bit */
 224 #define  CTL_EE_CLK        0x01000000   /* EEPROM Clock line */
 225 #define  CTL_EE_CS         0x02000000   /* EEPROM Chip Select */
 226 #define  CTL_EE_W          0x04000000   /* EEPROM Write bit */
 227 #define  CTL_EE_R          0x08000000   /* EEPROM Read bit */
 228 #define  CTL_EECHK         0x10000000   /* EEPROM Present bit */
 229 #define  CTL_EERLD         0x20000000   /* EEPROM Reload Register */
 230 #define  CTL_RESET         0x40000000   /* !! Adapter Reset !! */
 231 #define  CTL_READY         0x80000000   /* Local Init Done */
 232
 233 #define PLX_ID_REG      0x70    /*  hard-coded plx vendor and device ids */
 234
 235 #define PLX_REVISION_REG        0x74    /*  silicon revision */
 236
 237 #define PLX_DMA0_MODE_REG       0x80    /*  dma channel 0 mode register */
 238 #define PLX_DMA1_MODE_REG       0x94    /*  dma channel 0 mode register */
 239 #define  PLX_LOCAL_BUS_16_WIDE_BITS     0x1
 240 #define  PLX_LOCAL_BUS_32_WIDE_BITS     0x3
 241 #define  PLX_LOCAL_BUS_WIDTH_MASK       0x3
 242 #define  PLX_DMA_EN_READYIN_BIT 0x40    /*  enable ready in input */
 243 #define  PLX_EN_BTERM_BIT       0x80    /*  enable BTERM# input */
 244 #define  PLX_DMA_LOCAL_BURST_EN_BIT     0x100   /*  enable local burst mode */
 245 #define  PLX_EN_CHAIN_BIT       0x200   /*  enables chaining */
 246 /*  enables interrupt on dma done */
 247 #define  PLX_EN_DMA_DONE_INTR_BIT       0x400
 248 /*  hold local address constant (don't increment) */
 249 #define  PLX_LOCAL_ADDR_CONST_BIT       0x800
 250 /*  enables demand-mode for dma transfer */
 251 #define  PLX_DEMAND_MODE_BIT    0x1000
 252 #define  PLX_EOT_ENABLE_BIT     0x4000
 253 #define  PLX_STOP_MODE_BIT 0x8000
 254 /*  routes dma interrupt to pci bus (instead of local bus) */
 255 #define  PLX_DMA_INTR_PCI_BIT   0x20000
 256
 257 /*  pci address that dma transfers start at */
 258 #define PLX_DMA0_PCI_ADDRESS_REG        0x84
 259 #define PLX_DMA1_PCI_ADDRESS_REG        0x98
 260
 261 /*  local address that dma transfers start at */
 262 #define PLX_DMA0_LOCAL_ADDRESS_REG      0x88
 263 #define PLX_DMA1_LOCAL_ADDRESS_REG      0x9c
 264
 265 /*  number of bytes to transfer (first 23 bits) */
 266 #define PLX_DMA0_TRANSFER_SIZE_REG      0x8c
 267 #define PLX_DMA1_TRANSFER_SIZE_REG      0xa0
 268
 269 #define PLX_DMA0_DESCRIPTOR_REG 0x90    /*  descriptor pointer register */
 270 #define PLX_DMA1_DESCRIPTOR_REG 0xa4
 271 /*  descriptor is located in pci space (not local space) */
 272 #define  PLX_DESC_IN_PCI_BIT    0x1
 273 #define  PLX_END_OF_CHAIN_BIT   0x2     /*  end of chain bit */
 274 /*  interrupt when this descriptor's transfer is finished */
 275 #define  PLX_INTR_TERM_COUNT    0x4
 276 /*  transfer from local to pci bus (not pci to local) */
 277 #define  PLX_XFER_LOCAL_TO_PCI 0x8
 278
 279 #define PLX_DMA0_CS_REG 0xa8    /*  command status register */
 280 #define PLX_DMA1_CS_REG 0xa9
 281 #define  PLX_DMA_EN_BIT 0x1     /*  enable dma channel */
 282 #define  PLX_DMA_START_BIT      0x2     /*  start dma transfer */
 283 #define  PLX_DMA_ABORT_BIT      0x4     /*  abort dma transfer */
 284 #define  PLX_CLEAR_DMA_INTR_BIT 0x8     /*  clear dma interrupt */
 285 #define  PLX_DMA_DONE_BIT       0x10    /*  transfer done status bit */
 286
 287 #define PLX_DMA0_THRESHOLD_REG  0xb0    /*  command status register */
 288
 289 /*
 290  * Accesses near the end of memory can cause the PLX chip
 291  * to pre-fetch data off of end-of-ram.  Limit the size of
 292  * memory so host-side accesses cannot occur.
 293  */
 294
 295 #define PLX_PREFETCH   32
 296
 297 /*
 298  * The PCI Interface, via the PCI-9060 Chip, has up to eight (8) Mailbox
 299  * Registers.  The PUTS (Power-Up Test Suite) handles the board-side
 300  * interface/interaction using the first 4 registers.  Specifications for
 301  * the use of the full PUTS' command and status interface is contained
 302  * within a separate SBE PUTS Manual.  The Host-Side Device Driver only
 303  * uses a subset of the full PUTS interface.
 304  */
 305
 306 /*****************************************/
 307 /***    MAILBOX #(-1) - MEM ACCESS STS ***/
 308 /*****************************************/
 309
 310 #define MBX_STS_VALID      0x57584744   /* 'WXGD' */
 311 #define MBX_STS_DILAV      0x44475857   /* swapped = 'DGXW' */
 312
 313 /*****************************************/
 314 /***    MAILBOX #0  -  PUTS STATUS     ***/
 315 /*****************************************/
 316
 317 #define MBX_STS_MASK       0x000000ff   /* PUTS Status Register bits */
 318 #define MBX_STS_TMASK      0x0000000f   /* register bits for TEST number */
 319
 320 #define MBX_STS_PCIRESET   0x00000100   /* Host issued PCI reset request */
 321 #define MBX_STS_BUSY       0x00000080   /* PUTS is in progress */
 322 #define MBX_STS_ERROR      0x00000040   /* PUTS has failed */
 323 /*
 324  * Undefined -> status in transition. We are in process of changing bits;
 325  * we SET Error bit before RESET of Busy bit
 326  */
 327 #define MBX_STS_RESERVED   0x000000c0
 328
 329 #define MBX_RESERVED_5     0x00000020   /* FYI: reserved/unused bit */
 330 #define MBX_RESERVED_4     0x00000010   /* FYI: reserved/unused bit */
 331
 332 /******************************************/
 333 /***    MAILBOX #1  -  PUTS COMMANDS    ***/
 334 /******************************************/
 335
 336 /*
 337  * Any attempt to execute an unimplement command results in the PUTS
 338  * interface executing a NOOP and continuing as if the offending command
 339  * completed normally.  Note: this supplies a simple method to interrogate
 340  * mailbox command processing functionality.
 341  */
 342
 343 #define MBX_CMD_MASK       0xffff0000   /* PUTS Command Register bits */
 344
 345 #define MBX_CMD_ABORTJ     0x85000000   /* abort and jump */
 346 #define MBX_CMD_RESETP     0x86000000   /* reset and pause at start */
 347 #define MBX_CMD_PAUSE      0x87000000   /* pause immediately */
 348 #define MBX_CMD_PAUSEC     0x88000000   /* pause on completion */
 349 #define MBX_CMD_RESUME     0x89000000   /* resume operation */
 350 #define MBX_CMD_STEP       0x8a000000   /* single step tests */
 351
 352 #define MBX_CMD_BSWAP      0x8c000000   /* identify byte swap scheme */
 353 #define MBX_CMD_BSWAP_0    0x8c000000   /* use scheme 0 */
 354 #define MBX_CMD_BSWAP_1    0x8c000001   /* use scheme 1 */
 355
 356 /* setup host memory access window size */
 357 #define MBX_CMD_SETHMS     0x8d000000
 358 /* setup host memory access base address */
 359 #define MBX_CMD_SETHBA     0x8e000000
 360 /* perform memory setup and continue (IE. Done) */
 361 #define MBX_CMD_MGO        0x8f000000
 362 #define MBX_CMD_NOOP       0xFF000000   /* dummy, illegal command */
 363
 364 /*****************************************/
 365 /***    MAILBOX #2  -  MEMORY SIZE     ***/
 366 /*****************************************/
 367
 368 #define MBX_MEMSZ_MASK     0xffff0000   /* PUTS Memory Size Register bits */
 369
 370 #define MBX_MEMSZ_128KB    0x00020000   /* 128 kilobyte board */
 371 #define MBX_MEMSZ_256KB    0x00040000   /* 256 kilobyte board */
 372 #define MBX_MEMSZ_512KB    0x00080000   /* 512 kilobyte board */
 373 #define MBX_MEMSZ_1MB      0x00100000   /* 1 megabyte board */
 374 #define MBX_MEMSZ_2MB      0x00200000   /* 2 megabyte board */
 375 #define MBX_MEMSZ_4MB      0x00400000   /* 4 megabyte board */
 376 #define MBX_MEMSZ_8MB      0x00800000   /* 8 megabyte board */
 377 #define MBX_MEMSZ_16MB     0x01000000   /* 16 megabyte board */
 378
 379 /***************************************/
 380 /***    MAILBOX #2  -  BOARD TYPE    ***/
 381 /***************************************/
 382
 383 #define MBX_BTYPE_MASK          0x0000ffff      /* PUTS Board Type Register */
 384 /* PUTS Board Family Register */
 385 #define MBX_BTYPE_FAMILY_MASK   0x0000ff00
 386 #define MBX_BTYPE_SUBTYPE_MASK  0x000000ff      /* PUTS Board Subtype */
 387
 388 #define MBX_BTYPE_PLX9060       0x00000100      /* PLX family type */
 389 #define MBX_BTYPE_PLX9080       0x00000300      /* PLX wanXL100s family type */
 390
 391 #define MBX_BTYPE_WANXL_4       0x00000104      /* wanXL400, 4-port */
 392 #define MBX_BTYPE_WANXL_2       0x00000102      /* wanXL200, 2-port */
 393 #define MBX_BTYPE_WANXL_1s      0x00000301      /* wanXL100s, 1-port */
 394 #define MBX_BTYPE_WANXL_1t      0x00000401      /* wanXL100T1, 1-port */
 395
 396 /*****************************************/
 397 /***    MAILBOX #3  -  SHMQ MAILBOX    ***/
 398 /*****************************************/
 399
 400 #define MBX_SMBX_MASK           0x000000ff      /* PUTS SHMQ Mailbox bits */
 401
 402 /***************************************/
 403 /***    GENERIC HOST-SIDE DRIVER     ***/
 404 /***************************************/
 405
 406 #define MBX_ERR    0
 407 #define MBX_OK     1
 408
 409 /* mailbox check routine - type of testing */
 410 #define MBXCHK_STS      0x00    /* check for PUTS status */
 411 #define MBXCHK_NOWAIT   0x01    /* dont care about PUTS status */
 412
 413 /* system allocates this many bytes for address mapping mailbox space */
 414 #define MBX_ADDR_SPACE_360 0x80 /* wanXL100s/200/400 */
 415 #define MBX_ADDR_MASK_360 (MBX_ADDR_SPACE_360 - 1)
 416
 417 static inline int plx9080_abort_dma(void __iomem *iobase, unsigned int channel)
 418 {
 419         void __iomem *dma_cs_addr;
 420         u8 dma_status;
 421         const int timeout = 10000;
 422         unsigned int i;
 423
 424         if (channel)
 425                 dma_cs_addr = iobase + PLX_DMA1_CS_REG;
 426         else
 427                 dma_cs_addr = iobase + PLX_DMA0_CS_REG;
 428
 429         /*  abort dma transfer if necessary */
 430         dma_status = readb(dma_cs_addr);
 431         if ((dma_status & PLX_DMA_EN_BIT) == 0)
 432                 return 0;
 433
 434         /*  wait to make sure done bit is zero */
 435         for (i = 0; (dma_status & PLX_DMA_DONE_BIT) && i < timeout; i++) {
 436                 udelay(1);
 437                 dma_status = readb(dma_cs_addr);
 438         }
 439         if (i == timeout)
 440                 return -ETIMEDOUT;
 441
 442         /*  disable and abort channel */
 443         writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
 444         /*  wait for dma done bit */
 445         dma_status = readb(dma_cs_addr);
 446         for (i = 0; (dma_status & PLX_DMA_DONE_BIT) == 0 && i < timeout; i++) {
 447                 udelay(1);
 448                 dma_status = readb(dma_cs_addr);
 449         }
 450         if (i == timeout)
 451                 return -ETIMEDOUT;
 452
 453         return 0;
 454 }
 455
 456 #endif /* __COMEDI_PLX9080_H */