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Merge tag 'stable/for-linus-3.14-rc1-tag' of git://git.kernel.org/pub/scm/linux/kerne...
[deliverable/linux.git] / drivers / staging / dgnc / dgnc_neo.c
1 /*
2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 *
20 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE!
21 *
22 * This is shared code between Digi's CVS archive and the
23 * Linux Kernel sources.
24 * Changing the source just for reformatting needlessly breaks
25 * our CVS diff history.
26 *
27 * Send any bug fixes/changes to: Eng.Linux at digi dot com.
28 * Thank you.
29 *
30 */
31
32
33 #include <linux/kernel.h>
34 #include <linux/sched.h> /* For jiffies, task states */
35 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
36 #include <linux/delay.h> /* For udelay */
37 #include <asm/io.h> /* For read[bwl]/write[bwl] */
38 #include <linux/serial.h> /* For struct async_serial */
39 #include <linux/serial_reg.h> /* For the various UART offsets */
40
41 #include "dgnc_driver.h" /* Driver main header file */
42 #include "dgnc_neo.h" /* Our header file */
43 #include "dgnc_tty.h"
44 #include "dgnc_trace.h"
45
46 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
47 static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
48 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
49 static inline void neo_clear_break(struct channel_t *ch, int force);
50 static inline void neo_set_cts_flow_control(struct channel_t *ch);
51 static inline void neo_set_rts_flow_control(struct channel_t *ch);
52 static inline void neo_set_ixon_flow_control(struct channel_t *ch);
53 static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
54 static inline void neo_set_no_output_flow_control(struct channel_t *ch);
55 static inline void neo_set_no_input_flow_control(struct channel_t *ch);
56 static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
57 static void neo_parse_modem(struct channel_t *ch, uchar signals);
58 static void neo_tasklet(unsigned long data);
59 static void neo_vpd(struct dgnc_board *brd);
60 static void neo_uart_init(struct channel_t *ch);
61 static void neo_uart_off(struct channel_t *ch);
62 static int neo_drain(struct tty_struct *tty, uint seconds);
63 static void neo_param(struct tty_struct *tty);
64 static void neo_assert_modem_signals(struct channel_t *ch);
65 static void neo_flush_uart_write(struct channel_t *ch);
66 static void neo_flush_uart_read(struct channel_t *ch);
67 static void neo_disable_receiver(struct channel_t *ch);
68 static void neo_enable_receiver(struct channel_t *ch);
69 static void neo_send_break(struct channel_t *ch, int msecs);
70 static void neo_send_start_character(struct channel_t *ch);
71 static void neo_send_stop_character(struct channel_t *ch);
72 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
73 static uint neo_get_uart_bytes_left(struct channel_t *ch);
74 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
75 static irqreturn_t neo_intr(int irq, void *voidbrd);
76
77
78 struct board_ops dgnc_neo_ops = {
79 .tasklet = neo_tasklet,
80 .intr = neo_intr,
81 .uart_init = neo_uart_init,
82 .uart_off = neo_uart_off,
83 .drain = neo_drain,
84 .param = neo_param,
85 .vpd = neo_vpd,
86 .assert_modem_signals = neo_assert_modem_signals,
87 .flush_uart_write = neo_flush_uart_write,
88 .flush_uart_read = neo_flush_uart_read,
89 .disable_receiver = neo_disable_receiver,
90 .enable_receiver = neo_enable_receiver,
91 .send_break = neo_send_break,
92 .send_start_character = neo_send_start_character,
93 .send_stop_character = neo_send_stop_character,
94 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
95 .get_uart_bytes_left = neo_get_uart_bytes_left,
96 .send_immediate_char = neo_send_immediate_char
97 };
98
99 static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
100
101
102 /*
103 * This function allows calls to ensure that all outstanding
104 * PCI writes have been completed, by doing a PCI read against
105 * a non-destructive, read-only location on the Neo card.
106 *
107 * In this case, we are reading the DVID (Read-only Device Identification)
108 * value of the Neo card.
109 */
110 static inline void neo_pci_posting_flush(struct dgnc_board *bd)
111 {
112 readb(bd->re_map_membase + 0x8D);
113 }
114
115 static inline void neo_set_cts_flow_control(struct channel_t *ch)
116 {
117 uchar ier = readb(&ch->ch_neo_uart->ier);
118 uchar efr = readb(&ch->ch_neo_uart->efr);
119
120
121 DPR_PARAM(("Setting CTSFLOW\n"));
122
123 /* Turn on auto CTS flow control */
124 #if 1
125 ier |= (UART_17158_IER_CTSDSR);
126 #else
127 ier &= ~(UART_17158_IER_CTSDSR);
128 #endif
129
130 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
131
132 /* Turn off auto Xon flow control */
133 efr &= ~(UART_17158_EFR_IXON);
134
135 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
136 writeb(0, &ch->ch_neo_uart->efr);
137
138 /* Turn on UART enhanced bits */
139 writeb(efr, &ch->ch_neo_uart->efr);
140
141 /* Turn on table D, with 8 char hi/low watermarks */
142 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
143
144 /* Feed the UART our trigger levels */
145 writeb(8, &ch->ch_neo_uart->tfifo);
146 ch->ch_t_tlevel = 8;
147
148 writeb(ier, &ch->ch_neo_uart->ier);
149
150 neo_pci_posting_flush(ch->ch_bd);
151 }
152
153
154 static inline void neo_set_rts_flow_control(struct channel_t *ch)
155 {
156 uchar ier = readb(&ch->ch_neo_uart->ier);
157 uchar efr = readb(&ch->ch_neo_uart->efr);
158
159 DPR_PARAM(("Setting RTSFLOW\n"));
160
161 /* Turn on auto RTS flow control */
162 #if 1
163 ier |= (UART_17158_IER_RTSDTR);
164 #else
165 ier &= ~(UART_17158_IER_RTSDTR);
166 #endif
167 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
168
169 /* Turn off auto Xoff flow control */
170 ier &= ~(UART_17158_IER_XOFF);
171 efr &= ~(UART_17158_EFR_IXOFF);
172
173 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
174 writeb(0, &ch->ch_neo_uart->efr);
175
176 /* Turn on UART enhanced bits */
177 writeb(efr, &ch->ch_neo_uart->efr);
178
179 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
180 ch->ch_r_watermark = 4;
181
182 writeb(32, &ch->ch_neo_uart->rfifo);
183 ch->ch_r_tlevel = 32;
184
185 writeb(ier, &ch->ch_neo_uart->ier);
186
187 /*
188 * From the Neo UART spec sheet:
189 * The auto RTS/DTR function must be started by asserting
190 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
191 * it is enabled.
192 */
193 ch->ch_mostat |= (UART_MCR_RTS);
194
195 neo_pci_posting_flush(ch->ch_bd);
196 }
197
198
199 static inline void neo_set_ixon_flow_control(struct channel_t *ch)
200 {
201 uchar ier = readb(&ch->ch_neo_uart->ier);
202 uchar efr = readb(&ch->ch_neo_uart->efr);
203
204 DPR_PARAM(("Setting IXON FLOW\n"));
205
206 /* Turn off auto CTS flow control */
207 ier &= ~(UART_17158_IER_CTSDSR);
208 efr &= ~(UART_17158_EFR_CTSDSR);
209
210 /* Turn on auto Xon flow control */
211 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
212
213 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
214 writeb(0, &ch->ch_neo_uart->efr);
215
216 /* Turn on UART enhanced bits */
217 writeb(efr, &ch->ch_neo_uart->efr);
218
219 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
220 ch->ch_r_watermark = 4;
221
222 writeb(32, &ch->ch_neo_uart->rfifo);
223 ch->ch_r_tlevel = 32;
224
225 /* Tell UART what start/stop chars it should be looking for */
226 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
227 writeb(0, &ch->ch_neo_uart->xonchar2);
228
229 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
230 writeb(0, &ch->ch_neo_uart->xoffchar2);
231
232 writeb(ier, &ch->ch_neo_uart->ier);
233
234 neo_pci_posting_flush(ch->ch_bd);
235 }
236
237
238 static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
239 {
240 uchar ier = readb(&ch->ch_neo_uart->ier);
241 uchar efr = readb(&ch->ch_neo_uart->efr);
242
243 DPR_PARAM(("Setting IXOFF FLOW\n"));
244
245 /* Turn off auto RTS flow control */
246 ier &= ~(UART_17158_IER_RTSDTR);
247 efr &= ~(UART_17158_EFR_RTSDTR);
248
249 /* Turn on auto Xoff flow control */
250 ier |= (UART_17158_IER_XOFF);
251 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
252
253 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
254 writeb(0, &ch->ch_neo_uart->efr);
255
256 /* Turn on UART enhanced bits */
257 writeb(efr, &ch->ch_neo_uart->efr);
258
259 /* Turn on table D, with 8 char hi/low watermarks */
260 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
261
262 writeb(8, &ch->ch_neo_uart->tfifo);
263 ch->ch_t_tlevel = 8;
264
265 /* Tell UART what start/stop chars it should be looking for */
266 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
267 writeb(0, &ch->ch_neo_uart->xonchar2);
268
269 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
270 writeb(0, &ch->ch_neo_uart->xoffchar2);
271
272 writeb(ier, &ch->ch_neo_uart->ier);
273
274 neo_pci_posting_flush(ch->ch_bd);
275 }
276
277
278 static inline void neo_set_no_input_flow_control(struct channel_t *ch)
279 {
280 uchar ier = readb(&ch->ch_neo_uart->ier);
281 uchar efr = readb(&ch->ch_neo_uart->efr);
282
283 DPR_PARAM(("Unsetting Input FLOW\n"));
284
285 /* Turn off auto RTS flow control */
286 ier &= ~(UART_17158_IER_RTSDTR);
287 efr &= ~(UART_17158_EFR_RTSDTR);
288
289 /* Turn off auto Xoff flow control */
290 ier &= ~(UART_17158_IER_XOFF);
291 if (ch->ch_c_iflag & IXON)
292 efr &= ~(UART_17158_EFR_IXOFF);
293 else
294 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
295
296
297 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
298 writeb(0, &ch->ch_neo_uart->efr);
299
300 /* Turn on UART enhanced bits */
301 writeb(efr, &ch->ch_neo_uart->efr);
302
303 /* Turn on table D, with 8 char hi/low watermarks */
304 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
305
306 ch->ch_r_watermark = 0;
307
308 writeb(16, &ch->ch_neo_uart->tfifo);
309 ch->ch_t_tlevel = 16;
310
311 writeb(16, &ch->ch_neo_uart->rfifo);
312 ch->ch_r_tlevel = 16;
313
314 writeb(ier, &ch->ch_neo_uart->ier);
315
316 neo_pci_posting_flush(ch->ch_bd);
317 }
318
319
320 static inline void neo_set_no_output_flow_control(struct channel_t *ch)
321 {
322 uchar ier = readb(&ch->ch_neo_uart->ier);
323 uchar efr = readb(&ch->ch_neo_uart->efr);
324
325 DPR_PARAM(("Unsetting Output FLOW\n"));
326
327 /* Turn off auto CTS flow control */
328 ier &= ~(UART_17158_IER_CTSDSR);
329 efr &= ~(UART_17158_EFR_CTSDSR);
330
331 /* Turn off auto Xon flow control */
332 if (ch->ch_c_iflag & IXOFF)
333 efr &= ~(UART_17158_EFR_IXON);
334 else
335 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
336
337 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
338 writeb(0, &ch->ch_neo_uart->efr);
339
340 /* Turn on UART enhanced bits */
341 writeb(efr, &ch->ch_neo_uart->efr);
342
343 /* Turn on table D, with 8 char hi/low watermarks */
344 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
345
346 ch->ch_r_watermark = 0;
347
348 writeb(16, &ch->ch_neo_uart->tfifo);
349 ch->ch_t_tlevel = 16;
350
351 writeb(16, &ch->ch_neo_uart->rfifo);
352 ch->ch_r_tlevel = 16;
353
354 writeb(ier, &ch->ch_neo_uart->ier);
355
356 neo_pci_posting_flush(ch->ch_bd);
357 }
358
359
360 /* change UARTs start/stop chars */
361 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
362 {
363
364 /* if hardware flow control is set, then skip this whole thing */
365 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS)
366 return;
367
368 DPR_PARAM(("In new start stop chars\n"));
369
370 /* Tell UART what start/stop chars it should be looking for */
371 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
372 writeb(0, &ch->ch_neo_uart->xonchar2);
373
374 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
375 writeb(0, &ch->ch_neo_uart->xoffchar2);
376
377 neo_pci_posting_flush(ch->ch_bd);
378 }
379
380
381 /*
382 * No locks are assumed to be held when calling this function.
383 */
384 static inline void neo_clear_break(struct channel_t *ch, int force)
385 {
386 ulong lock_flags;
387
388 DGNC_LOCK(ch->ch_lock, lock_flags);
389
390 /* Bail if we aren't currently sending a break. */
391 if (!ch->ch_stop_sending_break) {
392 DGNC_UNLOCK(ch->ch_lock, lock_flags);
393 return;
394 }
395
396 /* Turn break off, and unset some variables */
397 if (ch->ch_flags & CH_BREAK_SENDING) {
398 if ((jiffies >= ch->ch_stop_sending_break) || force) {
399 uchar temp = readb(&ch->ch_neo_uart->lcr);
400 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
401 neo_pci_posting_flush(ch->ch_bd);
402 ch->ch_flags &= ~(CH_BREAK_SENDING);
403 ch->ch_stop_sending_break = 0;
404 DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
405 }
406 }
407 DGNC_UNLOCK(ch->ch_lock, lock_flags);
408 }
409
410
411 /*
412 * Parse the ISR register.
413 */
414 static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
415 {
416 struct channel_t *ch;
417 uchar isr;
418 uchar cause;
419 ulong lock_flags;
420
421 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
422 return;
423
424 if (port > brd->maxports)
425 return;
426
427 ch = brd->channels[port];
428 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
429 return;
430
431 /* Here we try to figure out what caused the interrupt to happen */
432 while (1) {
433
434 isr = readb(&ch->ch_neo_uart->isr_fcr);
435
436 /* Bail if no pending interrupt */
437 if (isr & UART_IIR_NO_INT) {
438 break;
439 }
440
441 /*
442 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
443 */
444 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
445
446 DPR_INTR(("%s:%d isr: %x\n", __FILE__, __LINE__, isr));
447
448 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
449 /* Read data from uart -> queue */
450 brd->intr_rx++;
451 ch->ch_intr_rx++;
452 neo_copy_data_from_uart_to_queue(ch);
453
454 /* Call our tty layer to enforce queue flow control if needed. */
455 DGNC_LOCK(ch->ch_lock, lock_flags);
456 dgnc_check_queue_flow_control(ch);
457 DGNC_UNLOCK(ch->ch_lock, lock_flags);
458 }
459
460 if (isr & UART_IIR_THRI) {
461 brd->intr_tx++;
462 ch->ch_intr_tx++;
463 /* Transfer data (if any) from Write Queue -> UART. */
464 DGNC_LOCK(ch->ch_lock, lock_flags);
465 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
466 DGNC_UNLOCK(ch->ch_lock, lock_flags);
467 neo_copy_data_from_queue_to_uart(ch);
468 }
469
470 if (isr & UART_17158_IIR_XONXOFF) {
471 cause = readb(&ch->ch_neo_uart->xoffchar1);
472
473 DPR_INTR(("Port %d. Got ISR_XONXOFF: cause:%x\n", port, cause));
474
475 /*
476 * Since the UART detected either an XON or
477 * XOFF match, we need to figure out which
478 * one it was, so we can suspend or resume data flow.
479 */
480 if (cause == UART_17158_XON_DETECT) {
481 /* Is output stopped right now, if so, resume it */
482 if (brd->channels[port]->ch_flags & CH_STOP) {
483 DGNC_LOCK(ch->ch_lock, lock_flags);
484 ch->ch_flags &= ~(CH_STOP);
485 DGNC_UNLOCK(ch->ch_lock, lock_flags);
486 }
487 DPR_INTR(("Port %d. XON detected in incoming data\n", port));
488 }
489 else if (cause == UART_17158_XOFF_DETECT) {
490 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
491 DGNC_LOCK(ch->ch_lock, lock_flags);
492 ch->ch_flags |= CH_STOP;
493 DGNC_UNLOCK(ch->ch_lock, lock_flags);
494 DPR_INTR(("Setting CH_STOP\n"));
495 }
496 DPR_INTR(("Port: %d. XOFF detected in incoming data\n", port));
497 }
498 }
499
500 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
501 /*
502 * If we get here, this means the hardware is doing auto flow control.
503 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
504 */
505 brd->intr_modem++;
506 ch->ch_intr_modem++;
507 cause = readb(&ch->ch_neo_uart->mcr);
508 /* Which pin is doing auto flow? RTS or DTR? */
509 if ((cause & 0x4) == 0) {
510 if (cause & UART_MCR_RTS) {
511 DGNC_LOCK(ch->ch_lock, lock_flags);
512 ch->ch_mostat |= UART_MCR_RTS;
513 DGNC_UNLOCK(ch->ch_lock, lock_flags);
514 }
515 else {
516 DGNC_LOCK(ch->ch_lock, lock_flags);
517 ch->ch_mostat &= ~(UART_MCR_RTS);
518 DGNC_UNLOCK(ch->ch_lock, lock_flags);
519 }
520 } else {
521 if (cause & UART_MCR_DTR) {
522 DGNC_LOCK(ch->ch_lock, lock_flags);
523 ch->ch_mostat |= UART_MCR_DTR;
524 DGNC_UNLOCK(ch->ch_lock, lock_flags);
525 }
526 else {
527 DGNC_LOCK(ch->ch_lock, lock_flags);
528 ch->ch_mostat &= ~(UART_MCR_DTR);
529 DGNC_UNLOCK(ch->ch_lock, lock_flags);
530 }
531 }
532 }
533
534 /* Parse any modem signal changes */
535 DPR_INTR(("MOD_STAT: sending to parse_modem_sigs\n"));
536 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
537 }
538 }
539
540
541 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
542 {
543 struct channel_t *ch;
544 int linestatus;
545 ulong lock_flags;
546
547 if (!brd)
548 return;
549
550 if (brd->magic != DGNC_BOARD_MAGIC)
551 return;
552
553 if (port > brd->maxports)
554 return;
555
556 ch = brd->channels[port];
557 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
558 return;
559
560 linestatus = readb(&ch->ch_neo_uart->lsr);
561
562 DPR_INTR(("%s:%d port: %d linestatus: %x\n", __FILE__, __LINE__, port, linestatus));
563
564 ch->ch_cached_lsr |= linestatus;
565
566 if (ch->ch_cached_lsr & UART_LSR_DR) {
567 brd->intr_rx++;
568 ch->ch_intr_rx++;
569 /* Read data from uart -> queue */
570 neo_copy_data_from_uart_to_queue(ch);
571 DGNC_LOCK(ch->ch_lock, lock_flags);
572 dgnc_check_queue_flow_control(ch);
573 DGNC_UNLOCK(ch->ch_lock, lock_flags);
574 }
575
576 /*
577 * This is a special flag. It indicates that at least 1
578 * RX error (parity, framing, or break) has happened.
579 * Mark this in our struct, which will tell me that I have
580 *to do the special RX+LSR read for this FIFO load.
581 */
582 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR) {
583 DPR_INTR(("%s:%d Port: %d Got an RX error, need to parse LSR\n",
584 __FILE__, __LINE__, port));
585 }
586
587 /*
588 * The next 3 tests should *NOT* happen, as the above test
589 * should encapsulate all 3... At least, thats what Exar says.
590 */
591
592 if (linestatus & UART_LSR_PE) {
593 ch->ch_err_parity++;
594 DPR_INTR(("%s:%d Port: %d. PAR ERR!\n", __FILE__, __LINE__, port));
595 }
596
597 if (linestatus & UART_LSR_FE) {
598 ch->ch_err_frame++;
599 DPR_INTR(("%s:%d Port: %d. FRM ERR!\n", __FILE__, __LINE__, port));
600 }
601
602 if (linestatus & UART_LSR_BI) {
603 ch->ch_err_break++;
604 DPR_INTR(("%s:%d Port: %d. BRK INTR!\n", __FILE__, __LINE__, port));
605 }
606
607 if (linestatus & UART_LSR_OE) {
608 /*
609 * Rx Oruns. Exar says that an orun will NOT corrupt
610 * the FIFO. It will just replace the holding register
611 * with this new data byte. So basically just ignore this.
612 * Probably we should eventually have an orun stat in our driver...
613 */
614 ch->ch_err_overrun++;
615 DPR_INTR(("%s:%d Port: %d. Rx Overrun!\n", __FILE__, __LINE__, port));
616 }
617
618 if (linestatus & UART_LSR_THRE) {
619 brd->intr_tx++;
620 ch->ch_intr_tx++;
621 DGNC_LOCK(ch->ch_lock, lock_flags);
622 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
623 DGNC_UNLOCK(ch->ch_lock, lock_flags);
624
625 /* Transfer data (if any) from Write Queue -> UART. */
626 neo_copy_data_from_queue_to_uart(ch);
627 }
628 else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
629 brd->intr_tx++;
630 ch->ch_intr_tx++;
631 DGNC_LOCK(ch->ch_lock, lock_flags);
632 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
633 DGNC_UNLOCK(ch->ch_lock, lock_flags);
634
635 /* Transfer data (if any) from Write Queue -> UART. */
636 neo_copy_data_from_queue_to_uart(ch);
637 }
638 }
639
640
641 /*
642 * neo_param()
643 * Send any/all changes to the line to the UART.
644 */
645 static void neo_param(struct tty_struct *tty)
646 {
647 uchar lcr = 0;
648 uchar uart_lcr = 0;
649 uchar ier = 0;
650 uchar uart_ier = 0;
651 uint baud = 9600;
652 int quot = 0;
653 struct dgnc_board *bd;
654 struct channel_t *ch;
655 struct un_t *un;
656
657 if (!tty || tty->magic != TTY_MAGIC) {
658 return;
659 }
660
661 un = (struct un_t *) tty->driver_data;
662 if (!un || un->magic != DGNC_UNIT_MAGIC) {
663 return;
664 }
665
666 ch = un->un_ch;
667 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
668 return;
669 }
670
671 bd = ch->ch_bd;
672 if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
673 return;
674 }
675
676 DPR_PARAM(("param start: tdev: %x cflags: %x oflags: %x iflags: %x\n",
677 ch->ch_tun.un_dev, ch->ch_c_cflag, ch->ch_c_oflag, ch->ch_c_iflag));
678
679 /*
680 * If baud rate is zero, flush queues, and set mval to drop DTR.
681 */
682 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
683 ch->ch_r_head = ch->ch_r_tail = 0;
684 ch->ch_e_head = ch->ch_e_tail = 0;
685 ch->ch_w_head = ch->ch_w_tail = 0;
686
687 neo_flush_uart_write(ch);
688 neo_flush_uart_read(ch);
689
690 /* The baudrate is B0 so all modem lines are to be dropped. */
691 ch->ch_flags |= (CH_BAUD0);
692 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
693 neo_assert_modem_signals(ch);
694 ch->ch_old_baud = 0;
695 return;
696
697 } else if (ch->ch_custom_speed) {
698
699 baud = ch->ch_custom_speed;
700 /* Handle transition from B0 */
701 if (ch->ch_flags & CH_BAUD0) {
702 ch->ch_flags &= ~(CH_BAUD0);
703
704 /*
705 * Bring back up RTS and DTR...
706 * Also handle RTS or DTR toggle if set.
707 */
708 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
709 ch->ch_mostat |= (UART_MCR_RTS);
710 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
711 ch->ch_mostat |= (UART_MCR_DTR);
712 }
713 } else {
714 int iindex = 0;
715 int jindex = 0;
716
717 ulong bauds[4][16] = {
718 { /* slowbaud */
719 0, 50, 75, 110,
720 134, 150, 200, 300,
721 600, 1200, 1800, 2400,
722 4800, 9600, 19200, 38400 },
723 { /* slowbaud & CBAUDEX */
724 0, 57600, 115200, 230400,
725 460800, 150, 200, 921600,
726 600, 1200, 1800, 2400,
727 4800, 9600, 19200, 38400 },
728 { /* fastbaud */
729 0, 57600, 76800, 115200,
730 131657, 153600, 230400, 460800,
731 921600, 1200, 1800, 2400,
732 4800, 9600, 19200, 38400 },
733 { /* fastbaud & CBAUDEX */
734 0, 57600, 115200, 230400,
735 460800, 150, 200, 921600,
736 600, 1200, 1800, 2400,
737 4800, 9600, 19200, 38400 }
738 };
739
740 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
741 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT))
742 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
743 else
744 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
745
746 if (ch->ch_c_cflag & CBAUDEX)
747 iindex = 1;
748
749 if (ch->ch_digi.digi_flags & DIGI_FAST)
750 iindex += 2;
751
752 jindex = baud;
753
754 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16)) {
755 baud = bauds[iindex][jindex];
756 } else {
757 DPR_IOCTL(("baud indices were out of range (%d)(%d)",
758 iindex, jindex));
759 baud = 0;
760 }
761
762 if (baud == 0)
763 baud = 9600;
764
765 /* Handle transition from B0 */
766 if (ch->ch_flags & CH_BAUD0) {
767 ch->ch_flags &= ~(CH_BAUD0);
768
769 /*
770 * Bring back up RTS and DTR...
771 * Also handle RTS or DTR toggle if set.
772 */
773 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
774 ch->ch_mostat |= (UART_MCR_RTS);
775 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
776 ch->ch_mostat |= (UART_MCR_DTR);
777 }
778 }
779
780 if (ch->ch_c_cflag & PARENB) {
781 lcr |= UART_LCR_PARITY;
782 }
783
784 if (!(ch->ch_c_cflag & PARODD)) {
785 lcr |= UART_LCR_EPAR;
786 }
787
788 /*
789 * Not all platforms support mark/space parity,
790 * so this will hide behind an ifdef.
791 */
792 #ifdef CMSPAR
793 if (ch->ch_c_cflag & CMSPAR)
794 lcr |= UART_LCR_SPAR;
795 #endif
796
797 if (ch->ch_c_cflag & CSTOPB)
798 lcr |= UART_LCR_STOP;
799
800 switch (ch->ch_c_cflag & CSIZE) {
801 case CS5:
802 lcr |= UART_LCR_WLEN5;
803 break;
804 case CS6:
805 lcr |= UART_LCR_WLEN6;
806 break;
807 case CS7:
808 lcr |= UART_LCR_WLEN7;
809 break;
810 case CS8:
811 default:
812 lcr |= UART_LCR_WLEN8;
813 break;
814 }
815
816 ier = uart_ier = readb(&ch->ch_neo_uart->ier);
817 uart_lcr = readb(&ch->ch_neo_uart->lcr);
818
819 if (baud == 0)
820 baud = 9600;
821
822 quot = ch->ch_bd->bd_dividend / baud;
823
824 if (quot != 0 && ch->ch_old_baud != baud) {
825 ch->ch_old_baud = baud;
826 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
827 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
828 writeb((quot >> 8), &ch->ch_neo_uart->ier);
829 writeb(lcr, &ch->ch_neo_uart->lcr);
830 }
831
832 if (uart_lcr != lcr)
833 writeb(lcr, &ch->ch_neo_uart->lcr);
834
835 if (ch->ch_c_cflag & CREAD) {
836 ier |= (UART_IER_RDI | UART_IER_RLSI);
837 }
838 else {
839 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
840 }
841
842 /*
843 * Have the UART interrupt on modem signal changes ONLY when
844 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
845 */
846 if ((ch->ch_digi.digi_flags & CTSPACE) || (ch->ch_digi.digi_flags & RTSPACE) ||
847 (ch->ch_c_cflag & CRTSCTS) || !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
848 !(ch->ch_c_cflag & CLOCAL))
849 {
850 ier |= UART_IER_MSI;
851 }
852 else {
853 ier &= ~UART_IER_MSI;
854 }
855
856 ier |= UART_IER_THRI;
857
858 if (ier != uart_ier)
859 writeb(ier, &ch->ch_neo_uart->ier);
860
861 /* Set new start/stop chars */
862 neo_set_new_start_stop_chars(ch);
863
864 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
865 neo_set_cts_flow_control(ch);
866 }
867 else if (ch->ch_c_iflag & IXON) {
868 /* If start/stop is set to disable, then we should disable flow control */
869 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
870 neo_set_no_output_flow_control(ch);
871 else
872 neo_set_ixon_flow_control(ch);
873 }
874 else {
875 neo_set_no_output_flow_control(ch);
876 }
877
878 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
879 neo_set_rts_flow_control(ch);
880 }
881 else if (ch->ch_c_iflag & IXOFF) {
882 /* If start/stop is set to disable, then we should disable flow control */
883 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
884 neo_set_no_input_flow_control(ch);
885 else
886 neo_set_ixoff_flow_control(ch);
887 }
888 else {
889 neo_set_no_input_flow_control(ch);
890 }
891
892 /*
893 * Adjust the RX FIFO Trigger level if baud is less than 9600.
894 * Not exactly elegant, but this is needed because of the Exar chip's
895 * delay on firing off the RX FIFO interrupt on slower baud rates.
896 */
897 if (baud < 9600) {
898 writeb(1, &ch->ch_neo_uart->rfifo);
899 ch->ch_r_tlevel = 1;
900 }
901
902 neo_assert_modem_signals(ch);
903
904 /* Get current status of the modem signals now */
905 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
906 }
907
908
909 /*
910 * Our board poller function.
911 */
912 static void neo_tasklet(unsigned long data)
913 {
914 struct dgnc_board *bd = (struct dgnc_board *) data;
915 struct channel_t *ch;
916 ulong lock_flags;
917 int i;
918 int state = 0;
919 int ports = 0;
920
921 if (!bd || bd->magic != DGNC_BOARD_MAGIC) {
922 APR(("poll_tasklet() - NULL or bad bd.\n"));
923 return;
924 }
925
926 /* Cache a couple board values */
927 DGNC_LOCK(bd->bd_lock, lock_flags);
928 state = bd->state;
929 ports = bd->nasync;
930 DGNC_UNLOCK(bd->bd_lock, lock_flags);
931
932 /*
933 * Do NOT allow the interrupt routine to read the intr registers
934 * Until we release this lock.
935 */
936 DGNC_LOCK(bd->bd_intr_lock, lock_flags);
937
938 /*
939 * If board is ready, parse deeper to see if there is anything to do.
940 */
941 if ((state == BOARD_READY) && (ports > 0)) {
942 /* Loop on each port */
943 for (i = 0; i < ports; i++) {
944 ch = bd->channels[i];
945
946 /* Just being careful... */
947 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
948 continue;
949
950 /*
951 * NOTE: Remember you CANNOT hold any channel
952 * locks when calling the input routine.
953 *
954 * During input processing, its possible we
955 * will call the Linux ld, which might in turn,
956 * do a callback right back into us, resulting
957 * in us trying to grab the channel lock twice!
958 */
959 dgnc_input(ch);
960
961 /*
962 * Channel lock is grabbed and then released
963 * inside both of these routines, but neither
964 * call anything else that could call back into us.
965 */
966 neo_copy_data_from_queue_to_uart(ch);
967 dgnc_wakeup_writes(ch);
968
969 /*
970 * Call carrier carrier function, in case something
971 * has changed.
972 */
973 dgnc_carrier(ch);
974
975 /*
976 * Check to see if we need to turn off a sending break.
977 * The timing check is done inside clear_break()
978 */
979 if (ch->ch_stop_sending_break)
980 neo_clear_break(ch, 0);
981 }
982 }
983
984 /* Allow interrupt routine to access the interrupt register again */
985 DGNC_UNLOCK(bd->bd_intr_lock, lock_flags);
986
987 }
988
989
990 /*
991 * dgnc_neo_intr()
992 *
993 * Neo specific interrupt handler.
994 */
995 static irqreturn_t neo_intr(int irq, void *voidbrd)
996 {
997 struct dgnc_board *brd = (struct dgnc_board *) voidbrd;
998 struct channel_t *ch;
999 int port = 0;
1000 int type = 0;
1001 int current_port;
1002 u32 tmp;
1003 u32 uart_poll;
1004 unsigned long lock_flags;
1005 unsigned long lock_flags2;
1006
1007 if (!brd) {
1008 APR(("Received interrupt (%d) with null board associated\n", irq));
1009 return IRQ_NONE;
1010 }
1011
1012 /*
1013 * Check to make sure its for us.
1014 */
1015 if (brd->magic != DGNC_BOARD_MAGIC) {
1016 APR(("Received interrupt (%d) with a board pointer that wasn't ours!\n", irq));
1017 return IRQ_NONE;
1018 }
1019
1020 brd->intr_count++;
1021
1022 /* Lock out the slow poller from running on this board. */
1023 DGNC_LOCK(brd->bd_intr_lock, lock_flags);
1024
1025 /*
1026 * Read in "extended" IRQ information from the 32bit Neo register.
1027 * Bits 0-7: What port triggered the interrupt.
1028 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1029 */
1030 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1031
1032 DPR_INTR(("%s:%d uart_poll: %x\n", __FILE__, __LINE__, uart_poll));
1033
1034 /*
1035 * If 0, no interrupts pending.
1036 * This can happen if the IRQ is shared among a couple Neo/Classic boards.
1037 */
1038 if (!uart_poll) {
1039 DPR_INTR(("Kernel interrupted to me, but no pending interrupts...\n"));
1040 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
1041 return IRQ_NONE;
1042 }
1043
1044 /* At this point, we have at least SOMETHING to service, dig further... */
1045
1046 current_port = 0;
1047
1048 /* Loop on each port */
1049 while ((uart_poll & 0xff) != 0) {
1050
1051 tmp = uart_poll;
1052
1053 /* Check current port to see if it has interrupt pending */
1054 if ((tmp & dgnc_offset_table[current_port]) != 0) {
1055 port = current_port;
1056 type = tmp >> (8 + (port * 3));
1057 type &= 0x7;
1058 } else {
1059 current_port++;
1060 continue;
1061 }
1062
1063 DPR_INTR(("%s:%d port: %x type: %x\n", __FILE__, __LINE__, port, type));
1064
1065 /* Remove this port + type from uart_poll */
1066 uart_poll &= ~(dgnc_offset_table[port]);
1067
1068 if (!type) {
1069 /* If no type, just ignore it, and move onto next port */
1070 DPR_INTR(("Interrupt with no type! port: %d\n", port));
1071 continue;
1072 }
1073
1074 /* Switch on type of interrupt we have */
1075 switch (type) {
1076
1077 case UART_17158_RXRDY_TIMEOUT:
1078 /*
1079 * RXRDY Time-out is cleared by reading data in the
1080 * RX FIFO until it falls below the trigger level.
1081 */
1082
1083 /* Verify the port is in range. */
1084 if (port > brd->nasync)
1085 continue;
1086
1087 ch = brd->channels[port];
1088 neo_copy_data_from_uart_to_queue(ch);
1089
1090 /* Call our tty layer to enforce queue flow control if needed. */
1091 DGNC_LOCK(ch->ch_lock, lock_flags2);
1092 dgnc_check_queue_flow_control(ch);
1093 DGNC_UNLOCK(ch->ch_lock, lock_flags2);
1094
1095 continue;
1096
1097 case UART_17158_RX_LINE_STATUS:
1098 /*
1099 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1100 */
1101 neo_parse_lsr(brd, port);
1102 continue;
1103
1104 case UART_17158_TXRDY:
1105 /*
1106 * TXRDY interrupt clears after reading ISR register for the UART channel.
1107 */
1108
1109 /*
1110 * Yes, this is odd...
1111 * Why would I check EVERY possibility of type of
1112 * interrupt, when we know its TXRDY???
1113 * Becuz for some reason, even tho we got triggered for TXRDY,
1114 * it seems to be occasionally wrong. Instead of TX, which
1115 * it should be, I was getting things like RXDY too. Weird.
1116 */
1117 neo_parse_isr(brd, port);
1118 continue;
1119
1120 case UART_17158_MSR:
1121 /*
1122 * MSR or flow control was seen.
1123 */
1124 neo_parse_isr(brd, port);
1125 continue;
1126
1127 default:
1128 /*
1129 * The UART triggered us with a bogus interrupt type.
1130 * It appears the Exar chip, when REALLY bogged down, will throw
1131 * these once and awhile.
1132 * Its harmless, just ignore it and move on.
1133 */
1134 DPR_INTR(("%s:%d Unknown Interrupt type: %x\n", __FILE__, __LINE__, type));
1135 continue;
1136 }
1137 }
1138
1139 /*
1140 * Schedule tasklet to more in-depth servicing at a better time.
1141 */
1142 tasklet_schedule(&brd->helper_tasklet);
1143
1144 DGNC_UNLOCK(brd->bd_intr_lock, lock_flags);
1145
1146 DPR_INTR(("dgnc_intr finish.\n"));
1147 return IRQ_HANDLED;
1148 }
1149
1150
1151 /*
1152 * Neo specific way of turning off the receiver.
1153 * Used as a way to enforce queue flow control when in
1154 * hardware flow control mode.
1155 */
1156 static void neo_disable_receiver(struct channel_t *ch)
1157 {
1158 uchar tmp = readb(&ch->ch_neo_uart->ier);
1159 tmp &= ~(UART_IER_RDI);
1160 writeb(tmp, &ch->ch_neo_uart->ier);
1161 neo_pci_posting_flush(ch->ch_bd);
1162 }
1163
1164
1165 /*
1166 * Neo specific way of turning on the receiver.
1167 * Used as a way to un-enforce queue flow control when in
1168 * hardware flow control mode.
1169 */
1170 static void neo_enable_receiver(struct channel_t *ch)
1171 {
1172 uchar tmp = readb(&ch->ch_neo_uart->ier);
1173 tmp |= (UART_IER_RDI);
1174 writeb(tmp, &ch->ch_neo_uart->ier);
1175 neo_pci_posting_flush(ch->ch_bd);
1176 }
1177
1178
1179 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1180 {
1181 int qleft = 0;
1182 uchar linestatus = 0;
1183 uchar error_mask = 0;
1184 int n = 0;
1185 int total = 0;
1186 ushort head;
1187 ushort tail;
1188 ulong lock_flags;
1189
1190 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1191 return;
1192
1193 DGNC_LOCK(ch->ch_lock, lock_flags);
1194
1195 /* cache head and tail of queue */
1196 head = ch->ch_r_head & RQUEUEMASK;
1197 tail = ch->ch_r_tail & RQUEUEMASK;
1198
1199 /* Get our cached LSR */
1200 linestatus = ch->ch_cached_lsr;
1201 ch->ch_cached_lsr = 0;
1202
1203 /* Store how much space we have left in the queue */
1204 if ((qleft = tail - head - 1) < 0)
1205 qleft += RQUEUEMASK + 1;
1206
1207 /*
1208 * If the UART is not in FIFO mode, force the FIFO copy to
1209 * NOT be run, by setting total to 0.
1210 *
1211 * On the other hand, if the UART IS in FIFO mode, then ask
1212 * the UART to give us an approximation of data it has RX'ed.
1213 */
1214 if (!(ch->ch_flags & CH_FIFO_ENABLED))
1215 total = 0;
1216 else {
1217 total = readb(&ch->ch_neo_uart->rfifo);
1218
1219 /*
1220 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1221 *
1222 * This resolves a problem/bug with the Exar chip that sometimes
1223 * returns a bogus value in the rfifo register.
1224 * The count can be any where from 0-3 bytes "off".
1225 * Bizarre, but true.
1226 */
1227 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID) {
1228 total -= 1;
1229 }
1230 else {
1231 total -= 3;
1232 }
1233 }
1234
1235
1236 /*
1237 * Finally, bound the copy to make sure we don't overflow
1238 * our own queue...
1239 * The byte by byte copy loop below this loop this will
1240 * deal with the queue overflow possibility.
1241 */
1242 total = min(total, qleft);
1243
1244 while (total > 0) {
1245
1246 /*
1247 * Grab the linestatus register, we need to check
1248 * to see if there are any errors in the FIFO.
1249 */
1250 linestatus = readb(&ch->ch_neo_uart->lsr);
1251
1252 /*
1253 * Break out if there is a FIFO error somewhere.
1254 * This will allow us to go byte by byte down below,
1255 * finding the exact location of the error.
1256 */
1257 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1258 break;
1259
1260 /* Make sure we don't go over the end of our queue */
1261 n = min(((uint) total), (RQUEUESIZE - (uint) head));
1262
1263 /*
1264 * Cut down n even further if needed, this is to fix
1265 * a problem with memcpy_fromio() with the Neo on the
1266 * IBM pSeries platform.
1267 * 15 bytes max appears to be the magic number.
1268 */
1269 n = min((uint) n, (uint) 12);
1270
1271 /*
1272 * Since we are grabbing the linestatus register, which
1273 * will reset some bits after our read, we need to ensure
1274 * we don't miss our TX FIFO emptys.
1275 */
1276 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1277 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1278 }
1279
1280 linestatus = 0;
1281
1282 /* Copy data from uart to the queue */
1283 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
1284 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, n);
1285
1286 /*
1287 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
1288 * that all the data currently in the FIFO is free of
1289 * breaks and parity/frame/orun errors.
1290 */
1291 memset(ch->ch_equeue + head, 0, n);
1292
1293 /* Add to and flip head if needed */
1294 head = (head + n) & RQUEUEMASK;
1295 total -= n;
1296 qleft -= n;
1297 ch->ch_rxcount += n;
1298 }
1299
1300 /*
1301 * Create a mask to determine whether we should
1302 * insert the character (if any) into our queue.
1303 */
1304 if (ch->ch_c_iflag & IGNBRK)
1305 error_mask |= UART_LSR_BI;
1306
1307 /*
1308 * Now cleanup any leftover bytes still in the UART.
1309 * Also deal with any possible queue overflow here as well.
1310 */
1311 while (1) {
1312
1313 /*
1314 * Its possible we have a linestatus from the loop above
1315 * this, so we "OR" on any extra bits.
1316 */
1317 linestatus |= readb(&ch->ch_neo_uart->lsr);
1318
1319 /*
1320 * If the chip tells us there is no more data pending to
1321 * be read, we can then leave.
1322 * But before we do, cache the linestatus, just in case.
1323 */
1324 if (!(linestatus & UART_LSR_DR)) {
1325 ch->ch_cached_lsr = linestatus;
1326 break;
1327 }
1328
1329 /* No need to store this bit */
1330 linestatus &= ~UART_LSR_DR;
1331
1332 /*
1333 * Since we are grabbing the linestatus register, which
1334 * will reset some bits after our read, we need to ensure
1335 * we don't miss our TX FIFO emptys.
1336 */
1337 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1338 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
1339 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1340 }
1341
1342 /*
1343 * Discard character if we are ignoring the error mask.
1344 */
1345 if (linestatus & error_mask) {
1346 uchar discard;
1347 linestatus = 0;
1348 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1349 continue;
1350 }
1351
1352 /*
1353 * If our queue is full, we have no choice but to drop some data.
1354 * The assumption is that HWFLOW or SWFLOW should have stopped
1355 * things way way before we got to this point.
1356 *
1357 * I decided that I wanted to ditch the oldest data first,
1358 * I hope thats okay with everyone? Yes? Good.
1359 */
1360 while (qleft < 1) {
1361 DPR_READ(("Queue full, dropping DATA:%x LSR:%x\n",
1362 ch->ch_rqueue[tail], ch->ch_equeue[tail]));
1363
1364 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
1365 ch->ch_err_overrun++;
1366 qleft++;
1367 }
1368
1369 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
1370 ch->ch_equeue[head] = (uchar) linestatus;
1371 dgnc_sniff_nowait_nolock(ch, "UART READ", ch->ch_rqueue + head, 1);
1372
1373 DPR_READ(("DATA/LSR pair: %x %x\n", ch->ch_rqueue[head], ch->ch_equeue[head]));
1374
1375 /* Ditch any remaining linestatus value. */
1376 linestatus = 0;
1377
1378 /* Add to and flip head if needed */
1379 head = (head + 1) & RQUEUEMASK;
1380
1381 qleft--;
1382 ch->ch_rxcount++;
1383 }
1384
1385 /*
1386 * Write new final heads to channel structure.
1387 */
1388 ch->ch_r_head = head & RQUEUEMASK;
1389 ch->ch_e_head = head & EQUEUEMASK;
1390
1391 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1392 }
1393
1394
1395 /*
1396 * This function basically goes to sleep for secs, or until
1397 * it gets signalled that the port has fully drained.
1398 */
1399 static int neo_drain(struct tty_struct *tty, uint seconds)
1400 {
1401 ulong lock_flags;
1402 struct channel_t *ch;
1403 struct un_t *un;
1404 int rc = 0;
1405
1406 if (!tty || tty->magic != TTY_MAGIC) {
1407 return -ENXIO;
1408 }
1409
1410 un = (struct un_t *) tty->driver_data;
1411 if (!un || un->magic != DGNC_UNIT_MAGIC) {
1412 return -ENXIO;
1413 }
1414
1415 ch = un->un_ch;
1416 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1417 return -ENXIO;
1418 }
1419
1420 DPR_IOCTL(("%d Drain wait started.\n", __LINE__));
1421
1422 DGNC_LOCK(ch->ch_lock, lock_flags);
1423 un->un_flags |= UN_EMPTY;
1424 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1425
1426 /*
1427 * Go to sleep waiting for the tty layer to wake me back up when
1428 * the empty flag goes away.
1429 *
1430 * NOTE: TODO: Do something with time passed in.
1431 */
1432 rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0));
1433
1434 /* If ret is non-zero, user ctrl-c'ed us */
1435 if (rc) {
1436 DPR_IOCTL(("%d Drain - User ctrl c'ed\n", __LINE__));
1437 }
1438 else {
1439 DPR_IOCTL(("%d Drain wait finished.\n", __LINE__));
1440 }
1441
1442 return rc;
1443 }
1444
1445
1446 /*
1447 * Flush the WRITE FIFO on the Neo.
1448 *
1449 * NOTE: Channel lock MUST be held before calling this function!
1450 */
1451 static void neo_flush_uart_write(struct channel_t *ch)
1452 {
1453 uchar tmp = 0;
1454 int i = 0;
1455
1456 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1457 return;
1458 }
1459
1460 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1461 neo_pci_posting_flush(ch->ch_bd);
1462
1463 for (i = 0; i < 10; i++) {
1464
1465 /* Check to see if the UART feels it completely flushed the FIFO. */
1466 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1467 if (tmp & 4) {
1468 DPR_IOCTL(("Still flushing TX UART... i: %d\n", i));
1469 udelay(10);
1470 }
1471 else
1472 break;
1473 }
1474
1475 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1476 }
1477
1478
1479 /*
1480 * Flush the READ FIFO on the Neo.
1481 *
1482 * NOTE: Channel lock MUST be held before calling this function!
1483 */
1484 static void neo_flush_uart_read(struct channel_t *ch)
1485 {
1486 uchar tmp = 0;
1487 int i = 0;
1488
1489 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC) {
1490 return;
1491 }
1492
1493 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
1494 neo_pci_posting_flush(ch->ch_bd);
1495
1496 for (i = 0; i < 10; i++) {
1497
1498 /* Check to see if the UART feels it completely flushed the FIFO. */
1499 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1500 if (tmp & 2) {
1501 DPR_IOCTL(("Still flushing RX UART... i: %d\n", i));
1502 udelay(10);
1503 }
1504 else
1505 break;
1506 }
1507 }
1508
1509
1510 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1511 {
1512 ushort head;
1513 ushort tail;
1514 int n;
1515 int s;
1516 int qlen;
1517 uint len_written = 0;
1518 ulong lock_flags;
1519
1520 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1521 return;
1522
1523 DGNC_LOCK(ch->ch_lock, lock_flags);
1524
1525 /* No data to write to the UART */
1526 if (ch->ch_w_tail == ch->ch_w_head) {
1527 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1528 return;
1529 }
1530
1531 /* If port is "stopped", don't send any data to the UART */
1532 if ((ch->ch_flags & CH_FORCED_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) {
1533 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1534 return;
1535 }
1536
1537 /*
1538 * If FIFOs are disabled. Send data directly to txrx register
1539 */
1540 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1541 uchar lsrbits = readb(&ch->ch_neo_uart->lsr);
1542
1543 /* Cache the LSR bits for later parsing */
1544 ch->ch_cached_lsr |= lsrbits;
1545 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1546 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1547
1548 /*
1549 * If RTS Toggle mode is on, turn on RTS now if not already set,
1550 * and make sure we get an event when the data transfer has completed.
1551 */
1552 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1553 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1554 ch->ch_mostat |= (UART_MCR_RTS);
1555 neo_assert_modem_signals(ch);
1556 }
1557 ch->ch_tun.un_flags |= (UN_EMPTY);
1558 }
1559 /*
1560 * If DTR Toggle mode is on, turn on DTR now if not already set,
1561 * and make sure we get an event when the data transfer has completed.
1562 */
1563 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1564 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1565 ch->ch_mostat |= (UART_MCR_DTR);
1566 neo_assert_modem_signals(ch);
1567 }
1568 ch->ch_tun.un_flags |= (UN_EMPTY);
1569 }
1570
1571 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
1572 DPR_WRITE(("Tx data: %x\n", ch->ch_wqueue[ch->ch_w_head]));
1573 ch->ch_w_tail++;
1574 ch->ch_w_tail &= WQUEUEMASK;
1575 ch->ch_txcount++;
1576 }
1577 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1578 return;
1579 }
1580
1581 /*
1582 * We have to do it this way, because of the EXAR TXFIFO count bug.
1583 */
1584 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1585 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
1586 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1587 return;
1588 }
1589
1590 len_written = 0;
1591
1592 n = readb(&ch->ch_neo_uart->tfifo);
1593
1594 if ((unsigned int) n > ch->ch_t_tlevel) {
1595 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1596 return;
1597 }
1598
1599 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1600 }
1601 else {
1602 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1603 }
1604
1605 /* cache head and tail of queue */
1606 head = ch->ch_w_head & WQUEUEMASK;
1607 tail = ch->ch_w_tail & WQUEUEMASK;
1608 qlen = (head - tail) & WQUEUEMASK;
1609
1610 /* Find minimum of the FIFO space, versus queue length */
1611 n = min(n, qlen);
1612
1613 while (n > 0) {
1614
1615 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1616 s = min(s, n);
1617
1618 if (s <= 0)
1619 break;
1620
1621 /*
1622 * If RTS Toggle mode is on, turn on RTS now if not already set,
1623 * and make sure we get an event when the data transfer has completed.
1624 */
1625 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1626 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1627 ch->ch_mostat |= (UART_MCR_RTS);
1628 neo_assert_modem_signals(ch);
1629 }
1630 ch->ch_tun.un_flags |= (UN_EMPTY);
1631 }
1632
1633 /*
1634 * If DTR Toggle mode is on, turn on DTR now if not already set,
1635 * and make sure we get an event when the data transfer has completed.
1636 */
1637 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1638 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1639 ch->ch_mostat |= (UART_MCR_DTR);
1640 neo_assert_modem_signals(ch);
1641 }
1642 ch->ch_tun.un_flags |= (UN_EMPTY);
1643 }
1644
1645 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
1646 dgnc_sniff_nowait_nolock(ch, "UART WRITE", ch->ch_wqueue + tail, s);
1647
1648 /* Add and flip queue if needed */
1649 tail = (tail + s) & WQUEUEMASK;
1650 n -= s;
1651 ch->ch_txcount += s;
1652 len_written += s;
1653 }
1654
1655 /* Update the final tail */
1656 ch->ch_w_tail = tail & WQUEUEMASK;
1657
1658 if (len_written > 0) {
1659 neo_pci_posting_flush(ch->ch_bd);
1660 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1661 }
1662
1663 DGNC_UNLOCK(ch->ch_lock, lock_flags);
1664 }
1665
1666
1667 static void neo_parse_modem(struct channel_t *ch, uchar signals)
1668 {
1669 volatile uchar msignals = signals;
1670
1671 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1672 return;
1673
1674 DPR_MSIGS(("neo_parse_modem: port: %d msignals: %x\n", ch->ch_portnum, msignals));
1675
1676 /*
1677 * Do altpin switching. Altpin switches DCD and DSR.
1678 * This prolly breaks DSRPACE, so we should be more clever here.
1679 */
1680 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1681 uchar mswap = msignals;
1682
1683 if (mswap & UART_MSR_DDCD) {
1684 msignals &= ~UART_MSR_DDCD;
1685 msignals |= UART_MSR_DDSR;
1686 }
1687 if (mswap & UART_MSR_DDSR) {
1688 msignals &= ~UART_MSR_DDSR;
1689 msignals |= UART_MSR_DDCD;
1690 }
1691 if (mswap & UART_MSR_DCD) {
1692 msignals &= ~UART_MSR_DCD;
1693 msignals |= UART_MSR_DSR;
1694 }
1695 if (mswap & UART_MSR_DSR) {
1696 msignals &= ~UART_MSR_DSR;
1697 msignals |= UART_MSR_DCD;
1698 }
1699 }
1700
1701 /* Scrub off lower bits. They signify delta's, which I don't care about */
1702 msignals &= 0xf0;
1703
1704 if (msignals & UART_MSR_DCD)
1705 ch->ch_mistat |= UART_MSR_DCD;
1706 else
1707 ch->ch_mistat &= ~UART_MSR_DCD;
1708
1709 if (msignals & UART_MSR_DSR)
1710 ch->ch_mistat |= UART_MSR_DSR;
1711 else
1712 ch->ch_mistat &= ~UART_MSR_DSR;
1713
1714 if (msignals & UART_MSR_RI)
1715 ch->ch_mistat |= UART_MSR_RI;
1716 else
1717 ch->ch_mistat &= ~UART_MSR_RI;
1718
1719 if (msignals & UART_MSR_CTS)
1720 ch->ch_mistat |= UART_MSR_CTS;
1721 else
1722 ch->ch_mistat &= ~UART_MSR_CTS;
1723
1724 DPR_MSIGS(("Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
1725 ch->ch_portnum,
1726 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
1727 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
1728 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
1729 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
1730 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
1731 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)));
1732 }
1733
1734
1735 /* Make the UART raise any of the output signals we want up */
1736 static void neo_assert_modem_signals(struct channel_t *ch)
1737 {
1738 uchar out;
1739
1740 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1741 return;
1742
1743 out = ch->ch_mostat;
1744
1745 if (ch->ch_flags & CH_LOOPBACK)
1746 out |= UART_MCR_LOOP;
1747
1748 writeb(out, &ch->ch_neo_uart->mcr);
1749 neo_pci_posting_flush(ch->ch_bd);
1750
1751 /* Give time for the UART to actually raise/drop the signals */
1752 udelay(10);
1753 }
1754
1755
1756 static void neo_send_start_character(struct channel_t *ch)
1757 {
1758 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1759 return;
1760
1761 if (ch->ch_startc != _POSIX_VDISABLE) {
1762 ch->ch_xon_sends++;
1763 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1764 neo_pci_posting_flush(ch->ch_bd);
1765 udelay(10);
1766 }
1767 }
1768
1769
1770 static void neo_send_stop_character(struct channel_t *ch)
1771 {
1772 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1773 return;
1774
1775 if (ch->ch_stopc != _POSIX_VDISABLE) {
1776 ch->ch_xoff_sends++;
1777 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1778 neo_pci_posting_flush(ch->ch_bd);
1779 udelay(10);
1780 }
1781 }
1782
1783
1784 /*
1785 * neo_uart_init
1786 */
1787 static void neo_uart_init(struct channel_t *ch)
1788 {
1789
1790 writeb(0, &ch->ch_neo_uart->ier);
1791 writeb(0, &ch->ch_neo_uart->efr);
1792 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1793
1794
1795 /* Clear out UART and FIFO */
1796 readb(&ch->ch_neo_uart->txrx);
1797 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1798 readb(&ch->ch_neo_uart->lsr);
1799 readb(&ch->ch_neo_uart->msr);
1800
1801 ch->ch_flags |= CH_FIFO_ENABLED;
1802
1803 /* Assert any signals we want up */
1804 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1805 neo_pci_posting_flush(ch->ch_bd);
1806 }
1807
1808
1809 /*
1810 * Make the UART completely turn off.
1811 */
1812 static void neo_uart_off(struct channel_t *ch)
1813 {
1814 /* Turn off UART enhanced bits */
1815 writeb(0, &ch->ch_neo_uart->efr);
1816
1817 /* Stop all interrupts from occurring. */
1818 writeb(0, &ch->ch_neo_uart->ier);
1819 neo_pci_posting_flush(ch->ch_bd);
1820 }
1821
1822
1823 static uint neo_get_uart_bytes_left(struct channel_t *ch)
1824 {
1825 uchar left = 0;
1826 uchar lsr = readb(&ch->ch_neo_uart->lsr);
1827
1828 /* We must cache the LSR as some of the bits get reset once read... */
1829 ch->ch_cached_lsr |= lsr;
1830
1831 /* Determine whether the Transmitter is empty or not */
1832 if (!(lsr & UART_LSR_TEMT)) {
1833 if (ch->ch_flags & CH_TX_FIFO_EMPTY) {
1834 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1835 }
1836 left = 1;
1837 } else {
1838 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1839 left = 0;
1840 }
1841
1842 return left;
1843 }
1844
1845
1846 /* Channel lock MUST be held by the calling function! */
1847 static void neo_send_break(struct channel_t *ch, int msecs)
1848 {
1849 /*
1850 * If we receive a time of 0, this means turn off the break.
1851 */
1852 if (msecs == 0) {
1853 if (ch->ch_flags & CH_BREAK_SENDING) {
1854 uchar temp = readb(&ch->ch_neo_uart->lcr);
1855 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1856 neo_pci_posting_flush(ch->ch_bd);
1857 ch->ch_flags &= ~(CH_BREAK_SENDING);
1858 ch->ch_stop_sending_break = 0;
1859 DPR_IOCTL(("Finishing UART_LCR_SBC! finished: %lx\n", jiffies));
1860 }
1861 return;
1862 }
1863
1864 /*
1865 * Set the time we should stop sending the break.
1866 * If we are already sending a break, toss away the existing
1867 * time to stop, and use this new value instead.
1868 */
1869 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1870
1871 /* Tell the UART to start sending the break */
1872 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1873 uchar temp = readb(&ch->ch_neo_uart->lcr);
1874 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1875 neo_pci_posting_flush(ch->ch_bd);
1876 ch->ch_flags |= (CH_BREAK_SENDING);
1877 DPR_IOCTL(("Port %d. Starting UART_LCR_SBC! start: %lx should end: %lx\n",
1878 ch->ch_portnum, jiffies, ch->ch_stop_sending_break));
1879 }
1880 }
1881
1882
1883 /*
1884 * neo_send_immediate_char.
1885 *
1886 * Sends a specific character as soon as possible to the UART,
1887 * jumping over any bytes that might be in the write queue.
1888 *
1889 * The channel lock MUST be held by the calling function.
1890 */
1891 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1892 {
1893 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1894 return;
1895
1896 writeb(c, &ch->ch_neo_uart->txrx);
1897 neo_pci_posting_flush(ch->ch_bd);
1898 }
1899
1900
1901 static unsigned int neo_read_eeprom(unsigned char __iomem *base, unsigned int address)
1902 {
1903 unsigned int enable;
1904 unsigned int bits;
1905 unsigned int databit;
1906 unsigned int val;
1907
1908 /* enable chip select */
1909 writeb(NEO_EECS, base + NEO_EEREG);
1910 /* READ */
1911 enable = (address | 0x180);
1912
1913 for (bits = 9; bits--; ) {
1914 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1915 /* Set read address */
1916 writeb(databit | NEO_EECS, base + NEO_EEREG);
1917 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1918 }
1919
1920 val = 0;
1921
1922 for (bits = 17; bits--; ) {
1923 /* clock to EEPROM */
1924 writeb(NEO_EECS, base + NEO_EEREG);
1925 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1926 val <<= 1;
1927 /* read EEPROM */
1928 if (readb(base + NEO_EEREG) & NEO_EEDO)
1929 val |= 1;
1930 }
1931
1932 /* clock falling edge */
1933 writeb(NEO_EECS, base + NEO_EEREG);
1934
1935 /* drop chip select */
1936 writeb(0x00, base + NEO_EEREG);
1937
1938 return val;
1939 }
1940
1941
1942 static void neo_vpd(struct dgnc_board *brd)
1943 {
1944 unsigned int i = 0;
1945 unsigned int a;
1946
1947 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1948 return;
1949
1950 if (!brd->re_map_membase)
1951 return;
1952
1953 /* Store the VPD into our buffer */
1954 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1955 a = neo_read_eeprom(brd->re_map_membase, i);
1956 brd->vpd[i*2] = a & 0xff;
1957 brd->vpd[(i*2)+1] = (a >> 8) & 0xff;
1958 }
1959
1960 if (((brd->vpd[0x08] != 0x82) /* long resource name tag */
1961 && (brd->vpd[0x10] != 0x82)) /* long resource name tag (PCI-66 files)*/
1962 || (brd->vpd[0x7F] != 0x78)) /* small resource end tag */
1963 {
1964 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1965 }
1966 else {
1967 /* Search for the serial number */
1968 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++) {
1969 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N') {
1970 strncpy(brd->serial_num, &(brd->vpd[i + 3]), 9);
1971 }
1972 }
1973 }
1974 }
Linux kernel - Deliverables
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