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[deliverable/linux.git] / drivers / staging / iio / adc / mxs-lradc.c
1 /*
2 * Freescale MXS LRADC driver
3 *
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Marek Vasut <marex@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/device.h>
22 #include <linux/err.h>
23 #include <linux/input.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/mutex.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
33 #include <linux/stmp_device.h>
34 #include <linux/sysfs.h>
35
36 #include <linux/iio/buffer.h>
37 #include <linux/iio/iio.h>
38 #include <linux/iio/trigger.h>
39 #include <linux/iio/trigger_consumer.h>
40 #include <linux/iio/triggered_buffer.h>
41 #include <linux/iio/sysfs.h>
42
43 #define DRIVER_NAME "mxs-lradc"
44
45 #define LRADC_MAX_DELAY_CHANS 4
46 #define LRADC_MAX_MAPPED_CHANS 8
47 #define LRADC_MAX_TOTAL_CHANS 16
48
49 #define LRADC_DELAY_TIMER_HZ 2000
50
51 /*
52 * Make this runtime configurable if necessary. Currently, if the buffered mode
53 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
54 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
55 * seconds. The result is that the samples arrive every 500mS.
56 */
57 #define LRADC_DELAY_TIMER_PER 200
58 #define LRADC_DELAY_TIMER_LOOP 5
59
60 /*
61 * Once the pen touches the touchscreen, the touchscreen switches from
62 * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
63 * is realized by worker thread, which is called every 20 or so milliseconds.
64 * This gives the touchscreen enough fluency and does not strain the system
65 * too much.
66 */
67 #define LRADC_TS_SAMPLE_DELAY_MS 5
68
69 /*
70 * The LRADC reads the following amount of samples from each touchscreen
71 * channel and the driver then computes average of these.
72 */
73 #define LRADC_TS_SAMPLE_AMOUNT 4
74
75 enum mxs_lradc_id {
76 IMX23_LRADC,
77 IMX28_LRADC,
78 };
79
80 static const char * const mx23_lradc_irq_names[] = {
81 "mxs-lradc-touchscreen",
82 "mxs-lradc-channel0",
83 "mxs-lradc-channel1",
84 "mxs-lradc-channel2",
85 "mxs-lradc-channel3",
86 "mxs-lradc-channel4",
87 "mxs-lradc-channel5",
88 "mxs-lradc-channel6",
89 "mxs-lradc-channel7",
90 };
91
92 static const char * const mx28_lradc_irq_names[] = {
93 "mxs-lradc-touchscreen",
94 "mxs-lradc-thresh0",
95 "mxs-lradc-thresh1",
96 "mxs-lradc-channel0",
97 "mxs-lradc-channel1",
98 "mxs-lradc-channel2",
99 "mxs-lradc-channel3",
100 "mxs-lradc-channel4",
101 "mxs-lradc-channel5",
102 "mxs-lradc-channel6",
103 "mxs-lradc-channel7",
104 "mxs-lradc-button0",
105 "mxs-lradc-button1",
106 };
107
108 struct mxs_lradc_of_config {
109 const int irq_count;
110 const char * const *irq_name;
111 const uint32_t *vref_mv;
112 };
113
114 #define VREF_MV_BASE 1850
115
116 static const uint32_t mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
117 VREF_MV_BASE, /* CH0 */
118 VREF_MV_BASE, /* CH1 */
119 VREF_MV_BASE, /* CH2 */
120 VREF_MV_BASE, /* CH3 */
121 VREF_MV_BASE, /* CH4 */
122 VREF_MV_BASE, /* CH5 */
123 VREF_MV_BASE * 2, /* CH6 VDDIO */
124 VREF_MV_BASE * 4, /* CH7 VBATT */
125 VREF_MV_BASE, /* CH8 Temp sense 0 */
126 VREF_MV_BASE, /* CH9 Temp sense 1 */
127 VREF_MV_BASE, /* CH10 */
128 VREF_MV_BASE, /* CH11 */
129 VREF_MV_BASE, /* CH12 USB_DP */
130 VREF_MV_BASE, /* CH13 USB_DN */
131 VREF_MV_BASE, /* CH14 VBG */
132 VREF_MV_BASE * 4, /* CH15 VDD5V */
133 };
134
135 static const uint32_t mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = {
136 VREF_MV_BASE, /* CH0 */
137 VREF_MV_BASE, /* CH1 */
138 VREF_MV_BASE, /* CH2 */
139 VREF_MV_BASE, /* CH3 */
140 VREF_MV_BASE, /* CH4 */
141 VREF_MV_BASE, /* CH5 */
142 VREF_MV_BASE, /* CH6 */
143 VREF_MV_BASE * 4, /* CH7 VBATT */
144 VREF_MV_BASE, /* CH8 Temp sense 0 */
145 VREF_MV_BASE, /* CH9 Temp sense 1 */
146 VREF_MV_BASE * 2, /* CH10 VDDIO */
147 VREF_MV_BASE, /* CH11 VTH */
148 VREF_MV_BASE * 2, /* CH12 VDDA */
149 VREF_MV_BASE, /* CH13 VDDD */
150 VREF_MV_BASE, /* CH14 VBG */
151 VREF_MV_BASE * 4, /* CH15 VDD5V */
152 };
153
154 static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
155 [IMX23_LRADC] = {
156 .irq_count = ARRAY_SIZE(mx23_lradc_irq_names),
157 .irq_name = mx23_lradc_irq_names,
158 .vref_mv = mx23_vref_mv,
159 },
160 [IMX28_LRADC] = {
161 .irq_count = ARRAY_SIZE(mx28_lradc_irq_names),
162 .irq_name = mx28_lradc_irq_names,
163 .vref_mv = mx28_vref_mv,
164 },
165 };
166
167 enum mxs_lradc_ts {
168 MXS_LRADC_TOUCHSCREEN_NONE = 0,
169 MXS_LRADC_TOUCHSCREEN_4WIRE,
170 MXS_LRADC_TOUCHSCREEN_5WIRE,
171 };
172
173 /*
174 * Touchscreen handling
175 */
176 enum lradc_ts_plate {
177 LRADC_TOUCH = 0,
178 LRADC_SAMPLE_X,
179 LRADC_SAMPLE_Y,
180 LRADC_SAMPLE_PRESSURE,
181 LRADC_SAMPLE_VALID,
182 };
183
184 enum mxs_lradc_divbytwo {
185 MXS_LRADC_DIV_DISABLED = 0,
186 MXS_LRADC_DIV_ENABLED,
187 };
188
189 struct mxs_lradc_scale {
190 unsigned int integer;
191 unsigned int nano;
192 };
193
194 struct mxs_lradc {
195 struct device *dev;
196 void __iomem *base;
197 int irq[13];
198
199 struct clk *clk;
200
201 uint32_t *buffer;
202 struct iio_trigger *trig;
203
204 struct mutex lock;
205
206 struct completion completion;
207
208 const uint32_t *vref_mv;
209 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
210 unsigned long is_divided;
211
212 /*
213 * When the touchscreen is enabled, we give it two private virtual
214 * channels: #6 and #7. This means that only 6 virtual channels (instead
215 * of 8) will be available for buffered capture.
216 */
217 #define TOUCHSCREEN_VCHANNEL1 7
218 #define TOUCHSCREEN_VCHANNEL2 6
219 #define BUFFER_VCHANS_LIMITED 0x3f
220 #define BUFFER_VCHANS_ALL 0xff
221 u8 buffer_vchans;
222
223 /*
224 * Furthermore, certain LRADC channels are shared between touchscreen
225 * and/or touch-buttons and generic LRADC block. Therefore when using
226 * either of these, these channels are not available for the regular
227 * sampling. The shared channels are as follows:
228 *
229 * CH0 -- Touch button #0
230 * CH1 -- Touch button #1
231 * CH2 -- Touch screen XPUL
232 * CH3 -- Touch screen YPLL
233 * CH4 -- Touch screen XNUL
234 * CH5 -- Touch screen YNLR
235 * CH6 -- Touch screen WIPER (5-wire only)
236 *
237 * The bit fields below represents which parts of the LRADC block are
238 * switched into special mode of operation. These channels can not
239 * be sampled as regular LRADC channels. The driver will refuse any
240 * attempt to sample these channels.
241 */
242 #define CHAN_MASK_TOUCHBUTTON (BIT(1) | BIT(0))
243 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
244 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
245 enum mxs_lradc_ts use_touchscreen;
246 bool use_touchbutton;
247
248 struct input_dev *ts_input;
249
250 enum mxs_lradc_id soc;
251 enum lradc_ts_plate cur_plate; /* state machine */
252 bool ts_valid;
253 unsigned ts_x_pos;
254 unsigned ts_y_pos;
255 unsigned ts_pressure;
256
257 /* handle touchscreen's physical behaviour */
258 /* samples per coordinate */
259 unsigned over_sample_cnt;
260 /* time clocks between samples */
261 unsigned over_sample_delay;
262 /* time in clocks to wait after the plates where switched */
263 unsigned settling_delay;
264 };
265
266 #define LRADC_CTRL0 0x00
267 # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE BIT(23)
268 # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE BIT(22)
269 # define LRADC_CTRL0_MX28_YNNSW /* YM */ BIT(21)
270 # define LRADC_CTRL0_MX28_YPNSW /* YP */ BIT(20)
271 # define LRADC_CTRL0_MX28_YPPSW /* YP */ BIT(19)
272 # define LRADC_CTRL0_MX28_XNNSW /* XM */ BIT(18)
273 # define LRADC_CTRL0_MX28_XNPSW /* XM */ BIT(17)
274 # define LRADC_CTRL0_MX28_XPPSW /* XP */ BIT(16)
275
276 # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE BIT(20)
277 # define LRADC_CTRL0_MX23_YM BIT(19)
278 # define LRADC_CTRL0_MX23_XM BIT(18)
279 # define LRADC_CTRL0_MX23_YP BIT(17)
280 # define LRADC_CTRL0_MX23_XP BIT(16)
281
282 # define LRADC_CTRL0_MX28_PLATE_MASK \
283 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
284 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
285 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
286 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
287
288 # define LRADC_CTRL0_MX23_PLATE_MASK \
289 (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \
290 LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \
291 LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP)
292
293 #define LRADC_CTRL1 0x10
294 #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN BIT(24)
295 #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
296 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
297 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
298 #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
299 #define LRADC_CTRL1_TOUCH_DETECT_IRQ BIT(8)
300 #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
301 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
302 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
303 #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
304
305 #define LRADC_CTRL2 0x20
306 #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24
307 #define LRADC_CTRL2_TEMPSENSE_PWD BIT(15)
308
309 #define LRADC_STATUS 0x40
310 #define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0)
311
312 #define LRADC_CH(n) (0x50 + (0x10 * (n)))
313 #define LRADC_CH_ACCUMULATE BIT(29)
314 #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
315 #define LRADC_CH_NUM_SAMPLES_OFFSET 24
316 #define LRADC_CH_NUM_SAMPLES(x) \
317 ((x) << LRADC_CH_NUM_SAMPLES_OFFSET)
318 #define LRADC_CH_VALUE_MASK 0x3ffff
319 #define LRADC_CH_VALUE_OFFSET 0
320
321 #define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
322 #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
323 #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
324 #define LRADC_DELAY_TRIGGER(x) \
325 (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \
326 LRADC_DELAY_TRIGGER_LRADCS_MASK)
327 #define LRADC_DELAY_KICK (1 << 20)
328 #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
329 #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
330 #define LRADC_DELAY_TRIGGER_DELAYS(x) \
331 (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \
332 LRADC_DELAY_TRIGGER_DELAYS_MASK)
333 #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
334 #define LRADC_DELAY_LOOP_COUNT_OFFSET 11
335 #define LRADC_DELAY_LOOP(x) \
336 (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \
337 LRADC_DELAY_LOOP_COUNT_MASK)
338 #define LRADC_DELAY_DELAY_MASK 0x7ff
339 #define LRADC_DELAY_DELAY_OFFSET 0
340 #define LRADC_DELAY_DELAY(x) \
341 (((x) << LRADC_DELAY_DELAY_OFFSET) & \
342 LRADC_DELAY_DELAY_MASK)
343
344 #define LRADC_CTRL4 0x140
345 #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
346 #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
347 #define LRADC_CTRL4_LRADCSELECT(n, x) \
348 (((x) << LRADC_CTRL4_LRADCSELECT_OFFSET(n)) & \
349 LRADC_CTRL4_LRADCSELECT_MASK(n))
350
351 #define LRADC_RESOLUTION 12
352 #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
353
354 static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg)
355 {
356 writel(val, lradc->base + reg + STMP_OFFSET_REG_SET);
357 }
358
359 static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg)
360 {
361 writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR);
362 }
363
364 static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg)
365 {
366 writel(val, lradc->base + reg);
367 }
368
369 static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc)
370 {
371 if (lradc->soc == IMX23_LRADC)
372 return LRADC_CTRL0_MX23_PLATE_MASK;
373 return LRADC_CTRL0_MX28_PLATE_MASK;
374 }
375
376 static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc)
377 {
378 if (lradc->soc == IMX23_LRADC)
379 return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK;
380 return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK;
381 }
382
383 static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc)
384 {
385 if (lradc->soc == IMX23_LRADC)
386 return LRADC_CTRL1_MX23_LRADC_IRQ_MASK;
387 return LRADC_CTRL1_MX28_LRADC_IRQ_MASK;
388 }
389
390 static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc)
391 {
392 if (lradc->soc == IMX23_LRADC)
393 return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE;
394 return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE;
395 }
396
397 static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc)
398 {
399 if (lradc->soc == IMX23_LRADC)
400 return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM;
401 return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
402 }
403
404 static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc)
405 {
406 if (lradc->soc == IMX23_LRADC)
407 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM;
408 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
409 }
410
411 static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc)
412 {
413 if (lradc->soc == IMX23_LRADC)
414 return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM;
415 return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
416 }
417
418 static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc)
419 {
420 return !!(readl(lradc->base + LRADC_STATUS) &
421 LRADC_STATUS_TOUCH_DETECT_RAW);
422 }
423
424 static void mxs_lradc_map_channel(struct mxs_lradc *lradc, unsigned vch,
425 unsigned ch)
426 {
427 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(vch),
428 LRADC_CTRL4);
429 mxs_lradc_reg_set(lradc, LRADC_CTRL4_LRADCSELECT(vch, ch), LRADC_CTRL4);
430 }
431
432 static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch)
433 {
434 /*
435 * prepare for oversampling conversion
436 *
437 * from the datasheet:
438 * "The ACCUMULATE bit in the appropriate channel register
439 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
440 * otherwise, the IRQs will not fire."
441 */
442 mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE |
443 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1),
444 LRADC_CH(ch));
445
446 /* from the datasheet:
447 * "Software must clear this register in preparation for a
448 * multi-cycle accumulation.
449 */
450 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch));
451
452 /*
453 * prepare the delay/loop unit according to the oversampling count
454 *
455 * from the datasheet:
456 * "The DELAY fields in HW_LRADC_DELAY0, HW_LRADC_DELAY1,
457 * HW_LRADC_DELAY2, and HW_LRADC_DELAY3 must be non-zero; otherwise,
458 * the LRADC will not trigger the delay group."
459 */
460 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) |
461 LRADC_DELAY_TRIGGER_DELAYS(0) |
462 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
463 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
464 LRADC_DELAY(3));
465
466 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch), LRADC_CTRL1);
467
468 /*
469 * after changing the touchscreen plates setting
470 * the signals need some initial time to settle. Start the
471 * SoC's delay unit and start the conversion later
472 * and automatically.
473 */
474 mxs_lradc_reg_wrt(lradc,
475 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
476 LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */
477 LRADC_DELAY_KICK |
478 LRADC_DELAY_DELAY(lradc->settling_delay),
479 LRADC_DELAY(2));
480 }
481
482 /*
483 * Pressure detection is special:
484 * We want to do both required measurements for the pressure detection in
485 * one turn. Use the hardware features to chain both conversions and let the
486 * hardware report one interrupt if both conversions are done
487 */
488 static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1,
489 unsigned ch2)
490 {
491 u32 reg;
492
493 /*
494 * prepare for oversampling conversion
495 *
496 * from the datasheet:
497 * "The ACCUMULATE bit in the appropriate channel register
498 * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0;
499 * otherwise, the IRQs will not fire."
500 */
501 reg = LRADC_CH_ACCUMULATE |
502 LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1);
503 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1));
504 mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2));
505
506 /* from the datasheet:
507 * "Software must clear this register in preparation for a
508 * multi-cycle accumulation.
509 */
510 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1));
511 mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2));
512
513 /* prepare the delay/loop unit according to the oversampling count */
514 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch1) |
515 LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */
516 LRADC_DELAY_TRIGGER_DELAYS(0) |
517 LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) |
518 LRADC_DELAY_DELAY(lradc->over_sample_delay - 1),
519 LRADC_DELAY(3));
520
521 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(ch2), LRADC_CTRL1);
522
523 /*
524 * after changing the touchscreen plates setting
525 * the signals need some initial time to settle. Start the
526 * SoC's delay unit and start the conversion later
527 * and automatically.
528 */
529 mxs_lradc_reg_wrt(lradc,
530 LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */
531 LRADC_DELAY_TRIGGER_DELAYS(BIT(3)) | /* trigger DELAY unit#3 */
532 LRADC_DELAY_KICK |
533 LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2));
534 }
535
536 static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc,
537 unsigned channel)
538 {
539 u32 reg;
540 unsigned num_samples, val;
541
542 reg = readl(lradc->base + LRADC_CH(channel));
543 if (reg & LRADC_CH_ACCUMULATE)
544 num_samples = lradc->over_sample_cnt;
545 else
546 num_samples = 1;
547
548 val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET;
549 return val / num_samples;
550 }
551
552 static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc,
553 unsigned ch1, unsigned ch2)
554 {
555 u32 reg, mask;
556 unsigned pressure, m1, m2;
557
558 mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2);
559 reg = readl(lradc->base + LRADC_CTRL1) & mask;
560
561 while (reg != mask) {
562 reg = readl(lradc->base + LRADC_CTRL1) & mask;
563 dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg);
564 }
565
566 m1 = mxs_lradc_read_raw_channel(lradc, ch1);
567 m2 = mxs_lradc_read_raw_channel(lradc, ch2);
568
569 if (m2 == 0) {
570 dev_warn(lradc->dev, "Cannot calculate pressure\n");
571 return 1 << (LRADC_RESOLUTION - 1);
572 }
573
574 /* simply scale the value from 0 ... max ADC resolution */
575 pressure = m1;
576 pressure *= (1 << LRADC_RESOLUTION);
577 pressure /= m2;
578
579 dev_dbg(lradc->dev, "Pressure = %u\n", pressure);
580 return pressure;
581 }
582
583 #define TS_CH_XP 2
584 #define TS_CH_YP 3
585 #define TS_CH_XM 4
586 #define TS_CH_YM 5
587
588 /*
589 * YP(open)--+-------------+
590 * | |--+
591 * | | |
592 * YM(-)--+-------------+ |
593 * +--------------+
594 * | |
595 * XP(weak+) XM(open)
596 *
597 * "weak+" means 200k Ohm VDDIO
598 * (-) means GND
599 */
600 static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc)
601 {
602 /*
603 * In order to detect a touch event the 'touch detect enable' bit
604 * enables:
605 * - a weak pullup to the X+ connector
606 * - a strong ground at the Y- connector
607 */
608 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
609 mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc),
610 LRADC_CTRL0);
611 }
612
613 /*
614 * YP(meas)--+-------------+
615 * | |--+
616 * | | |
617 * YM(open)--+-------------+ |
618 * +--------------+
619 * | |
620 * XP(+) XM(-)
621 *
622 * (+) means here 1.85 V
623 * (-) means here GND
624 */
625 static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc)
626 {
627 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
628 mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0);
629
630 lradc->cur_plate = LRADC_SAMPLE_X;
631 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YP);
632 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
633 }
634
635 /*
636 * YP(+)--+-------------+
637 * | |--+
638 * | | |
639 * YM(-)--+-------------+ |
640 * +--------------+
641 * | |
642 * XP(open) XM(meas)
643 *
644 * (+) means here 1.85 V
645 * (-) means here GND
646 */
647 static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc)
648 {
649 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
650 mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0);
651
652 lradc->cur_plate = LRADC_SAMPLE_Y;
653 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_XM);
654 mxs_lradc_setup_ts_channel(lradc, TOUCHSCREEN_VCHANNEL1);
655 }
656
657 /*
658 * YP(+)--+-------------+
659 * | |--+
660 * | | |
661 * YM(meas)--+-------------+ |
662 * +--------------+
663 * | |
664 * XP(meas) XM(-)
665 *
666 * (+) means here 1.85 V
667 * (-) means here GND
668 */
669 static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc)
670 {
671 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
672 mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0);
673
674 lradc->cur_plate = LRADC_SAMPLE_PRESSURE;
675 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL1, TS_CH_YM);
676 mxs_lradc_map_channel(lradc, TOUCHSCREEN_VCHANNEL2, TS_CH_XP);
677 mxs_lradc_setup_ts_pressure(lradc, TOUCHSCREEN_VCHANNEL2,
678 TOUCHSCREEN_VCHANNEL1);
679 }
680
681 static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc)
682 {
683 mxs_lradc_setup_touch_detection(lradc);
684
685 lradc->cur_plate = LRADC_TOUCH;
686 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
687 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
688 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
689 }
690
691 static void mxs_lradc_start_touch_event(struct mxs_lradc *lradc)
692 {
693 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
694 LRADC_CTRL1);
695 mxs_lradc_reg_set(lradc,
696 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1), LRADC_CTRL1);
697 /*
698 * start with the Y-pos, because it uses nearly the same plate
699 * settings like the touch detection
700 */
701 mxs_lradc_prepare_y_pos(lradc);
702 }
703
704 static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc)
705 {
706 input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos);
707 input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos);
708 input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure);
709 input_report_key(lradc->ts_input, BTN_TOUCH, 1);
710 input_sync(lradc->ts_input);
711 }
712
713 static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc)
714 {
715 mxs_lradc_setup_touch_detection(lradc);
716 lradc->cur_plate = LRADC_SAMPLE_VALID;
717 /*
718 * start a dummy conversion to burn time to settle the signals
719 * note: we are not interested in the conversion's value
720 */
721 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(TOUCHSCREEN_VCHANNEL1));
722 mxs_lradc_reg_clear(lradc,
723 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
724 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1);
725 mxs_lradc_reg_wrt(lradc,
726 LRADC_DELAY_TRIGGER(1 << TOUCHSCREEN_VCHANNEL1) |
727 LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */
728 LRADC_DELAY(2));
729 }
730
731 /*
732 * in order to avoid false measurements, report only samples where
733 * the surface is still touched after the position measurement
734 */
735 static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid)
736 {
737 /* if it is still touched, report the sample */
738 if (valid && mxs_lradc_check_touch_event(lradc)) {
739 lradc->ts_valid = true;
740 mxs_lradc_report_ts_event(lradc);
741 }
742
743 /* if it is even still touched, continue with the next measurement */
744 if (mxs_lradc_check_touch_event(lradc)) {
745 mxs_lradc_prepare_y_pos(lradc);
746 return;
747 }
748
749 if (lradc->ts_valid) {
750 /* signal the release */
751 lradc->ts_valid = false;
752 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
753 input_sync(lradc->ts_input);
754 }
755
756 /* if it is released, wait for the next touch via IRQ */
757 lradc->cur_plate = LRADC_TOUCH;
758 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
759 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
760 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ |
761 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
762 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1), LRADC_CTRL1);
763 mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1);
764 }
765
766 /* touchscreen's state machine */
767 static void mxs_lradc_handle_touch(struct mxs_lradc *lradc)
768 {
769 switch (lradc->cur_plate) {
770 case LRADC_TOUCH:
771 if (mxs_lradc_check_touch_event(lradc))
772 mxs_lradc_start_touch_event(lradc);
773 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ,
774 LRADC_CTRL1);
775 return;
776
777 case LRADC_SAMPLE_Y:
778 lradc->ts_y_pos = mxs_lradc_read_raw_channel(lradc,
779 TOUCHSCREEN_VCHANNEL1);
780 mxs_lradc_prepare_x_pos(lradc);
781 return;
782
783 case LRADC_SAMPLE_X:
784 lradc->ts_x_pos = mxs_lradc_read_raw_channel(lradc,
785 TOUCHSCREEN_VCHANNEL1);
786 mxs_lradc_prepare_pressure(lradc);
787 return;
788
789 case LRADC_SAMPLE_PRESSURE:
790 lradc->ts_pressure = mxs_lradc_read_ts_pressure(lradc,
791 TOUCHSCREEN_VCHANNEL2,
792 TOUCHSCREEN_VCHANNEL1);
793 mxs_lradc_complete_touch_event(lradc);
794 return;
795
796 case LRADC_SAMPLE_VALID:
797 mxs_lradc_finish_touch_event(lradc, 1);
798 break;
799 }
800 }
801
802 /*
803 * Raw I/O operations
804 */
805 static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val)
806 {
807 struct mxs_lradc *lradc = iio_priv(iio_dev);
808 int ret;
809
810 /*
811 * See if there is no buffered operation in progress. If there is, simply
812 * bail out. This can be improved to support both buffered and raw IO at
813 * the same time, yet the code becomes horribly complicated. Therefore I
814 * applied KISS principle here.
815 */
816 ret = mutex_trylock(&lradc->lock);
817 if (!ret)
818 return -EBUSY;
819
820 reinit_completion(&lradc->completion);
821
822 /*
823 * No buffered operation in progress, map the channel and trigger it.
824 * Virtual channel 0 is always used here as the others are always not
825 * used if doing raw sampling.
826 */
827 if (lradc->soc == IMX28_LRADC)
828 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0),
829 LRADC_CTRL1);
830 mxs_lradc_reg_clear(lradc, 0x1, LRADC_CTRL0);
831
832 /* Enable / disable the divider per requirement */
833 if (test_bit(chan, &lradc->is_divided))
834 mxs_lradc_reg_set(lradc, 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
835 LRADC_CTRL2);
836 else
837 mxs_lradc_reg_clear(lradc,
838 1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, LRADC_CTRL2);
839
840 /* Clean the slot's previous content, then set new one. */
841 mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0),
842 LRADC_CTRL4);
843 mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4);
844
845 mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0));
846
847 /* Enable the IRQ and start sampling the channel. */
848 mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
849 mxs_lradc_reg_set(lradc, BIT(0), LRADC_CTRL0);
850
851 /* Wait for completion on the channel, 1 second max. */
852 ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
853 if (!ret)
854 ret = -ETIMEDOUT;
855 if (ret < 0)
856 goto err;
857
858 /* Read the data. */
859 *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
860 ret = IIO_VAL_INT;
861
862 err:
863 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1);
864
865 mutex_unlock(&lradc->lock);
866
867 return ret;
868 }
869
870 static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val)
871 {
872 int ret, min, max;
873
874 ret = mxs_lradc_read_single(iio_dev, 8, &min);
875 if (ret != IIO_VAL_INT)
876 return ret;
877
878 ret = mxs_lradc_read_single(iio_dev, 9, &max);
879 if (ret != IIO_VAL_INT)
880 return ret;
881
882 *val = max - min;
883
884 return IIO_VAL_INT;
885 }
886
887 static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
888 const struct iio_chan_spec *chan,
889 int *val, int *val2, long m)
890 {
891 struct mxs_lradc *lradc = iio_priv(iio_dev);
892
893 switch (m) {
894 case IIO_CHAN_INFO_RAW:
895 if (chan->type == IIO_TEMP)
896 return mxs_lradc_read_temp(iio_dev, val);
897
898 return mxs_lradc_read_single(iio_dev, chan->channel, val);
899
900 case IIO_CHAN_INFO_SCALE:
901 if (chan->type == IIO_TEMP) {
902 /* From the datasheet, we have to multiply by 1.012 and
903 * divide by 4
904 */
905 *val = 0;
906 *val2 = 253000;
907 return IIO_VAL_INT_PLUS_MICRO;
908 }
909
910 *val = lradc->vref_mv[chan->channel];
911 *val2 = chan->scan_type.realbits -
912 test_bit(chan->channel, &lradc->is_divided);
913 return IIO_VAL_FRACTIONAL_LOG2;
914
915 case IIO_CHAN_INFO_OFFSET:
916 if (chan->type == IIO_TEMP) {
917 /* The calculated value from the ADC is in Kelvin, we
918 * want Celsius for hwmon so the offset is
919 * -272.15 * scale
920 */
921 *val = -1075;
922 *val2 = 691699;
923
924 return IIO_VAL_INT_PLUS_MICRO;
925 }
926
927 return -EINVAL;
928
929 default:
930 break;
931 }
932
933 return -EINVAL;
934 }
935
936 static int mxs_lradc_write_raw(struct iio_dev *iio_dev,
937 const struct iio_chan_spec *chan,
938 int val, int val2, long m)
939 {
940 struct mxs_lradc *lradc = iio_priv(iio_dev);
941 struct mxs_lradc_scale *scale_avail =
942 lradc->scale_avail[chan->channel];
943 int ret;
944
945 ret = mutex_trylock(&lradc->lock);
946 if (!ret)
947 return -EBUSY;
948
949 switch (m) {
950 case IIO_CHAN_INFO_SCALE:
951 ret = -EINVAL;
952 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
953 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
954 /* divider by two disabled */
955 clear_bit(chan->channel, &lradc->is_divided);
956 ret = 0;
957 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
958 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
959 /* divider by two enabled */
960 set_bit(chan->channel, &lradc->is_divided);
961 ret = 0;
962 }
963
964 break;
965 default:
966 ret = -EINVAL;
967 break;
968 }
969
970 mutex_unlock(&lradc->lock);
971
972 return ret;
973 }
974
975 static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev,
976 const struct iio_chan_spec *chan,
977 long m)
978 {
979 return IIO_VAL_INT_PLUS_NANO;
980 }
981
982 static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev,
983 struct device_attribute *attr,
984 char *buf,
985 int ch)
986 {
987 struct iio_dev *iio = dev_to_iio_dev(dev);
988 struct mxs_lradc *lradc = iio_priv(iio);
989 int i, len = 0;
990
991 for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++)
992 len += sprintf(buf + len, "%u.%09u ",
993 lradc->scale_avail[ch][i].integer,
994 lradc->scale_avail[ch][i].nano);
995
996 len += sprintf(buf + len, "\n");
997
998 return len;
999 }
1000
1001 static ssize_t mxs_lradc_show_scale_available(struct device *dev,
1002 struct device_attribute *attr,
1003 char *buf)
1004 {
1005 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
1006
1007 return mxs_lradc_show_scale_available_ch(dev, attr, buf,
1008 iio_attr->address);
1009 }
1010
1011 #define SHOW_SCALE_AVAILABLE_ATTR(ch) \
1012 static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO, \
1013 mxs_lradc_show_scale_available, NULL, ch)
1014
1015 SHOW_SCALE_AVAILABLE_ATTR(0);
1016 SHOW_SCALE_AVAILABLE_ATTR(1);
1017 SHOW_SCALE_AVAILABLE_ATTR(2);
1018 SHOW_SCALE_AVAILABLE_ATTR(3);
1019 SHOW_SCALE_AVAILABLE_ATTR(4);
1020 SHOW_SCALE_AVAILABLE_ATTR(5);
1021 SHOW_SCALE_AVAILABLE_ATTR(6);
1022 SHOW_SCALE_AVAILABLE_ATTR(7);
1023 SHOW_SCALE_AVAILABLE_ATTR(10);
1024 SHOW_SCALE_AVAILABLE_ATTR(11);
1025 SHOW_SCALE_AVAILABLE_ATTR(12);
1026 SHOW_SCALE_AVAILABLE_ATTR(13);
1027 SHOW_SCALE_AVAILABLE_ATTR(14);
1028 SHOW_SCALE_AVAILABLE_ATTR(15);
1029
1030 static struct attribute *mxs_lradc_attributes[] = {
1031 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
1032 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
1033 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
1034 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
1035 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
1036 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
1037 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
1038 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
1039 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
1040 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
1041 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
1042 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
1043 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
1044 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
1045 NULL
1046 };
1047
1048 static const struct attribute_group mxs_lradc_attribute_group = {
1049 .attrs = mxs_lradc_attributes,
1050 };
1051
1052 static const struct iio_info mxs_lradc_iio_info = {
1053 .driver_module = THIS_MODULE,
1054 .read_raw = mxs_lradc_read_raw,
1055 .write_raw = mxs_lradc_write_raw,
1056 .write_raw_get_fmt = mxs_lradc_write_raw_get_fmt,
1057 .attrs = &mxs_lradc_attribute_group,
1058 };
1059
1060 static int mxs_lradc_ts_open(struct input_dev *dev)
1061 {
1062 struct mxs_lradc *lradc = input_get_drvdata(dev);
1063
1064 /* Enable the touch-detect circuitry. */
1065 mxs_lradc_enable_touch_detection(lradc);
1066
1067 return 0;
1068 }
1069
1070 static void mxs_lradc_disable_ts(struct mxs_lradc *lradc)
1071 {
1072 /* stop all interrupts from firing */
1073 mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
1074 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL1) |
1075 LRADC_CTRL1_LRADC_IRQ_EN(TOUCHSCREEN_VCHANNEL2), LRADC_CTRL1);
1076
1077 /* Power-down touchscreen touch-detect circuitry. */
1078 mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0);
1079 }
1080
1081 static void mxs_lradc_ts_close(struct input_dev *dev)
1082 {
1083 struct mxs_lradc *lradc = input_get_drvdata(dev);
1084
1085 mxs_lradc_disable_ts(lradc);
1086 }
1087
1088 static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
1089 {
1090 struct input_dev *input;
1091 struct device *dev = lradc->dev;
1092 int ret;
1093
1094 if (!lradc->use_touchscreen)
1095 return 0;
1096
1097 input = input_allocate_device();
1098 if (!input)
1099 return -ENOMEM;
1100
1101 input->name = DRIVER_NAME;
1102 input->id.bustype = BUS_HOST;
1103 input->dev.parent = dev;
1104 input->open = mxs_lradc_ts_open;
1105 input->close = mxs_lradc_ts_close;
1106
1107 __set_bit(EV_ABS, input->evbit);
1108 __set_bit(EV_KEY, input->evbit);
1109 __set_bit(BTN_TOUCH, input->keybit);
1110 input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1111 input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
1112 input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
1113 0, 0);
1114
1115 lradc->ts_input = input;
1116 input_set_drvdata(input, lradc);
1117 ret = input_register_device(input);
1118 if (ret)
1119 input_free_device(lradc->ts_input);
1120
1121 return ret;
1122 }
1123
1124 static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
1125 {
1126 if (!lradc->use_touchscreen)
1127 return;
1128
1129 mxs_lradc_disable_ts(lradc);
1130 input_unregister_device(lradc->ts_input);
1131 }
1132
1133 /*
1134 * IRQ Handling
1135 */
1136 static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
1137 {
1138 struct iio_dev *iio = data;
1139 struct mxs_lradc *lradc = iio_priv(iio);
1140 unsigned long reg = readl(lradc->base + LRADC_CTRL1);
1141 uint32_t clr_irq = mxs_lradc_irq_mask(lradc);
1142 const uint32_t ts_irq_mask =
1143 LRADC_CTRL1_TOUCH_DETECT_IRQ |
1144 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1145 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2);
1146
1147 if (!(reg & mxs_lradc_irq_mask(lradc)))
1148 return IRQ_NONE;
1149
1150 if (lradc->use_touchscreen && (reg & ts_irq_mask)) {
1151 mxs_lradc_handle_touch(lradc);
1152
1153 /* Make sure we don't clear the next conversion's interrupt. */
1154 clr_irq &= ~(LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL1) |
1155 LRADC_CTRL1_LRADC_IRQ(TOUCHSCREEN_VCHANNEL2));
1156 }
1157
1158 if (iio_buffer_enabled(iio)) {
1159 if (reg & lradc->buffer_vchans)
1160 iio_trigger_poll(iio->trig);
1161 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
1162 complete(&lradc->completion);
1163 }
1164
1165 mxs_lradc_reg_clear(lradc, reg & clr_irq, LRADC_CTRL1);
1166
1167 return IRQ_HANDLED;
1168 }
1169
1170 /*
1171 * Trigger handling
1172 */
1173 static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
1174 {
1175 struct iio_poll_func *pf = p;
1176 struct iio_dev *iio = pf->indio_dev;
1177 struct mxs_lradc *lradc = iio_priv(iio);
1178 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1179 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1180 unsigned int i, j = 0;
1181
1182 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1183 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
1184 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j));
1185 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
1186 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
1187 j++;
1188 }
1189
1190 iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
1191
1192 iio_trigger_notify_done(iio->trig);
1193
1194 return IRQ_HANDLED;
1195 }
1196
1197 static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
1198 {
1199 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
1200 struct mxs_lradc *lradc = iio_priv(iio);
1201 const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
1202
1203 mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st);
1204
1205 return 0;
1206 }
1207
1208 static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
1209 .owner = THIS_MODULE,
1210 .set_trigger_state = &mxs_lradc_configure_trigger,
1211 };
1212
1213 static int mxs_lradc_trigger_init(struct iio_dev *iio)
1214 {
1215 int ret;
1216 struct iio_trigger *trig;
1217 struct mxs_lradc *lradc = iio_priv(iio);
1218
1219 trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
1220 if (trig == NULL)
1221 return -ENOMEM;
1222
1223 trig->dev.parent = lradc->dev;
1224 iio_trigger_set_drvdata(trig, iio);
1225 trig->ops = &mxs_lradc_trigger_ops;
1226
1227 ret = iio_trigger_register(trig);
1228 if (ret) {
1229 iio_trigger_free(trig);
1230 return ret;
1231 }
1232
1233 lradc->trig = trig;
1234
1235 return 0;
1236 }
1237
1238 static void mxs_lradc_trigger_remove(struct iio_dev *iio)
1239 {
1240 struct mxs_lradc *lradc = iio_priv(iio);
1241
1242 iio_trigger_unregister(lradc->trig);
1243 iio_trigger_free(lradc->trig);
1244 }
1245
1246 static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
1247 {
1248 struct mxs_lradc *lradc = iio_priv(iio);
1249 int ret = 0, chan, ofs = 0;
1250 unsigned long enable = 0;
1251 uint32_t ctrl4_set = 0;
1252 uint32_t ctrl4_clr = 0;
1253 uint32_t ctrl1_irq = 0;
1254 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
1255 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
1256 const int len = bitmap_weight(iio->active_scan_mask,
1257 LRADC_MAX_TOTAL_CHANS);
1258
1259 if (!len)
1260 return -EINVAL;
1261
1262 /*
1263 * Lock the driver so raw access can not be done during buffered
1264 * operation. This simplifies the code a lot.
1265 */
1266 ret = mutex_trylock(&lradc->lock);
1267 if (!ret)
1268 return -EBUSY;
1269
1270 lradc->buffer = kmalloc_array(len, sizeof(*lradc->buffer), GFP_KERNEL);
1271 if (!lradc->buffer) {
1272 ret = -ENOMEM;
1273 goto err_mem;
1274 }
1275
1276 if (lradc->soc == IMX28_LRADC)
1277 mxs_lradc_reg_clear(lradc,
1278 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1279 LRADC_CTRL1);
1280 mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
1281
1282 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
1283 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
1284 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
1285 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
1286 mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs));
1287 bitmap_set(&enable, ofs, 1);
1288 ofs++;
1289 }
1290
1291 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1292 LRADC_DELAY_KICK, LRADC_DELAY(0));
1293 mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4);
1294 mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4);
1295 mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1);
1296 mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
1297 LRADC_DELAY(0));
1298
1299 return 0;
1300
1301 err_mem:
1302 mutex_unlock(&lradc->lock);
1303 return ret;
1304 }
1305
1306 static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
1307 {
1308 struct mxs_lradc *lradc = iio_priv(iio);
1309
1310 mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK |
1311 LRADC_DELAY_KICK, LRADC_DELAY(0));
1312
1313 mxs_lradc_reg_clear(lradc, lradc->buffer_vchans, LRADC_CTRL0);
1314 if (lradc->soc == IMX28_LRADC)
1315 mxs_lradc_reg_clear(lradc,
1316 lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
1317 LRADC_CTRL1);
1318
1319 kfree(lradc->buffer);
1320 mutex_unlock(&lradc->lock);
1321
1322 return 0;
1323 }
1324
1325 static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
1326 const unsigned long *mask)
1327 {
1328 struct mxs_lradc *lradc = iio_priv(iio);
1329 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
1330 int rsvd_chans = 0;
1331 unsigned long rsvd_mask = 0;
1332
1333 if (lradc->use_touchbutton)
1334 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
1335 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
1336 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
1337 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1338 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
1339
1340 if (lradc->use_touchbutton)
1341 rsvd_chans++;
1342 if (lradc->use_touchscreen)
1343 rsvd_chans += 2;
1344
1345 /* Test for attempts to map channels with special mode of operation. */
1346 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
1347 return false;
1348
1349 /* Test for attempts to map more channels then available slots. */
1350 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
1351 return false;
1352
1353 return true;
1354 }
1355
1356 static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
1357 .preenable = &mxs_lradc_buffer_preenable,
1358 .postenable = &iio_triggered_buffer_postenable,
1359 .predisable = &iio_triggered_buffer_predisable,
1360 .postdisable = &mxs_lradc_buffer_postdisable,
1361 .validate_scan_mask = &mxs_lradc_validate_scan_mask,
1362 };
1363
1364 /*
1365 * Driver initialization
1366 */
1367
1368 #define MXS_ADC_CHAN(idx, chan_type) { \
1369 .type = (chan_type), \
1370 .indexed = 1, \
1371 .scan_index = (idx), \
1372 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1373 BIT(IIO_CHAN_INFO_SCALE), \
1374 .channel = (idx), \
1375 .address = (idx), \
1376 .scan_type = { \
1377 .sign = 'u', \
1378 .realbits = LRADC_RESOLUTION, \
1379 .storagebits = 32, \
1380 }, \
1381 }
1382
1383 static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
1384 MXS_ADC_CHAN(0, IIO_VOLTAGE),
1385 MXS_ADC_CHAN(1, IIO_VOLTAGE),
1386 MXS_ADC_CHAN(2, IIO_VOLTAGE),
1387 MXS_ADC_CHAN(3, IIO_VOLTAGE),
1388 MXS_ADC_CHAN(4, IIO_VOLTAGE),
1389 MXS_ADC_CHAN(5, IIO_VOLTAGE),
1390 MXS_ADC_CHAN(6, IIO_VOLTAGE),
1391 MXS_ADC_CHAN(7, IIO_VOLTAGE),
1392 /* Combined Temperature sensors */
1393 {
1394 .type = IIO_TEMP,
1395 .indexed = 1,
1396 .scan_index = 8,
1397 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1398 BIT(IIO_CHAN_INFO_OFFSET) |
1399 BIT(IIO_CHAN_INFO_SCALE),
1400 .channel = 8,
1401 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
1402 },
1403 /* Hidden channel to keep indexes */
1404 {
1405 .type = IIO_TEMP,
1406 .indexed = 1,
1407 .scan_index = -1,
1408 .channel = 9,
1409 },
1410 MXS_ADC_CHAN(10, IIO_VOLTAGE),
1411 MXS_ADC_CHAN(11, IIO_VOLTAGE),
1412 MXS_ADC_CHAN(12, IIO_VOLTAGE),
1413 MXS_ADC_CHAN(13, IIO_VOLTAGE),
1414 MXS_ADC_CHAN(14, IIO_VOLTAGE),
1415 MXS_ADC_CHAN(15, IIO_VOLTAGE),
1416 };
1417
1418 static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
1419 {
1420 /* The ADC always uses DELAY CHANNEL 0. */
1421 const uint32_t adc_cfg =
1422 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
1423 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
1424
1425 int ret = stmp_reset_block(lradc->base);
1426
1427 if (ret)
1428 return ret;
1429
1430 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
1431 mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0));
1432
1433 /* Disable remaining DELAY CHANNELs */
1434 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1));
1435 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2));
1436 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3));
1437
1438 /* Configure the touchscreen type */
1439 if (lradc->soc == IMX28_LRADC) {
1440 mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1441 LRADC_CTRL0);
1442
1443 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
1444 mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
1445 LRADC_CTRL0);
1446 }
1447
1448 /* Start internal temperature sensing. */
1449 mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2);
1450
1451 return 0;
1452 }
1453
1454 static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
1455 {
1456 int i;
1457
1458 mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1);
1459
1460 for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
1461 mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i));
1462 }
1463
1464 static const struct of_device_id mxs_lradc_dt_ids[] = {
1465 { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
1466 { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
1467 { /* sentinel */ }
1468 };
1469 MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
1470
1471 static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc,
1472 struct device_node *lradc_node)
1473 {
1474 int ret;
1475 u32 ts_wires = 0, adapt;
1476
1477 ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires",
1478 &ts_wires);
1479 if (ret)
1480 return -ENODEV; /* touchscreen feature disabled */
1481
1482 switch (ts_wires) {
1483 case 4:
1484 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
1485 break;
1486 case 5:
1487 if (lradc->soc == IMX28_LRADC) {
1488 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
1489 break;
1490 }
1491 /* fall through an error message for i.MX23 */
1492 default:
1493 dev_err(lradc->dev,
1494 "Unsupported number of touchscreen wires (%d)\n",
1495 ts_wires);
1496 return -EINVAL;
1497 }
1498
1499 if (of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt)) {
1500 lradc->over_sample_cnt = 4;
1501 } else {
1502 if (adapt < 1 || adapt > 32) {
1503 dev_err(lradc->dev, "Invalid sample count (%u)\n",
1504 adapt);
1505 return -EINVAL;
1506 }
1507 lradc->over_sample_cnt = adapt;
1508 }
1509
1510 if (of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt)) {
1511 lradc->over_sample_delay = 2;
1512 } else {
1513 if (adapt < 2 || adapt > LRADC_DELAY_DELAY_MASK + 1) {
1514 dev_err(lradc->dev, "Invalid sample delay (%u)\n",
1515 adapt);
1516 return -EINVAL;
1517 }
1518 lradc->over_sample_delay = adapt;
1519 }
1520
1521 if (of_property_read_u32(lradc_node, "fsl,settling", &adapt)) {
1522 lradc->settling_delay = 10;
1523 } else {
1524 if (adapt < 1 || adapt > LRADC_DELAY_DELAY_MASK) {
1525 dev_err(lradc->dev, "Invalid settling delay (%u)\n",
1526 adapt);
1527 return -EINVAL;
1528 }
1529 lradc->settling_delay = adapt;
1530 }
1531
1532 return 0;
1533 }
1534
1535 static int mxs_lradc_probe(struct platform_device *pdev)
1536 {
1537 const struct of_device_id *of_id =
1538 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
1539 const struct mxs_lradc_of_config *of_cfg =
1540 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
1541 struct device *dev = &pdev->dev;
1542 struct device_node *node = dev->of_node;
1543 struct mxs_lradc *lradc;
1544 struct iio_dev *iio;
1545 struct resource *iores;
1546 int ret = 0, touch_ret;
1547 int i, s;
1548 uint64_t scale_uv;
1549
1550 /* Allocate the IIO device. */
1551 iio = devm_iio_device_alloc(dev, sizeof(*lradc));
1552 if (!iio) {
1553 dev_err(dev, "Failed to allocate IIO device\n");
1554 return -ENOMEM;
1555 }
1556
1557 lradc = iio_priv(iio);
1558 lradc->soc = (enum mxs_lradc_id)of_id->data;
1559
1560 /* Grab the memory area */
1561 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1562 lradc->dev = &pdev->dev;
1563 lradc->base = devm_ioremap_resource(dev, iores);
1564 if (IS_ERR(lradc->base))
1565 return PTR_ERR(lradc->base);
1566
1567 lradc->clk = devm_clk_get(&pdev->dev, NULL);
1568 if (IS_ERR(lradc->clk)) {
1569 dev_err(dev, "Failed to get the delay unit clock\n");
1570 return PTR_ERR(lradc->clk);
1571 }
1572 ret = clk_prepare_enable(lradc->clk);
1573 if (ret != 0) {
1574 dev_err(dev, "Failed to enable the delay unit clock\n");
1575 return ret;
1576 }
1577
1578 touch_ret = mxs_lradc_probe_touchscreen(lradc, node);
1579
1580 if (touch_ret == 0)
1581 lradc->buffer_vchans = BUFFER_VCHANS_LIMITED;
1582 else
1583 lradc->buffer_vchans = BUFFER_VCHANS_ALL;
1584
1585 /* Grab all IRQ sources */
1586 for (i = 0; i < of_cfg->irq_count; i++) {
1587 lradc->irq[i] = platform_get_irq(pdev, i);
1588 if (lradc->irq[i] < 0) {
1589 ret = lradc->irq[i];
1590 goto err_clk;
1591 }
1592
1593 ret = devm_request_irq(dev, lradc->irq[i],
1594 mxs_lradc_handle_irq, 0,
1595 of_cfg->irq_name[i], iio);
1596 if (ret)
1597 goto err_clk;
1598 }
1599
1600 lradc->vref_mv = of_cfg->vref_mv;
1601
1602 platform_set_drvdata(pdev, iio);
1603
1604 init_completion(&lradc->completion);
1605 mutex_init(&lradc->lock);
1606
1607 iio->name = pdev->name;
1608 iio->dev.parent = &pdev->dev;
1609 iio->info = &mxs_lradc_iio_info;
1610 iio->modes = INDIO_DIRECT_MODE;
1611 iio->channels = mxs_lradc_chan_spec;
1612 iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
1613 iio->masklength = LRADC_MAX_TOTAL_CHANS;
1614
1615 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
1616 &mxs_lradc_trigger_handler,
1617 &mxs_lradc_buffer_ops);
1618 if (ret)
1619 goto err_clk;
1620
1621 ret = mxs_lradc_trigger_init(iio);
1622 if (ret)
1623 goto err_trig;
1624
1625 /* Populate available ADC input ranges */
1626 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
1627 for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) {
1628 /*
1629 * [s=0] = optional divider by two disabled (default)
1630 * [s=1] = optional divider by two enabled
1631 *
1632 * The scale is calculated by doing:
1633 * Vref >> (realbits - s)
1634 * which multiplies by two on the second component
1635 * of the array.
1636 */
1637 scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >>
1638 (LRADC_RESOLUTION - s);
1639 lradc->scale_avail[i][s].nano =
1640 do_div(scale_uv, 100000000) * 10;
1641 lradc->scale_avail[i][s].integer = scale_uv;
1642 }
1643 }
1644
1645 /* Configure the hardware. */
1646 ret = mxs_lradc_hw_init(lradc);
1647 if (ret)
1648 goto err_dev;
1649
1650 /* Register the touchscreen input device. */
1651 if (touch_ret == 0) {
1652 ret = mxs_lradc_ts_register(lradc);
1653 if (ret)
1654 goto err_ts_register;
1655 }
1656
1657 /* Register IIO device. */
1658 ret = iio_device_register(iio);
1659 if (ret) {
1660 dev_err(dev, "Failed to register IIO device\n");
1661 goto err_ts;
1662 }
1663
1664 return 0;
1665
1666 err_ts:
1667 mxs_lradc_ts_unregister(lradc);
1668 err_ts_register:
1669 mxs_lradc_hw_stop(lradc);
1670 err_dev:
1671 mxs_lradc_trigger_remove(iio);
1672 err_trig:
1673 iio_triggered_buffer_cleanup(iio);
1674 err_clk:
1675 clk_disable_unprepare(lradc->clk);
1676 return ret;
1677 }
1678
1679 static int mxs_lradc_remove(struct platform_device *pdev)
1680 {
1681 struct iio_dev *iio = platform_get_drvdata(pdev);
1682 struct mxs_lradc *lradc = iio_priv(iio);
1683
1684 iio_device_unregister(iio);
1685 mxs_lradc_ts_unregister(lradc);
1686 mxs_lradc_hw_stop(lradc);
1687 mxs_lradc_trigger_remove(iio);
1688 iio_triggered_buffer_cleanup(iio);
1689
1690 clk_disable_unprepare(lradc->clk);
1691 return 0;
1692 }
1693
1694 static struct platform_driver mxs_lradc_driver = {
1695 .driver = {
1696 .name = DRIVER_NAME,
1697 .of_match_table = mxs_lradc_dt_ids,
1698 },
1699 .probe = mxs_lradc_probe,
1700 .remove = mxs_lradc_remove,
1701 };
1702
1703 module_platform_driver(mxs_lradc_driver);
1704
1705 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1706 MODULE_DESCRIPTION("Freescale MXS LRADC driver");
1707 MODULE_LICENSE("GPL v2");
1708 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux kernel - Deliverables
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