Merge branch 'x86/espfix' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip...
[deliverable/linux.git] / drivers / staging / media / solo6x10 / solo6x10-enc.c
1 /*
2 * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
3 *
4 * Original author:
5 * Ben Collins <bcollins@ubuntu.com>
6 *
7 * Additional work by:
8 * John Brooks <john.brooks@bluecherry.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/font.h>
27 #include <linux/bitrev.h>
28 #include <linux/slab.h>
29
30 #include "solo6x10.h"
31
32 #define VI_PROG_HSIZE (1280 - 16)
33 #define VI_PROG_VSIZE (1024 - 16)
34
35 #define IRQ_LEVEL 2
36
37 static void solo_capture_config(struct solo_dev *solo_dev)
38 {
39 unsigned long height;
40 unsigned long width;
41 void *buf;
42 int i;
43
44 solo_reg_write(solo_dev, SOLO_CAP_BASE,
45 SOLO_CAP_MAX_PAGE((SOLO_CAP_EXT_SIZE(solo_dev)
46 - SOLO_CAP_PAGE_SIZE) >> 16)
47 | SOLO_CAP_BASE_ADDR(SOLO_CAP_EXT_ADDR(solo_dev) >> 16));
48
49 /* XXX: Undocumented bits at b17 and b24 */
50 if (solo_dev->type == SOLO_DEV_6110) {
51 /* NOTE: Ref driver has (62 << 24) here as well, but it causes
52 * wacked out frame timing on 4-port 6110. */
53 solo_reg_write(solo_dev, SOLO_CAP_BTW,
54 (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
55 SOLO_CAP_MAX_BANDWIDTH(36));
56 } else {
57 solo_reg_write(solo_dev, SOLO_CAP_BTW,
58 (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
59 SOLO_CAP_MAX_BANDWIDTH(32));
60 }
61
62 /* Set scale 1, 9 dimension */
63 width = solo_dev->video_hsize;
64 height = solo_dev->video_vsize;
65 solo_reg_write(solo_dev, SOLO_DIM_SCALE1,
66 SOLO_DIM_H_MB_NUM(width / 16) |
67 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
68 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
69
70 /* Set scale 2, 10 dimension */
71 width = solo_dev->video_hsize / 2;
72 height = solo_dev->video_vsize;
73 solo_reg_write(solo_dev, SOLO_DIM_SCALE2,
74 SOLO_DIM_H_MB_NUM(width / 16) |
75 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
76 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
77
78 /* Set scale 3, 11 dimension */
79 width = solo_dev->video_hsize / 2;
80 height = solo_dev->video_vsize / 2;
81 solo_reg_write(solo_dev, SOLO_DIM_SCALE3,
82 SOLO_DIM_H_MB_NUM(width / 16) |
83 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
84 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
85
86 /* Set scale 4, 12 dimension */
87 width = solo_dev->video_hsize / 3;
88 height = solo_dev->video_vsize / 3;
89 solo_reg_write(solo_dev, SOLO_DIM_SCALE4,
90 SOLO_DIM_H_MB_NUM(width / 16) |
91 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
92 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
93
94 /* Set scale 5, 13 dimension */
95 width = solo_dev->video_hsize / 4;
96 height = solo_dev->video_vsize / 2;
97 solo_reg_write(solo_dev, SOLO_DIM_SCALE5,
98 SOLO_DIM_H_MB_NUM(width / 16) |
99 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
100 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
101
102 /* Progressive */
103 width = VI_PROG_HSIZE;
104 height = VI_PROG_VSIZE;
105 solo_reg_write(solo_dev, SOLO_DIM_PROG,
106 SOLO_DIM_H_MB_NUM(width / 16) |
107 SOLO_DIM_V_MB_NUM_FRAME(height / 16) |
108 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
109
110 /* Clear OSD */
111 solo_reg_write(solo_dev, SOLO_VE_OSD_CH, 0);
112 solo_reg_write(solo_dev, SOLO_VE_OSD_BASE, SOLO_EOSD_EXT_ADDR >> 16);
113 solo_reg_write(solo_dev, SOLO_VE_OSD_CLR,
114 0xF0 << 16 | 0x80 << 8 | 0x80);
115
116 if (solo_dev->type == SOLO_DEV_6010)
117 solo_reg_write(solo_dev, SOLO_VE_OSD_OPT,
118 SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);
119 else
120 solo_reg_write(solo_dev, SOLO_VE_OSD_OPT, SOLO_VE_OSD_V_DOUBLE
121 | SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);
122
123 /* Clear OSG buffer */
124 buf = kzalloc(SOLO_EOSD_EXT_SIZE(solo_dev), GFP_KERNEL);
125 if (!buf)
126 return;
127
128 for (i = 0; i < solo_dev->nr_chans; i++) {
129 solo_p2m_dma(solo_dev, 1, buf,
130 SOLO_EOSD_EXT_ADDR +
131 (SOLO_EOSD_EXT_SIZE(solo_dev) * i),
132 SOLO_EOSD_EXT_SIZE(solo_dev), 0, 0);
133 }
134 kfree(buf);
135 }
136
137 #define SOLO_OSD_WRITE_SIZE (16 * OSD_TEXT_MAX)
138
139 /* Should be called with enable_lock held */
140 int solo_osd_print(struct solo_enc_dev *solo_enc)
141 {
142 struct solo_dev *solo_dev = solo_enc->solo_dev;
143 unsigned char *str = solo_enc->osd_text;
144 u8 *buf = solo_enc->osd_buf;
145 u32 reg;
146 const struct font_desc *vga = find_font("VGA8x16");
147 const unsigned char *vga_data;
148 int i, j;
149
150 if (WARN_ON_ONCE(!vga))
151 return -ENODEV;
152
153 reg = solo_reg_read(solo_dev, SOLO_VE_OSD_CH);
154 if (!*str) {
155 /* Disable OSD on this channel */
156 reg &= ~(1 << solo_enc->ch);
157 goto out;
158 }
159
160 memset(buf, 0, SOLO_OSD_WRITE_SIZE);
161 vga_data = (const unsigned char *)vga->data;
162
163 for (i = 0; *str; i++, str++) {
164 for (j = 0; j < 16; j++) {
165 buf[(j << 1) | (i & 1) | ((i & ~1) << 4)] =
166 bitrev8(vga_data[(*str << 4) | j]);
167 }
168 }
169
170 solo_p2m_dma(solo_dev, 1, buf,
171 SOLO_EOSD_EXT_ADDR_CHAN(solo_dev, solo_enc->ch),
172 SOLO_OSD_WRITE_SIZE, 0, 0);
173
174 /* Enable OSD on this channel */
175 reg |= (1 << solo_enc->ch);
176
177 out:
178 solo_reg_write(solo_dev, SOLO_VE_OSD_CH, reg);
179 return 0;
180 }
181
182 /**
183 * Set channel Quality Profile (0-3).
184 */
185 void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
186 unsigned int qp)
187 {
188 unsigned long flags;
189 unsigned int idx, reg;
190
191 if ((ch > 31) || (qp > 3))
192 return;
193
194 if (solo_dev->type == SOLO_DEV_6010)
195 return;
196
197 if (ch < 16) {
198 idx = 0;
199 reg = SOLO_VE_JPEG_QP_CH_L;
200 } else {
201 ch -= 16;
202 idx = 1;
203 reg = SOLO_VE_JPEG_QP_CH_H;
204 }
205 ch *= 2;
206
207 spin_lock_irqsave(&solo_dev->jpeg_qp_lock, flags);
208
209 solo_dev->jpeg_qp[idx] &= ~(3 << ch);
210 solo_dev->jpeg_qp[idx] |= (qp & 3) << ch;
211
212 solo_reg_write(solo_dev, reg, solo_dev->jpeg_qp[idx]);
213
214 spin_unlock_irqrestore(&solo_dev->jpeg_qp_lock, flags);
215 }
216
217 int solo_g_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch)
218 {
219 int idx;
220
221 if (solo_dev->type == SOLO_DEV_6010)
222 return 2;
223
224 if (WARN_ON_ONCE(ch > 31))
225 return 2;
226
227 if (ch < 16) {
228 idx = 0;
229 } else {
230 ch -= 16;
231 idx = 1;
232 }
233 ch *= 2;
234
235 return (solo_dev->jpeg_qp[idx] >> ch) & 3;
236 }
237
238 #define SOLO_QP_INIT 0xaaaaaaaa
239
240 static void solo_jpeg_config(struct solo_dev *solo_dev)
241 {
242 if (solo_dev->type == SOLO_DEV_6010) {
243 solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
244 (2 << 24) | (2 << 16) | (2 << 8) | 2);
245 } else {
246 solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
247 (4 << 24) | (3 << 16) | (2 << 8) | 1);
248 }
249
250 spin_lock_init(&solo_dev->jpeg_qp_lock);
251
252 /* Initialize Quality Profile for all channels */
253 solo_dev->jpeg_qp[0] = solo_dev->jpeg_qp[1] = SOLO_QP_INIT;
254 solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_L, SOLO_QP_INIT);
255 solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_H, SOLO_QP_INIT);
256
257 solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG,
258 (SOLO_JPEG_EXT_SIZE(solo_dev) & 0xffff0000) |
259 ((SOLO_JPEG_EXT_ADDR(solo_dev) >> 16) & 0x0000ffff));
260 solo_reg_write(solo_dev, SOLO_VE_JPEG_CTRL, 0xffffffff);
261 if (solo_dev->type == SOLO_DEV_6110) {
262 solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG1,
263 (0 << 16) | (30 << 8) | 60);
264 }
265 }
266
267 static void solo_mp4e_config(struct solo_dev *solo_dev)
268 {
269 int i;
270 u32 cfg;
271
272 solo_reg_write(solo_dev, SOLO_VE_CFG0,
273 SOLO_VE_INTR_CTRL(IRQ_LEVEL) |
274 SOLO_VE_BLOCK_SIZE(SOLO_MP4E_EXT_SIZE(solo_dev) >> 16) |
275 SOLO_VE_BLOCK_BASE(SOLO_MP4E_EXT_ADDR(solo_dev) >> 16));
276
277
278 cfg = SOLO_VE_BYTE_ALIGN(2) | SOLO_VE_INSERT_INDEX
279 | SOLO_VE_MOTION_MODE(0);
280 if (solo_dev->type != SOLO_DEV_6010) {
281 cfg |= SOLO_VE_MPEG_SIZE_H(
282 (SOLO_MP4E_EXT_SIZE(solo_dev) >> 24) & 0x0f);
283 cfg |= SOLO_VE_JPEG_SIZE_H(
284 (SOLO_JPEG_EXT_SIZE(solo_dev) >> 24) & 0x0f);
285 }
286 solo_reg_write(solo_dev, SOLO_VE_CFG1, cfg);
287
288 solo_reg_write(solo_dev, SOLO_VE_WMRK_POLY, 0);
289 solo_reg_write(solo_dev, SOLO_VE_VMRK_INIT_KEY, 0);
290 solo_reg_write(solo_dev, SOLO_VE_WMRK_STRL, 0);
291 if (solo_dev->type == SOLO_DEV_6110)
292 solo_reg_write(solo_dev, SOLO_VE_WMRK_ENABLE, 0);
293 solo_reg_write(solo_dev, SOLO_VE_ENCRYP_POLY, 0);
294 solo_reg_write(solo_dev, SOLO_VE_ENCRYP_INIT, 0);
295
296 solo_reg_write(solo_dev, SOLO_VE_ATTR,
297 SOLO_VE_LITTLE_ENDIAN |
298 SOLO_COMP_ATTR_FCODE(1) |
299 SOLO_COMP_TIME_INC(0) |
300 SOLO_COMP_TIME_WIDTH(15) |
301 SOLO_DCT_INTERVAL(solo_dev->type == SOLO_DEV_6010 ? 9 : 10));
302
303 for (i = 0; i < solo_dev->nr_chans; i++) {
304 solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE(i),
305 (SOLO_EREF_EXT_ADDR(solo_dev) +
306 (i * SOLO_EREF_EXT_SIZE)) >> 16);
307 solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE_E(i),
308 (SOLO_EREF_EXT_ADDR(solo_dev) +
309 ((i + 16) * SOLO_EREF_EXT_SIZE)) >> 16);
310 }
311
312 if (solo_dev->type == SOLO_DEV_6110) {
313 solo_reg_write(solo_dev, SOLO_VE_COMPT_MOT, 0x00040008);
314 } else {
315 for (i = 0; i < solo_dev->nr_chans; i++)
316 solo_reg_write(solo_dev, SOLO_VE_CH_MOT(i), 0x100);
317 }
318 }
319
320 int solo_enc_init(struct solo_dev *solo_dev)
321 {
322 int i;
323
324 solo_capture_config(solo_dev);
325 solo_mp4e_config(solo_dev);
326 solo_jpeg_config(solo_dev);
327
328 for (i = 0; i < solo_dev->nr_chans; i++) {
329 solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
330 solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
331 }
332
333 return 0;
334 }
335
336 void solo_enc_exit(struct solo_dev *solo_dev)
337 {
338 int i;
339
340 for (i = 0; i < solo_dev->nr_chans; i++) {
341 solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
342 solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
343 }
344 }
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