Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph...
[deliverable/linux.git] / drivers / staging / media / solo6x10 / solo6x10-enc.c
1 /*
2 * Copyright (C) 2010-2013 Bluecherry, LLC <http://www.bluecherrydvr.com>
3 *
4 * Original author:
5 * Ben Collins <bcollins@ubuntu.com>
6 *
7 * Additional work by:
8 * John Brooks <john.brooks@bluecherry.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/font.h>
27 #include <linux/bitrev.h>
28 #include <linux/slab.h>
29
30 #include "solo6x10.h"
31
32 #define VI_PROG_HSIZE (1280 - 16)
33 #define VI_PROG_VSIZE (1024 - 16)
34
35 #define IRQ_LEVEL 2
36
37 static void solo_capture_config(struct solo_dev *solo_dev)
38 {
39 unsigned long height;
40 unsigned long width;
41 void *buf;
42 int i;
43
44 solo_reg_write(solo_dev, SOLO_CAP_BASE,
45 SOLO_CAP_MAX_PAGE((SOLO_CAP_EXT_SIZE(solo_dev)
46 - SOLO_CAP_PAGE_SIZE) >> 16)
47 | SOLO_CAP_BASE_ADDR(SOLO_CAP_EXT_ADDR(solo_dev) >> 16));
48
49 /* XXX: Undocumented bits at b17 and b24 */
50 if (solo_dev->type == SOLO_DEV_6110) {
51 /* NOTE: Ref driver has (62 << 24) here as well, but it causes
52 * wacked out frame timing on 4-port 6110. */
53 solo_reg_write(solo_dev, SOLO_CAP_BTW,
54 (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
55 SOLO_CAP_MAX_BANDWIDTH(36));
56 } else {
57 solo_reg_write(solo_dev, SOLO_CAP_BTW,
58 (1 << 17) | SOLO_CAP_PROG_BANDWIDTH(2) |
59 SOLO_CAP_MAX_BANDWIDTH(32));
60 }
61
62 /* Set scale 1, 9 dimension */
63 width = solo_dev->video_hsize;
64 height = solo_dev->video_vsize;
65 solo_reg_write(solo_dev, SOLO_DIM_SCALE1,
66 SOLO_DIM_H_MB_NUM(width / 16) |
67 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
68 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
69
70 /* Set scale 2, 10 dimension */
71 width = solo_dev->video_hsize / 2;
72 height = solo_dev->video_vsize;
73 solo_reg_write(solo_dev, SOLO_DIM_SCALE2,
74 SOLO_DIM_H_MB_NUM(width / 16) |
75 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
76 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
77
78 /* Set scale 3, 11 dimension */
79 width = solo_dev->video_hsize / 2;
80 height = solo_dev->video_vsize / 2;
81 solo_reg_write(solo_dev, SOLO_DIM_SCALE3,
82 SOLO_DIM_H_MB_NUM(width / 16) |
83 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
84 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
85
86 /* Set scale 4, 12 dimension */
87 width = solo_dev->video_hsize / 3;
88 height = solo_dev->video_vsize / 3;
89 solo_reg_write(solo_dev, SOLO_DIM_SCALE4,
90 SOLO_DIM_H_MB_NUM(width / 16) |
91 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
92 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
93
94 /* Set scale 5, 13 dimension */
95 width = solo_dev->video_hsize / 4;
96 height = solo_dev->video_vsize / 2;
97 solo_reg_write(solo_dev, SOLO_DIM_SCALE5,
98 SOLO_DIM_H_MB_NUM(width / 16) |
99 SOLO_DIM_V_MB_NUM_FRAME(height / 8) |
100 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
101
102 /* Progressive */
103 width = VI_PROG_HSIZE;
104 height = VI_PROG_VSIZE;
105 solo_reg_write(solo_dev, SOLO_DIM_PROG,
106 SOLO_DIM_H_MB_NUM(width / 16) |
107 SOLO_DIM_V_MB_NUM_FRAME(height / 16) |
108 SOLO_DIM_V_MB_NUM_FIELD(height / 16));
109
110 /* Clear OSD */
111 solo_reg_write(solo_dev, SOLO_VE_OSD_CH, 0);
112 solo_reg_write(solo_dev, SOLO_VE_OSD_BASE, SOLO_EOSD_EXT_ADDR >> 16);
113 solo_reg_write(solo_dev, SOLO_VE_OSD_CLR,
114 0xF0 << 16 | 0x80 << 8 | 0x80);
115
116 if (solo_dev->type == SOLO_DEV_6010)
117 solo_reg_write(solo_dev, SOLO_VE_OSD_OPT,
118 SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);
119 else
120 solo_reg_write(solo_dev, SOLO_VE_OSD_OPT, SOLO_VE_OSD_V_DOUBLE
121 | SOLO_VE_OSD_H_SHADOW | SOLO_VE_OSD_V_SHADOW);
122
123 /* Clear OSG buffer */
124 buf = kzalloc(SOLO_EOSD_EXT_SIZE(solo_dev), GFP_KERNEL);
125 if (!buf)
126 return;
127
128 for (i = 0; i < solo_dev->nr_chans; i++) {
129 solo_p2m_dma(solo_dev, 1, buf,
130 SOLO_EOSD_EXT_ADDR +
131 (SOLO_EOSD_EXT_SIZE(solo_dev) * i),
132 SOLO_EOSD_EXT_SIZE(solo_dev), 0, 0);
133 }
134 kfree(buf);
135 }
136
137 /* Should be called with enable_lock held */
138 int solo_osd_print(struct solo_enc_dev *solo_enc)
139 {
140 struct solo_dev *solo_dev = solo_enc->solo_dev;
141 unsigned char *str = solo_enc->osd_text;
142 u8 *buf = solo_enc->osd_buf;
143 u32 reg = solo_reg_read(solo_dev, SOLO_VE_OSD_CH);
144 const struct font_desc *vga = find_font("VGA8x16");
145 const unsigned char *vga_data;
146 int len;
147 int i, j;
148
149 if (WARN_ON_ONCE(!vga))
150 return -ENODEV;
151
152 len = strlen(str);
153
154 if (len == 0) {
155 /* Disable OSD on this channel */
156 reg &= ~(1 << solo_enc->ch);
157 solo_reg_write(solo_dev, SOLO_VE_OSD_CH, reg);
158 return 0;
159 }
160
161 memset(buf, 0, SOLO_EOSD_EXT_SIZE_MAX);
162 vga_data = (const unsigned char *)vga->data;
163
164 for (i = 0; i < len; i++) {
165 unsigned char c = str[i];
166
167 for (j = 0; j < 16; j++) {
168 buf[(j * 2) + (i % 2) + (i / 2 * 32)] =
169 bitrev8(vga_data[(c * 16) + j]);
170 }
171 }
172
173 solo_p2m_dma(solo_dev, 1, buf,
174 SOLO_EOSD_EXT_ADDR +
175 (solo_enc->ch * SOLO_EOSD_EXT_SIZE(solo_dev)),
176 SOLO_EOSD_EXT_SIZE(solo_dev), 0, 0);
177
178 /* Enable OSD on this channel */
179 reg |= (1 << solo_enc->ch);
180 solo_reg_write(solo_dev, SOLO_VE_OSD_CH, reg);
181
182 return 0;
183 }
184
185 /**
186 * Set channel Quality Profile (0-3).
187 */
188 void solo_s_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch,
189 unsigned int qp)
190 {
191 unsigned long flags;
192 unsigned int idx, reg;
193
194 if ((ch > 31) || (qp > 3))
195 return;
196
197 if (solo_dev->type == SOLO_DEV_6010)
198 return;
199
200 if (ch < 16) {
201 idx = 0;
202 reg = SOLO_VE_JPEG_QP_CH_L;
203 } else {
204 ch -= 16;
205 idx = 1;
206 reg = SOLO_VE_JPEG_QP_CH_H;
207 }
208 ch *= 2;
209
210 spin_lock_irqsave(&solo_dev->jpeg_qp_lock, flags);
211
212 solo_dev->jpeg_qp[idx] &= ~(3 << ch);
213 solo_dev->jpeg_qp[idx] |= (qp & 3) << ch;
214
215 solo_reg_write(solo_dev, reg, solo_dev->jpeg_qp[idx]);
216
217 spin_unlock_irqrestore(&solo_dev->jpeg_qp_lock, flags);
218 }
219
220 int solo_g_jpeg_qp(struct solo_dev *solo_dev, unsigned int ch)
221 {
222 int idx;
223
224 if (solo_dev->type == SOLO_DEV_6010)
225 return 2;
226
227 if (WARN_ON_ONCE(ch > 31))
228 return 2;
229
230 if (ch < 16) {
231 idx = 0;
232 } else {
233 ch -= 16;
234 idx = 1;
235 }
236 ch *= 2;
237
238 return (solo_dev->jpeg_qp[idx] >> ch) & 3;
239 }
240
241 #define SOLO_QP_INIT 0xaaaaaaaa
242
243 static void solo_jpeg_config(struct solo_dev *solo_dev)
244 {
245 if (solo_dev->type == SOLO_DEV_6010) {
246 solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
247 (2 << 24) | (2 << 16) | (2 << 8) | 2);
248 } else {
249 solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_TBL,
250 (4 << 24) | (3 << 16) | (2 << 8) | 1);
251 }
252
253 spin_lock_init(&solo_dev->jpeg_qp_lock);
254
255 /* Initialize Quality Profile for all channels */
256 solo_dev->jpeg_qp[0] = solo_dev->jpeg_qp[1] = SOLO_QP_INIT;
257 solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_L, SOLO_QP_INIT);
258 solo_reg_write(solo_dev, SOLO_VE_JPEG_QP_CH_H, SOLO_QP_INIT);
259
260 solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG,
261 (SOLO_JPEG_EXT_SIZE(solo_dev) & 0xffff0000) |
262 ((SOLO_JPEG_EXT_ADDR(solo_dev) >> 16) & 0x0000ffff));
263 solo_reg_write(solo_dev, SOLO_VE_JPEG_CTRL, 0xffffffff);
264 if (solo_dev->type == SOLO_DEV_6110) {
265 solo_reg_write(solo_dev, SOLO_VE_JPEG_CFG1,
266 (0 << 16) | (30 << 8) | 60);
267 }
268 }
269
270 static void solo_mp4e_config(struct solo_dev *solo_dev)
271 {
272 int i;
273 u32 cfg;
274
275 solo_reg_write(solo_dev, SOLO_VE_CFG0,
276 SOLO_VE_INTR_CTRL(IRQ_LEVEL) |
277 SOLO_VE_BLOCK_SIZE(SOLO_MP4E_EXT_SIZE(solo_dev) >> 16) |
278 SOLO_VE_BLOCK_BASE(SOLO_MP4E_EXT_ADDR(solo_dev) >> 16));
279
280
281 cfg = SOLO_VE_BYTE_ALIGN(2) | SOLO_VE_INSERT_INDEX
282 | SOLO_VE_MOTION_MODE(0);
283 if (solo_dev->type != SOLO_DEV_6010) {
284 cfg |= SOLO_VE_MPEG_SIZE_H(
285 (SOLO_MP4E_EXT_SIZE(solo_dev) >> 24) & 0x0f);
286 cfg |= SOLO_VE_JPEG_SIZE_H(
287 (SOLO_JPEG_EXT_SIZE(solo_dev) >> 24) & 0x0f);
288 }
289 solo_reg_write(solo_dev, SOLO_VE_CFG1, cfg);
290
291 solo_reg_write(solo_dev, SOLO_VE_WMRK_POLY, 0);
292 solo_reg_write(solo_dev, SOLO_VE_VMRK_INIT_KEY, 0);
293 solo_reg_write(solo_dev, SOLO_VE_WMRK_STRL, 0);
294 if (solo_dev->type == SOLO_DEV_6110)
295 solo_reg_write(solo_dev, SOLO_VE_WMRK_ENABLE, 0);
296 solo_reg_write(solo_dev, SOLO_VE_ENCRYP_POLY, 0);
297 solo_reg_write(solo_dev, SOLO_VE_ENCRYP_INIT, 0);
298
299 solo_reg_write(solo_dev, SOLO_VE_ATTR,
300 SOLO_VE_LITTLE_ENDIAN |
301 SOLO_COMP_ATTR_FCODE(1) |
302 SOLO_COMP_TIME_INC(0) |
303 SOLO_COMP_TIME_WIDTH(15) |
304 SOLO_DCT_INTERVAL(solo_dev->type == SOLO_DEV_6010 ? 9 : 10));
305
306 for (i = 0; i < solo_dev->nr_chans; i++) {
307 solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE(i),
308 (SOLO_EREF_EXT_ADDR(solo_dev) +
309 (i * SOLO_EREF_EXT_SIZE)) >> 16);
310 solo_reg_write(solo_dev, SOLO_VE_CH_REF_BASE_E(i),
311 (SOLO_EREF_EXT_ADDR(solo_dev) +
312 ((i + 16) * SOLO_EREF_EXT_SIZE)) >> 16);
313 }
314
315 if (solo_dev->type == SOLO_DEV_6110) {
316 solo_reg_write(solo_dev, SOLO_VE_COMPT_MOT, 0x00040008);
317 } else {
318 for (i = 0; i < solo_dev->nr_chans; i++)
319 solo_reg_write(solo_dev, SOLO_VE_CH_MOT(i), 0x100);
320 }
321 }
322
323 int solo_enc_init(struct solo_dev *solo_dev)
324 {
325 int i;
326
327 solo_capture_config(solo_dev);
328 solo_mp4e_config(solo_dev);
329 solo_jpeg_config(solo_dev);
330
331 for (i = 0; i < solo_dev->nr_chans; i++) {
332 solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
333 solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
334 }
335
336 return 0;
337 }
338
339 void solo_enc_exit(struct solo_dev *solo_dev)
340 {
341 int i;
342
343 for (i = 0; i < solo_dev->nr_chans; i++) {
344 solo_reg_write(solo_dev, SOLO_CAP_CH_SCALE(i), 0);
345 solo_reg_write(solo_dev, SOLO_CAP_CH_COMP_ENA_E(i), 0);
346 }
347 }
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