2 * Copyright (c) 2003-2012 Broadcom Corporation
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the Broadcom
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
22 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <linux/phy.h>
35 #include <linux/delay.h>
36 #include <linux/netdevice.h>
37 #include <linux/smp.h>
38 #include <linux/ethtool.h>
39 #include <linux/module.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/jiffies.h>
43 #include <linux/interrupt.h>
44 #include <linux/platform_device.h>
46 #include <asm/mipsregs.h>
48 * fmn.h - For FMN credit configuration and registering fmn_handler.
49 * FMN is communication mechanism that allows processing agents within
50 * XLR/XLS to communicate each other.
52 #include <asm/netlogic/xlr/fmn.h>
54 #include "platform_net.h"
58 * The readl/writel implementation byteswaps on XLR/XLS, so
59 * we need to use __raw_ IO to read the NAE registers
60 * because they are in the big-endian MMIO area on the SoC.
62 static inline void xlr_nae_wreg(u32 __iomem
*base
, unsigned int reg
, u32 val
)
64 __raw_writel(val
, base
+ reg
);
67 static inline u32
xlr_nae_rdreg(u32 __iomem
*base
, unsigned int reg
)
69 return __raw_readl(base
+ reg
);
72 static inline void xlr_reg_update(u32
*base_addr
, u32 off
, u32 val
, u32 mask
)
76 tmp
= xlr_nae_rdreg(base_addr
, off
);
77 xlr_nae_wreg(base_addr
, off
, (tmp
& ~mask
) | (val
& mask
));
80 #define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES
82 static int send_to_rfr_fifo(struct xlr_net_priv
*priv
, void *addr
)
84 struct nlm_fmn_msg msg
;
85 int ret
= 0, num_try
= 0, stnid
;
86 unsigned long paddr
, mflags
;
88 paddr
= virt_to_bus(addr
);
89 msg
.msg0
= (u64
)paddr
& 0xffffffffe0ULL
;
93 stnid
= priv
->nd
->rfr_station
;
95 mflags
= nlm_cop2_enable_irqsave();
96 ret
= nlm_fmn_send(1, 0, stnid
, &msg
);
97 nlm_cop2_disable_irqrestore(mflags
);
100 } while (++num_try
< 10000);
102 netdev_err(priv
->ndev
, "Send to RFR failed in RX path\n");
106 static inline unsigned char *xlr_alloc_skb(void)
109 int buf_len
= sizeof(struct sk_buff
*);
110 unsigned char *skb_data
;
112 /* skb->data is cache aligned */
113 skb
= alloc_skb(XLR_RX_BUF_SIZE
, GFP_ATOMIC
);
116 skb_data
= skb
->data
;
117 skb_put(skb
, MAC_SKB_BACK_PTR_SIZE
);
118 skb_pull(skb
, MAC_SKB_BACK_PTR_SIZE
);
119 memcpy(skb_data
, &skb
, buf_len
);
124 static void xlr_net_fmn_handler(int bkt
, int src_stnid
, int size
, int code
,
125 struct nlm_fmn_msg
*msg
, void *arg
)
128 void *skb_data
= NULL
;
129 struct net_device
*ndev
;
130 struct xlr_net_priv
*priv
;
133 struct xlr_adapter
*adapter
= arg
;
135 length
= (msg
->msg0
>> 40) & 0x3fff;
137 addr
= bus_to_virt(msg
->msg0
& 0xffffffffffULL
);
138 addr
= addr
- MAC_SKB_BACK_PTR_SIZE
;
139 skb
= (struct sk_buff
*)(*(unsigned long *)addr
);
140 dev_kfree_skb_any((struct sk_buff
*)addr
);
142 addr
= (unsigned char *)
143 bus_to_virt(msg
->msg0
& 0xffffffffe0ULL
);
144 length
= length
- BYTE_OFFSET
- MAC_CRC_LEN
;
145 port
= ((int)msg
->msg0
) & 0x0f;
146 addr
= addr
- MAC_SKB_BACK_PTR_SIZE
;
147 skb
= (struct sk_buff
*)(*(unsigned long *)addr
);
148 skb
->dev
= adapter
->netdev
[port
];
152 priv
= netdev_priv(ndev
);
154 /* 16 byte IP header align */
155 skb_reserve(skb
, BYTE_OFFSET
);
156 skb_put(skb
, length
);
157 skb
->protocol
= eth_type_trans(skb
, skb
->dev
);
158 skb
->dev
->last_rx
= jiffies
;
161 skb_data
= xlr_alloc_skb();
163 send_to_rfr_fifo(priv
, skb_data
);
167 static struct phy_device
*xlr_get_phydev(struct xlr_net_priv
*priv
)
169 return mdiobus_get_phy(priv
->mii_bus
, priv
->phy_addr
);
175 static int xlr_get_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
177 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
178 struct phy_device
*phydev
= xlr_get_phydev(priv
);
182 return phy_ethtool_gset(phydev
, ecmd
);
185 static int xlr_set_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
187 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
188 struct phy_device
*phydev
= xlr_get_phydev(priv
);
192 return phy_ethtool_sset(phydev
, ecmd
);
195 static struct ethtool_ops xlr_ethtool_ops
= {
196 .get_settings
= xlr_get_settings
,
197 .set_settings
= xlr_set_settings
,
203 static int xlr_net_fill_rx_ring(struct net_device
*ndev
)
206 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
209 for (i
= 0; i
< MAX_FRIN_SPILL
/ 4; i
++) {
210 skb_data
= xlr_alloc_skb();
212 netdev_err(ndev
, "SKB allocation failed\n");
215 send_to_rfr_fifo(priv
, skb_data
);
217 netdev_info(ndev
, "Rx ring setup done\n");
221 static int xlr_net_open(struct net_device
*ndev
)
224 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
225 struct phy_device
*phydev
= xlr_get_phydev(priv
);
227 /* schedule a link state check */
230 err
= phy_start_aneg(phydev
);
232 pr_err("Autoneg failed\n");
235 /* Setup the speed from PHY to internal reg*/
236 xlr_set_gmac_speed(priv
);
238 netif_tx_start_all_queues(ndev
);
243 static int xlr_net_stop(struct net_device
*ndev
)
245 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
246 struct phy_device
*phydev
= xlr_get_phydev(priv
);
249 netif_tx_stop_all_queues(ndev
);
253 static void xlr_make_tx_desc(struct nlm_fmn_msg
*msg
, unsigned long addr
,
256 unsigned long physkb
= virt_to_phys(skb
);
257 int cpu_core
= nlm_core_id();
258 int fr_stn_id
= cpu_core
* 8 + XLR_FB_STN
; /* FB to 6th bucket */
260 msg
->msg0
= (((u64
)1 << 63) | /* End of packet descriptor */
261 ((u64
)127 << 54) | /* No Free back */
262 (u64
)skb
->len
<< 40 | /* Length of data */
264 msg
->msg1
= (((u64
)1 << 63) |
265 ((u64
)fr_stn_id
<< 54) | /* Free back id */
266 (u64
)0 << 40 | /* Set len to 0 */
267 ((u64
)physkb
& 0xffffffff)); /* 32bit address */
272 static void __maybe_unused
xlr_wakeup_queue(unsigned long dev
)
274 struct net_device
*ndev
= (struct net_device
*)dev
;
275 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
276 struct phy_device
*phydev
= xlr_get_phydev(priv
);
279 netif_tx_wake_queue(netdev_get_tx_queue(ndev
, priv
->wakeup_q
));
282 static netdev_tx_t
xlr_net_start_xmit(struct sk_buff
*skb
,
283 struct net_device
*ndev
)
285 struct nlm_fmn_msg msg
;
286 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
290 xlr_make_tx_desc(&msg
, virt_to_phys(skb
->data
), skb
);
291 flags
= nlm_cop2_enable_irqsave();
292 ret
= nlm_fmn_send(2, 0, priv
->tx_stnid
, &msg
);
293 nlm_cop2_disable_irqrestore(flags
);
295 dev_kfree_skb_any(skb
);
299 static u16
xlr_net_select_queue(struct net_device
*ndev
, struct sk_buff
*skb
,
301 select_queue_fallback_t fallback
)
303 return (u16
)smp_processor_id();
306 static void xlr_hw_set_mac_addr(struct net_device
*ndev
)
308 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
310 /* set mac station address */
311 xlr_nae_wreg(priv
->base_addr
, R_MAC_ADDR0
,
312 ((ndev
->dev_addr
[5] << 24) | (ndev
->dev_addr
[4] << 16) |
313 (ndev
->dev_addr
[3] << 8) | (ndev
->dev_addr
[2])));
314 xlr_nae_wreg(priv
->base_addr
, R_MAC_ADDR0
+ 1,
315 ((ndev
->dev_addr
[1] << 24) | (ndev
->dev_addr
[0] << 16)));
317 xlr_nae_wreg(priv
->base_addr
, R_MAC_ADDR_MASK2
, 0xffffffff);
318 xlr_nae_wreg(priv
->base_addr
, R_MAC_ADDR_MASK2
+ 1, 0xffffffff);
319 xlr_nae_wreg(priv
->base_addr
, R_MAC_ADDR_MASK3
, 0xffffffff);
320 xlr_nae_wreg(priv
->base_addr
, R_MAC_ADDR_MASK3
+ 1, 0xffffffff);
322 xlr_nae_wreg(priv
->base_addr
, R_MAC_FILTER_CONFIG
,
323 (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN
) |
324 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN
) |
325 (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID
));
327 if (priv
->nd
->phy_interface
== PHY_INTERFACE_MODE_RGMII
||
328 priv
->nd
->phy_interface
== PHY_INTERFACE_MODE_SGMII
)
329 xlr_reg_update(priv
->base_addr
, R_IPG_IFG
, MAC_B2B_IPG
, 0x7f);
332 static int xlr_net_set_mac_addr(struct net_device
*ndev
, void *data
)
336 err
= eth_mac_addr(ndev
, data
);
339 xlr_hw_set_mac_addr(ndev
);
343 static void xlr_set_rx_mode(struct net_device
*ndev
)
345 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
348 regval
= xlr_nae_rdreg(priv
->base_addr
, R_MAC_FILTER_CONFIG
);
350 if (ndev
->flags
& IFF_PROMISC
) {
351 regval
|= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN
) |
352 (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN
) |
353 (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN
) |
354 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN
);
356 regval
&= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN
) |
357 (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN
));
360 xlr_nae_wreg(priv
->base_addr
, R_MAC_FILTER_CONFIG
, regval
);
363 static void xlr_stats(struct net_device
*ndev
, struct rtnl_link_stats64
*stats
)
365 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
367 stats
->rx_packets
= xlr_nae_rdreg(priv
->base_addr
, RX_PACKET_COUNTER
);
368 stats
->tx_packets
= xlr_nae_rdreg(priv
->base_addr
, TX_PACKET_COUNTER
);
369 stats
->rx_bytes
= xlr_nae_rdreg(priv
->base_addr
, RX_BYTE_COUNTER
);
370 stats
->tx_bytes
= xlr_nae_rdreg(priv
->base_addr
, TX_BYTE_COUNTER
);
371 stats
->tx_errors
= xlr_nae_rdreg(priv
->base_addr
, TX_FCS_ERROR_COUNTER
);
372 stats
->rx_dropped
= xlr_nae_rdreg(priv
->base_addr
,
373 RX_DROP_PACKET_COUNTER
);
374 stats
->tx_dropped
= xlr_nae_rdreg(priv
->base_addr
,
375 TX_DROP_FRAME_COUNTER
);
377 stats
->multicast
= xlr_nae_rdreg(priv
->base_addr
,
378 RX_MULTICAST_PACKET_COUNTER
);
379 stats
->collisions
= xlr_nae_rdreg(priv
->base_addr
,
380 TX_TOTAL_COLLISION_COUNTER
);
382 stats
->rx_length_errors
= xlr_nae_rdreg(priv
->base_addr
,
383 RX_FRAME_LENGTH_ERROR_COUNTER
);
384 stats
->rx_over_errors
= xlr_nae_rdreg(priv
->base_addr
,
385 RX_DROP_PACKET_COUNTER
);
386 stats
->rx_crc_errors
= xlr_nae_rdreg(priv
->base_addr
,
387 RX_FCS_ERROR_COUNTER
);
388 stats
->rx_frame_errors
= xlr_nae_rdreg(priv
->base_addr
,
389 RX_ALIGNMENT_ERROR_COUNTER
);
391 stats
->rx_fifo_errors
= xlr_nae_rdreg(priv
->base_addr
,
392 RX_DROP_PACKET_COUNTER
);
393 stats
->rx_missed_errors
= xlr_nae_rdreg(priv
->base_addr
,
394 RX_CARRIER_SENSE_ERROR_COUNTER
);
396 stats
->rx_errors
= (stats
->rx_over_errors
+ stats
->rx_crc_errors
+
397 stats
->rx_frame_errors
+ stats
->rx_fifo_errors
+
398 stats
->rx_missed_errors
);
400 stats
->tx_aborted_errors
= xlr_nae_rdreg(priv
->base_addr
,
401 TX_EXCESSIVE_COLLISION_PACKET_COUNTER
);
402 stats
->tx_carrier_errors
= xlr_nae_rdreg(priv
->base_addr
,
403 TX_DROP_FRAME_COUNTER
);
404 stats
->tx_fifo_errors
= xlr_nae_rdreg(priv
->base_addr
,
405 TX_DROP_FRAME_COUNTER
);
408 static struct rtnl_link_stats64
*xlr_get_stats64(struct net_device
*ndev
,
409 struct rtnl_link_stats64
*stats
412 xlr_stats(ndev
, stats
);
416 static struct net_device_ops xlr_netdev_ops
= {
417 .ndo_open
= xlr_net_open
,
418 .ndo_stop
= xlr_net_stop
,
419 .ndo_start_xmit
= xlr_net_start_xmit
,
420 .ndo_select_queue
= xlr_net_select_queue
,
421 .ndo_set_mac_address
= xlr_net_set_mac_addr
,
422 .ndo_set_rx_mode
= xlr_set_rx_mode
,
423 .ndo_get_stats64
= xlr_get_stats64
,
429 static void *xlr_config_spill(struct xlr_net_priv
*priv
, int reg_start_0
,
430 int reg_start_1
, int reg_size
, int size
)
434 unsigned long phys_addr
;
437 base
= priv
->base_addr
;
439 spill
= kmalloc(spill_size
+ SMP_CACHE_BYTES
, GFP_ATOMIC
);
441 pr_err("Unable to allocate memory for spill area!\n");
442 return ZERO_SIZE_PTR
;
445 spill
= PTR_ALIGN(spill
, SMP_CACHE_BYTES
);
446 phys_addr
= virt_to_phys(spill
);
447 dev_dbg(&priv
->ndev
->dev
, "Allocated spill %d bytes at %lx\n",
449 xlr_nae_wreg(base
, reg_start_0
, (phys_addr
>> 5) & 0xffffffff);
450 xlr_nae_wreg(base
, reg_start_1
, ((u64
)phys_addr
>> 37) & 0x07);
451 xlr_nae_wreg(base
, reg_size
, spill_size
);
457 * Configure the 6 FIFO's that are used by the network accelarator to
458 * communicate with the rest of the XLx device. 4 of the FIFO's are for
459 * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding
460 * the NA with free descriptors.
462 static void xlr_config_fifo_spill_area(struct xlr_net_priv
*priv
)
464 priv
->frin_spill
= xlr_config_spill(priv
,
465 R_REG_FRIN_SPILL_MEM_START_0
,
466 R_REG_FRIN_SPILL_MEM_START_1
,
467 R_REG_FRIN_SPILL_MEM_SIZE
,
470 priv
->frout_spill
= xlr_config_spill(priv
,
471 R_FROUT_SPILL_MEM_START_0
,
472 R_FROUT_SPILL_MEM_START_1
,
473 R_FROUT_SPILL_MEM_SIZE
,
476 priv
->class_0_spill
= xlr_config_spill(priv
,
477 R_CLASS0_SPILL_MEM_START_0
,
478 R_CLASS0_SPILL_MEM_START_1
,
479 R_CLASS0_SPILL_MEM_SIZE
,
482 priv
->class_1_spill
= xlr_config_spill(priv
,
483 R_CLASS1_SPILL_MEM_START_0
,
484 R_CLASS1_SPILL_MEM_START_1
,
485 R_CLASS1_SPILL_MEM_SIZE
,
488 priv
->class_2_spill
= xlr_config_spill(priv
,
489 R_CLASS2_SPILL_MEM_START_0
,
490 R_CLASS2_SPILL_MEM_START_1
,
491 R_CLASS2_SPILL_MEM_SIZE
,
494 priv
->class_3_spill
= xlr_config_spill(priv
,
495 R_CLASS3_SPILL_MEM_START_0
,
496 R_CLASS3_SPILL_MEM_START_1
,
497 R_CLASS3_SPILL_MEM_SIZE
,
503 * Configure PDE to Round-Robin distribution of packets to the
506 static void xlr_config_pde(struct xlr_net_priv
*priv
)
511 /* Each core has 8 buckets(station) */
512 for (i
= 0; i
< hweight32(priv
->nd
->cpu_mask
); i
++)
513 bkt_map
|= (0xff << (i
* 8));
515 xlr_nae_wreg(priv
->base_addr
, R_PDE_CLASS_0
, (bkt_map
& 0xffffffff));
516 xlr_nae_wreg(priv
->base_addr
, R_PDE_CLASS_0
+ 1,
517 ((bkt_map
>> 32) & 0xffffffff));
519 xlr_nae_wreg(priv
->base_addr
, R_PDE_CLASS_1
, (bkt_map
& 0xffffffff));
520 xlr_nae_wreg(priv
->base_addr
, R_PDE_CLASS_1
+ 1,
521 ((bkt_map
>> 32) & 0xffffffff));
523 xlr_nae_wreg(priv
->base_addr
, R_PDE_CLASS_2
, (bkt_map
& 0xffffffff));
524 xlr_nae_wreg(priv
->base_addr
, R_PDE_CLASS_2
+ 1,
525 ((bkt_map
>> 32) & 0xffffffff));
527 xlr_nae_wreg(priv
->base_addr
, R_PDE_CLASS_3
, (bkt_map
& 0xffffffff));
528 xlr_nae_wreg(priv
->base_addr
, R_PDE_CLASS_3
+ 1,
529 ((bkt_map
>> 32) & 0xffffffff));
533 * Setup the Message ring credits, bucket size and other
534 * common configuration
536 static int xlr_config_common(struct xlr_net_priv
*priv
)
538 struct xlr_fmn_info
*gmac
= priv
->nd
->gmac_fmn_info
;
539 int start_stn_id
= gmac
->start_stn_id
;
540 int end_stn_id
= gmac
->end_stn_id
;
541 int *bucket_size
= priv
->nd
->bucket_size
;
544 /* Setting non-core MsgBktSize(0x321 - 0x325) */
545 for (i
= start_stn_id
; i
<= end_stn_id
; i
++) {
546 xlr_nae_wreg(priv
->base_addr
,
547 R_GMAC_RFR0_BUCKET_SIZE
+ i
- start_stn_id
,
552 * Setting non-core Credit counter register
553 * Distributing Gmac's credit to CPU's
555 for (i
= 0; i
< 8; i
++) {
556 for (j
= 0; j
< 8; j
++)
557 xlr_nae_wreg(priv
->base_addr
,
558 (R_CC_CPU0_0
+ (i
* 8)) + j
,
559 gmac
->credit_config
[(i
* 8) + j
]);
562 xlr_nae_wreg(priv
->base_addr
, R_MSG_TX_THRESHOLD
, 3);
563 xlr_nae_wreg(priv
->base_addr
, R_DMACR0
, 0xffffffff);
564 xlr_nae_wreg(priv
->base_addr
, R_DMACR1
, 0xffffffff);
565 xlr_nae_wreg(priv
->base_addr
, R_DMACR2
, 0xffffffff);
566 xlr_nae_wreg(priv
->base_addr
, R_DMACR3
, 0xffffffff);
567 xlr_nae_wreg(priv
->base_addr
, R_FREEQCARVE
, 0);
569 err
= xlr_net_fill_rx_ring(priv
->ndev
);
572 nlm_register_fmn_handler(start_stn_id
, end_stn_id
, xlr_net_fmn_handler
,
577 static void xlr_config_translate_table(struct xlr_net_priv
*priv
)
581 int bkts
[32]; /* one bucket is assumed for each cpu */
582 int b1
, b2
, c1
, c2
, i
, j
, k
;
586 cpu_mask
= priv
->nd
->cpu_mask
;
588 pr_info("Using %s-based distribution\n",
589 (use_bkt
) ? "bucket" : "class");
591 for (i
= 0; i
< 32; i
++) {
592 if ((1 << i
) & cpu_mask
) {
593 /* for each cpu, mark the 4+threadid bucket */
594 bkts
[j
] = ((i
/ 4) * 8) + (i
% 4);
599 /*configure the 128 * 9 Translation table to send to available buckets*/
603 for (i
= 0; i
< 64; i
++) {
605 * On use_bkt set the b0, b1 are used, else
606 * the 4 classes are used, here implemented
607 * a logic to distribute the packets to the
608 * buckets equally or based on the class
617 val
= ((c1
<< 23) | (b1
<< 17) | (use_bkt
<< 16) |
618 (c2
<< 7) | (b2
<< 1) | (use_bkt
<< 0));
619 dev_dbg(&priv
->ndev
->dev
, "Table[%d] b1=%d b2=%d c1=%d c2=%d\n",
621 xlr_nae_wreg(priv
->base_addr
, R_TRANSLATETABLE
+ i
, val
);
626 static void xlr_config_parser(struct xlr_net_priv
*priv
)
630 /* Mark it as ETHERNET type */
631 xlr_nae_wreg(priv
->base_addr
, R_L2TYPE_0
, 0x01);
633 /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
634 xlr_nae_wreg(priv
->base_addr
, R_PARSERCONFIGREG
,
635 ((0x7f << 8) | (1 << 1)));
637 /* configure the parser : L2 Type is configured in the bootloader */
638 /* extract IP: src, dest protocol */
639 xlr_nae_wreg(priv
->base_addr
, R_L3CTABLE
,
640 (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
642 xlr_nae_wreg(priv
->base_addr
, R_L3CTABLE
+ 1,
643 (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) |
646 /* Configure to extract SRC port and Dest port for TCP and UDP pkts */
647 xlr_nae_wreg(priv
->base_addr
, R_L4CTABLE
, 6);
648 xlr_nae_wreg(priv
->base_addr
, R_L4CTABLE
+ 2, 17);
649 val
= ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
650 xlr_nae_wreg(priv
->base_addr
, R_L4CTABLE
+ 1, val
);
651 xlr_nae_wreg(priv
->base_addr
, R_L4CTABLE
+ 3, val
);
653 xlr_config_translate_table(priv
);
656 static int xlr_phy_write(u32
*base_addr
, int phy_addr
, int regnum
, u16 val
)
658 unsigned long timeout
, stoptime
, checktime
;
662 timeout
= msecs_to_jiffies(100);
663 stoptime
= jiffies
+ timeout
;
666 xlr_nae_wreg(base_addr
, R_MII_MGMT_ADDRESS
, (phy_addr
<< 8) | regnum
);
668 /* Write the data which starts the write cycle */
669 xlr_nae_wreg(base_addr
, R_MII_MGMT_WRITE_DATA
, (u32
)val
);
671 /* poll for the read cycle to complete */
674 if (xlr_nae_rdreg(base_addr
, R_MII_MGMT_INDICATORS
) == 0)
676 timedout
= time_after(checktime
, stoptime
);
679 pr_info("Phy device write err: device busy");
686 static int xlr_phy_read(u32
*base_addr
, int phy_addr
, int regnum
)
688 unsigned long timeout
, stoptime
, checktime
;
692 timeout
= msecs_to_jiffies(100);
693 stoptime
= jiffies
+ timeout
;
696 /* setup the phy reg to be used */
697 xlr_nae_wreg(base_addr
, R_MII_MGMT_ADDRESS
,
698 (phy_addr
<< 8) | (regnum
<< 0));
700 /* Issue the read command */
701 xlr_nae_wreg(base_addr
, R_MII_MGMT_COMMAND
,
702 (1 << O_MII_MGMT_COMMAND__rstat
));
704 /* poll for the read cycle to complete */
707 if (xlr_nae_rdreg(base_addr
, R_MII_MGMT_INDICATORS
) == 0)
709 timedout
= time_after(checktime
, stoptime
);
712 pr_info("Phy device read err: device busy");
716 /* clear the read cycle */
717 xlr_nae_wreg(base_addr
, R_MII_MGMT_COMMAND
, 0);
720 return xlr_nae_rdreg(base_addr
, R_MII_MGMT_STATUS
);
723 static int xlr_mii_write(struct mii_bus
*bus
, int phy_addr
, int regnum
, u16 val
)
725 struct xlr_net_priv
*priv
= bus
->priv
;
728 ret
= xlr_phy_write(priv
->mii_addr
, phy_addr
, regnum
, val
);
729 dev_dbg(&priv
->ndev
->dev
, "mii_write phy %d : %d <- %x [%x]\n",
730 phy_addr
, regnum
, val
, ret
);
734 static int xlr_mii_read(struct mii_bus
*bus
, int phy_addr
, int regnum
)
736 struct xlr_net_priv
*priv
= bus
->priv
;
739 ret
= xlr_phy_read(priv
->mii_addr
, phy_addr
, regnum
);
740 dev_dbg(&priv
->ndev
->dev
, "mii_read phy %d : %d [%x]\n",
741 phy_addr
, regnum
, ret
);
746 * XLR ports are RGMII. XLS ports are SGMII mostly except the port0,
747 * which can be configured either SGMII or RGMII, considered SGMII
748 * by default, if board setup to RGMII the port_type need to set
749 * accordingly.Serdes and PCS layer need to configured for SGMII
751 static void xlr_sgmii_init(struct xlr_net_priv
*priv
)
755 xlr_phy_write(priv
->serdes_addr
, 26, 0, 0x6DB0);
756 xlr_phy_write(priv
->serdes_addr
, 26, 1, 0xFFFF);
757 xlr_phy_write(priv
->serdes_addr
, 26, 2, 0xB6D0);
758 xlr_phy_write(priv
->serdes_addr
, 26, 3, 0x00FF);
759 xlr_phy_write(priv
->serdes_addr
, 26, 4, 0x0000);
760 xlr_phy_write(priv
->serdes_addr
, 26, 5, 0x0000);
761 xlr_phy_write(priv
->serdes_addr
, 26, 6, 0x0005);
762 xlr_phy_write(priv
->serdes_addr
, 26, 7, 0x0001);
763 xlr_phy_write(priv
->serdes_addr
, 26, 8, 0x0000);
764 xlr_phy_write(priv
->serdes_addr
, 26, 9, 0x0000);
765 xlr_phy_write(priv
->serdes_addr
, 26, 10, 0x0000);
767 /* program GPIO values for serdes init parameters */
768 xlr_nae_wreg(priv
->gpio_addr
, 0x20, 0x7e6802);
769 xlr_nae_wreg(priv
->gpio_addr
, 0x10, 0x7104);
771 xlr_nae_wreg(priv
->gpio_addr
, 0x22, 0x7e6802);
772 xlr_nae_wreg(priv
->gpio_addr
, 0x21, 0x7104);
774 /* enable autoneg - more magic */
775 phy
= priv
->phy_addr
% 4 + 27;
776 xlr_phy_write(priv
->pcs_addr
, phy
, 0, 0x1000);
777 xlr_phy_write(priv
->pcs_addr
, phy
, 0, 0x0200);
780 void xlr_set_gmac_speed(struct xlr_net_priv
*priv
)
782 struct phy_device
*phydev
= xlr_get_phydev(priv
);
785 if (phydev
->interface
== PHY_INTERFACE_MODE_SGMII
)
786 xlr_sgmii_init(priv
);
788 if (phydev
->speed
!= priv
->phy_speed
) {
789 speed
= phydev
->speed
;
790 if (speed
== SPEED_1000
) {
791 /* Set interface to Byte mode */
792 xlr_nae_wreg(priv
->base_addr
, R_MAC_CONFIG_2
, 0x7217);
793 priv
->phy_speed
= speed
;
794 } else if (speed
== SPEED_100
|| speed
== SPEED_10
) {
795 /* Set interface to Nibble mode */
796 xlr_nae_wreg(priv
->base_addr
, R_MAC_CONFIG_2
, 0x7117);
797 priv
->phy_speed
= speed
;
799 /* Set SGMII speed in Interface control reg */
800 if (phydev
->interface
== PHY_INTERFACE_MODE_SGMII
) {
801 if (speed
== SPEED_10
)
802 xlr_nae_wreg(priv
->base_addr
,
805 if (speed
== SPEED_100
)
806 xlr_nae_wreg(priv
->base_addr
,
809 if (speed
== SPEED_1000
)
810 xlr_nae_wreg(priv
->base_addr
,
814 if (speed
== SPEED_10
)
815 xlr_nae_wreg(priv
->base_addr
, R_CORECONTROL
, 0x2);
816 if (speed
== SPEED_100
)
817 xlr_nae_wreg(priv
->base_addr
, R_CORECONTROL
, 0x1);
818 if (speed
== SPEED_1000
)
819 xlr_nae_wreg(priv
->base_addr
, R_CORECONTROL
, 0x0);
821 pr_info("gmac%d : %dMbps\n", priv
->port_id
, priv
->phy_speed
);
824 static void xlr_gmac_link_adjust(struct net_device
*ndev
)
826 struct xlr_net_priv
*priv
= netdev_priv(ndev
);
827 struct phy_device
*phydev
= xlr_get_phydev(priv
);
830 intreg
= xlr_nae_rdreg(priv
->base_addr
, R_INTREG
);
832 if (phydev
->speed
!= priv
->phy_speed
) {
833 xlr_set_gmac_speed(priv
);
834 pr_info("gmac%d : Link up\n", priv
->port_id
);
837 xlr_set_gmac_speed(priv
);
838 pr_info("gmac%d : Link down\n", priv
->port_id
);
842 static int xlr_mii_probe(struct xlr_net_priv
*priv
)
844 struct phy_device
*phydev
= xlr_get_phydev(priv
);
847 pr_err("no PHY found on phy_addr %d\n", priv
->phy_addr
);
851 /* Attach MAC to PHY */
852 phydev
= phy_connect(priv
->ndev
, phydev_name(phydev
),
853 &xlr_gmac_link_adjust
, priv
->nd
->phy_interface
);
855 if (IS_ERR(phydev
)) {
856 pr_err("could not attach PHY\n");
857 return PTR_ERR(phydev
);
859 phydev
->supported
&= (ADVERTISED_10baseT_Full
860 | ADVERTISED_10baseT_Half
861 | ADVERTISED_100baseT_Full
862 | ADVERTISED_100baseT_Half
863 | ADVERTISED_1000baseT_Full
867 phydev
->advertising
= phydev
->supported
;
868 phy_attached_info(phydev
);
872 static int xlr_setup_mdio(struct xlr_net_priv
*priv
,
873 struct platform_device
*pdev
)
877 priv
->mii_bus
= mdiobus_alloc();
878 if (!priv
->mii_bus
) {
879 pr_err("mdiobus alloc failed\n");
883 priv
->mii_bus
->priv
= priv
;
884 priv
->mii_bus
->name
= "xlr-mdio";
885 snprintf(priv
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%s-%d",
886 priv
->mii_bus
->name
, priv
->port_id
);
887 priv
->mii_bus
->read
= xlr_mii_read
;
888 priv
->mii_bus
->write
= xlr_mii_write
;
889 priv
->mii_bus
->parent
= &pdev
->dev
;
891 /* Scan only the enabled address */
892 priv
->mii_bus
->phy_mask
= ~(1 << priv
->phy_addr
);
894 /* setting clock divisor to 54 */
895 xlr_nae_wreg(priv
->base_addr
, R_MII_MGMT_CONFIG
, 0x7);
897 err
= mdiobus_register(priv
->mii_bus
);
899 mdiobus_free(priv
->mii_bus
);
900 pr_err("mdio bus registration failed\n");
904 pr_info("Registered mdio bus id : %s\n", priv
->mii_bus
->id
);
905 err
= xlr_mii_probe(priv
);
907 mdiobus_free(priv
->mii_bus
);
913 static void xlr_port_enable(struct xlr_net_priv
*priv
)
915 u32 prid
= (read_c0_prid() & 0xf000);
917 /* Setup MAC_CONFIG reg if (xls & rgmii) */
918 if ((prid
== 0x8000 || prid
== 0x4000 || prid
== 0xc000) &&
919 priv
->nd
->phy_interface
== PHY_INTERFACE_MODE_RGMII
)
920 xlr_reg_update(priv
->base_addr
, R_RX_CONTROL
,
921 (1 << O_RX_CONTROL__RGMII
),
922 (1 << O_RX_CONTROL__RGMII
));
925 xlr_reg_update(priv
->base_addr
, R_MAC_CONFIG_1
,
926 ((1 << O_MAC_CONFIG_1__rxen
) |
927 (1 << O_MAC_CONFIG_1__txen
) |
928 (1 << O_MAC_CONFIG_1__rxfc
) |
929 (1 << O_MAC_CONFIG_1__txfc
)),
930 ((1 << O_MAC_CONFIG_1__rxen
) |
931 (1 << O_MAC_CONFIG_1__txen
) |
932 (1 << O_MAC_CONFIG_1__rxfc
) |
933 (1 << O_MAC_CONFIG_1__txfc
)));
935 /* Setup tx control reg */
936 xlr_reg_update(priv
->base_addr
, R_TX_CONTROL
,
937 ((1 << O_TX_CONTROL__TXENABLE
) |
938 (512 << O_TX_CONTROL__TXTHRESHOLD
)), 0x3fff);
940 /* Setup rx control reg */
941 xlr_reg_update(priv
->base_addr
, R_RX_CONTROL
,
942 1 << O_RX_CONTROL__RXENABLE
,
943 1 << O_RX_CONTROL__RXENABLE
);
946 static void xlr_port_disable(struct xlr_net_priv
*priv
)
948 /* Setup MAC_CONFIG reg */
950 xlr_reg_update(priv
->base_addr
, R_MAC_CONFIG_1
,
951 ((1 << O_MAC_CONFIG_1__rxen
) |
952 (1 << O_MAC_CONFIG_1__txen
) |
953 (1 << O_MAC_CONFIG_1__rxfc
) |
954 (1 << O_MAC_CONFIG_1__txfc
)), 0x0);
956 /* Setup tx control reg */
957 xlr_reg_update(priv
->base_addr
, R_TX_CONTROL
,
958 ((1 << O_TX_CONTROL__TXENABLE
) |
959 (512 << O_TX_CONTROL__TXTHRESHOLD
)), 0);
961 /* Setup rx control reg */
962 xlr_reg_update(priv
->base_addr
, R_RX_CONTROL
,
963 1 << O_RX_CONTROL__RXENABLE
, 0);
967 * Initialization of gmac
969 static int xlr_gmac_init(struct xlr_net_priv
*priv
,
970 struct platform_device
*pdev
)
974 pr_info("Initializing the gmac%d\n", priv
->port_id
);
976 xlr_port_disable(priv
);
978 xlr_nae_wreg(priv
->base_addr
, R_DESC_PACK_CTRL
,
979 (1 << O_DESC_PACK_CTRL__MAXENTRY
) |
980 (BYTE_OFFSET
<< O_DESC_PACK_CTRL__BYTEOFFSET
) |
981 (1600 << O_DESC_PACK_CTRL__REGULARSIZE
));
983 ret
= xlr_setup_mdio(priv
, pdev
);
986 xlr_port_enable(priv
);
988 /* Enable Full-duplex/1000Mbps/CRC */
989 xlr_nae_wreg(priv
->base_addr
, R_MAC_CONFIG_2
, 0x7217);
991 xlr_nae_wreg(priv
->base_addr
, R_CORECONTROL
, 0x02);
992 /* Setup Interrupt mask reg */
993 xlr_nae_wreg(priv
->base_addr
, R_INTMASK
, (1 << O_INTMASK__TXILLEGAL
) |
994 (1 << O_INTMASK__MDINT
) | (1 << O_INTMASK__TXFETCHERROR
) |
995 (1 << O_INTMASK__P2PSPILLECC
) | (1 << O_INTMASK__TAGFULL
) |
996 (1 << O_INTMASK__UNDERRUN
) | (1 << O_INTMASK__ABORT
));
998 /* Clear all stats */
999 xlr_reg_update(priv
->base_addr
, R_STATCTRL
, 0, 1 << O_STATCTRL__CLRCNT
);
1000 xlr_reg_update(priv
->base_addr
, R_STATCTRL
, 1 << 2, 1 << 2);
1004 static int xlr_net_probe(struct platform_device
*pdev
)
1006 struct xlr_net_priv
*priv
= NULL
;
1007 struct net_device
*ndev
;
1008 struct resource
*res
;
1009 struct xlr_adapter
*adapter
;
1012 pr_info("XLR/XLS Ethernet Driver controller %d\n", pdev
->id
);
1014 * Allocate our adapter data structure and attach it to the device.
1016 adapter
= (struct xlr_adapter
*)
1017 devm_kzalloc(&pdev
->dev
, sizeof(*adapter
), GFP_KERNEL
);
1024 * XLR and XLS have 1 and 2 NAE controller respectively
1025 * Each controller has 4 gmac ports, mapping each controller
1026 * under one parent device, 4 gmac ports under one device.
1028 for (port
= 0; port
< pdev
->num_resources
/ 2; port
++) {
1029 ndev
= alloc_etherdev_mq(sizeof(struct xlr_net_priv
), 32);
1032 "Allocation of Ethernet device failed\n");
1036 priv
= netdev_priv(ndev
);
1039 priv
->port_id
= (pdev
->id
* 4) + port
;
1040 priv
->nd
= (struct xlr_net_data
*)pdev
->dev
.platform_data
;
1041 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, port
);
1042 priv
->base_addr
= devm_ioremap_resource(&pdev
->dev
, res
);
1043 if (IS_ERR(priv
->base_addr
)) {
1044 err
= PTR_ERR(priv
->base_addr
);
1047 priv
->adapter
= adapter
;
1048 adapter
->netdev
[port
] = ndev
;
1050 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, port
);
1052 dev_err(&pdev
->dev
, "No irq resource for MAC %d\n",
1058 ndev
->irq
= res
->start
;
1060 priv
->phy_addr
= priv
->nd
->phy_addr
[port
];
1061 priv
->tx_stnid
= priv
->nd
->tx_stnid
[port
];
1062 priv
->mii_addr
= priv
->nd
->mii_addr
;
1063 priv
->serdes_addr
= priv
->nd
->serdes_addr
;
1064 priv
->pcs_addr
= priv
->nd
->pcs_addr
;
1065 priv
->gpio_addr
= priv
->nd
->gpio_addr
;
1067 ndev
->netdev_ops
= &xlr_netdev_ops
;
1068 ndev
->watchdog_timeo
= HZ
;
1070 /* Setup Mac address and Rx mode */
1071 eth_hw_addr_random(ndev
);
1072 xlr_hw_set_mac_addr(ndev
);
1073 xlr_set_rx_mode(ndev
);
1075 priv
->num_rx_desc
+= MAX_NUM_DESC_SPILL
;
1076 ndev
->ethtool_ops
= &xlr_ethtool_ops
;
1077 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1079 xlr_config_fifo_spill_area(priv
);
1080 /* Configure PDE to Round-Robin pkt distribution */
1081 xlr_config_pde(priv
);
1082 xlr_config_parser(priv
);
1084 /* Call init with respect to port */
1085 if (strcmp(res
->name
, "gmac") == 0) {
1086 err
= xlr_gmac_init(priv
, pdev
);
1088 dev_err(&pdev
->dev
, "gmac%d init failed\n",
1094 if (priv
->port_id
== 0 || priv
->port_id
== 4) {
1095 err
= xlr_config_common(priv
);
1100 err
= register_netdev(ndev
);
1103 "Registering netdev failed for gmac%d\n",
1107 platform_set_drvdata(pdev
, priv
);
1113 mdiobus_free(priv
->mii_bus
);
1119 static int xlr_net_remove(struct platform_device
*pdev
)
1121 struct xlr_net_priv
*priv
= platform_get_drvdata(pdev
);
1123 unregister_netdev(priv
->ndev
);
1124 mdiobus_unregister(priv
->mii_bus
);
1125 mdiobus_free(priv
->mii_bus
);
1126 free_netdev(priv
->ndev
);
1130 static struct platform_driver xlr_net_driver
= {
1131 .probe
= xlr_net_probe
,
1132 .remove
= xlr_net_remove
,
1138 module_platform_driver(xlr_net_driver
);
1140 MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@broadcom.com>");
1141 MODULE_DESCRIPTION("Ethernet driver for Netlogic XLR/XLS");
1142 MODULE_LICENSE("Dual BSD/GPL");
1143 MODULE_ALIAS("platform:xlr-net");