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Merge tag 'cris-for-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/jesper...
[deliverable/linux.git] / drivers / staging / rdma / hfi1 / firmware.c
1 /*
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2015 Intel Corporation.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * BSD LICENSE
20 *
21 * Copyright(c) 2015 Intel Corporation.
22 *
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
25 * are met:
26 *
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
32 * distribution.
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 */
50
51 #include <linux/firmware.h>
52 #include <linux/mutex.h>
53 #include <linux/module.h>
54 #include <linux/delay.h>
55 #include <linux/crc32.h>
56
57 #include "hfi.h"
58 #include "trace.h"
59
60 /*
61 * Make it easy to toggle firmware file name and if it gets loaded by
62 * editing the following. This may be something we do while in development
63 * but not necessarily something a user would ever need to use.
64 */
65 #define DEFAULT_FW_8051_NAME_FPGA "hfi_dc8051.bin"
66 #define DEFAULT_FW_8051_NAME_ASIC "hfi1_dc8051.fw"
67 #define DEFAULT_FW_FABRIC_NAME "hfi1_fabric.fw"
68 #define DEFAULT_FW_SBUS_NAME "hfi1_sbus.fw"
69 #define DEFAULT_FW_PCIE_NAME "hfi1_pcie.fw"
70 #define DEFAULT_PLATFORM_CONFIG_NAME "hfi1_platform.dat"
71 #define ALT_FW_8051_NAME_ASIC "hfi1_dc8051_d.fw"
72 #define ALT_FW_FABRIC_NAME "hfi1_fabric_d.fw"
73 #define ALT_FW_SBUS_NAME "hfi1_sbus_d.fw"
74 #define ALT_FW_PCIE_NAME "hfi1_pcie_d.fw"
75
76 static uint fw_8051_load = 1;
77 static uint fw_fabric_serdes_load = 1;
78 static uint fw_pcie_serdes_load = 1;
79 static uint fw_sbus_load = 1;
80 static uint platform_config_load = 1;
81
82 /* Firmware file names get set in hfi1_firmware_init() based on the above */
83 static char *fw_8051_name;
84 static char *fw_fabric_serdes_name;
85 static char *fw_sbus_name;
86 static char *fw_pcie_serdes_name;
87 static char *platform_config_name;
88
89 #define SBUS_MAX_POLL_COUNT 100
90 #define SBUS_COUNTER(reg, name) \
91 (((reg) >> ASIC_STS_SBUS_COUNTERS_##name##_CNT_SHIFT) & \
92 ASIC_STS_SBUS_COUNTERS_##name##_CNT_MASK)
93
94 /*
95 * Firmware security header.
96 */
97 struct css_header {
98 u32 module_type;
99 u32 header_len;
100 u32 header_version;
101 u32 module_id;
102 u32 module_vendor;
103 u32 date; /* BCD yyyymmdd */
104 u32 size; /* in DWORDs */
105 u32 key_size; /* in DWORDs */
106 u32 modulus_size; /* in DWORDs */
107 u32 exponent_size; /* in DWORDs */
108 u32 reserved[22];
109 };
110 /* expected field values */
111 #define CSS_MODULE_TYPE 0x00000006
112 #define CSS_HEADER_LEN 0x000000a1
113 #define CSS_HEADER_VERSION 0x00010000
114 #define CSS_MODULE_VENDOR 0x00008086
115
116 #define KEY_SIZE 256
117 #define MU_SIZE 8
118 #define EXPONENT_SIZE 4
119
120 /* the file itself */
121 struct firmware_file {
122 struct css_header css_header;
123 u8 modulus[KEY_SIZE];
124 u8 exponent[EXPONENT_SIZE];
125 u8 signature[KEY_SIZE];
126 u8 firmware[];
127 };
128
129 struct augmented_firmware_file {
130 struct css_header css_header;
131 u8 modulus[KEY_SIZE];
132 u8 exponent[EXPONENT_SIZE];
133 u8 signature[KEY_SIZE];
134 u8 r2[KEY_SIZE];
135 u8 mu[MU_SIZE];
136 u8 firmware[];
137 };
138
139 /* augmented file size difference */
140 #define AUGMENT_SIZE (sizeof(struct augmented_firmware_file) - \
141 sizeof(struct firmware_file))
142
143 struct firmware_details {
144 /* Linux core piece */
145 const struct firmware *fw;
146
147 struct css_header *css_header;
148 u8 *firmware_ptr; /* pointer to binary data */
149 u32 firmware_len; /* length in bytes */
150 u8 *modulus; /* pointer to the modulus */
151 u8 *exponent; /* pointer to the exponent */
152 u8 *signature; /* pointer to the signature */
153 u8 *r2; /* pointer to r2 */
154 u8 *mu; /* pointer to mu */
155 struct augmented_firmware_file dummy_header;
156 };
157
158 /*
159 * The mutex protects fw_state, fw_err, and all of the firmware_details
160 * variables.
161 */
162 static DEFINE_MUTEX(fw_mutex);
163 enum fw_state {
164 FW_EMPTY,
165 FW_TRY,
166 FW_FINAL,
167 FW_ERR
168 };
169 static enum fw_state fw_state = FW_EMPTY;
170 static int fw_err;
171 static struct firmware_details fw_8051;
172 static struct firmware_details fw_fabric;
173 static struct firmware_details fw_pcie;
174 static struct firmware_details fw_sbus;
175 static const struct firmware *platform_config;
176
177 /* flags for turn_off_spicos() */
178 #define SPICO_SBUS 0x1
179 #define SPICO_FABRIC 0x2
180 #define ENABLE_SPICO_SMASK 0x1
181
182 /* security block commands */
183 #define RSA_CMD_INIT 0x1
184 #define RSA_CMD_START 0x2
185
186 /* security block status */
187 #define RSA_STATUS_IDLE 0x0
188 #define RSA_STATUS_ACTIVE 0x1
189 #define RSA_STATUS_DONE 0x2
190 #define RSA_STATUS_FAILED 0x3
191
192 /* RSA engine timeout, in ms */
193 #define RSA_ENGINE_TIMEOUT 100 /* ms */
194
195 /* hardware mutex timeout, in ms */
196 #define HM_TIMEOUT 4000 /* 4 s */
197
198 /* 8051 memory access timeout, in us */
199 #define DC8051_ACCESS_TIMEOUT 100 /* us */
200
201 /* the number of fabric SerDes on the SBus */
202 #define NUM_FABRIC_SERDES 4
203
204 /* SBus fabric SerDes addresses, one set per HFI */
205 static const u8 fabric_serdes_addrs[2][NUM_FABRIC_SERDES] = {
206 { 0x01, 0x02, 0x03, 0x04 },
207 { 0x28, 0x29, 0x2a, 0x2b }
208 };
209
210 /* SBus PCIe SerDes addresses, one set per HFI */
211 static const u8 pcie_serdes_addrs[2][NUM_PCIE_SERDES] = {
212 { 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16,
213 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26 },
214 { 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d,
215 0x3f, 0x41, 0x43, 0x45, 0x47, 0x49, 0x4b, 0x4d }
216 };
217
218 /* SBus PCIe PCS addresses, one set per HFI */
219 const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES] = {
220 { 0x09, 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17,
221 0x19, 0x1b, 0x1d, 0x1f, 0x21, 0x23, 0x25, 0x27 },
222 { 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
223 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e }
224 };
225
226 /* SBus fabric SerDes broadcast addresses, one per HFI */
227 static const u8 fabric_serdes_broadcast[2] = { 0xe4, 0xe5 };
228 static const u8 all_fabric_serdes_broadcast = 0xe1;
229
230 /* SBus PCIe SerDes broadcast addresses, one per HFI */
231 const u8 pcie_serdes_broadcast[2] = { 0xe2, 0xe3 };
232 static const u8 all_pcie_serdes_broadcast = 0xe0;
233
234 /* forwards */
235 static void dispose_one_firmware(struct firmware_details *fdet);
236
237 /*
238 * Read a single 64-bit value from 8051 data memory.
239 *
240 * Expects:
241 * o caller to have already set up data read, no auto increment
242 * o caller to turn off read enable when finished
243 *
244 * The address argument is a byte offset. Bits 0:2 in the address are
245 * ignored - i.e. the hardware will always do aligned 8-byte reads as if
246 * the lower bits are zero.
247 *
248 * Return 0 on success, -ENXIO on a read error (timeout).
249 */
250 static int __read_8051_data(struct hfi1_devdata *dd, u32 addr, u64 *result)
251 {
252 u64 reg;
253 int count;
254
255 /* start the read at the given address */
256 reg = ((addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
257 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT)
258 | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK;
259 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
260
261 /* wait until ACCESS_COMPLETED is set */
262 count = 0;
263 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
264 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
265 == 0) {
266 count++;
267 if (count > DC8051_ACCESS_TIMEOUT) {
268 dd_dev_err(dd, "timeout reading 8051 data\n");
269 return -ENXIO;
270 }
271 ndelay(10);
272 }
273
274 /* gather the data */
275 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA);
276
277 return 0;
278 }
279
280 /*
281 * Read 8051 data starting at addr, for len bytes. Will read in 8-byte chunks.
282 * Return 0 on success, -errno on error.
283 */
284 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result)
285 {
286 unsigned long flags;
287 u32 done;
288 int ret = 0;
289
290 spin_lock_irqsave(&dd->dc8051_memlock, flags);
291
292 /* data read set-up, no auto-increment */
293 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
294
295 for (done = 0; done < len; addr += 8, done += 8, result++) {
296 ret = __read_8051_data(dd, addr, result);
297 if (ret)
298 break;
299 }
300
301 /* turn off read enable */
302 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
303
304 spin_unlock_irqrestore(&dd->dc8051_memlock, flags);
305
306 return ret;
307 }
308
309 /*
310 * Write data or code to the 8051 code or data RAM.
311 */
312 static int write_8051(struct hfi1_devdata *dd, int code, u32 start,
313 const u8 *data, u32 len)
314 {
315 u64 reg;
316 u32 offset;
317 int aligned, count;
318
319 /* check alignment */
320 aligned = ((unsigned long)data & 0x7) == 0;
321
322 /* write set-up */
323 reg = (code ? DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK : 0ull)
324 | DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK;
325 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg);
326
327 reg = ((start & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
328 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT)
329 | DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK;
330 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
331
332 /* write */
333 for (offset = 0; offset < len; offset += 8) {
334 int bytes = len - offset;
335
336 if (bytes < 8) {
337 reg = 0;
338 memcpy(&reg, &data[offset], bytes);
339 } else if (aligned) {
340 reg = *(u64 *)&data[offset];
341 } else {
342 memcpy(&reg, &data[offset], 8);
343 }
344 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg);
345
346 /* wait until ACCESS_COMPLETED is set */
347 count = 0;
348 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
349 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
350 == 0) {
351 count++;
352 if (count > DC8051_ACCESS_TIMEOUT) {
353 dd_dev_err(dd, "timeout writing 8051 data\n");
354 return -ENXIO;
355 }
356 udelay(1);
357 }
358 }
359
360 /* turn off write access, auto increment (also sets to data access) */
361 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
362 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
363
364 return 0;
365 }
366
367 /* return 0 if values match, non-zero and complain otherwise */
368 static int invalid_header(struct hfi1_devdata *dd, const char *what,
369 u32 actual, u32 expected)
370 {
371 if (actual == expected)
372 return 0;
373
374 dd_dev_err(dd,
375 "invalid firmware header field %s: expected 0x%x, actual 0x%x\n",
376 what, expected, actual);
377 return 1;
378 }
379
380 /*
381 * Verify that the static fields in the CSS header match.
382 */
383 static int verify_css_header(struct hfi1_devdata *dd, struct css_header *css)
384 {
385 /* verify CSS header fields (most sizes are in DW, so add /4) */
386 if (invalid_header(dd, "module_type", css->module_type, CSS_MODULE_TYPE)
387 || invalid_header(dd, "header_len", css->header_len,
388 (sizeof(struct firmware_file)/4))
389 || invalid_header(dd, "header_version",
390 css->header_version, CSS_HEADER_VERSION)
391 || invalid_header(dd, "module_vendor",
392 css->module_vendor, CSS_MODULE_VENDOR)
393 || invalid_header(dd, "key_size",
394 css->key_size, KEY_SIZE/4)
395 || invalid_header(dd, "modulus_size",
396 css->modulus_size, KEY_SIZE/4)
397 || invalid_header(dd, "exponent_size",
398 css->exponent_size, EXPONENT_SIZE/4)) {
399 return -EINVAL;
400 }
401 return 0;
402 }
403
404 /*
405 * Make sure there are at least some bytes after the prefix.
406 */
407 static int payload_check(struct hfi1_devdata *dd, const char *name,
408 long file_size, long prefix_size)
409 {
410 /* make sure we have some payload */
411 if (prefix_size >= file_size) {
412 dd_dev_err(dd,
413 "firmware \"%s\", size %ld, must be larger than %ld bytes\n",
414 name, file_size, prefix_size);
415 return -EINVAL;
416 }
417
418 return 0;
419 }
420
421 /*
422 * Request the firmware from the system. Extract the pieces and fill in
423 * fdet. If successful, the caller will need to call dispose_one_firmware().
424 * Returns 0 on success, -ERRNO on error.
425 */
426 static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name,
427 struct firmware_details *fdet)
428 {
429 struct css_header *css;
430 int ret;
431
432 memset(fdet, 0, sizeof(*fdet));
433
434 ret = request_firmware(&fdet->fw, name, &dd->pcidev->dev);
435 if (ret) {
436 dd_dev_err(dd, "cannot find firmware \"%s\", err %d\n",
437 name, ret);
438 return ret;
439 }
440
441 /* verify the firmware */
442 if (fdet->fw->size < sizeof(struct css_header)) {
443 dd_dev_err(dd, "firmware \"%s\" is too small\n", name);
444 ret = -EINVAL;
445 goto done;
446 }
447 css = (struct css_header *)fdet->fw->data;
448
449 hfi1_cdbg(FIRMWARE, "Firmware %s details:", name);
450 hfi1_cdbg(FIRMWARE, "file size: 0x%lx bytes", fdet->fw->size);
451 hfi1_cdbg(FIRMWARE, "CSS structure:");
452 hfi1_cdbg(FIRMWARE, " module_type 0x%x", css->module_type);
453 hfi1_cdbg(FIRMWARE, " header_len 0x%03x (0x%03x bytes)",
454 css->header_len, 4 * css->header_len);
455 hfi1_cdbg(FIRMWARE, " header_version 0x%x", css->header_version);
456 hfi1_cdbg(FIRMWARE, " module_id 0x%x", css->module_id);
457 hfi1_cdbg(FIRMWARE, " module_vendor 0x%x", css->module_vendor);
458 hfi1_cdbg(FIRMWARE, " date 0x%x", css->date);
459 hfi1_cdbg(FIRMWARE, " size 0x%03x (0x%03x bytes)",
460 css->size, 4 * css->size);
461 hfi1_cdbg(FIRMWARE, " key_size 0x%03x (0x%03x bytes)",
462 css->key_size, 4 * css->key_size);
463 hfi1_cdbg(FIRMWARE, " modulus_size 0x%03x (0x%03x bytes)",
464 css->modulus_size, 4 * css->modulus_size);
465 hfi1_cdbg(FIRMWARE, " exponent_size 0x%03x (0x%03x bytes)",
466 css->exponent_size, 4 * css->exponent_size);
467 hfi1_cdbg(FIRMWARE, "firmware size: 0x%lx bytes",
468 fdet->fw->size - sizeof(struct firmware_file));
469
470 /*
471 * If the file does not have a valid CSS header, fail.
472 * Otherwise, check the CSS size field for an expected size.
473 * The augmented file has r2 and mu inserted after the header
474 * was generated, so there will be a known difference between
475 * the CSS header size and the actual file size. Use this
476 * difference to identify an augmented file.
477 *
478 * Note: css->size is in DWORDs, multiply by 4 to get bytes.
479 */
480 ret = verify_css_header(dd, css);
481 if (ret) {
482 dd_dev_info(dd, "Invalid CSS header for \"%s\"\n", name);
483 } else if ((css->size*4) == fdet->fw->size) {
484 /* non-augmented firmware file */
485 struct firmware_file *ff = (struct firmware_file *)
486 fdet->fw->data;
487
488 /* make sure there are bytes in the payload */
489 ret = payload_check(dd, name, fdet->fw->size,
490 sizeof(struct firmware_file));
491 if (ret == 0) {
492 fdet->css_header = css;
493 fdet->modulus = ff->modulus;
494 fdet->exponent = ff->exponent;
495 fdet->signature = ff->signature;
496 fdet->r2 = fdet->dummy_header.r2; /* use dummy space */
497 fdet->mu = fdet->dummy_header.mu; /* use dummy space */
498 fdet->firmware_ptr = ff->firmware;
499 fdet->firmware_len = fdet->fw->size -
500 sizeof(struct firmware_file);
501 /*
502 * Header does not include r2 and mu - generate here.
503 * For now, fail.
504 */
505 dd_dev_err(dd, "driver is unable to validate firmware without r2 and mu (not in firmware file)\n");
506 ret = -EINVAL;
507 }
508 } else if ((css->size*4) + AUGMENT_SIZE == fdet->fw->size) {
509 /* augmented firmware file */
510 struct augmented_firmware_file *aff =
511 (struct augmented_firmware_file *)fdet->fw->data;
512
513 /* make sure there are bytes in the payload */
514 ret = payload_check(dd, name, fdet->fw->size,
515 sizeof(struct augmented_firmware_file));
516 if (ret == 0) {
517 fdet->css_header = css;
518 fdet->modulus = aff->modulus;
519 fdet->exponent = aff->exponent;
520 fdet->signature = aff->signature;
521 fdet->r2 = aff->r2;
522 fdet->mu = aff->mu;
523 fdet->firmware_ptr = aff->firmware;
524 fdet->firmware_len = fdet->fw->size -
525 sizeof(struct augmented_firmware_file);
526 }
527 } else {
528 /* css->size check failed */
529 dd_dev_err(dd,
530 "invalid firmware header field size: expected 0x%lx or 0x%lx, actual 0x%x\n",
531 fdet->fw->size/4, (fdet->fw->size - AUGMENT_SIZE)/4,
532 css->size);
533
534 ret = -EINVAL;
535 }
536
537 done:
538 /* if returning an error, clean up after ourselves */
539 if (ret)
540 dispose_one_firmware(fdet);
541 return ret;
542 }
543
544 static void dispose_one_firmware(struct firmware_details *fdet)
545 {
546 release_firmware(fdet->fw);
547 /* erase all previous information */
548 memset(fdet, 0, sizeof(*fdet));
549 }
550
551 /*
552 * Obtain the 4 firmwares from the OS. All must be obtained at once or not
553 * at all. If called with the firmware state in FW_TRY, use alternate names.
554 * On exit, this routine will have set the firmware state to one of FW_TRY,
555 * FW_FINAL, or FW_ERR.
556 *
557 * Must be holding fw_mutex.
558 */
559 static void __obtain_firmware(struct hfi1_devdata *dd)
560 {
561 int err = 0;
562
563 if (fw_state == FW_FINAL) /* nothing more to obtain */
564 return;
565 if (fw_state == FW_ERR) /* already in error */
566 return;
567
568 /* fw_state is FW_EMPTY or FW_TRY */
569 retry:
570 if (fw_state == FW_TRY) {
571 /*
572 * We tried the original and it failed. Move to the
573 * alternate.
574 */
575 dd_dev_info(dd, "using alternate firmware names\n");
576 /*
577 * Let others run. Some systems, when missing firmware, does
578 * something that holds for 30 seconds. If we do that twice
579 * in a row it triggers task blocked warning.
580 */
581 cond_resched();
582 if (fw_8051_load)
583 dispose_one_firmware(&fw_8051);
584 if (fw_fabric_serdes_load)
585 dispose_one_firmware(&fw_fabric);
586 if (fw_sbus_load)
587 dispose_one_firmware(&fw_sbus);
588 if (fw_pcie_serdes_load)
589 dispose_one_firmware(&fw_pcie);
590 fw_8051_name = ALT_FW_8051_NAME_ASIC;
591 fw_fabric_serdes_name = ALT_FW_FABRIC_NAME;
592 fw_sbus_name = ALT_FW_SBUS_NAME;
593 fw_pcie_serdes_name = ALT_FW_PCIE_NAME;
594 }
595
596 if (fw_8051_load) {
597 err = obtain_one_firmware(dd, fw_8051_name, &fw_8051);
598 if (err)
599 goto done;
600 }
601
602 if (fw_fabric_serdes_load) {
603 err = obtain_one_firmware(dd, fw_fabric_serdes_name,
604 &fw_fabric);
605 if (err)
606 goto done;
607 }
608
609 if (fw_sbus_load) {
610 err = obtain_one_firmware(dd, fw_sbus_name, &fw_sbus);
611 if (err)
612 goto done;
613 }
614
615 if (fw_pcie_serdes_load) {
616 err = obtain_one_firmware(dd, fw_pcie_serdes_name, &fw_pcie);
617 if (err)
618 goto done;
619 }
620
621 done:
622 if (err) {
623 /* oops, had problems obtaining a firmware */
624 if (fw_state == FW_EMPTY) {
625 /* retry with alternate */
626 fw_state = FW_TRY;
627 goto retry;
628 }
629 fw_state = FW_ERR;
630 fw_err = -ENOENT;
631 } else {
632 /* success */
633 if (fw_state == FW_EMPTY)
634 fw_state = FW_TRY; /* may retry later */
635 else
636 fw_state = FW_FINAL; /* cannot try again */
637 }
638 }
639
640 /*
641 * Called by all HFIs when loading their firmware - i.e. device probe time.
642 * The first one will do the actual firmware load. Use a mutex to resolve
643 * any possible race condition.
644 *
645 * The call to this routine cannot be moved to driver load because the kernel
646 * call request_firmware() requires a device which is only available after
647 * the first device probe.
648 */
649 static int obtain_firmware(struct hfi1_devdata *dd)
650 {
651 unsigned long timeout;
652 int err = 0;
653
654 mutex_lock(&fw_mutex);
655
656 /* 40s delay due to long delay on missing firmware on some systems */
657 timeout = jiffies + msecs_to_jiffies(40000);
658 while (fw_state == FW_TRY) {
659 /*
660 * Another device is trying the firmware. Wait until it
661 * decides what works (or not).
662 */
663 if (time_after(jiffies, timeout)) {
664 /* waited too long */
665 dd_dev_err(dd, "Timeout waiting for firmware try");
666 fw_state = FW_ERR;
667 fw_err = -ETIMEDOUT;
668 break;
669 }
670 mutex_unlock(&fw_mutex);
671 msleep(20); /* arbitrary delay */
672 mutex_lock(&fw_mutex);
673 }
674 /* not in FW_TRY state */
675
676 if (fw_state == FW_FINAL)
677 goto done; /* already acquired */
678 else if (fw_state == FW_ERR)
679 goto done; /* already tried and failed */
680 /* fw_state is FW_EMPTY */
681
682 /* set fw_state to FW_TRY, FW_FINAL, or FW_ERR, and fw_err */
683 __obtain_firmware(dd);
684
685 if (platform_config_load) {
686 platform_config = NULL;
687 err = request_firmware(&platform_config, platform_config_name,
688 &dd->pcidev->dev);
689 if (err)
690 platform_config = NULL;
691 }
692
693 done:
694 mutex_unlock(&fw_mutex);
695
696 return fw_err;
697 }
698
699 /*
700 * Called when the driver unloads. The timing is asymmetric with its
701 * counterpart, obtain_firmware(). If called at device remove time,
702 * then it is conceivable that another device could probe while the
703 * firmware is being disposed. The mutexes can be moved to do that
704 * safely, but then the firmware would be requested from the OS multiple
705 * times.
706 *
707 * No mutex is needed as the driver is unloading and there cannot be any
708 * other callers.
709 */
710 void dispose_firmware(void)
711 {
712 dispose_one_firmware(&fw_8051);
713 dispose_one_firmware(&fw_fabric);
714 dispose_one_firmware(&fw_pcie);
715 dispose_one_firmware(&fw_sbus);
716
717 release_firmware(platform_config);
718 platform_config = NULL;
719
720 /* retain the error state, otherwise revert to empty */
721 if (fw_state != FW_ERR)
722 fw_state = FW_EMPTY;
723 }
724
725 /*
726 * Called with the result of a firmware download.
727 *
728 * Return 1 to retry loading the firmware, 0 to stop.
729 */
730 static int retry_firmware(struct hfi1_devdata *dd, int load_result)
731 {
732 int retry;
733
734 mutex_lock(&fw_mutex);
735
736 if (load_result == 0) {
737 /*
738 * The load succeeded, so expect all others to do the same.
739 * Do not retry again.
740 */
741 if (fw_state == FW_TRY)
742 fw_state = FW_FINAL;
743 retry = 0; /* do NOT retry */
744 } else if (fw_state == FW_TRY) {
745 /* load failed, obtain alternate firmware */
746 __obtain_firmware(dd);
747 retry = (fw_state == FW_FINAL);
748 } else {
749 /* else in FW_FINAL or FW_ERR, no retry in either case */
750 retry = 0;
751 }
752
753 mutex_unlock(&fw_mutex);
754 return retry;
755 }
756
757 /*
758 * Write a block of data to a given array CSR. All calls will be in
759 * multiples of 8 bytes.
760 */
761 static void write_rsa_data(struct hfi1_devdata *dd, int what,
762 const u8 *data, int nbytes)
763 {
764 int qw_size = nbytes/8;
765 int i;
766
767 if (((unsigned long)data & 0x7) == 0) {
768 /* aligned */
769 u64 *ptr = (u64 *)data;
770
771 for (i = 0; i < qw_size; i++, ptr++)
772 write_csr(dd, what + (8*i), *ptr);
773 } else {
774 /* not aligned */
775 for (i = 0; i < qw_size; i++, data += 8) {
776 u64 value;
777
778 memcpy(&value, data, 8);
779 write_csr(dd, what + (8*i), value);
780 }
781 }
782 }
783
784 /*
785 * Write a block of data to a given CSR as a stream of writes. All calls will
786 * be in multiples of 8 bytes.
787 */
788 static void write_streamed_rsa_data(struct hfi1_devdata *dd, int what,
789 const u8 *data, int nbytes)
790 {
791 u64 *ptr = (u64 *)data;
792 int qw_size = nbytes/8;
793
794 for (; qw_size > 0; qw_size--, ptr++)
795 write_csr(dd, what, *ptr);
796 }
797
798 /*
799 * Download the signature and start the RSA mechanism. Wait for
800 * RSA_ENGINE_TIMEOUT before giving up.
801 */
802 static int run_rsa(struct hfi1_devdata *dd, const char *who,
803 const u8 *signature)
804 {
805 unsigned long timeout;
806 u64 reg;
807 u32 status;
808 int ret = 0;
809
810 /* write the signature */
811 write_rsa_data(dd, MISC_CFG_RSA_SIGNATURE, signature, KEY_SIZE);
812
813 /* initialize RSA */
814 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT);
815
816 /*
817 * Make sure the engine is idle and insert a delay between the two
818 * writes to MISC_CFG_RSA_CMD.
819 */
820 status = (read_csr(dd, MISC_CFG_FW_CTRL)
821 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
822 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
823 if (status != RSA_STATUS_IDLE) {
824 dd_dev_err(dd, "%s security engine not idle - giving up\n",
825 who);
826 return -EBUSY;
827 }
828
829 /* start RSA */
830 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START);
831
832 /*
833 * Look for the result.
834 *
835 * The RSA engine is hooked up to two MISC errors. The driver
836 * masks these errors as they do not respond to the standard
837 * error "clear down" mechanism. Look for these errors here and
838 * clear them when possible. This routine will exit with the
839 * errors of the current run still set.
840 *
841 * MISC_FW_AUTH_FAILED_ERR
842 * Firmware authorization failed. This can be cleared by
843 * re-initializing the RSA engine, then clearing the status bit.
844 * Do not re-init the RSA angine immediately after a successful
845 * run - this will reset the current authorization.
846 *
847 * MISC_KEY_MISMATCH_ERR
848 * Key does not match. The only way to clear this is to load
849 * a matching key then clear the status bit. If this error
850 * is raised, it will persist outside of this routine until a
851 * matching key is loaded.
852 */
853 timeout = msecs_to_jiffies(RSA_ENGINE_TIMEOUT) + jiffies;
854 while (1) {
855 status = (read_csr(dd, MISC_CFG_FW_CTRL)
856 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
857 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
858
859 if (status == RSA_STATUS_IDLE) {
860 /* should not happen */
861 dd_dev_err(dd, "%s firmware security bad idle state\n",
862 who);
863 ret = -EINVAL;
864 break;
865 } else if (status == RSA_STATUS_DONE) {
866 /* finished successfully */
867 break;
868 } else if (status == RSA_STATUS_FAILED) {
869 /* finished unsuccessfully */
870 ret = -EINVAL;
871 break;
872 }
873 /* else still active */
874
875 if (time_after(jiffies, timeout)) {
876 /*
877 * Timed out while active. We can't reset the engine
878 * if it is stuck active, but run through the
879 * error code to see what error bits are set.
880 */
881 dd_dev_err(dd, "%s firmware security time out\n", who);
882 ret = -ETIMEDOUT;
883 break;
884 }
885
886 msleep(20);
887 }
888
889 /*
890 * Arrive here on success or failure. Clear all RSA engine
891 * errors. All current errors will stick - the RSA logic is keeping
892 * error high. All previous errors will clear - the RSA logic
893 * is not keeping the error high.
894 */
895 write_csr(dd, MISC_ERR_CLEAR,
896 MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK
897 | MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK);
898 /*
899 * All that is left are the current errors. Print failure details,
900 * if any.
901 */
902 reg = read_csr(dd, MISC_ERR_STATUS);
903 if (ret) {
904 if (reg & MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK)
905 dd_dev_err(dd, "%s firmware authorization failed\n",
906 who);
907 if (reg & MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK)
908 dd_dev_err(dd, "%s firmware key mismatch\n", who);
909 }
910
911 return ret;
912 }
913
914 static void load_security_variables(struct hfi1_devdata *dd,
915 struct firmware_details *fdet)
916 {
917 /* Security variables a. Write the modulus */
918 write_rsa_data(dd, MISC_CFG_RSA_MODULUS, fdet->modulus, KEY_SIZE);
919 /* Security variables b. Write the r2 */
920 write_rsa_data(dd, MISC_CFG_RSA_R2, fdet->r2, KEY_SIZE);
921 /* Security variables c. Write the mu */
922 write_rsa_data(dd, MISC_CFG_RSA_MU, fdet->mu, MU_SIZE);
923 /* Security variables d. Write the header */
924 write_streamed_rsa_data(dd, MISC_CFG_SHA_PRELOAD,
925 (u8 *)fdet->css_header, sizeof(struct css_header));
926 }
927
928 /* return the 8051 firmware state */
929 static inline u32 get_firmware_state(struct hfi1_devdata *dd)
930 {
931 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
932
933 return (reg >> DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT)
934 & DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK;
935 }
936
937 /*
938 * Wait until the firmware is up and ready to take host requests.
939 * Return 0 on success, -ETIMEDOUT on timeout.
940 */
941 int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout)
942 {
943 unsigned long timeout;
944
945 /* in the simulator, the fake 8051 is always ready */
946 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
947 return 0;
948
949 timeout = msecs_to_jiffies(mstimeout) + jiffies;
950 while (1) {
951 if (get_firmware_state(dd) == 0xa0) /* ready */
952 return 0;
953 if (time_after(jiffies, timeout)) /* timed out */
954 return -ETIMEDOUT;
955 usleep_range(1950, 2050); /* sleep 2ms-ish */
956 }
957 }
958
959 /*
960 * Load the 8051 firmware.
961 */
962 static int load_8051_firmware(struct hfi1_devdata *dd,
963 struct firmware_details *fdet)
964 {
965 u64 reg;
966 int ret;
967 u8 ver_a, ver_b;
968
969 /*
970 * DC Reset sequence
971 * Load DC 8051 firmware
972 */
973 /*
974 * DC reset step 1: Reset DC8051
975 */
976 reg = DC_DC8051_CFG_RST_M8051W_SMASK
977 | DC_DC8051_CFG_RST_CRAM_SMASK
978 | DC_DC8051_CFG_RST_DRAM_SMASK
979 | DC_DC8051_CFG_RST_IRAM_SMASK
980 | DC_DC8051_CFG_RST_SFR_SMASK;
981 write_csr(dd, DC_DC8051_CFG_RST, reg);
982
983 /*
984 * DC reset step 2 (optional): Load 8051 data memory with link
985 * configuration
986 */
987
988 /*
989 * DC reset step 3: Load DC8051 firmware
990 */
991 /* release all but the core reset */
992 reg = DC_DC8051_CFG_RST_M8051W_SMASK;
993 write_csr(dd, DC_DC8051_CFG_RST, reg);
994
995 /* Firmware load step 1 */
996 load_security_variables(dd, fdet);
997
998 /*
999 * Firmware load step 2. Clear MISC_CFG_FW_CTRL.FW_8051_LOADED
1000 */
1001 write_csr(dd, MISC_CFG_FW_CTRL, 0);
1002
1003 /* Firmware load steps 3-5 */
1004 ret = write_8051(dd, 1/*code*/, 0, fdet->firmware_ptr,
1005 fdet->firmware_len);
1006 if (ret)
1007 return ret;
1008
1009 /*
1010 * DC reset step 4. Host starts the DC8051 firmware
1011 */
1012 /*
1013 * Firmware load step 6. Set MISC_CFG_FW_CTRL.FW_8051_LOADED
1014 */
1015 write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK);
1016
1017 /* Firmware load steps 7-10 */
1018 ret = run_rsa(dd, "8051", fdet->signature);
1019 if (ret)
1020 return ret;
1021
1022 /* clear all reset bits, releasing the 8051 */
1023 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
1024
1025 /*
1026 * DC reset step 5. Wait for firmware to be ready to accept host
1027 * requests.
1028 */
1029 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
1030 if (ret) { /* timed out */
1031 dd_dev_err(dd, "8051 start timeout, current state 0x%x\n",
1032 get_firmware_state(dd));
1033 return -ETIMEDOUT;
1034 }
1035
1036 read_misc_status(dd, &ver_a, &ver_b);
1037 dd_dev_info(dd, "8051 firmware version %d.%d\n",
1038 (int)ver_b, (int)ver_a);
1039 dd->dc8051_ver = dc8051_ver(ver_b, ver_a);
1040
1041 return 0;
1042 }
1043
1044 /*
1045 * Write the SBus request register
1046 *
1047 * No need for masking - the arguments are sized exactly.
1048 */
1049 void sbus_request(struct hfi1_devdata *dd,
1050 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1051 {
1052 write_csr(dd, ASIC_CFG_SBUS_REQUEST,
1053 ((u64)data_in << ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT)
1054 | ((u64)command << ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT)
1055 | ((u64)data_addr << ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT)
1056 | ((u64)receiver_addr
1057 << ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT));
1058 }
1059
1060 /*
1061 * Turn off the SBus and fabric serdes spicos.
1062 *
1063 * + Must be called with Sbus fast mode turned on.
1064 * + Must be called after fabric serdes broadcast is set up.
1065 * + Must be called before the 8051 is loaded - assumes 8051 is not loaded
1066 * when using MISC_CFG_FW_CTRL.
1067 */
1068 static void turn_off_spicos(struct hfi1_devdata *dd, int flags)
1069 {
1070 /* only needed on A0 */
1071 if (!is_ax(dd))
1072 return;
1073
1074 dd_dev_info(dd, "Turning off spicos:%s%s\n",
1075 flags & SPICO_SBUS ? " SBus" : "",
1076 flags & SPICO_FABRIC ? " fabric" : "");
1077
1078 write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK);
1079 /* disable SBus spico */
1080 if (flags & SPICO_SBUS)
1081 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01,
1082 WRITE_SBUS_RECEIVER, 0x00000040);
1083
1084 /* disable the fabric serdes spicos */
1085 if (flags & SPICO_FABRIC)
1086 sbus_request(dd, fabric_serdes_broadcast[dd->hfi1_id],
1087 0x07, WRITE_SBUS_RECEIVER, 0x00000000);
1088 write_csr(dd, MISC_CFG_FW_CTRL, 0);
1089 }
1090
1091 /*
1092 * Reset all of the fabric serdes for our HFI.
1093 */
1094 void fabric_serdes_reset(struct hfi1_devdata *dd)
1095 {
1096 u8 ra;
1097
1098 if (dd->icode != ICODE_RTL_SILICON) /* only for RTL */
1099 return;
1100
1101 ra = fabric_serdes_broadcast[dd->hfi1_id];
1102
1103 acquire_hw_mutex(dd);
1104 set_sbus_fast_mode(dd);
1105 /* place SerDes in reset and disable SPICO */
1106 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1107 /* wait 100 refclk cycles @ 156.25MHz => 640ns */
1108 udelay(1);
1109 /* remove SerDes reset */
1110 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1111 /* turn SPICO enable on */
1112 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1113 clear_sbus_fast_mode(dd);
1114 release_hw_mutex(dd);
1115 }
1116
1117 /* Access to the SBus in this routine should probably be serialized */
1118 int sbus_request_slow(struct hfi1_devdata *dd,
1119 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1120 {
1121 u64 reg, count = 0;
1122
1123 sbus_request(dd, receiver_addr, data_addr, command, data_in);
1124 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1125 ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK);
1126 /* Wait for both DONE and RCV_DATA_VALID to go high */
1127 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1128 while (!((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1129 (reg & ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK))) {
1130 if (count++ >= SBUS_MAX_POLL_COUNT) {
1131 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1132 /*
1133 * If the loop has timed out, we are OK if DONE bit
1134 * is set and RCV_DATA_VALID and EXECUTE counters
1135 * are the same. If not, we cannot proceed.
1136 */
1137 if ((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1138 (SBUS_COUNTER(counts, RCV_DATA_VALID) ==
1139 SBUS_COUNTER(counts, EXECUTE)))
1140 break;
1141 return -ETIMEDOUT;
1142 }
1143 udelay(1);
1144 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1145 }
1146 count = 0;
1147 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1148 /* Wait for DONE to clear after EXECUTE is cleared */
1149 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1150 while (reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) {
1151 if (count++ >= SBUS_MAX_POLL_COUNT)
1152 return -ETIME;
1153 udelay(1);
1154 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1155 }
1156 return 0;
1157 }
1158
1159 static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
1160 struct firmware_details *fdet)
1161 {
1162 int i, err;
1163 const u8 ra = fabric_serdes_broadcast[dd->hfi1_id]; /* receiver addr */
1164
1165 dd_dev_info(dd, "Downloading fabric firmware\n");
1166
1167 /* step 1: load security variables */
1168 load_security_variables(dd, fdet);
1169 /* step 2: place SerDes in reset and disable SPICO */
1170 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1171 /* wait 100 refclk cycles @ 156.25MHz => 640ns */
1172 udelay(1);
1173 /* step 3: remove SerDes reset */
1174 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1175 /* step 4: assert IMEM override */
1176 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x40000000);
1177 /* step 5: download SerDes machine code */
1178 for (i = 0; i < fdet->firmware_len; i += 4) {
1179 sbus_request(dd, ra, 0x0a, WRITE_SBUS_RECEIVER,
1180 *(u32 *)&fdet->firmware_ptr[i]);
1181 }
1182 /* step 6: IMEM override off */
1183 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x00000000);
1184 /* step 7: turn ECC on */
1185 sbus_request(dd, ra, 0x0b, WRITE_SBUS_RECEIVER, 0x000c0000);
1186
1187 /* steps 8-11: run the RSA engine */
1188 err = run_rsa(dd, "fabric serdes", fdet->signature);
1189 if (err)
1190 return err;
1191
1192 /* step 12: turn SPICO enable on */
1193 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1194 /* step 13: enable core hardware interrupts */
1195 sbus_request(dd, ra, 0x08, WRITE_SBUS_RECEIVER, 0x00000000);
1196
1197 return 0;
1198 }
1199
1200 static int load_sbus_firmware(struct hfi1_devdata *dd,
1201 struct firmware_details *fdet)
1202 {
1203 int i, err;
1204 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */
1205
1206 dd_dev_info(dd, "Downloading SBus firmware\n");
1207
1208 /* step 1: load security variables */
1209 load_security_variables(dd, fdet);
1210 /* step 2: place SPICO into reset and enable off */
1211 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x000000c0);
1212 /* step 3: remove reset, enable off, IMEM_CNTRL_EN on */
1213 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000240);
1214 /* step 4: set starting IMEM address for burst download */
1215 sbus_request(dd, ra, 0x03, WRITE_SBUS_RECEIVER, 0x80000000);
1216 /* step 5: download the SBus Master machine code */
1217 for (i = 0; i < fdet->firmware_len; i += 4) {
1218 sbus_request(dd, ra, 0x14, WRITE_SBUS_RECEIVER,
1219 *(u32 *)&fdet->firmware_ptr[i]);
1220 }
1221 /* step 6: set IMEM_CNTL_EN off */
1222 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000040);
1223 /* step 7: turn ECC on */
1224 sbus_request(dd, ra, 0x16, WRITE_SBUS_RECEIVER, 0x000c0000);
1225
1226 /* steps 8-11: run the RSA engine */
1227 err = run_rsa(dd, "SBus", fdet->signature);
1228 if (err)
1229 return err;
1230
1231 /* step 12: set SPICO_ENABLE on */
1232 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1233
1234 return 0;
1235 }
1236
1237 static int load_pcie_serdes_firmware(struct hfi1_devdata *dd,
1238 struct firmware_details *fdet)
1239 {
1240 int i;
1241 const u8 ra = SBUS_MASTER_BROADCAST; /* receiver address */
1242
1243 dd_dev_info(dd, "Downloading PCIe firmware\n");
1244
1245 /* step 1: load security variables */
1246 load_security_variables(dd, fdet);
1247 /* step 2: assert single step (halts the SBus Master spico) */
1248 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000001);
1249 /* step 3: enable XDMEM access */
1250 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000d40);
1251 /* step 4: load firmware into SBus Master XDMEM */
1252 /* NOTE: the dmem address, write_en, and wdata are all pre-packed,
1253 we only need to pick up the bytes and write them */
1254 for (i = 0; i < fdet->firmware_len; i += 4) {
1255 sbus_request(dd, ra, 0x04, WRITE_SBUS_RECEIVER,
1256 *(u32 *)&fdet->firmware_ptr[i]);
1257 }
1258 /* step 5: disable XDMEM access */
1259 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1260 /* step 6: allow SBus Spico to run */
1261 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000000);
1262
1263 /* steps 7-11: run RSA, if it succeeds, firmware is available to
1264 be swapped */
1265 return run_rsa(dd, "PCIe serdes", fdet->signature);
1266 }
1267
1268 /*
1269 * Set the given broadcast values on the given list of devices.
1270 */
1271 static void set_serdes_broadcast(struct hfi1_devdata *dd, u8 bg1, u8 bg2,
1272 const u8 *addrs, int count)
1273 {
1274 while (--count >= 0) {
1275 /*
1276 * Set BROADCAST_GROUP_1 and BROADCAST_GROUP_2, leave
1277 * defaults for everything else. Do not read-modify-write,
1278 * per instruction from the manufacturer.
1279 *
1280 * Register 0xfd:
1281 * bits what
1282 * ----- ---------------------------------
1283 * 0 IGNORE_BROADCAST (default 0)
1284 * 11:4 BROADCAST_GROUP_1 (default 0xff)
1285 * 23:16 BROADCAST_GROUP_2 (default 0xff)
1286 */
1287 sbus_request(dd, addrs[count], 0xfd, WRITE_SBUS_RECEIVER,
1288 (u32)bg1 << 4 | (u32)bg2 << 16);
1289 }
1290 }
1291
1292 int acquire_hw_mutex(struct hfi1_devdata *dd)
1293 {
1294 unsigned long timeout;
1295 int try = 0;
1296 u8 mask = 1 << dd->hfi1_id;
1297 u8 user;
1298
1299 retry:
1300 timeout = msecs_to_jiffies(HM_TIMEOUT) + jiffies;
1301 while (1) {
1302 write_csr(dd, ASIC_CFG_MUTEX, mask);
1303 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1304 if (user == mask)
1305 return 0; /* success */
1306 if (time_after(jiffies, timeout))
1307 break; /* timed out */
1308 msleep(20);
1309 }
1310
1311 /* timed out */
1312 dd_dev_err(dd,
1313 "Unable to acquire hardware mutex, mutex mask %u, my mask %u (%s)\n",
1314 (u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up");
1315
1316 if (try == 0) {
1317 /* break mutex and retry */
1318 write_csr(dd, ASIC_CFG_MUTEX, 0);
1319 try++;
1320 goto retry;
1321 }
1322
1323 return -EBUSY;
1324 }
1325
1326 void release_hw_mutex(struct hfi1_devdata *dd)
1327 {
1328 write_csr(dd, ASIC_CFG_MUTEX, 0);
1329 }
1330
1331 void set_sbus_fast_mode(struct hfi1_devdata *dd)
1332 {
1333 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1334 ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK);
1335 }
1336
1337 void clear_sbus_fast_mode(struct hfi1_devdata *dd)
1338 {
1339 u64 reg, count = 0;
1340
1341 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1342 while (SBUS_COUNTER(reg, EXECUTE) !=
1343 SBUS_COUNTER(reg, RCV_DATA_VALID)) {
1344 if (count++ >= SBUS_MAX_POLL_COUNT)
1345 break;
1346 udelay(1);
1347 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1348 }
1349 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1350 }
1351
1352 int load_firmware(struct hfi1_devdata *dd)
1353 {
1354 int ret;
1355
1356 if (fw_fabric_serdes_load) {
1357 ret = acquire_hw_mutex(dd);
1358 if (ret)
1359 return ret;
1360
1361 set_sbus_fast_mode(dd);
1362
1363 set_serdes_broadcast(dd, all_fabric_serdes_broadcast,
1364 fabric_serdes_broadcast[dd->hfi1_id],
1365 fabric_serdes_addrs[dd->hfi1_id],
1366 NUM_FABRIC_SERDES);
1367 turn_off_spicos(dd, SPICO_FABRIC);
1368 do {
1369 ret = load_fabric_serdes_firmware(dd, &fw_fabric);
1370 } while (retry_firmware(dd, ret));
1371
1372 clear_sbus_fast_mode(dd);
1373 release_hw_mutex(dd);
1374 if (ret)
1375 return ret;
1376 }
1377
1378 if (fw_8051_load) {
1379 do {
1380 ret = load_8051_firmware(dd, &fw_8051);
1381 } while (retry_firmware(dd, ret));
1382 if (ret)
1383 return ret;
1384 }
1385
1386 return 0;
1387 }
1388
1389 int hfi1_firmware_init(struct hfi1_devdata *dd)
1390 {
1391 /* only RTL can use these */
1392 if (dd->icode != ICODE_RTL_SILICON) {
1393 fw_fabric_serdes_load = 0;
1394 fw_pcie_serdes_load = 0;
1395 fw_sbus_load = 0;
1396 }
1397
1398 /* no 8051 or QSFP on simulator */
1399 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR) {
1400 fw_8051_load = 0;
1401 platform_config_load = 0;
1402 }
1403
1404 if (!fw_8051_name) {
1405 if (dd->icode == ICODE_RTL_SILICON)
1406 fw_8051_name = DEFAULT_FW_8051_NAME_ASIC;
1407 else
1408 fw_8051_name = DEFAULT_FW_8051_NAME_FPGA;
1409 }
1410 if (!fw_fabric_serdes_name)
1411 fw_fabric_serdes_name = DEFAULT_FW_FABRIC_NAME;
1412 if (!fw_sbus_name)
1413 fw_sbus_name = DEFAULT_FW_SBUS_NAME;
1414 if (!fw_pcie_serdes_name)
1415 fw_pcie_serdes_name = DEFAULT_FW_PCIE_NAME;
1416 if (!platform_config_name)
1417 platform_config_name = DEFAULT_PLATFORM_CONFIG_NAME;
1418
1419 return obtain_firmware(dd);
1420 }
1421
1422 int parse_platform_config(struct hfi1_devdata *dd)
1423 {
1424 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1425 u32 *ptr = NULL;
1426 u32 header1 = 0, header2 = 0, magic_num = 0, crc = 0;
1427 u32 record_idx = 0, table_type = 0, table_length_dwords = 0;
1428
1429 if (platform_config == NULL) {
1430 dd_dev_info(dd, "%s: Missing config file\n", __func__);
1431 goto bail;
1432 }
1433 ptr = (u32 *)platform_config->data;
1434
1435 magic_num = *ptr;
1436 ptr++;
1437 if (magic_num != PLATFORM_CONFIG_MAGIC_NUM) {
1438 dd_dev_info(dd, "%s: Bad config file\n", __func__);
1439 goto bail;
1440 }
1441
1442 while (ptr < (u32 *)(platform_config->data + platform_config->size)) {
1443 header1 = *ptr;
1444 header2 = *(ptr + 1);
1445 if (header1 != ~header2) {
1446 dd_dev_info(dd, "%s: Failed validation at offset %ld\n",
1447 __func__, (ptr - (u32 *)platform_config->data));
1448 goto bail;
1449 }
1450
1451 record_idx = *ptr &
1452 ((1 << PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS) - 1);
1453
1454 table_length_dwords = (*ptr >>
1455 PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT) &
1456 ((1 << PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS) - 1);
1457
1458 table_type = (*ptr >> PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT) &
1459 ((1 << PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS) - 1);
1460
1461 /* Done with this set of headers */
1462 ptr += 2;
1463
1464 if (record_idx) {
1465 /* data table */
1466 switch (table_type) {
1467 case PLATFORM_CONFIG_SYSTEM_TABLE:
1468 pcfgcache->config_tables[table_type].num_table =
1469 1;
1470 break;
1471 case PLATFORM_CONFIG_PORT_TABLE:
1472 pcfgcache->config_tables[table_type].num_table =
1473 2;
1474 break;
1475 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1476 /* fall through */
1477 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1478 /* fall through */
1479 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1480 /* fall through */
1481 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1482 pcfgcache->config_tables[table_type].num_table =
1483 table_length_dwords;
1484 break;
1485 default:
1486 dd_dev_info(dd,
1487 "%s: Unknown data table %d, offset %ld\n",
1488 __func__, table_type,
1489 (ptr - (u32 *)platform_config->data));
1490 goto bail; /* We don't trust this file now */
1491 }
1492 pcfgcache->config_tables[table_type].table = ptr;
1493 } else {
1494 /* metadata table */
1495 switch (table_type) {
1496 case PLATFORM_CONFIG_SYSTEM_TABLE:
1497 /* fall through */
1498 case PLATFORM_CONFIG_PORT_TABLE:
1499 /* fall through */
1500 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1501 /* fall through */
1502 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1503 /* fall through */
1504 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1505 /* fall through */
1506 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1507 break;
1508 default:
1509 dd_dev_info(dd,
1510 "%s: Unknown metadata table %d, offset %ld\n",
1511 __func__, table_type,
1512 (ptr - (u32 *)platform_config->data));
1513 goto bail; /* We don't trust this file now */
1514 }
1515 pcfgcache->config_tables[table_type].table_metadata =
1516 ptr;
1517 }
1518
1519 /* Calculate and check table crc */
1520 crc = crc32_le(~(u32)0, (unsigned char const *)ptr,
1521 (table_length_dwords * 4));
1522 crc ^= ~(u32)0;
1523
1524 /* Jump the table */
1525 ptr += table_length_dwords;
1526 if (crc != *ptr) {
1527 dd_dev_info(dd, "%s: Failed CRC check at offset %ld\n",
1528 __func__, (ptr - (u32 *)platform_config->data));
1529 goto bail;
1530 }
1531 /* Jump the CRC DWORD */
1532 ptr++;
1533 }
1534
1535 pcfgcache->cache_valid = 1;
1536 return 0;
1537 bail:
1538 memset(pcfgcache, 0, sizeof(struct platform_config_cache));
1539 return -EINVAL;
1540 }
1541
1542 static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table,
1543 int field, u32 *field_len_bits, u32 *field_start_bits)
1544 {
1545 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1546 u32 *src_ptr = NULL;
1547
1548 if (!pcfgcache->cache_valid)
1549 return -EINVAL;
1550
1551 switch (table) {
1552 case PLATFORM_CONFIG_SYSTEM_TABLE:
1553 /* fall through */
1554 case PLATFORM_CONFIG_PORT_TABLE:
1555 /* fall through */
1556 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1557 /* fall through */
1558 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1559 /* fall through */
1560 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1561 /* fall through */
1562 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1563 if (field && field < platform_config_table_limits[table])
1564 src_ptr =
1565 pcfgcache->config_tables[table].table_metadata + field;
1566 break;
1567 default:
1568 dd_dev_info(dd, "%s: Unknown table\n", __func__);
1569 break;
1570 }
1571
1572 if (!src_ptr)
1573 return -EINVAL;
1574
1575 if (field_start_bits)
1576 *field_start_bits = *src_ptr &
1577 ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1);
1578
1579 if (field_len_bits)
1580 *field_len_bits = (*src_ptr >> METADATA_TABLE_FIELD_LEN_SHIFT)
1581 & ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1);
1582
1583 return 0;
1584 }
1585
1586 /* This is the central interface to getting data out of the platform config
1587 * file. It depends on parse_platform_config() having populated the
1588 * platform_config_cache in hfi1_devdata, and checks the cache_valid member to
1589 * validate the sanity of the cache.
1590 *
1591 * The non-obvious parameters:
1592 * @table_index: Acts as a look up key into which instance of the tables the
1593 * relevant field is fetched from.
1594 *
1595 * This applies to the data tables that have multiple instances. The port table
1596 * is an exception to this rule as each HFI only has one port and thus the
1597 * relevant table can be distinguished by hfi_id.
1598 *
1599 * @data: pointer to memory that will be populated with the field requested.
1600 * @len: length of memory pointed by @data in bytes.
1601 */
1602 int get_platform_config_field(struct hfi1_devdata *dd,
1603 enum platform_config_table_type_encoding table_type,
1604 int table_index, int field_index, u32 *data, u32 len)
1605 {
1606 int ret = 0, wlen = 0, seek = 0;
1607 u32 field_len_bits = 0, field_start_bits = 0, *src_ptr = NULL;
1608 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1609
1610 if (data)
1611 memset(data, 0, len);
1612 else
1613 return -EINVAL;
1614
1615 ret = get_platform_fw_field_metadata(dd, table_type, field_index,
1616 &field_len_bits, &field_start_bits);
1617 if (ret)
1618 return -EINVAL;
1619
1620 /* Convert length to bits */
1621 len *= 8;
1622
1623 /* Our metadata function checked cache_valid and field_index for us */
1624 switch (table_type) {
1625 case PLATFORM_CONFIG_SYSTEM_TABLE:
1626 src_ptr = pcfgcache->config_tables[table_type].table;
1627
1628 if (field_index != SYSTEM_TABLE_QSFP_POWER_CLASS_MAX) {
1629 if (len < field_len_bits)
1630 return -EINVAL;
1631
1632 seek = field_start_bits/8;
1633 wlen = field_len_bits/8;
1634
1635 src_ptr = (u32 *)((u8 *)src_ptr + seek);
1636
1637 /* We expect the field to be byte aligned and whole byte
1638 * lengths if we are here */
1639 memcpy(data, src_ptr, wlen);
1640 return 0;
1641 }
1642 break;
1643 case PLATFORM_CONFIG_PORT_TABLE:
1644 /* Port table is 4 DWORDS in META_VERSION 0 */
1645 src_ptr = dd->hfi1_id ?
1646 pcfgcache->config_tables[table_type].table + 4 :
1647 pcfgcache->config_tables[table_type].table;
1648 break;
1649 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1650 /* fall through */
1651 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1652 /* fall through */
1653 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1654 /* fall through */
1655 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1656 src_ptr = pcfgcache->config_tables[table_type].table;
1657
1658 if (table_index <
1659 pcfgcache->config_tables[table_type].num_table)
1660 src_ptr += table_index;
1661 else
1662 src_ptr = NULL;
1663 break;
1664 default:
1665 dd_dev_info(dd, "%s: Unknown table\n", __func__);
1666 break;
1667 }
1668
1669 if (!src_ptr || len < field_len_bits)
1670 return -EINVAL;
1671
1672 src_ptr += (field_start_bits/32);
1673 *data = (*src_ptr >> (field_start_bits % 32)) &
1674 ((1 << field_len_bits) - 1);
1675
1676 return 0;
1677 }
1678
1679 /*
1680 * Download the firmware needed for the Gen3 PCIe SerDes. An update
1681 * to the SBus firmware is needed before updating the PCIe firmware.
1682 *
1683 * Note: caller must be holding the HW mutex.
1684 */
1685 int load_pcie_firmware(struct hfi1_devdata *dd)
1686 {
1687 int ret = 0;
1688
1689 /* both firmware loads below use the SBus */
1690 set_sbus_fast_mode(dd);
1691
1692 if (fw_sbus_load) {
1693 turn_off_spicos(dd, SPICO_SBUS);
1694 do {
1695 ret = load_sbus_firmware(dd, &fw_sbus);
1696 } while (retry_firmware(dd, ret));
1697 if (ret)
1698 goto done;
1699 }
1700
1701 if (fw_pcie_serdes_load) {
1702 dd_dev_info(dd, "Setting PCIe SerDes broadcast\n");
1703 set_serdes_broadcast(dd, all_pcie_serdes_broadcast,
1704 pcie_serdes_broadcast[dd->hfi1_id],
1705 pcie_serdes_addrs[dd->hfi1_id],
1706 NUM_PCIE_SERDES);
1707 do {
1708 ret = load_pcie_serdes_firmware(dd, &fw_pcie);
1709 } while (retry_firmware(dd, ret));
1710 if (ret)
1711 goto done;
1712 }
1713
1714 done:
1715 clear_sbus_fast_mode(dd);
1716
1717 return ret;
1718 }
1719
1720 /*
1721 * Read the GUID from the hardware, store it in dd.
1722 */
1723 void read_guid(struct hfi1_devdata *dd)
1724 {
1725 /* Take the DC out of reset to get a valid GUID value */
1726 write_csr(dd, CCE_DC_CTRL, 0);
1727 (void) read_csr(dd, CCE_DC_CTRL);
1728
1729 dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID);
1730 dd_dev_info(dd, "GUID %llx",
1731 (unsigned long long)dd->base_guid);
1732 }
Linux kernel - Deliverables
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