1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __INC_HAL8188EPHYCFG_H__
21 #define __INC_HAL8188EPHYCFG_H__
24 /*--------------------------Define Parameters-------------------------------*/
26 #define MAX_STALL_TIME 50 /* us */
27 #define AntennaDiversityValue 0x80
28 #define MAX_TXPWR_IDX_NMODE_92S 63
29 #define Reset_Cnt_Limit 3
31 #define IQK_MAC_REG_NUM 4
32 #define IQK_ADDA_REG_NUM 16
33 #define IQK_BB_REG_NUM 9
34 #define HP_THERMAL_NUM 8
36 #define MAX_AGGR_NUM 0x07
39 /*--------------------------Define Parameters-------------------------------*/
42 /*------------------------------Define structure----------------------------*/
45 CmdID_SetTxPowerLevel
,
48 CmdID_WritePortUshort
,
53 /* 1. Switch channel related */
55 enum sw_chnl_cmd_id CmdID
;
66 HW90_BLOCK_MAXIMUM
= 4, /* Never use this */
70 RF_PATH_A
= 0, /* Radio Path A */
71 RF_PATH_B
= 1, /* Radio Path B */
74 #define MAX_PG_GROUP 13
77 #define MAX_RF_PATH RF_PATH_MAX
78 #define MAX_TX_COUNT 4 /* path numbers */
80 #define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */
81 #define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8,
82 *ch9~11, ch12~13, CH 14
83 * total three groups */
84 #define CHANNEL_GROUP_MAX_88E 6
87 WIRELESS_MODE_UNKNOWN
= 0x00,
88 WIRELESS_MODE_A
= BIT(2),
89 WIRELESS_MODE_B
= BIT(0),
90 WIRELESS_MODE_G
= BIT(1),
91 WIRELESS_MODE_AUTO
= BIT(5),
92 WIRELESS_MODE_N_24G
= BIT(3),
93 WIRELESS_MODE_N_5G
= BIT(4),
94 WIRELESS_MODE_AC
= BIT(6)
97 enum phy_rate_tx_offset_area
{
98 RA_OFFSET_LEGACY_OFDM1
,
99 RA_OFFSET_LEGACY_OFDM2
,
110 RF_8225
= 1, /* 1 11b/g RF for verification only */
111 RF_8256
= 2, /* 2 11b/g/n */
112 RF_8258
= 3, /* 3 11a/b/g/n RF */
113 RF_6052
= 4, /* 4 11b/g/n RF */
114 /* TODO: We should remove this psudo PHY RF after we get new RF. */
115 RF_PSEUDO_11N
= 5, /* 5, It is a temporality RF. */
119 u32 rfintfs
; /* set software control: */
120 /* 0x870~0x877[8 bytes] */
121 u32 rfintfi
; /* readback data: */
122 /* 0x8e0~0x8e7[8 bytes] */
123 u32 rfintfo
; /* output data: */
124 /* 0x860~0x86f [16 bytes] */
125 u32 rfintfe
; /* output enable: */
126 /* 0x860~0x86f [16 bytes] */
127 u32 rf3wireOffset
; /* LSSI data: */
128 /* 0x840~0x84f [16 bytes] */
129 u32 rfLSSI_Select
; /* BB Band Select: */
130 /* 0x878~0x87f [8 bytes] */
131 u32 rfTxGainStage
; /* Tx gain stage: */
132 /* 0x80c~0x80f [4 bytes] */
133 u32 rfHSSIPara1
; /* wire parameter control1 : */
134 /* 0x820~0x823,0x828~0x82b,
135 * 0x830~0x833, 0x838~0x83b [16 bytes] */
136 u32 rfHSSIPara2
; /* wire parameter control2 : */
137 /* 0x824~0x827,0x82c~0x82f, 0x834~0x837,
138 * 0x83c~0x83f [16 bytes] */
139 u32 rfSwitchControl
; /* Tx Rx antenna control : */
140 /* 0x858~0x85f [16 bytes] */
141 u32 rfAGCControl1
; /* AGC parameter control1 : */
142 /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
143 * 0xc68~0xc6b [16 bytes] */
144 u32 rfAGCControl2
; /* AGC parameter control2 : */
145 /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
146 * 0xc6c~0xc6f [16 bytes] */
147 u32 rfRxIQImbalance
; /* OFDM Rx IQ imbalance matrix : */
148 /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
149 * 0xc2c~0xc2f [16 bytes] */
150 u32 rfRxAFE
; /* Rx IQ DC ofset and Rx digital filter,
151 * Rx DC notch filter : */
152 /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
153 * 0xc28~0xc2b [16 bytes] */
154 u32 rfTxIQImbalance
; /* OFDM Tx IQ imbalance matrix */
155 /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
156 * 0xc98~0xc9b [16 bytes] */
157 u32 rfTxAFE
; /* Tx IQ DC Offset and Tx DFIR type */
158 /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
159 * 0xc9c~0xc9f [16 bytes] */
160 u32 rfLSSIReadBack
; /* LSSI RF readback data SI mode */
161 /* 0x8a0~0x8af [16 bytes] */
162 u32 rfLSSIReadBackPi
; /* LSSI RF readback data PI mode 0x8b8-8bc for
166 struct ant_sel_ofdm
{
173 u32 r_ant_non_ht_s1
:4;
179 u8 r_cckrx_enable_2
:2;
184 /*------------------------------Define structure----------------------------*/
187 /*------------------------Export global variable----------------------------*/
188 /*------------------------Export global variable----------------------------*/
191 /*------------------------Export Marco Definition---------------------------*/
192 /*------------------------Export Marco Definition---------------------------*/
195 /*--------------------------Exported Function prototype---------------------*/
197 /* BB and RF register read/write */
200 /* Read initi reg value for tx power setting. */
201 void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter
*adapter
);
203 /* BB TX Power R/W */
204 void PHY_GetTxPowerLevel8188E(struct adapter
*adapter
, u32
*powerlevel
);
206 void PHY_ScanOperationBackup8188E(struct adapter
*Adapter
, u8 Operation
);
208 /* Call after initialization */
209 void ChkFwCmdIoDone(struct adapter
*adapter
);
211 /* BB/MAC/RF other monitor API */
212 void PHY_SetRFPathSwitch_8188E(struct adapter
*adapter
, bool main
);
214 void PHY_SwitchEphyParameter(struct adapter
*adapter
);
216 void PHY_EnableHostClkReq(struct adapter
*adapter
);
218 bool SetAntennaConfig92C(struct adapter
*adapter
, u8 defaultant
);
220 /*--------------------------Exported Function prototype---------------------*/
222 #define PHY_SetMacReg PHY_SetBBReg
224 #define SIC_HW_SUPPORT 0
226 #define SIC_MAX_POLL_CNT 5
228 #define SIC_CMD_READY 0
229 #define SIC_CMD_WRITE 1
230 #define SIC_CMD_READ 2
232 #define SIC_CMD_REG 0x1EB /* 1byte */
233 #define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
234 #define SIC_DATA_REG 0x1EC /* 1bc~1bf */
236 #endif /* __INC_HAL8192CPHYCFG_H */
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