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[deliverable/linux.git] / drivers / staging / rtl8192e / r8192E.h
1 /*
2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
8
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
13
14 We want to tanks the Authors of those projects and the Ndiswrapper
15 project Authors.
16 */
17
18 #ifndef R819xU_H
19 #define R819xU_H
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 //#include <linux/config.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/netdevice.h>
30 #include <linux/pci.h>
31 //#include <linux/usb.h>
32 #include <linux/etherdevice.h>
33 #include <linux/delay.h>
34 #include <linux/rtnetlink.h> //for rtnl_lock()
35 #include <linux/wireless.h>
36 #include <linux/timer.h>
37 #include <linux/proc_fs.h> // Necessary because we use the proc fs
38 #include <linux/if_arp.h>
39 #include <linux/random.h>
40 #include <linux/version.h>
41 #include <asm/io.h>
42 #include "ieee80211/ieee80211.h"
43
44
45
46
47 #define RTL819xE_MODULE_NAME "rtl819xE"
48 //added for HW security, john.0629
49 #define FALSE 0
50 #define TRUE 1
51 #define MAX_KEY_LEN 61
52 #define KEY_BUF_SIZE 5
53
54 #define BIT0 0x00000001
55 #define BIT1 0x00000002
56 #define BIT2 0x00000004
57 #define BIT3 0x00000008
58 #define BIT4 0x00000010
59 #define BIT5 0x00000020
60 #define BIT6 0x00000040
61 #define BIT7 0x00000080
62 #define BIT8 0x00000100
63 #define BIT9 0x00000200
64 #define BIT10 0x00000400
65 #define BIT11 0x00000800
66 #define BIT12 0x00001000
67 #define BIT13 0x00002000
68 #define BIT14 0x00004000
69 #define BIT15 0x00008000
70 #define BIT16 0x00010000
71 #define BIT17 0x00020000
72 #define BIT18 0x00040000
73 #define BIT19 0x00080000
74 #define BIT20 0x00100000
75 #define BIT21 0x00200000
76 #define BIT22 0x00400000
77 #define BIT23 0x00800000
78 #define BIT24 0x01000000
79 #define BIT25 0x02000000
80 #define BIT26 0x04000000
81 #define BIT27 0x08000000
82 #define BIT28 0x10000000
83 #define BIT29 0x20000000
84 #define BIT30 0x40000000
85 #define BIT31 0x80000000
86 // Rx smooth factor
87 #define Rx_Smooth_Factor 20
88 /* 2007/06/04 MH Define sliding window for RSSI history. */
89 #define PHY_RSSI_SLID_WIN_MAX 100
90 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
91
92 #define IC_VersionCut_D 0x3
93 #define IC_VersionCut_E 0x4
94
95 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
96 #define DMESG(x,a...) printk(KERN_INFO RTL819xE_MODULE_NAME ": " x "\n", ## a)
97 #else
98 #define DMESG(x,a...)
99 extern u32 rt_global_debug_component;
100 #define RT_TRACE(component, x, args...) \
101 do { if(rt_global_debug_component & component) \
102 printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x "\n" , \
103 ##args);\
104 }while(0);
105
106 #define COMP_TRACE BIT0 // For function call tracing.
107 #define COMP_DBG BIT1 // Only for temporary debug message.
108 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
109
110
111 #define COMP_RECV BIT3 // Reveive part data path.
112 #define COMP_SEND BIT4 // Send part path.
113 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
114 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
115 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
116 #define COMP_SWBW BIT8 // For bandwidth switch.
117 #define COMP_SEC BIT9// For Security.
118
119
120 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
121 #define COMP_QOS BIT11 // For QoS.
122
123 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
124 #define COMP_RXDESC BIT13 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
125 #define COMP_PHY BIT14
126 #define COMP_DIG BIT15 // For DIG, 2006.09.25, by rcnjko.
127 #define COMP_TXAGC BIT16 // For Tx power, 060928, by rcnjko.
128 #define COMP_HALDM BIT17 // For HW Dynamic Mechanism, 061010, by rcnjko.
129 #define COMP_POWER_TRACKING BIT18 //FOR 8190 TX POWER TRACKING
130 #define COMP_EVENTS BIT19 // Event handling
131
132 #define COMP_RF BIT20 // For RF.
133 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
134 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
135 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
136
137 #define COMP_FIRMWARE BIT21 //for firmware downloading
138 #define COMP_HT BIT22 // For 802.11n HT related information. by Emily 2006-8-11
139
140 #define COMP_RESET BIT23
141 #define COMP_CMDPKT BIT24
142 #define COMP_SCAN BIT25
143 #define COMP_IPS BIT26
144 #define COMP_DOWN BIT27 // for rm driver module
145 #define COMP_INTR BIT28 // for interrupt
146 #define COMP_ERR BIT31 // for error out, always on
147 #endif
148
149
150 //
151 // Queue Select Value in TxDesc
152 //
153 #define QSLT_BK 0x1
154 #define QSLT_BE 0x0
155 #define QSLT_VI 0x4
156 #define QSLT_VO 0x6
157 #define QSLT_BEACON 0x10
158 #define QSLT_HIGH 0x11
159 #define QSLT_MGNT 0x12
160 #define QSLT_CMD 0x13
161
162 #define DESC90_RATE1M 0x00
163 #define DESC90_RATE2M 0x01
164 #define DESC90_RATE5_5M 0x02
165 #define DESC90_RATE11M 0x03
166 #define DESC90_RATE6M 0x04
167 #define DESC90_RATE9M 0x05
168 #define DESC90_RATE12M 0x06
169 #define DESC90_RATE18M 0x07
170 #define DESC90_RATE24M 0x08
171 #define DESC90_RATE36M 0x09
172 #define DESC90_RATE48M 0x0a
173 #define DESC90_RATE54M 0x0b
174 #define DESC90_RATEMCS0 0x00
175 #define DESC90_RATEMCS1 0x01
176 #define DESC90_RATEMCS2 0x02
177 #define DESC90_RATEMCS3 0x03
178 #define DESC90_RATEMCS4 0x04
179 #define DESC90_RATEMCS5 0x05
180 #define DESC90_RATEMCS6 0x06
181 #define DESC90_RATEMCS7 0x07
182 #define DESC90_RATEMCS8 0x08
183 #define DESC90_RATEMCS9 0x09
184 #define DESC90_RATEMCS10 0x0a
185 #define DESC90_RATEMCS11 0x0b
186 #define DESC90_RATEMCS12 0x0c
187 #define DESC90_RATEMCS13 0x0d
188 #define DESC90_RATEMCS14 0x0e
189 #define DESC90_RATEMCS15 0x0f
190 #define DESC90_RATEMCS32 0x20
191
192 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
193 #define EEPROM_Default_LegacyHTTxPowerDiff 0x4
194 #define IEEE80211_WATCH_DOG_TIME 2000
195
196 /* For rtl819x */
197 typedef struct _tx_desc_819x_pci {
198 //DWORD 0
199 u16 PktSize;
200 u8 Offset;
201 u8 Reserved1:3;
202 u8 CmdInit:1;
203 u8 LastSeg:1;
204 u8 FirstSeg:1;
205 u8 LINIP:1;
206 u8 OWN:1;
207
208 //DWORD 1
209 u8 TxFWInfoSize;
210 u8 RATid:3;
211 u8 DISFB:1;
212 u8 USERATE:1;
213 u8 MOREFRAG:1;
214 u8 NoEnc:1;
215 u8 PIFS:1;
216 u8 QueueSelect:5;
217 u8 NoACM:1;
218 u8 Resv:2;
219 u8 SecCAMID:5;
220 u8 SecDescAssign:1;
221 u8 SecType:2;
222
223 //DWORD 2
224 u16 TxBufferSize;
225 u8 PktId:7;
226 u8 Resv1:1;
227 u8 Reserved2;
228
229 //DWORD 3
230 u32 TxBuffAddr;
231
232 //DWORD 4
233 u32 NextDescAddress;
234
235 //DWORD 5,6,7
236 u32 Reserved5;
237 u32 Reserved6;
238 u32 Reserved7;
239 }tx_desc_819x_pci, *ptx_desc_819x_pci;
240
241
242 typedef struct _tx_desc_cmd_819x_pci {
243 //DWORD 0
244 u16 PktSize;
245 u8 Reserved1;
246 u8 CmdType:3;
247 u8 CmdInit:1;
248 u8 LastSeg:1;
249 u8 FirstSeg:1;
250 u8 LINIP:1;
251 u8 OWN:1;
252
253 //DOWRD 1
254 u16 ElementReport;
255 u16 Reserved2;
256
257 //DOWRD 2
258 u16 TxBufferSize;
259 u16 Reserved3;
260
261 //DWORD 3,4,5
262 u32 TxBufferAddr;
263 u32 NextDescAddress;
264 u32 Reserved4;
265 u32 Reserved5;
266 u32 Reserved6;
267 }tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci;
268
269
270 typedef struct _tx_fwinfo_819x_pci {
271 //DOWRD 0
272 u8 TxRate:7;
273 u8 CtsEnable:1;
274 u8 RtsRate:7;
275 u8 RtsEnable:1;
276 u8 TxHT:1;
277 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
278 u8 TxBandwidth:1; // This is used for HT MCS rate only.
279 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
280 u8 STBC:2;
281 u8 AllowAggregation:1;
282 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
283 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
284 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
285 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
286 u8 RtsSTBC:2;
287 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
288
289 //DWORD 1
290 u8 RxMF:2;
291 u8 RxAMD:3;
292 u8 Reserved1:3;
293 u8 Reserved2;
294 u8 Reserved3;
295 u8 Reserved4;
296
297 //u32 Reserved;
298 }tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci;
299
300 typedef struct rtl8192_rx_info {
301 struct urb *urb;
302 struct net_device *dev;
303 u8 out_pipe;
304 }rtl8192_rx_info ;
305 typedef struct _rx_desc_819x_pci{
306 //DOWRD 0
307 u16 Length:14;
308 u16 CRC32:1;
309 u16 ICV:1;
310 u8 RxDrvInfoSize;
311 u8 Shift:2;
312 u8 PHYStatus:1;
313 u8 SWDec:1;
314 u8 LastSeg:1;
315 u8 FirstSeg:1;
316 u8 EOR:1;
317 u8 OWN:1;
318
319 //DWORD 1
320 u32 Reserved2;
321
322 //DWORD 2
323 u32 Reserved3;
324
325 //DWORD 3
326 u32 BufferAddress;
327
328 }rx_desc_819x_pci, *prx_desc_819x_pci;
329
330 typedef struct _rx_fwinfo_819x_pci{
331 //DWORD 0
332 u16 Reserved1:12;
333 u16 PartAggr:1;
334 u16 FirstAGGR:1;
335 u16 Reserved2:2;
336
337 u8 RxRate:7;
338 u8 RxHT:1;
339
340 u8 BW:1;
341 u8 SPLCP:1;
342 u8 Reserved3:2;
343 u8 PAM:1;
344 u8 Mcast:1;
345 u8 Bcast:1;
346 u8 Reserved4:1;
347
348 //DWORD 1
349 u32 TSFL;
350
351 }rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci;
352
353 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
354 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
355 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
356 #define ENCRYPTION_MAX_OVERHEAD 128
357 //#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
358 //#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
359 #define MAX_FRAGMENT_COUNT 8
360 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
361
362 #define scrclng 4 // octets for crc32 (FCS, ICV)
363 /* 8190 Loopback Mode definition */
364 typedef enum _rtl819x_loopback{
365 RTL819X_NO_LOOPBACK = 0,
366 RTL819X_MAC_LOOPBACK = 1,
367 RTL819X_DMA_LOOPBACK = 2,
368 RTL819X_CCK_LOOPBACK = 3,
369 }rtl819x_loopback_e;
370
371 /* due to rtl8192 firmware */
372 typedef enum _desc_packet_type_e{
373 DESC_PACKET_TYPE_INIT = 0,
374 DESC_PACKET_TYPE_NORMAL = 1,
375 }desc_packet_type_e;
376
377 typedef enum _firmware_source{
378 FW_SOURCE_IMG_FILE = 0,
379 FW_SOURCE_HEADER_FILE = 1, //from header file
380 }firmware_source_e, *pfirmware_source_e;
381
382 typedef enum _firmware_status{
383 FW_STATUS_0_INIT = 0,
384 FW_STATUS_1_MOVE_BOOT_CODE = 1,
385 FW_STATUS_2_MOVE_MAIN_CODE = 2,
386 FW_STATUS_3_TURNON_CPU = 3,
387 FW_STATUS_4_MOVE_DATA_CODE = 4,
388 FW_STATUS_5_READY = 5,
389 }firmware_status_e;
390
391 typedef struct _rt_firmare_seg_container {
392 u16 seg_size;
393 u8 *seg_ptr;
394 }fw_seg_container, *pfw_seg_container;
395
396 typedef struct _rt_firmware{
397 firmware_status_e firmware_status;
398 u16 cmdpacket_frag_thresold;
399 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
400 #define MAX_FW_INIT_STEP 3
401 u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
402 u16 firmware_buf_size[MAX_FW_INIT_STEP];
403 }rt_firmware, *prt_firmware;
404 //+by amy 080507
405 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
406
407 /* Firmware Queue Layout */
408 #define NUM_OF_FIRMWARE_QUEUE 10
409 #define NUM_OF_PAGES_IN_FW 0x100
410 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
411 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
412 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
413 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
414 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
415 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x2
416 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
417 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
418 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
419 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
420 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
421 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
422 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
423 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
424 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
425 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
426 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
427 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
428 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
429
430 //8187B Security
431 //#define RWCAM 0xA0 // Software read/write CAM config
432 //#define WCAMI 0xA4 // Software write CAM input content
433 //#define RCAMO 0xA8 // Output value from CAM according to 0xa0 setting
434 #define DCAM 0xAC // Debug CAM Interface
435 #define AESMSK_FC 0xB2 // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06.
436
437
438 #define CAM_CONTENT_COUNT 8
439 //#define CFG_DEFAULT_KEY BIT5
440 #define CFG_VALID BIT15
441 #if 0
442 //----------------------------------------------------------------------------
443 // 8187B WPA Config Register (offset 0xb0, 1 byte)
444 //----------------------------------------------------------------------------
445 #define SCR_UseDK 0x01
446 #define SCR_TxSecEnable 0x02
447 #define SCR_RxSecEnable 0x04
448
449 //----------------------------------------------------------------------------
450 // 8187B CAM Config Setting (offset 0xb0, 1 byte)
451 //----------------------------------------------------------------------------
452 #define CAM_VALID 0x8000
453 #define CAM_NOTVALID 0x0000
454 #define CAM_USEDK 0x0020
455
456
457 #define CAM_NONE 0x0
458 #define CAM_WEP40 0x01
459 #define CAM_TKIP 0x02
460 #define CAM_AES 0x04
461 #define CAM_WEP104 0x05
462
463 //#define CAM_SIZE 16
464 #define TOTAL_CAM_ENTRY 16
465 #define CAM_ENTRY_LEN_IN_DW 6 // 6, unit: in u4byte. Added by Annie, 2006-05-25.
466 #define CAM_ENTRY_LEN_IN_BYTE (CAM_ENTRY_LEN_IN_DW*sizeof(u32)) // 24, unit: in u1byte. Added by Annie, 2006-05-25.
467
468 #define CAM_CONFIG_USEDK 1
469 #define CAM_CONFIG_NO_USEDK 0
470
471 #define CAM_WRITE 0x00010000
472 #define CAM_READ 0x00000000
473 #define CAM_POLLINIG 0x80000000
474
475 //=================================================================
476 //=================================================================
477
478 #endif
479 #define EPROM_93c46 0
480 #define EPROM_93c56 1
481
482 #define DEFAULT_FRAG_THRESHOLD 2342U
483 #define MIN_FRAG_THRESHOLD 256U
484 #define DEFAULT_BEACONINTERVAL 0x64U
485 #define DEFAULT_BEACON_ESSID "Rtl819xU"
486
487 #define DEFAULT_SSID ""
488 #define DEFAULT_RETRY_RTS 7
489 #define DEFAULT_RETRY_DATA 7
490 #define PRISM_HDR_SIZE 64
491
492 #define PHY_RSSI_SLID_WIN_MAX 100
493
494
495 typedef enum _WIRELESS_MODE {
496 WIRELESS_MODE_UNKNOWN = 0x00,
497 WIRELESS_MODE_A = 0x01,
498 WIRELESS_MODE_B = 0x02,
499 WIRELESS_MODE_G = 0x04,
500 WIRELESS_MODE_AUTO = 0x08,
501 WIRELESS_MODE_N_24G = 0x10,
502 WIRELESS_MODE_N_5G = 0x20
503 } WIRELESS_MODE;
504
505 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
506
507 typedef struct buffer
508 {
509 struct buffer *next;
510 u32 *buf;
511 dma_addr_t dma;
512
513 } buffer;
514
515 typedef struct rtl_reg_debug{
516 unsigned int cmd;
517 struct {
518 unsigned char type;
519 unsigned char addr;
520 unsigned char page;
521 unsigned char length;
522 } head;
523 unsigned char buf[0xff];
524 }rtl_reg_debug;
525
526 #if 0
527
528 typedef struct tx_pendingbuf
529 {
530 struct ieee80211_txb *txb;
531 short ispending;
532 short descfrag;
533 } tx_pendigbuf;
534
535 #endif
536
537 typedef struct _rt_9x_tx_rate_history {
538 u32 cck[4];
539 u32 ofdm[8];
540 // HT_MCS[0][]: BW=0 SG=0
541 // HT_MCS[1][]: BW=1 SG=0
542 // HT_MCS[2][]: BW=0 SG=1
543 // HT_MCS[3][]: BW=1 SG=1
544 u32 ht_mcs[4][16];
545 }rt_tx_rahis_t, *prt_tx_rahis_t;
546
547 typedef struct _RT_SMOOTH_DATA_4RF {
548 char elements[4][100];//array to store values
549 u32 index; //index to current array to store
550 u32 TotalNum; //num of valid elements
551 u32 TotalVal[4]; //sum of valid elements
552 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
553
554 typedef enum _tag_TxCmd_Config_Index{
555 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
556 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
557 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
558 TXCMD_SET_TX_DURATION = 0xFF900003,
559 TXCMD_SET_RX_RSSI = 0xFF900004,
560 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
561 TXCMD_XXXX_CTRL,
562 }DCMD_TXCMD_OP;
563
564 typedef struct Stats
565 {
566 unsigned long txrdu;
567 unsigned long rxrdu;
568 //unsigned long rxnolast;
569 //unsigned long rxnodata;
570 // unsigned long rxreset;
571 // unsigned long rxnopointer;
572 unsigned long rxok;
573 unsigned long rxframgment;
574 unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
575 unsigned long rxurberr;
576 unsigned long rxstaterr;
577 unsigned long rxcrcerrmin;//crc error (0-500)
578 unsigned long rxcrcerrmid;//crc error (500-1000)
579 unsigned long rxcrcerrmax;//crc error (>1000)
580 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
581 unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
582 unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
583 unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
584 unsigned long numpacket_matchbssid; // debug use only.
585 unsigned long numpacket_toself; // debug use only.
586 unsigned long num_process_phyinfo; // debug use only.
587 unsigned long numqry_phystatus;
588 unsigned long numqry_phystatusCCK;
589 unsigned long numqry_phystatusHT;
590 unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
591 unsigned long txnperr;
592 unsigned long txnpdrop;
593 unsigned long txresumed;
594 // unsigned long rxerr;
595 unsigned long rxoverflow;
596 unsigned long rxint;
597 unsigned long txnpokint;
598 // unsigned long txhpokint;
599 // unsigned long txhperr;
600 unsigned long ints;
601 unsigned long shints;
602 unsigned long txoverflow;
603 // unsigned long rxdmafail;
604 // unsigned long txbeacon;
605 // unsigned long txbeaconerr;
606 unsigned long txlpokint;
607 unsigned long txlpdrop;
608 unsigned long txlperr;
609 unsigned long txbeokint;
610 unsigned long txbedrop;
611 unsigned long txbeerr;
612 unsigned long txbkokint;
613 unsigned long txbkdrop;
614 unsigned long txbkerr;
615 unsigned long txviokint;
616 unsigned long txvidrop;
617 unsigned long txvierr;
618 unsigned long txvookint;
619 unsigned long txvodrop;
620 unsigned long txvoerr;
621 unsigned long txbeaconokint;
622 unsigned long txbeacondrop;
623 unsigned long txbeaconerr;
624 unsigned long txmanageokint;
625 unsigned long txmanagedrop;
626 unsigned long txmanageerr;
627 unsigned long txcmdpktokint;
628 unsigned long txdatapkt;
629 unsigned long txfeedback;
630 unsigned long txfeedbackok;
631 unsigned long txoktotal;
632 unsigned long txokbytestotal;
633 unsigned long txokinperiod;
634 unsigned long txmulticast;
635 unsigned long txbytesmulticast;
636 unsigned long txbroadcast;
637 unsigned long txbytesbroadcast;
638 unsigned long txunicast;
639 unsigned long txbytesunicast;
640 unsigned long rxbytesunicast;
641 unsigned long txfeedbackfail;
642 unsigned long txerrtotal;
643 unsigned long txerrbytestotal;
644 unsigned long txerrmulticast;
645 unsigned long txerrbroadcast;
646 unsigned long txerrunicast;
647 unsigned long txretrycount;
648 unsigned long txfeedbackretry;
649 u8 last_packet_rate;
650 unsigned long slide_signal_strength[100];
651 unsigned long slide_evm[100];
652 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
653 unsigned long slide_evm_total; // For recording sliding window's EVM value
654 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
655 long signal_quality;
656 long last_signal_strength_inpercent;
657 long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
658 u8 rx_rssi_percentage[4];
659 u8 rx_evm_percentage[2];
660 long rxSNRdB[4];
661 rt_tx_rahis_t txrate;
662 u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
663 u32 Slide_Beacon_Total; //cosa add for beacon rssi
664 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
665 u32 CurrentShowTxate;
666
667
668 } Stats;
669
670
671 // Bandwidth Offset
672 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
673 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
674 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
675
676 //+by amy 080507
677
678 typedef struct ChnlAccessSetting {
679 u16 SIFS_Timer;
680 u16 DIFS_Timer;
681 u16 SlotTimeTimer;
682 u16 EIFS_Timer;
683 u16 CWminIndex;
684 u16 CWmaxIndex;
685 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
686
687 typedef struct _BB_REGISTER_DEFINITION{
688 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
689 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
690 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
691 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
692 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
693 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
694 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
695 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
696 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
697 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
698 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
699 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
700 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
701 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
702 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
703 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
704 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
705 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
706
707 typedef enum _RT_RF_TYPE_819xU{
708 RF_TYPE_MIN = 0,
709 RF_8225,
710 RF_8256,
711 RF_8258,
712 RF_PSEUDO_11N = 4,
713 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
714
715
716 typedef struct _rate_adaptive
717 {
718 u8 rate_adaptive_disabled;
719 u8 ratr_state;
720 u16 reserve;
721
722 u32 high_rssi_thresh_for_ra;
723 u32 high2low_rssi_thresh_for_ra;
724 u8 low2high_rssi_thresh_for_ra40M;
725 u32 low_rssi_thresh_for_ra40M;
726 u8 low2high_rssi_thresh_for_ra20M;
727 u32 low_rssi_thresh_for_ra20M;
728 u32 upper_rssi_threshold_ratr;
729 u32 middle_rssi_threshold_ratr;
730 u32 low_rssi_threshold_ratr;
731 u32 low_rssi_threshold_ratr_40M;
732 u32 low_rssi_threshold_ratr_20M;
733 u8 ping_rssi_enable; //cosa add for test
734 u32 ping_rssi_ratr; //cosa add for test
735 u32 ping_rssi_thresh_for_ra;//cosa add for test
736 u32 last_ratr;
737
738 } rate_adaptive, *prate_adaptive;
739 #define TxBBGainTableLength 37
740 #define CCKTxBBGainTableLength 23
741 typedef struct _txbbgain_struct
742 {
743 long txbb_iq_amplifygain;
744 u32 txbbgain_value;
745 } txbbgain_struct, *ptxbbgain_struct;
746
747 typedef struct _ccktxbbgain_struct
748 {
749 //The Value is from a22 to a29 one Byte one time is much Safer
750 u8 ccktxbb_valuearray[8];
751 } ccktxbbgain_struct,*pccktxbbgain_struct;
752
753
754 typedef struct _init_gain
755 {
756 u8 xaagccore1;
757 u8 xbagccore1;
758 u8 xcagccore1;
759 u8 xdagccore1;
760 u8 cca;
761
762 } init_gain, *pinit_gain;
763
764 /* 2007/11/02 MH Define RF mode temporarily for test. */
765 typedef enum tag_Rf_Operatetion_State
766 {
767 RF_STEP_INIT = 0,
768 RF_STEP_NORMAL,
769 RF_STEP_MAX
770 }RF_STEP_E;
771
772 typedef enum _RT_STATUS{
773 RT_STATUS_SUCCESS,
774 RT_STATUS_FAILURE,
775 RT_STATUS_PENDING,
776 RT_STATUS_RESOURCE
777 }RT_STATUS,*PRT_STATUS;
778
779 typedef enum _RT_CUSTOMER_ID
780 {
781 RT_CID_DEFAULT = 0,
782 RT_CID_8187_ALPHA0 = 1,
783 RT_CID_8187_SERCOMM_PS = 2,
784 RT_CID_8187_HW_LED = 3,
785 RT_CID_8187_NETGEAR = 4,
786 RT_CID_WHQL = 5,
787 RT_CID_819x_CAMEO = 6,
788 RT_CID_819x_RUNTOP = 7,
789 RT_CID_819x_Senao = 8,
790 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
791 RT_CID_819x_Netcore = 10,
792 RT_CID_Nettronix = 11,
793 RT_CID_DLINK = 12,
794 RT_CID_PRONET = 13,
795 RT_CID_COREGA = 14,
796 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
797
798 //================================================================================
799 // LED customization.
800 //================================================================================
801
802 typedef enum _LED_STRATEGY_8190{
803 SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
804 SW_LED_MODE1, // SW control for PCI Express
805 SW_LED_MODE2, // SW control for Cameo.
806 SW_LED_MODE3, // SW contorl for RunTop.
807 SW_LED_MODE4, // SW control for Netcore
808 SW_LED_MODE5, //added by vivi, for led new mode, DLINK
809 SW_LED_MODE6, //added by vivi, for led new mode, PRONET
810 HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
811 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
812
813 #define CHANNEL_PLAN_LEN 10
814
815 #define sCrcLng 4
816
817 typedef struct _TX_FWINFO_STRUCUTRE{
818 //DOWRD 0
819 u8 TxRate:7;
820 u8 CtsEnable:1;
821 u8 RtsRate:7;
822 u8 RtsEnable:1;
823 u8 TxHT:1;
824 u8 Short:1;
825 u8 TxBandwidth:1;
826 u8 TxSubCarrier:2;
827 u8 STBC:2;
828 u8 AllowAggregation:1;
829 u8 RtsHT:1;
830 u8 RtsShort:1;
831 u8 RtsBandwidth:1;
832 u8 RtsSubcarrier:2;
833 u8 RtsSTBC:2;
834 u8 EnableCPUDur:1;
835
836 //DWORD 1
837 u32 RxMF:2;
838 u32 RxAMD:3;
839 u32 Reserved1:3;
840 u32 TxAGCOffset:4;
841 u32 TxAGCSign:1;
842 u32 Tx_INFO_RSVD:6;
843 u32 PacketID:13;
844 }TX_FWINFO_T;
845
846
847 typedef struct _TX_FWINFO_8190PCI{
848 //DOWRD 0
849 u8 TxRate:7;
850 u8 CtsEnable:1;
851 u8 RtsRate:7;
852 u8 RtsEnable:1;
853 u8 TxHT:1;
854 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
855 u8 TxBandwidth:1; // This is used for HT MCS rate only.
856 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
857 u8 STBC:2;
858 u8 AllowAggregation:1;
859 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
860 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
861 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
862 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
863 u8 RtsSTBC:2;
864 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
865
866 //DWORD 1
867 u32 RxMF:2;
868 u32 RxAMD:3;
869 u32 TxPerPktInfoFeedback:1; // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd.
870 u32 Reserved1:2;
871 u32 TxAGCOffset:4; // Only 90 support
872 u32 TxAGCSign:1; // Only 90 support
873 u32 RAW_TXD:1; // MAC will send data in txpktbuffer without any processing,such as CRC check
874 u32 Retry_Limit:4; // CCX Support relative retry limit FW page only support 4 bits now.
875 u32 Reserved2:1;
876 u32 PacketID:13;
877
878 // DW 2
879
880 }TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
881
882 typedef struct _phy_ofdm_rx_status_report_819xpci
883 {
884 u8 trsw_gain_X[4];
885 u8 pwdb_all;
886 u8 cfosho_X[4];
887 u8 cfotail_X[4];
888 u8 rxevm_X[2];
889 u8 rxsnr_X[4];
890 u8 pdsnr_X[2];
891 u8 csi_current_X[2];
892 u8 csi_target_X[2];
893 u8 sigevm;
894 u8 max_ex_pwr;
895 u8 sgi_en;
896 u8 rxsc_sgien_exflg;
897 }phy_sts_ofdm_819xpci_t;
898
899 typedef struct _phy_cck_rx_status_report_819xpci
900 {
901 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
902 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
903 u8 adc_pwdb_X[4];
904 u8 sq_rpt;
905 u8 cck_agc_rpt;
906 }phy_sts_cck_819xpci_t;
907
908 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
909 u8 reserved:4;
910 u8 rxsc:2;
911 u8 sgi_en:1;
912 u8 ex_intf_flag:1;
913 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
914
915 typedef enum _RT_OP_MODE{
916 RT_OP_MODE_AP,
917 RT_OP_MODE_INFRASTRUCTURE,
918 RT_OP_MODE_IBSS,
919 RT_OP_MODE_NO_LINK,
920 }RT_OP_MODE, *PRT_OP_MODE;
921
922
923 /* 2007/11/02 MH Define RF mode temporarily for test. */
924 typedef enum tag_Rf_OpType
925 {
926 RF_OP_By_SW_3wire = 0,
927 RF_OP_By_FW,
928 RF_OP_MAX
929 }RF_OpType_E;
930
931 typedef enum _RESET_TYPE {
932 RESET_TYPE_NORESET = 0x00,
933 RESET_TYPE_NORMAL = 0x01,
934 RESET_TYPE_SILENT = 0x02
935 } RESET_TYPE;
936
937 typedef struct _tx_ring{
938 u32 * desc;
939 u8 nStuckCount;
940 struct _tx_ring * next;
941 }__attribute__ ((packed)) tx_ring, * ptx_ring;
942
943 struct rtl8192_tx_ring {
944 tx_desc_819x_pci *desc;
945 dma_addr_t dma;
946 unsigned int idx;
947 unsigned int entries;
948 struct sk_buff_head queue;
949 };
950
951 #define NIC_SEND_HANG_THRESHOLD_NORMAL 4
952 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8
953 #define MAX_TX_QUEUE 9 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
954
955 #define MAX_RX_COUNT 64
956 #define MAX_TX_QUEUE_COUNT 9
957
958 typedef struct r8192_priv
959 {
960 struct pci_dev *pdev;
961 //added for maintain info from eeprom
962 short epromtype;
963 u16 eeprom_vid;
964 u16 eeprom_did;
965 u8 eeprom_CustomerID;
966 u16 eeprom_ChannelPlan;
967 RT_CUSTOMER_ID CustomerID;
968 LED_STRATEGY_8190 LedStrategy;
969 //bool bDcut;
970 u8 IC_Cut;
971 int irq;
972 short irq_enabled;
973 struct ieee80211_device *ieee80211;
974 #ifdef ENABLE_LPS
975 bool ps_force;
976 bool force_lps;
977 bool bdisable_nic;
978 #endif
979 bool being_init_adapter;
980 u8 Rf_Mode;
981 short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
982 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
983 // short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
984 short enable_gpio0;
985 enum card_type {PCI,MINIPCI,CARDBUS,USB/*rtl8187*/}card_type;
986 short hw_plcp_len;
987 short plcp_preamble_mode;
988 u8 ScanDelay;
989 spinlock_t irq_th_lock;
990 spinlock_t tx_lock;
991 spinlock_t rf_ps_lock;
992 struct mutex mutex;
993 spinlock_t ps_lock;
994
995 u32 irq_mask;
996 // short irq_enabled;
997 // struct net_device *dev; //comment this out.
998 short chan;
999 short sens;
1000 short max_sens;
1001 u32 rx_prevlen;
1002 /*RX stuff*/
1003 rx_desc_819x_pci *rx_ring;
1004 dma_addr_t rx_ring_dma;
1005 unsigned int rx_idx;
1006 struct sk_buff *rx_buf[MAX_RX_COUNT];
1007 int rxringcount;
1008 u16 rxbuffersize;
1009
1010
1011 struct sk_buff *rx_skb;
1012 u32 *rxring;
1013 u32 *rxringtail;
1014 dma_addr_t rxringdma;
1015 struct buffer *rxbuffer;
1016 struct buffer *rxbufferhead;
1017 short rx_skb_complete;
1018 /*TX stuff*/
1019 struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
1020 int txringcount;
1021 //{
1022 //struct tx_pendingbuf txnp_pending;
1023 //struct tasklet_struct irq_tx_tasklet;
1024 struct tasklet_struct irq_rx_tasklet;
1025 struct tasklet_struct irq_tx_tasklet;
1026 struct tasklet_struct irq_prepare_beacon_tasklet;
1027 /* adhoc/master mode stuff */
1028 ptx_ring txbeaconringtail;
1029 dma_addr_t txbeaconringdma;
1030 ptx_ring txbeaconring;
1031 int txbeaconcount;
1032 struct buffer *txbeaconbufs;
1033 struct buffer *txbeaconbufstail;
1034 // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1035 // u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1036 // u8 cck_txpwr_base;
1037 // u8 ofdm_txpwr_base;
1038 // u8 challow[15]; //channels from 1 to 14, 0 not used
1039 short up;
1040 short crcmon; //if 1 allow bad crc frame reception in monitor mode
1041 // short prism_hdr;
1042
1043 // struct timer_list scan_timer;
1044 /*short scanpending;
1045 short stopscan;*/
1046 // spinlock_t scan_lock;
1047 // u8 active_probe;
1048 //u8 active_scan_num;
1049 struct semaphore wx_sem;
1050 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1051 // short hw_wep;
1052
1053 // short digphy;
1054 // short antb;
1055 // short diversity;
1056 // u8 cs_treshold;
1057 // short rcr_csense;
1058 u8 rf_type; //0 means 1T2R, 1 means 2T4R
1059 RT_RF_TYPE_819xU rf_chip;
1060
1061 // u32 key0[4];
1062 short (*rf_set_sens)(struct net_device *dev,short sens);
1063 u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1064 void (*rf_close)(struct net_device *dev);
1065 void (*rf_init)(struct net_device *dev);
1066 //short rate;
1067 short promisc;
1068 /*stats*/
1069 struct Stats stats;
1070 struct iw_statistics wstats;
1071 struct proc_dir_entry *dir_dev;
1072
1073 /*RX stuff*/
1074 // u32 *rxring;
1075 // u32 *rxringtail;
1076 // dma_addr_t rxringdma;
1077
1078 #ifdef THOMAS_BEACON
1079 u32 *oldaddr;
1080 #endif
1081 #ifdef THOMAS_TASKLET
1082 atomic_t irt_counter;//count for irq_rx_tasklet
1083 #endif
1084 #ifdef JACKSON_NEW_RX
1085 struct sk_buff **pp_rxskb;
1086 int rx_inx;
1087 #endif
1088
1089 /* modified by davad for Rx process */
1090 struct sk_buff_head rx_queue;
1091 struct sk_buff_head skb_queue;
1092 struct work_struct qos_activate;
1093 short tx_urb_index;
1094 atomic_t tx_pending[0x10];//UART_PRIORITY+1
1095
1096 struct urb *rxurb_task;
1097
1098 //2 Tx Related variables
1099 u16 ShortRetryLimit;
1100 u16 LongRetryLimit;
1101 u32 TransmitConfig;
1102 u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1103
1104 u32 LastRxDescTSFHigh;
1105 u32 LastRxDescTSFLow;
1106
1107
1108 //2 Rx Related variables
1109 u16 EarlyRxThreshold;
1110 u32 ReceiveConfig;
1111 u8 AcmControl;
1112
1113 u8 RFProgType;
1114
1115 u8 retry_data;
1116 u8 retry_rts;
1117 u16 rts;
1118
1119 struct ChnlAccessSetting ChannelAccessSetting;
1120
1121 struct work_struct reset_wq;
1122
1123 /**********************************************************/
1124 //for rtl819xPci
1125 // Data Rate Config. Added by Annie, 2006-04-13.
1126 u16 basic_rate;
1127 u8 short_preamble;
1128 u8 slot_time;
1129 u16 SifsTime;
1130 /* WirelessMode*/
1131 u8 RegWirelessMode;
1132 /*Firmware*/
1133 prt_firmware pFirmware;
1134 rtl819x_loopback_e LoopbackMode;
1135 firmware_source_e firmware_source;
1136 bool AutoloadFailFlag;
1137 u16 EEPROMTxPowerDiff;
1138 u16 EEPROMAntPwDiff; // Antenna gain offset from B/C/D to A
1139 u8 EEPROMThermalMeter;
1140 u8 EEPROMPwDiff;
1141 u8 EEPROMCrystalCap;
1142 u8 EEPROM_Def_Ver;
1143 u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14
1144 // The following definition is for eeprom 93c56
1145 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1146 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1147 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
1148 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1149 u8 EEPROMTxPowerLevelCCK_V1[3];
1150 u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1151 u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1152 u8 EEPROMLegacyHTTxPowerDiff; // Legacy to HT rate power diff
1153 bool bTXPowerDataReadFromEEPORM;
1154 /*channel plan*/
1155 u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user.
1156 u16 ChannelPlan;
1157 /*PS related*/
1158 bool RegRfOff;
1159 // Rf off action for power save
1160 u8 bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable
1161 /*PHY related*/
1162 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1163 // Read/write are allow for following hardware information variables
1164 u32 MCSTxPowerLevelOriginalOffset[6];
1165 u32 CCKTxPowerLevelOriginalOffset;
1166 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1167 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
1168 u8 TxPowerLevelCCK_C[14];
1169 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1170 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1171 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
1172 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
1173 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
1174 u8 TxPowerDiff;
1175 char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a
1176 u8 AntennaTxPwDiff[3]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1177 u8 CrystalCap; // CrystalCap.
1178 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1179 //05/27/2008 cck power enlarge
1180 u8 CckPwEnl;
1181 u16 TSSI_13dBm;
1182 u32 Pwr_Track;
1183 u8 CCKPresentAttentuation_20Mdefault;
1184 u8 CCKPresentAttentuation_40Mdefault;
1185 char CCKPresentAttentuation_difference;
1186 char CCKPresentAttentuation;
1187 // Use to calculate PWBD.
1188 u8 bCckHighPower;
1189 long undecorated_smoothed_pwdb;
1190 long undecorated_smoothed_cck_adc_pwdb[4];
1191 //for set channel
1192 u8 SwChnlInProgress;
1193 u8 SwChnlStage;
1194 u8 SwChnlStep;
1195 u8 SetBWModeInProgress;
1196 HT_CHANNEL_WIDTH CurrentChannelBW;
1197
1198 // 8190 40MHz mode
1199 //
1200 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1201 // Joseph test for shorten RF configuration time.
1202 // We save RF reg0 in this variable to reduce RF reading.
1203 //
1204 u32 RfReg0Value[4];
1205 u8 NumTotalRFPath;
1206 bool brfpath_rxenable[4];
1207 //+by amy 080507
1208 struct timer_list watch_dog_timer;
1209
1210 //+by amy 080515 for dynamic mechenism
1211 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1212 bool bdynamic_txpower; //bDynamicTxPower
1213 bool bDynamicTxHighPower; // Tx high power state
1214 bool bDynamicTxLowPower; // Tx low power state
1215 bool bLastDTPFlag_High;
1216 bool bLastDTPFlag_Low;
1217
1218 bool bstore_last_dtpflag;
1219 bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1220 //Add by amy for Rate Adaptive
1221 rate_adaptive rate_adaptive;
1222 //Add by amy for TX power tracking
1223 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1224 const txbbgain_struct * txbbgain_table;
1225 u8 txpower_count;//For 6 sec do tracking again
1226 bool btxpower_trackingInit;
1227 u8 OFDM_index;
1228 u8 CCK_index;
1229 u8 Record_CCK_20Mindex;
1230 u8 Record_CCK_40Mindex;
1231 //2007/09/10 Mars Add CCK TX Power Tracking
1232 const ccktxbbgain_struct *cck_txbbgain_table;
1233 const ccktxbbgain_struct *cck_txbbgain_ch14_table;
1234 u8 rfa_txpowertrackingindex;
1235 u8 rfa_txpowertrackingindex_real;
1236 u8 rfa_txpowertracking_default;
1237 u8 rfc_txpowertrackingindex;
1238 u8 rfc_txpowertrackingindex_real;
1239 u8 rfc_txpowertracking_default;
1240 bool btxpower_tracking;
1241 bool bcck_in_ch14;
1242
1243 //For Backup Initial Gain
1244 init_gain initgain_backup;
1245 u8 DefaultInitialGain[4];
1246 // For EDCA Turbo mode, Added by amy 080515.
1247 bool bis_any_nonbepkts;
1248 bool bcurrent_turbo_EDCA;
1249
1250 bool bis_cur_rdlstate;
1251 struct timer_list fsync_timer;
1252 bool bfsync_processing; // 500ms Fsync timer is active or not
1253 u32 rate_record;
1254 u32 rateCountDiffRecord;
1255 u32 ContiuneDiffCount;
1256 bool bswitch_fsync;
1257
1258 u8 framesync;
1259 u32 framesyncC34;
1260 u8 framesyncMonitor;
1261 //Added by amy 080516 for RX related
1262 u16 nrxAMPDU_size;
1263 u8 nrxAMPDU_aggr_num;
1264
1265 /*Last RxDesc TSF value*/
1266 u32 last_rxdesc_tsf_high;
1267 u32 last_rxdesc_tsf_low;
1268
1269 //by amy for gpio
1270 bool bHwRadioOff;
1271 //by amy for ps
1272 bool RFChangeInProgress; // RF Chnage in progress, by Bruce, 2007-10-30
1273 bool SetRFPowerStateInProgress;
1274 RT_OP_MODE OpMode;
1275 //by amy for reset_count
1276 u32 reset_count;
1277 bool bpbc_pressed;
1278 //by amy for debug
1279 u32 txpower_checkcnt;
1280 u32 txpower_tracking_callback_cnt;
1281 u8 thermal_read_val[40];
1282 u8 thermal_readback_index;
1283 u32 ccktxpower_adjustcnt_not_ch14;
1284 u32 ccktxpower_adjustcnt_ch14;
1285 u8 tx_fwinfo_force_subcarriermode;
1286 u8 tx_fwinfo_force_subcarrierval;
1287
1288 //by amy for silent reset
1289 RESET_TYPE ResetProgress;
1290 bool bForcedSilentReset;
1291 bool bDisableNormalResetCheck;
1292 u16 TxCounter;
1293 u16 RxCounter;
1294 int IrpPendingCount;
1295 bool bResetInProgress;
1296 bool force_reset;
1297 u8 InitialGainOperateType;
1298
1299 //define work item by amy 080526
1300 struct delayed_work update_beacon_wq;
1301 struct delayed_work watch_dog_wq;
1302 struct delayed_work txpower_tracking_wq;
1303 struct delayed_work rfpath_check_wq;
1304 struct delayed_work gpio_change_rf_wq;
1305 struct delayed_work initialgain_operate_wq;
1306 struct workqueue_struct *priv_wq;
1307 }r8192_priv;
1308
1309 // for rtl8187
1310 // now mirging to rtl8187B
1311 /*
1312 typedef enum{
1313 LOW_PRIORITY = 0x02,
1314 NORM_PRIORITY
1315 } priority_t;
1316 */
1317 //for rtl8187B
1318 #if 0
1319 typedef enum{
1320 BULK_PRIORITY = 0x01,
1321 //RSVD0,
1322 //RSVD1,
1323 LOW_PRIORITY,
1324 NORM_PRIORITY,
1325 VO_PRIORITY,
1326 VI_PRIORITY, //0x05
1327 BE_PRIORITY,
1328 BK_PRIORITY,
1329 CMD_PRIORITY,//0x8
1330 RSVD3,
1331 BEACON_PRIORITY, //0x0A
1332 HIGH_PRIORITY,
1333 MANAGE_PRIORITY,
1334 RSVD4,
1335 RSVD5,
1336 UART_PRIORITY //0x0F
1337 } priority_t;
1338 #endif
1339 typedef enum{
1340 NIC_8192E = 1,
1341 } nic_t;
1342
1343
1344 #if 0 //defined in Qos.h
1345 //typedef u32 AC_CODING;
1346 #define AC0_BE 0 // ACI: 0x00 // Best Effort
1347 #define AC1_BK 1 // ACI: 0x01 // Background
1348 #define AC2_VI 2 // ACI: 0x10 // Video
1349 #define AC3_VO 3 // ACI: 0x11 // Voice
1350 #define AC_MAX 4 // Max: define total number; Should not to be used as a real enum.
1351
1352 //
1353 // ECWmin/ECWmax field.
1354 // Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
1355 //
1356 typedef union _ECW{
1357 u8 charData;
1358 struct
1359 {
1360 u8 ECWmin:4;
1361 u8 ECWmax:4;
1362 }f; // Field
1363 }ECW, *PECW;
1364
1365 //
1366 // ACI/AIFSN Field.
1367 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
1368 //
1369 typedef union _ACI_AIFSN{
1370 u8 charData;
1371
1372 struct
1373 {
1374 u8 AIFSN:4;
1375 u8 ACM:1;
1376 u8 ACI:2;
1377 u8 Reserved:1;
1378 }f; // Field
1379 }ACI_AIFSN, *PACI_AIFSN;
1380
1381 //
1382 // AC Parameters Record Format.
1383 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
1384 //
1385 typedef union _AC_PARAM{
1386 u32 longData;
1387 u8 charData[4];
1388
1389 struct
1390 {
1391 ACI_AIFSN AciAifsn;
1392 ECW Ecw;
1393 u16 TXOPLimit;
1394 }f; // Field
1395 }AC_PARAM, *PAC_PARAM;
1396
1397 #endif
1398 bool init_firmware(struct net_device *dev);
1399 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1400 u32 read_cam(struct net_device *dev, u8 addr);
1401 void write_cam(struct net_device *dev, u8 addr, u32 data);
1402 u8 read_nic_byte(struct net_device *dev, int x);
1403 u8 read_nic_byte_E(struct net_device *dev, int x);
1404 u32 read_nic_dword(struct net_device *dev, int x);
1405 u16 read_nic_word(struct net_device *dev, int x) ;
1406 void write_nic_byte(struct net_device *dev, int x,u8 y);
1407 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1408 void write_nic_word(struct net_device *dev, int x,u16 y);
1409 void write_nic_dword(struct net_device *dev, int x,u32 y);
1410
1411 void rtl8192_halt_adapter(struct net_device *dev, bool reset);
1412 void rtl8192_rx_enable(struct net_device *);
1413 void rtl8192_tx_enable(struct net_device *);
1414
1415 void rtl8192_disassociate(struct net_device *dev);
1416 //void fix_rx_fifo(struct net_device *dev);
1417 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1418
1419 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1420 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1421 void rtl8192_update_msr(struct net_device *dev);
1422 int rtl8192_down(struct net_device *dev);
1423 int rtl8192_up(struct net_device *dev);
1424 void rtl8192_commit(struct net_device *dev);
1425 void rtl8192_set_chan(struct net_device *dev,short ch);
1426 void write_phy(struct net_device *dev, u8 adr, u8 data);
1427 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1428 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1429 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1430 void rtl8187_set_rxconf(struct net_device *dev);
1431 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1432 void CamResetAllEntry(struct net_device* dev);
1433 void EnableHWSecurityConfig8192(struct net_device *dev);
1434 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1435 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14);
1436 void firmware_init_param(struct net_device *dev);
1437 RT_STATUS cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
1438 void rtl8192_hw_wakeup_wq (struct work_struct *work);
1439
1440 short rtl8192_is_tx_queue_empty(struct net_device *dev);
1441 #ifdef ENABLE_IPS
1442 void IPSEnter(struct net_device *dev);
1443 void IPSLeave(struct net_device *dev);
1444 void InactivePsWorkItemCallback(struct net_device *dev);
1445 void IPSLeave_wq(void *data);
1446 void ieee80211_ips_leave_wq(struct net_device *dev);
1447 void ieee80211_ips_leave(struct net_device *dev);
1448 #endif
1449 #ifdef ENABLE_LPS
1450 void LeisurePSEnter(struct net_device *dev);
1451 void LeisurePSLeave(struct net_device *dev);
1452 #endif
1453
1454 bool NicIFEnableNIC(struct net_device* dev);
1455 bool NicIFDisableNIC(struct net_device* dev);
1456
1457 void rtl8192_irq_disable(struct net_device *dev);
1458 void PHY_SetRtl8192eRfOff(struct net_device* dev);
1459 #endif
Linux kernel - Deliverables
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