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Staging: add Realtek 8192 PCI wireless driver
[deliverable/linux.git] / drivers / staging / rtl8192e / r8192E.h
1 /*
2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
8
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
13
14 We want to tanks the Authors of those projects and the Ndiswrapper
15 project Authors.
16 */
17
18 #ifndef R819xU_H
19 #define R819xU_H
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 //#include <linux/config.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/netdevice.h>
30 #include <linux/pci.h>
31 //#include <linux/usb.h>
32 #include <linux/etherdevice.h>
33 #include <linux/delay.h>
34 #include <linux/rtnetlink.h> //for rtnl_lock()
35 #include <linux/wireless.h>
36 #include <linux/timer.h>
37 #include <linux/proc_fs.h> // Necessary because we use the proc fs
38 #include <linux/if_arp.h>
39 #include <linux/random.h>
40 #include <linux/version.h>
41 #include <asm/io.h>
42 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27))
43 #include <asm/semaphore.h>
44 #endif
45 #include "ieee80211.h"
46
47
48
49
50 #define RTL819xE_MODULE_NAME "rtl819xE"
51 //added for HW security, john.0629
52 #define FALSE 0
53 #define TRUE 1
54 #define MAX_KEY_LEN 61
55 #define KEY_BUF_SIZE 5
56
57 #define BIT0 0x00000001
58 #define BIT1 0x00000002
59 #define BIT2 0x00000004
60 #define BIT3 0x00000008
61 #define BIT4 0x00000010
62 #define BIT5 0x00000020
63 #define BIT6 0x00000040
64 #define BIT7 0x00000080
65 #define BIT8 0x00000100
66 #define BIT9 0x00000200
67 #define BIT10 0x00000400
68 #define BIT11 0x00000800
69 #define BIT12 0x00001000
70 #define BIT13 0x00002000
71 #define BIT14 0x00004000
72 #define BIT15 0x00008000
73 #define BIT16 0x00010000
74 #define BIT17 0x00020000
75 #define BIT18 0x00040000
76 #define BIT19 0x00080000
77 #define BIT20 0x00100000
78 #define BIT21 0x00200000
79 #define BIT22 0x00400000
80 #define BIT23 0x00800000
81 #define BIT24 0x01000000
82 #define BIT25 0x02000000
83 #define BIT26 0x04000000
84 #define BIT27 0x08000000
85 #define BIT28 0x10000000
86 #define BIT29 0x20000000
87 #define BIT30 0x40000000
88 #define BIT31 0x80000000
89 // Rx smooth factor
90 #define Rx_Smooth_Factor 20
91 /* 2007/06/04 MH Define sliding window for RSSI history. */
92 #define PHY_RSSI_SLID_WIN_MAX 100
93 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
94
95 #define IC_VersionCut_D 0x3
96 #define IC_VersionCut_E 0x4
97
98 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
99 #define DMESG(x,a...) printk(KERN_INFO RTL819xE_MODULE_NAME ": " x "\n", ## a)
100 #define DMESGW(x,a...) printk(KERN_WARNING RTL819xE_MODULE_NAME ": WW:" x "\n", ## a)
101 #define DMESGE(x,a...) printk(KERN_WARNING RTL819xE_MODULE_NAME ": EE:" x "\n", ## a)
102 #else
103 #define DMESG(x,a...)
104 #define DMESGW(x,a...)
105 #define DMESGE(x,a...)
106 extern u32 rt_global_debug_component;
107 #define RT_TRACE(component, x, args...) \
108 do { if(rt_global_debug_component & component) \
109 printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x "\n" , \
110 ##args);\
111 }while(0);
112
113 #define COMP_TRACE BIT0 // For function call tracing.
114 #define COMP_DBG BIT1 // Only for temporary debug message.
115 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
116
117
118 #define COMP_RECV BIT3 // Reveive part data path.
119 #define COMP_SEND BIT4 // Send part path.
120 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
121 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
122 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
123 #define COMP_SWBW BIT8 // For bandwidth switch.
124 #define COMP_SEC BIT9// For Security.
125
126
127 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
128 #define COMP_QOS BIT11 // For QoS.
129
130 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
131 #define COMP_RXDESC BIT13 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
132 #define COMP_PHY BIT14
133 #define COMP_DIG BIT15 // For DIG, 2006.09.25, by rcnjko.
134 #define COMP_TXAGC BIT16 // For Tx power, 060928, by rcnjko.
135 #define COMP_HALDM BIT17 // For HW Dynamic Mechanism, 061010, by rcnjko.
136 #define COMP_POWER_TRACKING BIT18 //FOR 8190 TX POWER TRACKING
137 #define COMP_EVENTS BIT19 // Event handling
138
139 #define COMP_RF BIT20 // For RF.
140 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
141 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
142 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
143
144 #define COMP_FIRMWARE BIT21 //for firmware downloading
145 #define COMP_HT BIT22 // For 802.11n HT related information. by Emily 2006-8-11
146
147 #define COMP_RESET BIT23
148 #define COMP_CMDPKT BIT24
149 #define COMP_SCAN BIT25
150 #define COMP_IPS BIT26
151 #define COMP_DOWN BIT27 // for rm driver module
152 #define COMP_INTR BIT28 // for interrupt
153 #define COMP_ERR BIT31 // for error out, always on
154 #endif
155
156 #define RTL819x_DEBUG
157 #ifdef RTL819x_DEBUG
158 #define assert(expr) \
159 if (!(expr)) { \
160 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
161 #expr,__FILE__,__FUNCTION__,__LINE__); \
162 }
163 //wb added to debug out data buf
164 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
165 #define RT_DEBUG_DATA(level, data, datalen) \
166 do{ if ((rt_global_debug_component & (level)) == (level)) \
167 { \
168 int i; \
169 u8* pdata = (u8*) data; \
170 printk(KERN_DEBUG RTL819xE_MODULE_NAME ": %s()\n", __FUNCTION__); \
171 for(i=0; i<(int)(datalen); i++) \
172 { \
173 printk("%2x ", pdata[i]); \
174 if ((i+1)%16 == 0) printk("\n"); \
175 } \
176 printk("\n"); \
177 } \
178 } while (0)
179 #else
180 #define assert(expr) do {} while (0)
181 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
182 #endif /* RTL8169_DEBUG */
183
184
185 //
186 // Queue Select Value in TxDesc
187 //
188 #define QSLT_BK 0x1
189 #define QSLT_BE 0x0
190 #define QSLT_VI 0x4
191 #define QSLT_VO 0x6
192 #define QSLT_BEACON 0x10
193 #define QSLT_HIGH 0x11
194 #define QSLT_MGNT 0x12
195 #define QSLT_CMD 0x13
196
197 #define DESC90_RATE1M 0x00
198 #define DESC90_RATE2M 0x01
199 #define DESC90_RATE5_5M 0x02
200 #define DESC90_RATE11M 0x03
201 #define DESC90_RATE6M 0x04
202 #define DESC90_RATE9M 0x05
203 #define DESC90_RATE12M 0x06
204 #define DESC90_RATE18M 0x07
205 #define DESC90_RATE24M 0x08
206 #define DESC90_RATE36M 0x09
207 #define DESC90_RATE48M 0x0a
208 #define DESC90_RATE54M 0x0b
209 #define DESC90_RATEMCS0 0x00
210 #define DESC90_RATEMCS1 0x01
211 #define DESC90_RATEMCS2 0x02
212 #define DESC90_RATEMCS3 0x03
213 #define DESC90_RATEMCS4 0x04
214 #define DESC90_RATEMCS5 0x05
215 #define DESC90_RATEMCS6 0x06
216 #define DESC90_RATEMCS7 0x07
217 #define DESC90_RATEMCS8 0x08
218 #define DESC90_RATEMCS9 0x09
219 #define DESC90_RATEMCS10 0x0a
220 #define DESC90_RATEMCS11 0x0b
221 #define DESC90_RATEMCS12 0x0c
222 #define DESC90_RATEMCS13 0x0d
223 #define DESC90_RATEMCS14 0x0e
224 #define DESC90_RATEMCS15 0x0f
225 #define DESC90_RATEMCS32 0x20
226
227 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
228 #define EEPROM_Default_LegacyHTTxPowerDiff 0x4
229 #define IEEE80211_WATCH_DOG_TIME 2000
230
231 /* For rtl819x */
232 typedef struct _tx_desc_819x_pci {
233 //DWORD 0
234 u16 PktSize;
235 u8 Offset;
236 u8 Reserved1:3;
237 u8 CmdInit:1;
238 u8 LastSeg:1;
239 u8 FirstSeg:1;
240 u8 LINIP:1;
241 u8 OWN:1;
242
243 //DWORD 1
244 u8 TxFWInfoSize;
245 u8 RATid:3;
246 u8 DISFB:1;
247 u8 USERATE:1;
248 u8 MOREFRAG:1;
249 u8 NoEnc:1;
250 u8 PIFS:1;
251 u8 QueueSelect:5;
252 u8 NoACM:1;
253 u8 Resv:2;
254 u8 SecCAMID:5;
255 u8 SecDescAssign:1;
256 u8 SecType:2;
257
258 //DWORD 2
259 u16 TxBufferSize;
260 u8 PktId:7;
261 u8 Resv1:1;
262 u8 Reserved2;
263
264 //DWORD 3
265 u32 TxBuffAddr;
266
267 //DWORD 4
268 u32 NextDescAddress;
269
270 //DWORD 5,6,7
271 u32 Reserved5;
272 u32 Reserved6;
273 u32 Reserved7;
274 }tx_desc_819x_pci, *ptx_desc_819x_pci;
275
276
277 typedef struct _tx_desc_cmd_819x_pci {
278 //DWORD 0
279 u16 PktSize;
280 u8 Reserved1;
281 u8 CmdType:3;
282 u8 CmdInit:1;
283 u8 LastSeg:1;
284 u8 FirstSeg:1;
285 u8 LINIP:1;
286 u8 OWN:1;
287
288 //DOWRD 1
289 u16 ElementReport;
290 u16 Reserved2;
291
292 //DOWRD 2
293 u16 TxBufferSize;
294 u16 Reserved3;
295
296 //DWORD 3,4,5
297 u32 TxBufferAddr;
298 u32 NextDescAddress;
299 u32 Reserved4;
300 u32 Reserved5;
301 u32 Reserved6;
302 }tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci;
303
304
305 typedef struct _tx_fwinfo_819x_pci {
306 //DOWRD 0
307 u8 TxRate:7;
308 u8 CtsEnable:1;
309 u8 RtsRate:7;
310 u8 RtsEnable:1;
311 u8 TxHT:1;
312 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
313 u8 TxBandwidth:1; // This is used for HT MCS rate only.
314 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
315 u8 STBC:2;
316 u8 AllowAggregation:1;
317 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
318 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
319 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
320 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
321 u8 RtsSTBC:2;
322 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
323
324 //DWORD 1
325 u8 RxMF:2;
326 u8 RxAMD:3;
327 u8 Reserved1:3;
328 u8 Reserved2;
329 u8 Reserved3;
330 u8 Reserved4;
331
332 //u32 Reserved;
333 }tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci;
334
335 typedef struct rtl8192_rx_info {
336 struct urb *urb;
337 struct net_device *dev;
338 u8 out_pipe;
339 }rtl8192_rx_info ;
340 typedef struct _rx_desc_819x_pci{
341 //DOWRD 0
342 u16 Length:14;
343 u16 CRC32:1;
344 u16 ICV:1;
345 u8 RxDrvInfoSize;
346 u8 Shift:2;
347 u8 PHYStatus:1;
348 u8 SWDec:1;
349 u8 LastSeg:1;
350 u8 FirstSeg:1;
351 u8 EOR:1;
352 u8 OWN:1;
353
354 //DWORD 1
355 u32 Reserved2;
356
357 //DWORD 2
358 u32 Reserved3;
359
360 //DWORD 3
361 u32 BufferAddress;
362
363 }rx_desc_819x_pci, *prx_desc_819x_pci;
364
365 typedef struct _rx_fwinfo_819x_pci{
366 //DWORD 0
367 u16 Reserved1:12;
368 u16 PartAggr:1;
369 u16 FirstAGGR:1;
370 u16 Reserved2:2;
371
372 u8 RxRate:7;
373 u8 RxHT:1;
374
375 u8 BW:1;
376 u8 SPLCP:1;
377 u8 Reserved3:2;
378 u8 PAM:1;
379 u8 Mcast:1;
380 u8 Bcast:1;
381 u8 Reserved4:1;
382
383 //DWORD 1
384 u32 TSFL;
385
386 }rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci;
387
388 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
389 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
390 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
391 #define ENCRYPTION_MAX_OVERHEAD 128
392 //#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
393 //#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
394 #define MAX_FRAGMENT_COUNT 8
395 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
396
397 #define scrclng 4 // octets for crc32 (FCS, ICV)
398 /* 8190 Loopback Mode definition */
399 typedef enum _rtl819x_loopback{
400 RTL819X_NO_LOOPBACK = 0,
401 RTL819X_MAC_LOOPBACK = 1,
402 RTL819X_DMA_LOOPBACK = 2,
403 RTL819X_CCK_LOOPBACK = 3,
404 }rtl819x_loopback_e;
405
406 /* due to rtl8192 firmware */
407 typedef enum _desc_packet_type_e{
408 DESC_PACKET_TYPE_INIT = 0,
409 DESC_PACKET_TYPE_NORMAL = 1,
410 }desc_packet_type_e;
411
412 typedef enum _firmware_source{
413 FW_SOURCE_IMG_FILE = 0,
414 FW_SOURCE_HEADER_FILE = 1, //from header file
415 }firmware_source_e, *pfirmware_source_e;
416
417 typedef enum _firmware_status{
418 FW_STATUS_0_INIT = 0,
419 FW_STATUS_1_MOVE_BOOT_CODE = 1,
420 FW_STATUS_2_MOVE_MAIN_CODE = 2,
421 FW_STATUS_3_TURNON_CPU = 3,
422 FW_STATUS_4_MOVE_DATA_CODE = 4,
423 FW_STATUS_5_READY = 5,
424 }firmware_status_e;
425
426 typedef struct _rt_firmare_seg_container {
427 u16 seg_size;
428 u8 *seg_ptr;
429 }fw_seg_container, *pfw_seg_container;
430
431 typedef struct _rt_firmware{
432 firmware_status_e firmware_status;
433 u16 cmdpacket_frag_thresold;
434 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
435 #define MAX_FW_INIT_STEP 3
436 u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
437 u16 firmware_buf_size[MAX_FW_INIT_STEP];
438 }rt_firmware, *prt_firmware;
439 //+by amy 080507
440 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
441
442 /* Firmware Queue Layout */
443 #define NUM_OF_FIRMWARE_QUEUE 10
444 #define NUM_OF_PAGES_IN_FW 0x100
445 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
446 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
447 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
448 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
449 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
450 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x2
451 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
452 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
453 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
454 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
455 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
456 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
457 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
458 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
459 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
460 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
461 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
462 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
463 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
464
465 //8187B Security
466 //#define RWCAM 0xA0 // Software read/write CAM config
467 //#define WCAMI 0xA4 // Software write CAM input content
468 //#define RCAMO 0xA8 // Output value from CAM according to 0xa0 setting
469 #define DCAM 0xAC // Debug CAM Interface
470 #define AESMSK_FC 0xB2 // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06.
471
472
473 #define CAM_CONTENT_COUNT 8
474 //#define CFG_DEFAULT_KEY BIT5
475 #define CFG_VALID BIT15
476 #if 0
477 //----------------------------------------------------------------------------
478 // 8187B WPA Config Register (offset 0xb0, 1 byte)
479 //----------------------------------------------------------------------------
480 #define SCR_UseDK 0x01
481 #define SCR_TxSecEnable 0x02
482 #define SCR_RxSecEnable 0x04
483
484 //----------------------------------------------------------------------------
485 // 8187B CAM Config Setting (offset 0xb0, 1 byte)
486 //----------------------------------------------------------------------------
487 #define CAM_VALID 0x8000
488 #define CAM_NOTVALID 0x0000
489 #define CAM_USEDK 0x0020
490
491
492 #define CAM_NONE 0x0
493 #define CAM_WEP40 0x01
494 #define CAM_TKIP 0x02
495 #define CAM_AES 0x04
496 #define CAM_WEP104 0x05
497
498 //#define CAM_SIZE 16
499 #define TOTAL_CAM_ENTRY 16
500 #define CAM_ENTRY_LEN_IN_DW 6 // 6, unit: in u4byte. Added by Annie, 2006-05-25.
501 #define CAM_ENTRY_LEN_IN_BYTE (CAM_ENTRY_LEN_IN_DW*sizeof(u32)) // 24, unit: in u1byte. Added by Annie, 2006-05-25.
502
503 #define CAM_CONFIG_USEDK 1
504 #define CAM_CONFIG_NO_USEDK 0
505
506 #define CAM_WRITE 0x00010000
507 #define CAM_READ 0x00000000
508 #define CAM_POLLINIG 0x80000000
509
510 //=================================================================
511 //=================================================================
512
513 #endif
514 #define EPROM_93c46 0
515 #define EPROM_93c56 1
516
517 #define DEFAULT_FRAG_THRESHOLD 2342U
518 #define MIN_FRAG_THRESHOLD 256U
519 #define DEFAULT_BEACONINTERVAL 0x64U
520 #define DEFAULT_BEACON_ESSID "Rtl819xU"
521
522 #define DEFAULT_SSID ""
523 #define DEFAULT_RETRY_RTS 7
524 #define DEFAULT_RETRY_DATA 7
525 #define PRISM_HDR_SIZE 64
526
527 #define PHY_RSSI_SLID_WIN_MAX 100
528
529
530 typedef enum _WIRELESS_MODE {
531 WIRELESS_MODE_UNKNOWN = 0x00,
532 WIRELESS_MODE_A = 0x01,
533 WIRELESS_MODE_B = 0x02,
534 WIRELESS_MODE_G = 0x04,
535 WIRELESS_MODE_AUTO = 0x08,
536 WIRELESS_MODE_N_24G = 0x10,
537 WIRELESS_MODE_N_5G = 0x20
538 } WIRELESS_MODE;
539
540 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
541
542 typedef struct buffer
543 {
544 struct buffer *next;
545 u32 *buf;
546 dma_addr_t dma;
547
548 } buffer;
549
550 typedef struct rtl_reg_debug{
551 unsigned int cmd;
552 struct {
553 unsigned char type;
554 unsigned char addr;
555 unsigned char page;
556 unsigned char length;
557 } head;
558 unsigned char buf[0xff];
559 }rtl_reg_debug;
560
561 #if 0
562
563 typedef struct tx_pendingbuf
564 {
565 struct ieee80211_txb *txb;
566 short ispending;
567 short descfrag;
568 } tx_pendigbuf;
569
570 #endif
571
572 typedef struct _rt_9x_tx_rate_history {
573 u32 cck[4];
574 u32 ofdm[8];
575 // HT_MCS[0][]: BW=0 SG=0
576 // HT_MCS[1][]: BW=1 SG=0
577 // HT_MCS[2][]: BW=0 SG=1
578 // HT_MCS[3][]: BW=1 SG=1
579 u32 ht_mcs[4][16];
580 }rt_tx_rahis_t, *prt_tx_rahis_t;
581
582 typedef struct _RT_SMOOTH_DATA_4RF {
583 char elements[4][100];//array to store values
584 u32 index; //index to current array to store
585 u32 TotalNum; //num of valid elements
586 u32 TotalVal[4]; //sum of valid elements
587 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
588
589 typedef enum _tag_TxCmd_Config_Index{
590 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
591 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
592 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
593 TXCMD_SET_TX_DURATION = 0xFF900003,
594 TXCMD_SET_RX_RSSI = 0xFF900004,
595 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
596 TXCMD_XXXX_CTRL,
597 }DCMD_TXCMD_OP;
598
599 typedef struct Stats
600 {
601 unsigned long txrdu;
602 unsigned long rxrdu;
603 //unsigned long rxnolast;
604 //unsigned long rxnodata;
605 // unsigned long rxreset;
606 // unsigned long rxnopointer;
607 unsigned long rxok;
608 unsigned long rxframgment;
609 unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
610 unsigned long rxurberr;
611 unsigned long rxstaterr;
612 unsigned long rxcrcerrmin;//crc error (0-500)
613 unsigned long rxcrcerrmid;//crc error (500-1000)
614 unsigned long rxcrcerrmax;//crc error (>1000)
615 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
616 unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
617 unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
618 unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
619 unsigned long numpacket_matchbssid; // debug use only.
620 unsigned long numpacket_toself; // debug use only.
621 unsigned long num_process_phyinfo; // debug use only.
622 unsigned long numqry_phystatus;
623 unsigned long numqry_phystatusCCK;
624 unsigned long numqry_phystatusHT;
625 unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
626 unsigned long txnperr;
627 unsigned long txnpdrop;
628 unsigned long txresumed;
629 // unsigned long rxerr;
630 unsigned long rxoverflow;
631 unsigned long rxint;
632 unsigned long txnpokint;
633 // unsigned long txhpokint;
634 // unsigned long txhperr;
635 unsigned long ints;
636 unsigned long shints;
637 unsigned long txoverflow;
638 // unsigned long rxdmafail;
639 // unsigned long txbeacon;
640 // unsigned long txbeaconerr;
641 unsigned long txlpokint;
642 unsigned long txlpdrop;
643 unsigned long txlperr;
644 unsigned long txbeokint;
645 unsigned long txbedrop;
646 unsigned long txbeerr;
647 unsigned long txbkokint;
648 unsigned long txbkdrop;
649 unsigned long txbkerr;
650 unsigned long txviokint;
651 unsigned long txvidrop;
652 unsigned long txvierr;
653 unsigned long txvookint;
654 unsigned long txvodrop;
655 unsigned long txvoerr;
656 unsigned long txbeaconokint;
657 unsigned long txbeacondrop;
658 unsigned long txbeaconerr;
659 unsigned long txmanageokint;
660 unsigned long txmanagedrop;
661 unsigned long txmanageerr;
662 unsigned long txcmdpktokint;
663 unsigned long txdatapkt;
664 unsigned long txfeedback;
665 unsigned long txfeedbackok;
666 unsigned long txoktotal;
667 unsigned long txokbytestotal;
668 unsigned long txokinperiod;
669 unsigned long txmulticast;
670 unsigned long txbytesmulticast;
671 unsigned long txbroadcast;
672 unsigned long txbytesbroadcast;
673 unsigned long txunicast;
674 unsigned long txbytesunicast;
675 unsigned long rxbytesunicast;
676 unsigned long txfeedbackfail;
677 unsigned long txerrtotal;
678 unsigned long txerrbytestotal;
679 unsigned long txerrmulticast;
680 unsigned long txerrbroadcast;
681 unsigned long txerrunicast;
682 unsigned long txretrycount;
683 unsigned long txfeedbackretry;
684 u8 last_packet_rate;
685 unsigned long slide_signal_strength[100];
686 unsigned long slide_evm[100];
687 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
688 unsigned long slide_evm_total; // For recording sliding window's EVM value
689 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
690 long signal_quality;
691 long last_signal_strength_inpercent;
692 long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
693 u8 rx_rssi_percentage[4];
694 u8 rx_evm_percentage[2];
695 long rxSNRdB[4];
696 rt_tx_rahis_t txrate;
697 u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
698 u32 Slide_Beacon_Total; //cosa add for beacon rssi
699 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
700 u32 CurrentShowTxate;
701
702
703 } Stats;
704
705
706 // Bandwidth Offset
707 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
708 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
709 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
710
711 //+by amy 080507
712
713 typedef struct ChnlAccessSetting {
714 u16 SIFS_Timer;
715 u16 DIFS_Timer;
716 u16 SlotTimeTimer;
717 u16 EIFS_Timer;
718 u16 CWminIndex;
719 u16 CWmaxIndex;
720 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
721
722 typedef struct _BB_REGISTER_DEFINITION{
723 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
724 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
725 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
726 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
727 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
728 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
729 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
730 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
731 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
732 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
733 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
734 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
735 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
736 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
737 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
738 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
739 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
740 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
741
742 typedef enum _RT_RF_TYPE_819xU{
743 RF_TYPE_MIN = 0,
744 RF_8225,
745 RF_8256,
746 RF_8258,
747 RF_PSEUDO_11N = 4,
748 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
749
750
751 typedef struct _rate_adaptive
752 {
753 u8 rate_adaptive_disabled;
754 u8 ratr_state;
755 u16 reserve;
756
757 u32 high_rssi_thresh_for_ra;
758 u32 high2low_rssi_thresh_for_ra;
759 u8 low2high_rssi_thresh_for_ra40M;
760 u32 low_rssi_thresh_for_ra40M;
761 u8 low2high_rssi_thresh_for_ra20M;
762 u32 low_rssi_thresh_for_ra20M;
763 u32 upper_rssi_threshold_ratr;
764 u32 middle_rssi_threshold_ratr;
765 u32 low_rssi_threshold_ratr;
766 u32 low_rssi_threshold_ratr_40M;
767 u32 low_rssi_threshold_ratr_20M;
768 u8 ping_rssi_enable; //cosa add for test
769 u32 ping_rssi_ratr; //cosa add for test
770 u32 ping_rssi_thresh_for_ra;//cosa add for test
771 u32 last_ratr;
772
773 } rate_adaptive, *prate_adaptive;
774 #define TxBBGainTableLength 37
775 #define CCKTxBBGainTableLength 23
776 typedef struct _txbbgain_struct
777 {
778 long txbb_iq_amplifygain;
779 u32 txbbgain_value;
780 } txbbgain_struct, *ptxbbgain_struct;
781
782 typedef struct _ccktxbbgain_struct
783 {
784 //The Value is from a22 to a29 one Byte one time is much Safer
785 u8 ccktxbb_valuearray[8];
786 } ccktxbbgain_struct,*pccktxbbgain_struct;
787
788
789 typedef struct _init_gain
790 {
791 u8 xaagccore1;
792 u8 xbagccore1;
793 u8 xcagccore1;
794 u8 xdagccore1;
795 u8 cca;
796
797 } init_gain, *pinit_gain;
798
799 /* 2007/11/02 MH Define RF mode temporarily for test. */
800 typedef enum tag_Rf_Operatetion_State
801 {
802 RF_STEP_INIT = 0,
803 RF_STEP_NORMAL,
804 RF_STEP_MAX
805 }RF_STEP_E;
806
807 typedef enum _RT_STATUS{
808 RT_STATUS_SUCCESS,
809 RT_STATUS_FAILURE,
810 RT_STATUS_PENDING,
811 RT_STATUS_RESOURCE
812 }RT_STATUS,*PRT_STATUS;
813
814 typedef enum _RT_CUSTOMER_ID
815 {
816 RT_CID_DEFAULT = 0,
817 RT_CID_8187_ALPHA0 = 1,
818 RT_CID_8187_SERCOMM_PS = 2,
819 RT_CID_8187_HW_LED = 3,
820 RT_CID_8187_NETGEAR = 4,
821 RT_CID_WHQL = 5,
822 RT_CID_819x_CAMEO = 6,
823 RT_CID_819x_RUNTOP = 7,
824 RT_CID_819x_Senao = 8,
825 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
826 RT_CID_819x_Netcore = 10,
827 RT_CID_Nettronix = 11,
828 RT_CID_DLINK = 12,
829 RT_CID_PRONET = 13,
830 RT_CID_COREGA = 14,
831 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
832
833 //================================================================================
834 // LED customization.
835 //================================================================================
836
837 typedef enum _LED_STRATEGY_8190{
838 SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
839 SW_LED_MODE1, // SW control for PCI Express
840 SW_LED_MODE2, // SW control for Cameo.
841 SW_LED_MODE3, // SW contorl for RunTop.
842 SW_LED_MODE4, // SW control for Netcore
843 SW_LED_MODE5, //added by vivi, for led new mode, DLINK
844 SW_LED_MODE6, //added by vivi, for led new mode, PRONET
845 HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
846 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
847
848 #define CHANNEL_PLAN_LEN 10
849
850 #define sCrcLng 4
851
852 typedef struct _TX_FWINFO_STRUCUTRE{
853 //DOWRD 0
854 u8 TxRate:7;
855 u8 CtsEnable:1;
856 u8 RtsRate:7;
857 u8 RtsEnable:1;
858 u8 TxHT:1;
859 u8 Short:1;
860 u8 TxBandwidth:1;
861 u8 TxSubCarrier:2;
862 u8 STBC:2;
863 u8 AllowAggregation:1;
864 u8 RtsHT:1;
865 u8 RtsShort:1;
866 u8 RtsBandwidth:1;
867 u8 RtsSubcarrier:2;
868 u8 RtsSTBC:2;
869 u8 EnableCPUDur:1;
870
871 //DWORD 1
872 u32 RxMF:2;
873 u32 RxAMD:3;
874 u32 Reserved1:3;
875 u32 TxAGCOffset:4;
876 u32 TxAGCSign:1;
877 u32 Tx_INFO_RSVD:6;
878 u32 PacketID:13;
879 }TX_FWINFO_T;
880
881
882 typedef struct _TX_FWINFO_8190PCI{
883 //DOWRD 0
884 u8 TxRate:7;
885 u8 CtsEnable:1;
886 u8 RtsRate:7;
887 u8 RtsEnable:1;
888 u8 TxHT:1;
889 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
890 u8 TxBandwidth:1; // This is used for HT MCS rate only.
891 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
892 u8 STBC:2;
893 u8 AllowAggregation:1;
894 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
895 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
896 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
897 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
898 u8 RtsSTBC:2;
899 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
900
901 //DWORD 1
902 u32 RxMF:2;
903 u32 RxAMD:3;
904 u32 TxPerPktInfoFeedback:1; // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd.
905 u32 Reserved1:2;
906 u32 TxAGCOffset:4; // Only 90 support
907 u32 TxAGCSign:1; // Only 90 support
908 u32 RAW_TXD:1; // MAC will send data in txpktbuffer without any processing,such as CRC check
909 u32 Retry_Limit:4; // CCX Support relative retry limit FW page only support 4 bits now.
910 u32 Reserved2:1;
911 u32 PacketID:13;
912
913 // DW 2
914
915 }TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
916
917 typedef struct _phy_ofdm_rx_status_report_819xpci
918 {
919 u8 trsw_gain_X[4];
920 u8 pwdb_all;
921 u8 cfosho_X[4];
922 u8 cfotail_X[4];
923 u8 rxevm_X[2];
924 u8 rxsnr_X[4];
925 u8 pdsnr_X[2];
926 u8 csi_current_X[2];
927 u8 csi_target_X[2];
928 u8 sigevm;
929 u8 max_ex_pwr;
930 u8 sgi_en;
931 u8 rxsc_sgien_exflg;
932 }phy_sts_ofdm_819xpci_t;
933
934 typedef struct _phy_cck_rx_status_report_819xpci
935 {
936 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
937 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
938 u8 adc_pwdb_X[4];
939 u8 sq_rpt;
940 u8 cck_agc_rpt;
941 }phy_sts_cck_819xpci_t;
942
943 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
944 u8 reserved:4;
945 u8 rxsc:2;
946 u8 sgi_en:1;
947 u8 ex_intf_flag:1;
948 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
949
950 typedef enum _RT_OP_MODE{
951 RT_OP_MODE_AP,
952 RT_OP_MODE_INFRASTRUCTURE,
953 RT_OP_MODE_IBSS,
954 RT_OP_MODE_NO_LINK,
955 }RT_OP_MODE, *PRT_OP_MODE;
956
957
958 /* 2007/11/02 MH Define RF mode temporarily for test. */
959 typedef enum tag_Rf_OpType
960 {
961 RF_OP_By_SW_3wire = 0,
962 RF_OP_By_FW,
963 RF_OP_MAX
964 }RF_OpType_E;
965
966 typedef enum _RESET_TYPE {
967 RESET_TYPE_NORESET = 0x00,
968 RESET_TYPE_NORMAL = 0x01,
969 RESET_TYPE_SILENT = 0x02
970 } RESET_TYPE;
971
972 typedef struct _tx_ring{
973 u32 * desc;
974 u8 nStuckCount;
975 struct _tx_ring * next;
976 }__attribute__ ((packed)) tx_ring, * ptx_ring;
977
978 struct rtl8192_tx_ring {
979 tx_desc_819x_pci *desc;
980 dma_addr_t dma;
981 unsigned int idx;
982 unsigned int entries;
983 struct sk_buff_head queue;
984 };
985
986 #define NIC_SEND_HANG_THRESHOLD_NORMAL 4
987 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8
988 #define MAX_TX_QUEUE 9 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
989
990 #define MAX_RX_COUNT 64
991 #define MAX_TX_QUEUE_COUNT 9
992
993 typedef struct r8192_priv
994 {
995 struct pci_dev *pdev;
996 //added for maintain info from eeprom
997 short epromtype;
998 u16 eeprom_vid;
999 u16 eeprom_did;
1000 u8 eeprom_CustomerID;
1001 u16 eeprom_ChannelPlan;
1002 RT_CUSTOMER_ID CustomerID;
1003 LED_STRATEGY_8190 LedStrategy;
1004 //bool bDcut;
1005 u8 IC_Cut;
1006 int irq;
1007 short irq_enabled;
1008 struct ieee80211_device *ieee80211;
1009 bool being_init_adapter;
1010 u8 Rf_Mode;
1011 short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
1012 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
1013 // short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
1014 short enable_gpio0;
1015 enum card_type {PCI,MINIPCI,CARDBUS,USB/*rtl8187*/}card_type;
1016 short hw_plcp_len;
1017 short plcp_preamble_mode;
1018 u8 ScanDelay;
1019 spinlock_t irq_lock;
1020 spinlock_t irq_th_lock;
1021 spinlock_t tx_lock;
1022 spinlock_t rf_ps_lock;
1023 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16))
1024 struct semaphore mutex;
1025 #else
1026 struct mutex mutex;
1027 #endif
1028 spinlock_t rf_lock; //used to lock rf write operation added by wb
1029 spinlock_t ps_lock;
1030
1031 u32 irq_mask;
1032 // short irq_enabled;
1033 // struct net_device *dev; //comment this out.
1034 short chan;
1035 short sens;
1036 short max_sens;
1037 u32 rx_prevlen;
1038 /*RX stuff*/
1039 rx_desc_819x_pci *rx_ring;
1040 dma_addr_t rx_ring_dma;
1041 unsigned int rx_idx;
1042 struct sk_buff *rx_buf[MAX_RX_COUNT];
1043 int rxringcount;
1044 u16 rxbuffersize;
1045
1046
1047 struct sk_buff *rx_skb;
1048 u32 *rxring;
1049 u32 *rxringtail;
1050 dma_addr_t rxringdma;
1051 struct buffer *rxbuffer;
1052 struct buffer *rxbufferhead;
1053 short rx_skb_complete;
1054 /*TX stuff*/
1055 struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
1056 int txringcount;
1057 //{
1058 int txbuffsize;
1059 int txfwbuffersize;
1060 //struct tx_pendingbuf txnp_pending;
1061 //struct tasklet_struct irq_tx_tasklet;
1062 struct tasklet_struct irq_rx_tasklet;
1063 struct tasklet_struct irq_tx_tasklet;
1064 struct tasklet_struct irq_prepare_beacon_tasklet;
1065 struct buffer *txmapbufs;
1066 struct buffer *txbkpbufs;
1067 struct buffer *txbepbufs;
1068 struct buffer *txvipbufs;
1069 struct buffer *txvopbufs;
1070 struct buffer *txcmdbufs;
1071 struct buffer *txmapbufstail;
1072 struct buffer *txbkpbufstail;
1073 struct buffer *txbepbufstail;
1074 struct buffer *txvipbufstail;
1075 struct buffer *txvopbufstail;
1076 struct buffer *txcmdbufstail;
1077 /* adhoc/master mode stuff */
1078 ptx_ring txbeaconringtail;
1079 dma_addr_t txbeaconringdma;
1080 ptx_ring txbeaconring;
1081 int txbeaconcount;
1082 struct buffer *txbeaconbufs;
1083 struct buffer *txbeaconbufstail;
1084 ptx_ring txmapring;
1085 ptx_ring txbkpring;
1086 ptx_ring txbepring;
1087 ptx_ring txvipring;
1088 ptx_ring txvopring;
1089 ptx_ring txcmdring;
1090 ptx_ring txmapringtail;
1091 ptx_ring txbkpringtail;
1092 ptx_ring txbepringtail;
1093 ptx_ring txvipringtail;
1094 ptx_ring txvopringtail;
1095 ptx_ring txcmdringtail;
1096 ptx_ring txmapringhead;
1097 ptx_ring txbkpringhead;
1098 ptx_ring txbepringhead;
1099 ptx_ring txvipringhead;
1100 ptx_ring txvopringhead;
1101 ptx_ring txcmdringhead;
1102 dma_addr_t txmapringdma;
1103 dma_addr_t txbkpringdma;
1104 dma_addr_t txbepringdma;
1105 dma_addr_t txvipringdma;
1106 dma_addr_t txvopringdma;
1107 dma_addr_t txcmdringdma;
1108 // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1109 // u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1110 // u8 cck_txpwr_base;
1111 // u8 ofdm_txpwr_base;
1112 // u8 challow[15]; //channels from 1 to 14, 0 not used
1113 short up;
1114 short crcmon; //if 1 allow bad crc frame reception in monitor mode
1115 // short prism_hdr;
1116
1117 // struct timer_list scan_timer;
1118 /*short scanpending;
1119 short stopscan;*/
1120 // spinlock_t scan_lock;
1121 // u8 active_probe;
1122 //u8 active_scan_num;
1123 struct semaphore wx_sem;
1124 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1125 // short hw_wep;
1126
1127 // short digphy;
1128 // short antb;
1129 // short diversity;
1130 // u8 cs_treshold;
1131 // short rcr_csense;
1132 u8 rf_type; //0 means 1T2R, 1 means 2T4R
1133 RT_RF_TYPE_819xU rf_chip;
1134
1135 // u32 key0[4];
1136 short (*rf_set_sens)(struct net_device *dev,short sens);
1137 u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1138 void (*rf_close)(struct net_device *dev);
1139 void (*rf_init)(struct net_device *dev);
1140 //short rate;
1141 short promisc;
1142 /*stats*/
1143 struct Stats stats;
1144 struct iw_statistics wstats;
1145 struct proc_dir_entry *dir_dev;
1146
1147 /*RX stuff*/
1148 // u32 *rxring;
1149 // u32 *rxringtail;
1150 // dma_addr_t rxringdma;
1151
1152 #ifdef THOMAS_BEACON
1153 u32 *oldaddr;
1154 #endif
1155 #ifdef THOMAS_TASKLET
1156 atomic_t irt_counter;//count for irq_rx_tasklet
1157 #endif
1158 #ifdef JACKSON_NEW_RX
1159 struct sk_buff **pp_rxskb;
1160 int rx_inx;
1161 #endif
1162
1163 /* modified by davad for Rx process */
1164 struct sk_buff_head rx_queue;
1165 struct sk_buff_head skb_queue;
1166 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0))
1167 struct tq_struct qos_activate;
1168 #else
1169 struct work_struct qos_activate;
1170 #endif
1171 short tx_urb_index;
1172 atomic_t tx_pending[0x10];//UART_PRIORITY+1
1173
1174 struct urb *rxurb_task;
1175
1176 //2 Tx Related variables
1177 u16 ShortRetryLimit;
1178 u16 LongRetryLimit;
1179 u32 TransmitConfig;
1180 u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1181
1182 u32 LastRxDescTSFHigh;
1183 u32 LastRxDescTSFLow;
1184
1185
1186 //2 Rx Related variables
1187 u16 EarlyRxThreshold;
1188 u32 ReceiveConfig;
1189 u8 AcmControl;
1190
1191 u8 RFProgType;
1192
1193 u8 retry_data;
1194 u8 retry_rts;
1195 u16 rts;
1196
1197 struct ChnlAccessSetting ChannelAccessSetting;
1198
1199 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1200 struct work_struct reset_wq;
1201 #else
1202 struct tq_struct reset_wq;
1203 #endif
1204
1205 /**********************************************************/
1206 //for rtl819xPci
1207 // Data Rate Config. Added by Annie, 2006-04-13.
1208 u16 basic_rate;
1209 u8 short_preamble;
1210 u8 slot_time;
1211 u16 SifsTime;
1212 /* WirelessMode*/
1213 u8 RegWirelessMode;
1214 /*Firmware*/
1215 prt_firmware pFirmware;
1216 rtl819x_loopback_e LoopbackMode;
1217 firmware_source_e firmware_source;
1218 bool AutoloadFailFlag;
1219 u16 EEPROMTxPowerDiff;
1220 u16 EEPROMAntPwDiff; // Antenna gain offset from B/C/D to A
1221 u8 EEPROMThermalMeter;
1222 u8 EEPROMPwDiff;
1223 u8 EEPROMCrystalCap;
1224 u8 EEPROM_Def_Ver;
1225 u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14
1226 // The following definition is for eeprom 93c56
1227 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1228 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1229 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
1230 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1231 u8 EEPROMTxPowerLevelCCK_V1[3];
1232 u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1233 u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1234 u8 EEPROMLegacyHTTxPowerDiff; // Legacy to HT rate power diff
1235 bool bTXPowerDataReadFromEEPORM;
1236 /*channel plan*/
1237 u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user.
1238 u16 ChannelPlan;
1239 /*PS related*/
1240 bool RegRfOff;
1241 // Rf off action for power save
1242 u8 bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable
1243 /*PHY related*/
1244 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1245 // Read/write are allow for following hardware information variables
1246 u32 MCSTxPowerLevelOriginalOffset[6];
1247 u32 CCKTxPowerLevelOriginalOffset;
1248 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1249 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
1250 u8 TxPowerLevelCCK_C[14];
1251 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1252 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1253 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
1254 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
1255 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
1256 u8 TxPowerDiff;
1257 char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a
1258 u8 AntennaTxPwDiff[3]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1259 u8 CrystalCap; // CrystalCap.
1260 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1261 //05/27/2008 cck power enlarge
1262 u8 CckPwEnl;
1263 u16 TSSI_13dBm;
1264 u32 Pwr_Track;
1265 u8 CCKPresentAttentuation_20Mdefault;
1266 u8 CCKPresentAttentuation_40Mdefault;
1267 char CCKPresentAttentuation_difference;
1268 char CCKPresentAttentuation;
1269 // Use to calculate PWBD.
1270 u8 bCckHighPower;
1271 long undecorated_smoothed_pwdb;
1272 long undecorated_smoothed_cck_adc_pwdb[4];
1273 //for set channel
1274 u8 SwChnlInProgress;
1275 u8 SwChnlStage;
1276 u8 SwChnlStep;
1277 u8 SetBWModeInProgress;
1278 HT_CHANNEL_WIDTH CurrentChannelBW;
1279
1280 // 8190 40MHz mode
1281 //
1282 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1283 // Joseph test for shorten RF configuration time.
1284 // We save RF reg0 in this variable to reduce RF reading.
1285 //
1286 u32 RfReg0Value[4];
1287 u8 NumTotalRFPath;
1288 bool brfpath_rxenable[4];
1289 //+by amy 080507
1290 struct timer_list watch_dog_timer;
1291
1292 //+by amy 080515 for dynamic mechenism
1293 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1294 bool bdynamic_txpower; //bDynamicTxPower
1295 bool bDynamicTxHighPower; // Tx high power state
1296 bool bDynamicTxLowPower; // Tx low power state
1297 bool bLastDTPFlag_High;
1298 bool bLastDTPFlag_Low;
1299
1300 bool bstore_last_dtpflag;
1301 bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1302 //Add by amy for Rate Adaptive
1303 rate_adaptive rate_adaptive;
1304 //Add by amy for TX power tracking
1305 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1306 txbbgain_struct txbbgain_table[TxBBGainTableLength];
1307 u8 txpower_count;//For 6 sec do tracking again
1308 bool btxpower_trackingInit;
1309 u8 OFDM_index;
1310 u8 CCK_index;
1311 u8 Record_CCK_20Mindex;
1312 u8 Record_CCK_40Mindex;
1313 //2007/09/10 Mars Add CCK TX Power Tracking
1314 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1315 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1316 u8 rfa_txpowertrackingindex;
1317 u8 rfa_txpowertrackingindex_real;
1318 u8 rfa_txpowertracking_default;
1319 u8 rfc_txpowertrackingindex;
1320 u8 rfc_txpowertrackingindex_real;
1321 u8 rfc_txpowertracking_default;
1322 bool btxpower_tracking;
1323 bool bcck_in_ch14;
1324
1325 //For Backup Initial Gain
1326 init_gain initgain_backup;
1327 u8 DefaultInitialGain[4];
1328 // For EDCA Turbo mode, Added by amy 080515.
1329 bool bis_any_nonbepkts;
1330 bool bcurrent_turbo_EDCA;
1331
1332 bool bis_cur_rdlstate;
1333 struct timer_list fsync_timer;
1334 bool bfsync_processing; // 500ms Fsync timer is active or not
1335 u32 rate_record;
1336 u32 rateCountDiffRecord;
1337 u32 ContiuneDiffCount;
1338 bool bswitch_fsync;
1339
1340 u8 framesync;
1341 u32 framesyncC34;
1342 u8 framesyncMonitor;
1343 //Added by amy 080516 for RX related
1344 u16 nrxAMPDU_size;
1345 u8 nrxAMPDU_aggr_num;
1346
1347 /*Last RxDesc TSF value*/
1348 u32 last_rxdesc_tsf_high;
1349 u32 last_rxdesc_tsf_low;
1350
1351 //by amy for gpio
1352 bool bHwRadioOff;
1353 //by amy for ps
1354 bool RFChangeInProgress; // RF Chnage in progress, by Bruce, 2007-10-30
1355 bool SetRFPowerStateInProgress;
1356 RT_OP_MODE OpMode;
1357 //by amy for reset_count
1358 u32 reset_count;
1359 bool bpbc_pressed;
1360 //by amy for debug
1361 u32 txpower_checkcnt;
1362 u32 txpower_tracking_callback_cnt;
1363 u8 thermal_read_val[40];
1364 u8 thermal_readback_index;
1365 u32 ccktxpower_adjustcnt_not_ch14;
1366 u32 ccktxpower_adjustcnt_ch14;
1367 u8 tx_fwinfo_force_subcarriermode;
1368 u8 tx_fwinfo_force_subcarrierval;
1369
1370 //by amy for silent reset
1371 RESET_TYPE ResetProgress;
1372 bool bForcedSilentReset;
1373 bool bDisableNormalResetCheck;
1374 u16 TxCounter;
1375 u16 RxCounter;
1376 int IrpPendingCount;
1377 bool bResetInProgress;
1378 bool force_reset;
1379 u8 InitialGainOperateType;
1380
1381 //define work item by amy 080526
1382 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
1383 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
1384 struct delayed_work update_beacon_wq;
1385 struct delayed_work watch_dog_wq;
1386 struct delayed_work txpower_tracking_wq;
1387 struct delayed_work rfpath_check_wq;
1388 struct delayed_work gpio_change_rf_wq;
1389 struct delayed_work initialgain_operate_wq;
1390 #else
1391 struct work_struct update_beacon_wq;
1392 struct work_struct watch_dog_wq;
1393 struct work_struct txpower_tracking_wq;
1394 struct work_struct rfpath_check_wq;
1395 struct work_struct gpio_change_rf_wq;
1396 struct work_struct initialgain_operate_wq;
1397 #endif
1398 struct workqueue_struct *priv_wq;
1399 #else
1400 struct tq_struct update_beacon_wq;
1401 /* used for periodly scan */
1402 struct tq_struct txpower_tracking_wq;
1403 struct tq_struct rfpath_check_wq;
1404 struct tq_struct watch_dog_wq;
1405 struct tq_struct gpio_change_rf_wq;
1406 struct tq_struct initialgain_operate_wq;
1407 #endif
1408 }r8192_priv;
1409
1410 // for rtl8187
1411 // now mirging to rtl8187B
1412 /*
1413 typedef enum{
1414 LOW_PRIORITY = 0x02,
1415 NORM_PRIORITY
1416 } priority_t;
1417 */
1418 //for rtl8187B
1419 #if 0
1420 typedef enum{
1421 BULK_PRIORITY = 0x01,
1422 //RSVD0,
1423 //RSVD1,
1424 LOW_PRIORITY,
1425 NORM_PRIORITY,
1426 VO_PRIORITY,
1427 VI_PRIORITY, //0x05
1428 BE_PRIORITY,
1429 BK_PRIORITY,
1430 CMD_PRIORITY,//0x8
1431 RSVD3,
1432 BEACON_PRIORITY, //0x0A
1433 HIGH_PRIORITY,
1434 MANAGE_PRIORITY,
1435 RSVD4,
1436 RSVD5,
1437 UART_PRIORITY //0x0F
1438 } priority_t;
1439 #endif
1440 typedef enum{
1441 NIC_8192E = 1,
1442 } nic_t;
1443
1444
1445 #if 0 //defined in Qos.h
1446 //typedef u32 AC_CODING;
1447 #define AC0_BE 0 // ACI: 0x00 // Best Effort
1448 #define AC1_BK 1 // ACI: 0x01 // Background
1449 #define AC2_VI 2 // ACI: 0x10 // Video
1450 #define AC3_VO 3 // ACI: 0x11 // Voice
1451 #define AC_MAX 4 // Max: define total number; Should not to be used as a real enum.
1452
1453 //
1454 // ECWmin/ECWmax field.
1455 // Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
1456 //
1457 typedef union _ECW{
1458 u8 charData;
1459 struct
1460 {
1461 u8 ECWmin:4;
1462 u8 ECWmax:4;
1463 }f; // Field
1464 }ECW, *PECW;
1465
1466 //
1467 // ACI/AIFSN Field.
1468 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
1469 //
1470 typedef union _ACI_AIFSN{
1471 u8 charData;
1472
1473 struct
1474 {
1475 u8 AIFSN:4;
1476 u8 ACM:1;
1477 u8 ACI:2;
1478 u8 Reserved:1;
1479 }f; // Field
1480 }ACI_AIFSN, *PACI_AIFSN;
1481
1482 //
1483 // AC Parameters Record Format.
1484 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
1485 //
1486 typedef union _AC_PARAM{
1487 u32 longData;
1488 u8 charData[4];
1489
1490 struct
1491 {
1492 ACI_AIFSN AciAifsn;
1493 ECW Ecw;
1494 u16 TXOPLimit;
1495 }f; // Field
1496 }AC_PARAM, *PAC_PARAM;
1497
1498 #endif
1499 bool init_firmware(struct net_device *dev);
1500 void rtl819xE_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1501 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1502 u32 read_cam(struct net_device *dev, u8 addr);
1503 void write_cam(struct net_device *dev, u8 addr, u32 data);
1504 u8 read_nic_byte(struct net_device *dev, int x);
1505 u8 read_nic_byte_E(struct net_device *dev, int x);
1506 u32 read_nic_dword(struct net_device *dev, int x);
1507 u16 read_nic_word(struct net_device *dev, int x) ;
1508 void write_nic_byte(struct net_device *dev, int x,u8 y);
1509 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1510 void write_nic_word(struct net_device *dev, int x,u16 y);
1511 void write_nic_dword(struct net_device *dev, int x,u32 y);
1512 void force_pci_posting(struct net_device *dev);
1513
1514 void rtl8192_rtx_disable(struct net_device *);
1515 void rtl8192_rx_enable(struct net_device *);
1516 void rtl8192_tx_enable(struct net_device *);
1517
1518 void rtl8192_disassociate(struct net_device *dev);
1519 //void fix_rx_fifo(struct net_device *dev);
1520 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1521
1522 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1523 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1524 void rtl8192_update_msr(struct net_device *dev);
1525 int rtl8192_down(struct net_device *dev);
1526 int rtl8192_up(struct net_device *dev);
1527 void rtl8192_commit(struct net_device *dev);
1528 void rtl8192_set_chan(struct net_device *dev,short ch);
1529 void write_phy(struct net_device *dev, u8 adr, u8 data);
1530 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1531 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1532 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1533 void rtl8187_set_rxconf(struct net_device *dev);
1534 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1535 void rtl8192_start_beacon(struct net_device *dev);
1536 void CamResetAllEntry(struct net_device* dev);
1537 void EnableHWSecurityConfig8192(struct net_device *dev);
1538 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1539 void CamPrintDbgReg(struct net_device* dev);
1540 extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
1541 extern void firmware_init_param(struct net_device *dev);
1542 extern RT_STATUS cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
1543 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
1544 void rtl8192_hw_wakeup_wq (struct work_struct *work);
1545 #else
1546 void rtl8192_hw_wakeup_wq(struct net_device *dev);
1547 #endif
1548
1549 short rtl8192_is_tx_queue_empty(struct net_device *dev);
1550 #ifdef ENABLE_IPS
1551 void IPSEnter(struct net_device *dev);
1552 void IPSLeave(struct net_device *dev);
1553 #endif
1554 #endif
Linux kernel - Deliverables
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