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Staging: rtl8192e: Remove unused struct members
[deliverable/linux.git] / drivers / staging / rtl8192e / r8192E_dm.c
1 /*++
2 Copyright-c Realtek Semiconductor Corp. All rights reserved.
3
4 Module Name:
5 r8192U_dm.c
6
7 Abstract:
8 HW dynamic mechanism.
9
10 Major Change History:
11 When Who What
12 ---------- --------------- -------------------------------
13 2008-05-14 amy create version 0 porting from windows code.
14
15 --*/
16 #include "r8192E.h"
17 #include "r8192E_dm.h"
18 #include "r8192E_hw.h"
19 #include "r819xE_phy.h"
20 #include "r819xE_phyreg.h"
21 #include "r8190_rtl8256.h"
22
23 #define DRV_NAME "rtl819xE"
24
25 //
26 // Indicate different AP vendor for IOT issue.
27 //
28 #ifdef RTL8190P
29 static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
30 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
31 static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
32 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
33 #else
34 #ifdef RTL8192E
35 static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
36 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5e4322, 0x5e4322};
37 static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
38 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5e4322, 0x5e4322, 0x5e4322};
39 #else
40 static const u32 edca_setting_DL[HT_IOT_PEER_MAX] =
41 { 0x5e4322, 0x5e4322, 0x5e4322, 0x604322, 0xa44f, 0x5ea44f, 0x5e4322};
42 static const u32 edca_setting_UL[HT_IOT_PEER_MAX] =
43 { 0x5e4322, 0xa44f, 0x5e4322, 0x604322, 0x5ea44f, 0x5ea44f, 0x5e4322};
44 #endif
45 #endif
46
47 #define RTK_UL_EDCA 0xa44f
48 #define RTK_DL_EDCA 0x5e4322
49
50
51 dig_t dm_digtable;
52 // For Dynamic Rx Path Selection by Signal Strength
53 DRxPathSel DM_RxPathSelTable;
54
55
56 /*--------------------Define export function prototype-----------------------*/
57 extern void init_hal_dm(struct net_device *dev);
58 extern void deinit_hal_dm(struct net_device *dev);
59
60 extern void hal_dm_watchdog(struct net_device *dev);
61
62
63 extern void init_rate_adaptive(struct net_device *dev);
64 extern void dm_txpower_trackingcallback(struct work_struct *work);
65
66 extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
67 extern void dm_restore_dynamic_mechanism_state(struct net_device *dev);
68 extern void dm_backup_dynamic_mechanism_state(struct net_device *dev);
69 extern void dm_change_dynamic_initgain_thresh(struct net_device *dev,
70 u32 dm_type,
71 u32 dm_value);
72 extern void DM_ChangeFsyncSetting(struct net_device *dev,
73 s32 DM_Type,
74 s32 DM_Value);
75 extern void dm_force_tx_fw_info(struct net_device *dev,
76 u32 force_type,
77 u32 force_value);
78 extern void dm_init_edca_turbo(struct net_device *dev);
79 extern void dm_rf_operation_test_callback(unsigned long data);
80 extern void dm_rf_pathcheck_workitemcallback(struct work_struct *work);
81 extern void dm_fsync_timer_callback(unsigned long data);
82 extern void dm_check_fsync(struct net_device *dev);
83 extern void dm_initialize_txpower_tracking(struct net_device *dev);
84
85 #ifdef RTL8192E
86 extern void dm_gpio_change_rf_callback(struct work_struct *work);
87 #endif
88
89
90 // DM --> Rate Adaptive
91 static void dm_check_rate_adaptive(struct net_device *dev);
92
93 // DM --> Bandwidth switch
94 static void dm_init_bandwidth_autoswitch(struct net_device *dev);
95 static void dm_bandwidth_autoswitch( struct net_device *dev);
96
97 // DM --> TX power control
98 static void dm_check_txpower_tracking(struct net_device *dev);
99
100 // DM --> BB init gain restore
101 #ifndef RTL8192U
102 static void dm_bb_initialgain_restore(struct net_device *dev);
103
104 // DM --> BB init gain backup
105 static void dm_bb_initialgain_backup(struct net_device *dev);
106 #endif
107
108 // DM --> Dynamic Init Gain by RSSI
109 static void dm_dig_init(struct net_device *dev);
110 static void dm_ctrl_initgain_byrssi(struct net_device *dev);
111 static void dm_ctrl_initgain_byrssi_highpwr(struct net_device *dev);
112 static void dm_ctrl_initgain_byrssi_by_driverrssi( struct net_device *dev);
113 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(struct net_device *dev);
114 static void dm_initial_gain(struct net_device *dev);
115 static void dm_pd_th(struct net_device *dev);
116 static void dm_cs_ratio(struct net_device *dev);
117
118 static void dm_init_ctstoself(struct net_device *dev);
119 // DM --> EDCA turboe mode control
120 static void dm_check_edca_turbo(struct net_device *dev);
121
122 // DM --> HW RF control
123 static void dm_check_rfctrl_gpio(struct net_device *dev);
124
125 // DM --> Check PBC
126 static void dm_check_pbc_gpio(struct net_device *dev);
127
128 // DM --> Check current RX RF path state
129 static void dm_check_rx_path_selection(struct net_device *dev);
130 static void dm_init_rxpath_selection(struct net_device *dev);
131 static void dm_rxpath_sel_byrssi(struct net_device *dev);
132
133 // DM --> Fsync for broadcom ap
134 static void dm_init_fsync(struct net_device *dev);
135 static void dm_deInit_fsync(struct net_device *dev);
136
137 static void dm_check_txrateandretrycount(struct net_device *dev);
138
139
140 /*---------------------Define of Tx Power Control For Near/Far Range --------*/ //Add by Jacken 2008/02/18
141 static void dm_init_dynamic_txpower(struct net_device *dev);
142 static void dm_dynamic_txpower(struct net_device *dev);
143
144 // DM --> For rate adaptive and DIG, we must send RSSI to firmware
145 static void dm_send_rssi_tofw(struct net_device *dev);
146 static void dm_ctstoself(struct net_device *dev);
147
148 /*
149 * Prepare SW resource for HW dynamic mechanism.
150 * This function is only invoked at driver intialization once.
151 */
152 void init_hal_dm(struct net_device *dev)
153 {
154 struct r8192_priv *priv = ieee80211_priv(dev);
155
156 // Undecorated Smoothed Signal Strength, it can utilized to dynamic mechanism.
157 priv->undecorated_smoothed_pwdb = -1;
158
159 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
160 dm_init_dynamic_txpower(dev);
161 init_rate_adaptive(dev);
162 //dm_initialize_txpower_tracking(dev);
163 dm_dig_init(dev);
164 dm_init_edca_turbo(dev);
165 dm_init_bandwidth_autoswitch(dev);
166 dm_init_fsync(dev);
167 dm_init_rxpath_selection(dev);
168 dm_init_ctstoself(dev);
169 #ifdef RTL8192E
170 INIT_DELAYED_WORK(&priv->gpio_change_rf_wq, dm_gpio_change_rf_callback);
171 #endif
172
173 }
174
175 void deinit_hal_dm(struct net_device *dev)
176 {
177
178 dm_deInit_fsync(dev);
179
180 }
181
182
183 #ifdef USB_RX_AGGREGATION_SUPPORT
184 void dm_CheckRxAggregation(struct net_device *dev) {
185 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
186 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
187 static unsigned long lastTxOkCnt = 0;
188 static unsigned long lastRxOkCnt = 0;
189 unsigned long curTxOkCnt = 0;
190 unsigned long curRxOkCnt = 0;
191
192 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
193 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
194
195 if((curTxOkCnt + curRxOkCnt) < 15000000) {
196 return;
197 }
198
199 if(curTxOkCnt > 4*curRxOkCnt) {
200 if (priv->bCurrentRxAggrEnable) {
201 write_nic_dword(dev, 0x1a8, 0);
202 priv->bCurrentRxAggrEnable = false;
203 }
204 }else{
205 if (!priv->bCurrentRxAggrEnable && !pHTInfo->bCurrentRT2RTAggregation) {
206 u32 ulValue;
207 ulValue = (pHTInfo->UsbRxFwAggrEn<<24) | (pHTInfo->UsbRxFwAggrPageNum<<16) |
208 (pHTInfo->UsbRxFwAggrPacketNum<<8) | (pHTInfo->UsbRxFwAggrTimeout);
209 /*
210 * If usb rx firmware aggregation is enabled,
211 * when anyone of three threshold conditions above is reached,
212 * firmware will send aggregated packet to driver.
213 */
214 write_nic_dword(dev, 0x1a8, ulValue);
215 priv->bCurrentRxAggrEnable = true;
216 }
217 }
218
219 lastTxOkCnt = priv->stats.txbytesunicast;
220 lastRxOkCnt = priv->stats.rxbytesunicast;
221 }
222 #endif
223
224
225 // call the script file to enable
226 void dm_check_ac_dc_power(struct net_device *dev)
227 {
228 struct r8192_priv *priv = ieee80211_priv(dev);
229 static char *ac_dc_check_script_path = "/etc/acpi/wireless-rtl-ac-dc-power.sh";
230 char *argv[] = {ac_dc_check_script_path,DRV_NAME,NULL};
231 static char *envp[] = {"HOME=/",
232 "TERM=linux",
233 "PATH=/usr/bin:/bin",
234 NULL};
235
236 if(priv->ResetProgress == RESET_TYPE_SILENT)
237 {
238 RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF), "GPIOChangeRFWorkItemCallBack(): Silent Reseting!!!!!!!\n");
239 return;
240 }
241
242 if(priv->ieee80211->state != IEEE80211_LINKED) {
243 return;
244 }
245 call_usermodehelper(ac_dc_check_script_path,argv,envp,1);
246 }
247
248 void hal_dm_watchdog(struct net_device *dev)
249 {
250 dm_check_ac_dc_power(dev);
251
252 /*Add by amy 2008/05/15 ,porting from windows code.*/
253 dm_check_rate_adaptive(dev);
254 dm_dynamic_txpower(dev);
255 dm_check_txrateandretrycount(dev);
256
257 dm_check_txpower_tracking(dev);
258
259 dm_ctrl_initgain_byrssi(dev);
260 dm_check_edca_turbo(dev);
261 dm_bandwidth_autoswitch(dev);
262
263 dm_check_rfctrl_gpio(dev);
264 dm_check_rx_path_selection(dev);
265 dm_check_fsync(dev);
266
267 // Add by amy 2008-05-15 porting from windows code.
268 dm_check_pbc_gpio(dev);
269 dm_send_rssi_tofw(dev);
270 dm_ctstoself(dev);
271
272 #ifdef USB_RX_AGGREGATION_SUPPORT
273 dm_CheckRxAggregation(dev);
274 #endif
275 }
276
277
278 /*
279 * Decide Rate Adaptive Set according to distance (signal strength)
280 * 01/11/2008 MHC Modify input arguments and RATR table level.
281 * 01/16/2008 MHC RF_Type is assigned in ReadAdapterInfo(). We must call
282 * the function after making sure RF_Type.
283 */
284 void init_rate_adaptive(struct net_device * dev)
285 {
286
287 struct r8192_priv *priv = ieee80211_priv(dev);
288 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
289
290 pra->ratr_state = DM_RATR_STA_MAX;
291 pra->high2low_rssi_thresh_for_ra = RateAdaptiveTH_High;
292 pra->low2high_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M+5;
293 pra->low2high_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M+5;
294
295 pra->high_rssi_thresh_for_ra = RateAdaptiveTH_High+5;
296 pra->low_rssi_thresh_for_ra20M = RateAdaptiveTH_Low_20M;
297 pra->low_rssi_thresh_for_ra40M = RateAdaptiveTH_Low_40M;
298
299 if(priv->CustomerID == RT_CID_819x_Netcore)
300 pra->ping_rssi_enable = 1;
301 else
302 pra->ping_rssi_enable = 0;
303 pra->ping_rssi_thresh_for_ra = 15;
304
305
306 if (priv->rf_type == RF_2T4R)
307 {
308 // 07/10/08 MH Modify for RA smooth scheme.
309 /* 2008/01/11 MH Modify 2T RATR table for different RSSI. 080515 porting by amy from windows code.*/
310 pra->upper_rssi_threshold_ratr = 0x8f0f0000;
311 pra->middle_rssi_threshold_ratr = 0x8f0ff000;
312 pra->low_rssi_threshold_ratr = 0x8f0ff001;
313 pra->low_rssi_threshold_ratr_40M = 0x8f0ff005;
314 pra->low_rssi_threshold_ratr_20M = 0x8f0ff001;
315 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
316 }
317 else if (priv->rf_type == RF_1T2R)
318 {
319 pra->upper_rssi_threshold_ratr = 0x000f0000;
320 pra->middle_rssi_threshold_ratr = 0x000ff000;
321 pra->low_rssi_threshold_ratr = 0x000ff001;
322 pra->low_rssi_threshold_ratr_40M = 0x000ff005;
323 pra->low_rssi_threshold_ratr_20M = 0x000ff001;
324 pra->ping_rssi_ratr = 0x0000000d;//cosa add for test
325 }
326
327 }
328
329
330 static void dm_check_rate_adaptive(struct net_device * dev)
331 {
332 struct r8192_priv *priv = ieee80211_priv(dev);
333 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
334 prate_adaptive pra = (prate_adaptive)&priv->rate_adaptive;
335 u32 currentRATR, targetRATR = 0;
336 u32 LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0;
337 bool bshort_gi_enabled = false;
338 static u8 ping_rssi_state=0;
339
340
341 if(!priv->up)
342 {
343 RT_TRACE(COMP_RATE, "<---- dm_check_rate_adaptive(): driver is going to unload\n");
344 return;
345 }
346
347 if(pra->rate_adaptive_disabled)//this variable is set by ioctl.
348 return;
349
350 // TODO: Only 11n mode is implemented currently,
351 if( !(priv->ieee80211->mode == WIRELESS_MODE_N_24G ||
352 priv->ieee80211->mode == WIRELESS_MODE_N_5G))
353 return;
354
355 if( priv->ieee80211->state == IEEE80211_LINKED )
356 {
357 // RT_TRACE(COMP_RATE, "dm_CheckRateAdaptive(): \t");
358
359 //
360 // Check whether Short GI is enabled
361 //
362 bshort_gi_enabled = (pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI40MHz) ||
363 (!pHTInfo->bCurTxBW40MHz && pHTInfo->bCurShortGI20MHz);
364
365
366 pra->upper_rssi_threshold_ratr =
367 (pra->upper_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
368
369 pra->middle_rssi_threshold_ratr =
370 (pra->middle_rssi_threshold_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
371
372 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
373 {
374 pra->low_rssi_threshold_ratr =
375 (pra->low_rssi_threshold_ratr_40M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
376 }
377 else
378 {
379 pra->low_rssi_threshold_ratr =
380 (pra->low_rssi_threshold_ratr_20M & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
381 }
382 //cosa add for test
383 pra->ping_rssi_ratr =
384 (pra->ping_rssi_ratr & (~BIT31)) | ((bshort_gi_enabled)? BIT31:0) ;
385
386 /* 2007/10/08 MH We support RA smooth scheme now. When it is the first
387 time to link with AP. We will not change upper/lower threshold. If
388 STA stay in high or low level, we must change two different threshold
389 to prevent jumping frequently. */
390 if (pra->ratr_state == DM_RATR_STA_HIGH)
391 {
392 HighRSSIThreshForRA = pra->high2low_rssi_thresh_for_ra;
393 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
394 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
395 }
396 else if (pra->ratr_state == DM_RATR_STA_LOW)
397 {
398 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
399 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
400 (pra->low2high_rssi_thresh_for_ra40M):(pra->low2high_rssi_thresh_for_ra20M);
401 }
402 else
403 {
404 HighRSSIThreshForRA = pra->high_rssi_thresh_for_ra;
405 LowRSSIThreshForRA = (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)?
406 (pra->low_rssi_thresh_for_ra40M):(pra->low_rssi_thresh_for_ra20M);
407 }
408
409 if(priv->undecorated_smoothed_pwdb >= (long)HighRSSIThreshForRA)
410 {
411 pra->ratr_state = DM_RATR_STA_HIGH;
412 targetRATR = pra->upper_rssi_threshold_ratr;
413 }else if(priv->undecorated_smoothed_pwdb >= (long)LowRSSIThreshForRA)
414 {
415 pra->ratr_state = DM_RATR_STA_MIDDLE;
416 targetRATR = pra->middle_rssi_threshold_ratr;
417 }else
418 {
419 pra->ratr_state = DM_RATR_STA_LOW;
420 targetRATR = pra->low_rssi_threshold_ratr;
421 }
422
423 //cosa add for test
424 if(pra->ping_rssi_enable)
425 {
426 //pHalData->UndecoratedSmoothedPWDB = 19;
427 if(priv->undecorated_smoothed_pwdb < (long)(pra->ping_rssi_thresh_for_ra+5))
428 {
429 if( (priv->undecorated_smoothed_pwdb < (long)pra->ping_rssi_thresh_for_ra) ||
430 ping_rssi_state )
431 {
432 pra->ratr_state = DM_RATR_STA_LOW;
433 targetRATR = pra->ping_rssi_ratr;
434 ping_rssi_state = 1;
435 }
436 }
437 else
438 {
439 ping_rssi_state = 0;
440 }
441 }
442
443 // 2008.04.01
444 #if 1
445 // For RTL819X, if pairwisekey = wep/tkip, we support only MCS0~7.
446 if(priv->ieee80211->GetHalfNmodeSupportByAPsHandler(dev))
447 targetRATR &= 0xf00fffff;
448 #endif
449
450 //
451 // Check whether updating of RATR0 is required
452 //
453 currentRATR = read_nic_dword(dev, RATR0);
454 if( targetRATR != currentRATR )
455 {
456 u32 ratr_value;
457 ratr_value = targetRATR;
458 RT_TRACE(COMP_RATE,"currentRATR = %x, targetRATR = %x\n", currentRATR, targetRATR);
459 if(priv->rf_type == RF_1T2R)
460 {
461 ratr_value &= ~(RATE_ALL_OFDM_2SS);
462 }
463 write_nic_dword(dev, RATR0, ratr_value);
464 write_nic_byte(dev, UFWP, 1);
465
466 pra->last_ratr = targetRATR;
467 }
468
469 }
470 else
471 {
472 pra->ratr_state = DM_RATR_STA_MAX;
473 }
474
475 }
476
477
478 static void dm_init_bandwidth_autoswitch(struct net_device * dev)
479 {
480 struct r8192_priv *priv = ieee80211_priv(dev);
481
482 priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz = BW_AUTO_SWITCH_LOW_HIGH;
483 priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz = BW_AUTO_SWITCH_HIGH_LOW;
484 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
485 priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable = false;
486
487 }
488
489
490 static void dm_bandwidth_autoswitch(struct net_device * dev)
491 {
492 struct r8192_priv *priv = ieee80211_priv(dev);
493
494 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ||!priv->ieee80211->bandwidth_auto_switch.bautoswitch_enable){
495 return;
496 }else{
497 if(priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz == false){//If send packets in 40 Mhz in 20/40
498 if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->bandwidth_auto_switch.threshold_40Mhzto20Mhz)
499 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = true;
500 }else{//in force send packets in 20 Mhz in 20/40
501 if(priv->undecorated_smoothed_pwdb >= priv->ieee80211->bandwidth_auto_switch.threshold_20Mhzto40Mhz)
502 priv->ieee80211->bandwidth_auto_switch.bforced_tx20Mhz = false;
503
504 }
505 }
506 }
507
508 //OFDM default at 0db, index=6.
509 #ifndef RTL8190P
510 static const u32 OFDMSwingTable[OFDM_Table_Length] = {
511 0x7f8001fe, // 0, +6db
512 0x71c001c7, // 1, +5db
513 0x65400195, // 2, +4db
514 0x5a400169, // 3, +3db
515 0x50800142, // 4, +2db
516 0x47c0011f, // 5, +1db
517 0x40000100, // 6, +0db ===> default, upper for higher temperature, lower for low temperature
518 0x390000e4, // 7, -1db
519 0x32c000cb, // 8, -2db
520 0x2d4000b5, // 9, -3db
521 0x288000a2, // 10, -4db
522 0x24000090, // 11, -5db
523 0x20000080, // 12, -6db
524 0x1c800072, // 13, -7db
525 0x19800066, // 14, -8db
526 0x26c0005b, // 15, -9db
527 0x24400051, // 16, -10db
528 0x12000048, // 17, -11db
529 0x10000040 // 18, -12db
530 };
531 static const u8 CCKSwingTable_Ch1_Ch13[CCK_Table_length][8] = {
532 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0db ===> CCK40M default
533 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 1, -1db
534 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 2, -2db
535 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 3, -3db
536 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 4, -4db
537 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 5, -5db
538 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 6, -6db ===> CCK20M default
539 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 7, -7db
540 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 8, -8db
541 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 9, -9db
542 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 10, -10db
543 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01} // 11, -11db
544 };
545
546 static const u8 CCKSwingTable_Ch14[CCK_Table_length][8] = {
547 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0db ===> CCK40M default
548 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 1, -1db
549 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 2, -2db
550 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 3, -3db
551 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 4, -4db
552 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 5, -5db
553 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 6, -6db ===> CCK20M default
554 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 7, -7db
555 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 8, -8db
556 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 9, -9db
557 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 10, -10db
558 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00} // 11, -11db
559 };
560 #endif
561 #define Pw_Track_Flag 0x11d
562 #define Tssi_Mea_Value 0x13c
563 #define Tssi_Report_Value1 0x134
564 #define Tssi_Report_Value2 0x13e
565 #define FW_Busy_Flag 0x13f
566 static void dm_TXPowerTrackingCallback_TSSI(struct net_device * dev)
567 {
568 struct r8192_priv *priv = ieee80211_priv(dev);
569 bool bHighpowerstate, viviflag = FALSE;
570 DCMD_TXCMD_T tx_cmd;
571 u8 powerlevelOFDM24G;
572 int i =0, j = 0, k = 0;
573 u8 RF_Type, tmp_report[5]={0, 0, 0, 0, 0};
574 u32 Value;
575 u8 Pwr_Flag;
576 u16 Avg_TSSI_Meas, TSSI_13dBm, Avg_TSSI_Meas_from_driver=0;
577 #ifdef RTL8192U
578 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
579 #endif
580 // bool rtStatus = true;
581 u32 delta=0;
582 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
583 // write_nic_byte(dev, 0x1ba, 0);
584 write_nic_byte(dev, Pw_Track_Flag, 0);
585 write_nic_byte(dev, FW_Busy_Flag, 0);
586 priv->ieee80211->bdynamic_txpower_enable = false;
587 bHighpowerstate = priv->bDynamicTxHighPower;
588
589 powerlevelOFDM24G = (u8)(priv->Pwr_Track>>24);
590 RF_Type = priv->rf_type;
591 Value = (RF_Type<<8) | powerlevelOFDM24G;
592
593 RT_TRACE(COMP_POWER_TRACKING, "powerlevelOFDM24G = %x\n", powerlevelOFDM24G);
594
595 for(j = 0; j<=30; j++)
596 { //fill tx_cmd
597
598 tx_cmd.Op = TXCMD_SET_TX_PWR_TRACKING;
599 tx_cmd.Length = 4;
600 tx_cmd.Value = Value;
601 #ifdef RTL8192U
602 rtStatus = SendTxCommandPacket(dev, &tx_cmd, 12);
603 if (rtStatus == RT_STATUS_FAILURE)
604 {
605 RT_TRACE(COMP_POWER_TRACKING, "Set configuration with tx cmd queue fail!\n");
606 }
607 #else
608 cmpk_message_handle_tx(dev, (u8*)&tx_cmd, DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
609 #endif
610 mdelay(1);
611
612 for(i = 0;i <= 30; i++)
613 {
614 Pwr_Flag = read_nic_byte(dev, Pw_Track_Flag);
615
616 if (Pwr_Flag == 0)
617 {
618 mdelay(1);
619 continue;
620 }
621
622 Avg_TSSI_Meas = read_nic_word(dev, Tssi_Mea_Value);
623
624 if(Avg_TSSI_Meas == 0)
625 {
626 write_nic_byte(dev, Pw_Track_Flag, 0);
627 write_nic_byte(dev, FW_Busy_Flag, 0);
628 return;
629 }
630
631 for(k = 0;k < 5; k++)
632 {
633 if(k !=4)
634 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value1+k);
635 else
636 tmp_report[k] = read_nic_byte(dev, Tssi_Report_Value2);
637
638 RT_TRACE(COMP_POWER_TRACKING, "TSSI_report_value = %d\n", tmp_report[k]);
639 }
640
641 //check if the report value is right
642 for(k = 0;k < 5; k++)
643 {
644 if(tmp_report[k] <= 20)
645 {
646 viviflag =TRUE;
647 break;
648 }
649 }
650 if(viviflag ==TRUE)
651 {
652 write_nic_byte(dev, Pw_Track_Flag, 0);
653 viviflag = FALSE;
654 RT_TRACE(COMP_POWER_TRACKING, "we filted this data\n");
655 for(k = 0;k < 5; k++)
656 tmp_report[k] = 0;
657 break;
658 }
659
660 for(k = 0;k < 5; k++)
661 {
662 Avg_TSSI_Meas_from_driver += tmp_report[k];
663 }
664
665 Avg_TSSI_Meas_from_driver = Avg_TSSI_Meas_from_driver*100/5;
666 RT_TRACE(COMP_POWER_TRACKING, "Avg_TSSI_Meas_from_driver = %d\n", Avg_TSSI_Meas_from_driver);
667 TSSI_13dBm = priv->TSSI_13dBm;
668 RT_TRACE(COMP_POWER_TRACKING, "TSSI_13dBm = %d\n", TSSI_13dBm);
669
670 //if(abs(Avg_TSSI_Meas_from_driver - TSSI_13dBm) <= E_FOR_TX_POWER_TRACK)
671 // For MacOS-compatible
672 if(Avg_TSSI_Meas_from_driver > TSSI_13dBm)
673 delta = Avg_TSSI_Meas_from_driver - TSSI_13dBm;
674 else
675 delta = TSSI_13dBm - Avg_TSSI_Meas_from_driver;
676
677 if(delta <= E_FOR_TX_POWER_TRACK)
678 {
679 priv->ieee80211->bdynamic_txpower_enable = TRUE;
680 write_nic_byte(dev, Pw_Track_Flag, 0);
681 write_nic_byte(dev, FW_Busy_Flag, 0);
682 RT_TRACE(COMP_POWER_TRACKING, "tx power track is done\n");
683 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
684 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
685 #ifdef RTL8190P
686 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
687 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
688 #endif
689 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
690 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
691 return;
692 }
693 else
694 {
695 if(Avg_TSSI_Meas_from_driver < TSSI_13dBm - E_FOR_TX_POWER_TRACK)
696 {
697 if (RF_Type == RF_2T4R)
698 {
699
700 if((priv->rfa_txpowertrackingindex > 0) &&(priv->rfc_txpowertrackingindex > 0))
701 {
702 priv->rfa_txpowertrackingindex--;
703 if(priv->rfa_txpowertrackingindex_real > 4)
704 {
705 priv->rfa_txpowertrackingindex_real--;
706 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
707 }
708
709 priv->rfc_txpowertrackingindex--;
710 if(priv->rfc_txpowertrackingindex_real > 4)
711 {
712 priv->rfc_txpowertrackingindex_real--;
713 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
714 }
715 }
716 else
717 {
718 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
719 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
720 }
721 }
722 else
723 {
724 if(priv->rfc_txpowertrackingindex > 0)
725 {
726 priv->rfc_txpowertrackingindex--;
727 if(priv->rfc_txpowertrackingindex_real > 4)
728 {
729 priv->rfc_txpowertrackingindex_real--;
730 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
731 }
732 }
733 else
734 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[4].txbbgain_value);
735 }
736 }
737 else
738 {
739 if (RF_Type == RF_2T4R)
740 {
741 if((priv->rfa_txpowertrackingindex < TxBBGainTableLength - 1) &&(priv->rfc_txpowertrackingindex < TxBBGainTableLength - 1))
742 {
743 priv->rfa_txpowertrackingindex++;
744 priv->rfa_txpowertrackingindex_real++;
745 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex_real].txbbgain_value);
746 priv->rfc_txpowertrackingindex++;
747 priv->rfc_txpowertrackingindex_real++;
748 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
749 }
750 else
751 {
752 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
753 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
754 }
755 }
756 else
757 {
758 if(priv->rfc_txpowertrackingindex < (TxBBGainTableLength - 1))
759 {
760 priv->rfc_txpowertrackingindex++;
761 priv->rfc_txpowertrackingindex_real++;
762 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex_real].txbbgain_value);
763 }
764 else
765 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[TxBBGainTableLength - 1].txbbgain_value);
766 }
767 }
768 if (RF_Type == RF_2T4R)
769 priv->CCKPresentAttentuation_difference
770 = priv->rfa_txpowertrackingindex - priv->rfa_txpowertracking_default;
771 else
772 priv->CCKPresentAttentuation_difference
773 = priv->rfc_txpowertrackingindex - priv->rfc_txpowertracking_default;
774
775 if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
776 priv->CCKPresentAttentuation
777 = priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
778 else
779 priv->CCKPresentAttentuation
780 = priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
781
782 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
783 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
784 if(priv->CCKPresentAttentuation < 0)
785 priv->CCKPresentAttentuation = 0;
786
787 if(1)
788 {
789 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
790 {
791 priv->bcck_in_ch14 = TRUE;
792 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
793 }
794 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
795 {
796 priv->bcck_in_ch14 = FALSE;
797 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
798 }
799 else
800 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
801 }
802 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex = %d\n", priv->rfa_txpowertrackingindex);
803 RT_TRACE(COMP_POWER_TRACKING, "priv->rfa_txpowertrackingindex_real = %d\n", priv->rfa_txpowertrackingindex_real);
804 #ifdef RTL8190P
805 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex = %d\n", priv->rfc_txpowertrackingindex);
806 RT_TRACE(COMP_POWER_TRACKING, "priv->rfc_txpowertrackingindex_real = %d\n", priv->rfc_txpowertrackingindex_real);
807 #endif
808 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation_difference = %d\n", priv->CCKPresentAttentuation_difference);
809 RT_TRACE(COMP_POWER_TRACKING, "priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
810
811 if (priv->CCKPresentAttentuation_difference <= -12||priv->CCKPresentAttentuation_difference >= 24)
812 {
813 priv->ieee80211->bdynamic_txpower_enable = TRUE;
814 write_nic_byte(dev, Pw_Track_Flag, 0);
815 write_nic_byte(dev, FW_Busy_Flag, 0);
816 RT_TRACE(COMP_POWER_TRACKING, "tx power track--->limited\n");
817 return;
818 }
819
820
821 }
822 write_nic_byte(dev, Pw_Track_Flag, 0);
823 Avg_TSSI_Meas_from_driver = 0;
824 for(k = 0;k < 5; k++)
825 tmp_report[k] = 0;
826 break;
827 }
828 write_nic_byte(dev, FW_Busy_Flag, 0);
829 }
830 priv->ieee80211->bdynamic_txpower_enable = TRUE;
831 write_nic_byte(dev, Pw_Track_Flag, 0);
832 }
833 #ifndef RTL8190P
834 static void dm_TXPowerTrackingCallback_ThermalMeter(struct net_device * dev)
835 {
836 #define ThermalMeterVal 9
837 struct r8192_priv *priv = ieee80211_priv(dev);
838 u32 tmpRegA, TempCCk;
839 u8 tmpOFDMindex, tmpCCKindex, tmpCCK20Mindex, tmpCCK40Mindex, tmpval;
840 int i =0, CCKSwingNeedUpdate=0;
841
842 if(!priv->btxpower_trackingInit)
843 {
844 //Query OFDM default setting
845 tmpRegA= rtl8192_QueryBBReg(dev, rOFDM0_XATxIQImbalance, bMaskDWord);
846 for(i=0; i<OFDM_Table_Length; i++) //find the index
847 {
848 if(tmpRegA == OFDMSwingTable[i])
849 {
850 priv->OFDM_index= (u8)i;
851 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, OFDM_index=0x%x\n",
852 rOFDM0_XATxIQImbalance, tmpRegA, priv->OFDM_index);
853 }
854 }
855
856 //Query CCK default setting From 0xa22
857 TempCCk = rtl8192_QueryBBReg(dev, rCCK0_TxFilter1, bMaskByte2);
858 for(i=0 ; i<CCK_Table_length ; i++)
859 {
860 if(TempCCk == (u32)CCKSwingTable_Ch1_Ch13[i][0])
861 {
862 priv->CCK_index =(u8) i;
863 RT_TRACE(COMP_POWER_TRACKING, "Initial reg0x%x = 0x%x, CCK_index=0x%x\n",
864 rCCK0_TxFilter1, TempCCk, priv->CCK_index);
865 break;
866 }
867 }
868 priv->btxpower_trackingInit = TRUE;
869 //pHalData->TXPowercount = 0;
870 return;
871 }
872
873 // read and filter out unreasonable value
874 tmpRegA = rtl8192_phy_QueryRFReg(dev, RF90_PATH_A, 0x12, 0x078); // 0x12: RF Reg[10:7]
875 RT_TRACE(COMP_POWER_TRACKING, "Readback ThermalMeterA = %d \n", tmpRegA);
876 if(tmpRegA < 3 || tmpRegA > 13)
877 return;
878 if(tmpRegA >= 12) // if over 12, TP will be bad when high temperature
879 tmpRegA = 12;
880 RT_TRACE(COMP_POWER_TRACKING, "Valid ThermalMeterA = %d \n", tmpRegA);
881 priv->ThermalMeter[0] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
882 priv->ThermalMeter[1] = ThermalMeterVal; //We use fixed value by Bryant's suggestion
883
884 //Get current RF-A temperature index
885 if(priv->ThermalMeter[0] >= (u8)tmpRegA) //lower temperature
886 {
887 tmpOFDMindex = tmpCCK20Mindex = 6+(priv->ThermalMeter[0]-(u8)tmpRegA);
888 tmpCCK40Mindex = tmpCCK20Mindex - 6;
889 if(tmpOFDMindex >= OFDM_Table_Length)
890 tmpOFDMindex = OFDM_Table_Length-1;
891 if(tmpCCK20Mindex >= CCK_Table_length)
892 tmpCCK20Mindex = CCK_Table_length-1;
893 if(tmpCCK40Mindex >= CCK_Table_length)
894 tmpCCK40Mindex = CCK_Table_length-1;
895 }
896 else
897 {
898 tmpval = ((u8)tmpRegA - priv->ThermalMeter[0]);
899 if(tmpval >= 6) // higher temperature
900 tmpOFDMindex = tmpCCK20Mindex = 0; // max to +6dB
901 else
902 tmpOFDMindex = tmpCCK20Mindex = 6 - tmpval;
903 tmpCCK40Mindex = 0;
904 }
905
906 if(priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) //40M
907 tmpCCKindex = tmpCCK40Mindex;
908 else
909 tmpCCKindex = tmpCCK20Mindex;
910
911 //record for bandwidth swith
912 priv->Record_CCK_20Mindex = tmpCCK20Mindex;
913 priv->Record_CCK_40Mindex = tmpCCK40Mindex;
914 RT_TRACE(COMP_POWER_TRACKING, "Record_CCK_20Mindex / Record_CCK_40Mindex = %d / %d.\n",
915 priv->Record_CCK_20Mindex, priv->Record_CCK_40Mindex);
916
917 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
918 {
919 priv->bcck_in_ch14 = TRUE;
920 CCKSwingNeedUpdate = 1;
921 }
922 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
923 {
924 priv->bcck_in_ch14 = FALSE;
925 CCKSwingNeedUpdate = 1;
926 }
927
928 if(priv->CCK_index != tmpCCKindex)
929 {
930 priv->CCK_index = tmpCCKindex;
931 CCKSwingNeedUpdate = 1;
932 }
933
934 if(CCKSwingNeedUpdate)
935 {
936 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
937 }
938 if(priv->OFDM_index != tmpOFDMindex)
939 {
940 priv->OFDM_index = tmpOFDMindex;
941 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[priv->OFDM_index]);
942 RT_TRACE(COMP_POWER_TRACKING, "Update OFDMSwing[%d] = 0x%x\n",
943 priv->OFDM_index, OFDMSwingTable[priv->OFDM_index]);
944 }
945 priv->txpower_count = 0;
946 }
947 #endif
948 void dm_txpower_trackingcallback(struct work_struct *work)
949 {
950 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
951 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,txpower_tracking_wq);
952 struct net_device *dev = priv->ieee80211->dev;
953
954 #ifdef RTL8190P
955 dm_TXPowerTrackingCallback_TSSI(dev);
956 #else
957 //if(priv->bDcut == TRUE)
958 if(priv->IC_Cut >= IC_VersionCut_D)
959 dm_TXPowerTrackingCallback_TSSI(dev);
960 else
961 dm_TXPowerTrackingCallback_ThermalMeter(dev);
962 #endif
963 }
964
965
966 static const txbbgain_struct rtl8192_txbbgain_table[] = {
967 { 12, 0x7f8001fe },
968 { 11, 0x788001e2 },
969 { 10, 0x71c001c7 },
970 { 9, 0x6b8001ae },
971 { 8, 0x65400195 },
972 { 7, 0x5fc0017f },
973 { 6, 0x5a400169 },
974 { 5, 0x55400155 },
975 { 4, 0x50800142 },
976 { 3, 0x4c000130 },
977 { 2, 0x47c0011f },
978 { 1, 0x43c0010f },
979 { 0, 0x40000100 },
980 { -1, 0x3c8000f2 },
981 { -2, 0x390000e4 },
982 { -3, 0x35c000d7 },
983 { -4, 0x32c000cb },
984 { -5, 0x300000c0 },
985 { -6, 0x2d4000b5 },
986 { -7, 0x2ac000ab },
987 { -8, 0x288000a2 },
988 { -9, 0x26000098 },
989 { -10, 0x24000090 },
990 { -11, 0x22000088 },
991 { -12, 0x20000080 },
992 { -13, 0x1a00006c },
993 { -14, 0x1c800072 },
994 { -15, 0x18000060 },
995 { -16, 0x19800066 },
996 { -17, 0x15800056 },
997 { -18, 0x26c0005b },
998 { -19, 0x14400051 },
999 { -20, 0x24400051 },
1000 { -21, 0x1300004c },
1001 { -22, 0x12000048 },
1002 { -23, 0x11000044 },
1003 { -24, 0x10000040 },
1004 };
1005
1006 /*
1007 * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1008 * This Table is for CH1~CH13
1009 */
1010 static const ccktxbbgain_struct rtl8192_cck_txbbgain_table[] = {
1011 {{ 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 }},
1012 {{ 0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04 }},
1013 {{ 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03 }},
1014 {{ 0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03 }},
1015 {{ 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 }},
1016 {{ 0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03 }},
1017 {{ 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 }},
1018 {{ 0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03 }},
1019 {{ 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02 }},
1020 {{ 0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02 }},
1021 {{ 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02 }},
1022 {{ 0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02 }},
1023 {{ 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02 }},
1024 {{ 0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02 }},
1025 {{ 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02 }},
1026 {{ 0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02 }},
1027 {{ 0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01 }},
1028 {{ 0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02 }},
1029 {{ 0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01 }},
1030 {{ 0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01 }},
1031 {{ 0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01 }},
1032 {{ 0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01 }},
1033 {{ 0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01 }},
1034 };
1035
1036 /*
1037 * ccktxbb_valuearray[0] is 0xA22 [1] is 0xA24 ...[7] is 0xA29
1038 * This Table is for CH14
1039 */
1040 static const ccktxbbgain_struct rtl8192_cck_txbbgain_ch14_table[] = {
1041 {{ 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 }},
1042 {{ 0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00 }},
1043 {{ 0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00 }},
1044 {{ 0x2d, 0x2d, 0x27, 0x17, 0x00, 0x00, 0x00, 0x00 }},
1045 {{ 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 }},
1046 {{ 0x28, 0x28, 0x22, 0x14, 0x00, 0x00, 0x00, 0x00 }},
1047 {{ 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00 }},
1048 {{ 0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00 }},
1049 {{ 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00 }},
1050 {{ 0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00 }},
1051 {{ 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00 }},
1052 {{ 0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00 }},
1053 {{ 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00 }},
1054 {{ 0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00 }},
1055 {{ 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00 }},
1056 {{ 0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00 }},
1057 {{ 0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00 }},
1058 {{ 0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00 }},
1059 {{ 0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00 }},
1060 {{ 0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00 }},
1061 {{ 0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00 }},
1062 {{ 0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00 }},
1063 {{ 0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00 }},
1064 };
1065
1066 static void dm_InitializeTXPowerTracking_TSSI(struct net_device *dev)
1067 {
1068 struct r8192_priv *priv = ieee80211_priv(dev);
1069
1070 priv->txbbgain_table = rtl8192_txbbgain_table;
1071 priv->cck_txbbgain_table = rtl8192_cck_txbbgain_table;
1072 priv->cck_txbbgain_ch14_table = rtl8192_cck_txbbgain_ch14_table;
1073
1074 priv->btxpower_tracking = TRUE;
1075 priv->txpower_count = 0;
1076 priv->btxpower_trackingInit = FALSE;
1077
1078 }
1079 #ifndef RTL8190P
1080 static void dm_InitializeTXPowerTracking_ThermalMeter(struct net_device *dev)
1081 {
1082 struct r8192_priv *priv = ieee80211_priv(dev);
1083
1084 // Tx Power tracking by Theremal Meter require Firmware R/W 3-wire. This mechanism
1085 // can be enabled only when Firmware R/W 3-wire is enabled. Otherwise, frequent r/w
1086 // 3-wire by driver cause RF goes into wrong state.
1087 if(priv->ieee80211->FwRWRF)
1088 priv->btxpower_tracking = TRUE;
1089 else
1090 priv->btxpower_tracking = FALSE;
1091 priv->txpower_count = 0;
1092 priv->btxpower_trackingInit = FALSE;
1093 }
1094 #endif
1095
1096 void dm_initialize_txpower_tracking(struct net_device *dev)
1097 {
1098 #ifndef RTL8190P
1099 struct r8192_priv *priv = ieee80211_priv(dev);
1100 #endif
1101 #ifdef RTL8190P
1102 dm_InitializeTXPowerTracking_TSSI(dev);
1103 #else
1104 if(priv->IC_Cut >= IC_VersionCut_D)
1105 dm_InitializeTXPowerTracking_TSSI(dev);
1106 else
1107 dm_InitializeTXPowerTracking_ThermalMeter(dev);
1108 #endif
1109 }
1110
1111
1112 static void dm_CheckTXPowerTracking_TSSI(struct net_device *dev)
1113 {
1114 struct r8192_priv *priv = ieee80211_priv(dev);
1115 static u32 tx_power_track_counter = 0;
1116 RT_TRACE(COMP_POWER_TRACKING,"%s()\n",__FUNCTION__);
1117 if(read_nic_byte(dev, 0x11e) ==1)
1118 return;
1119 if(!priv->btxpower_tracking)
1120 return;
1121 tx_power_track_counter++;
1122
1123 if (tx_power_track_counter > 90) {
1124 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1125 tx_power_track_counter =0;
1126 }
1127 }
1128
1129 #ifndef RTL8190P
1130 static void dm_CheckTXPowerTracking_ThermalMeter(struct net_device *dev)
1131 {
1132 struct r8192_priv *priv = ieee80211_priv(dev);
1133 static u8 TM_Trigger=0;
1134
1135 if(!priv->btxpower_tracking)
1136 return;
1137 else
1138 {
1139 if(priv->txpower_count <= 2)
1140 {
1141 priv->txpower_count++;
1142 return;
1143 }
1144 }
1145
1146 if(!TM_Trigger)
1147 {
1148 //Attention!! You have to wirte all 12bits data to RF, or it may cause RF to crash
1149 //actually write reg0x02 bit1=0, then bit1=1.
1150 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1151 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1152 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4d);
1153 rtl8192_phy_SetRFReg(dev, RF90_PATH_A, 0x02, bMask12Bits, 0x4f);
1154 TM_Trigger = 1;
1155 return;
1156 }
1157 else {
1158 queue_delayed_work(priv->priv_wq,&priv->txpower_tracking_wq,0);
1159 TM_Trigger = 0;
1160 }
1161 }
1162 #endif
1163
1164 static void dm_check_txpower_tracking(struct net_device *dev)
1165 {
1166 #ifndef RTL8190P
1167 struct r8192_priv *priv = ieee80211_priv(dev);
1168 //static u32 tx_power_track_counter = 0;
1169 #endif
1170 #ifdef RTL8190P
1171 dm_CheckTXPowerTracking_TSSI(dev);
1172 #else
1173 //if(priv->bDcut == TRUE)
1174 if(priv->IC_Cut >= IC_VersionCut_D)
1175 dm_CheckTXPowerTracking_TSSI(dev);
1176 else
1177 dm_CheckTXPowerTracking_ThermalMeter(dev);
1178 #endif
1179
1180 }
1181
1182
1183 static void dm_CCKTxPowerAdjust_TSSI(struct net_device *dev, bool bInCH14)
1184 {
1185 u32 TempVal;
1186 struct r8192_priv *priv = ieee80211_priv(dev);
1187 //Write 0xa22 0xa23
1188 TempVal = 0;
1189 if(!bInCH14){
1190 //Write 0xa22 0xa23
1191 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1192 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1193
1194 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1195 //Write 0xa24 ~ 0xa27
1196 TempVal = 0;
1197 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1198 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1199 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1200 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1201 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1202 //Write 0xa28 0xa29
1203 TempVal = 0;
1204 TempVal = (u32)(priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1205 (priv->cck_txbbgain_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1206
1207 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1208 }
1209 else
1210 {
1211 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[0] +
1212 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[1]<<8)) ;
1213
1214 rtl8192_setBBreg(dev, rCCK0_TxFilter1,bMaskHWord, TempVal);
1215 //Write 0xa24 ~ 0xa27
1216 TempVal = 0;
1217 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[2] +
1218 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[3]<<8) +
1219 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[4]<<16 )+
1220 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[5]<<24));
1221 rtl8192_setBBreg(dev, rCCK0_TxFilter2,bMaskDWord, TempVal);
1222 //Write 0xa28 0xa29
1223 TempVal = 0;
1224 TempVal = (u32)(priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[6] +
1225 (priv->cck_txbbgain_ch14_table[(u8)(priv->CCKPresentAttentuation)].ccktxbb_valuearray[7]<<8)) ;
1226
1227 rtl8192_setBBreg(dev, rCCK0_DebugPort,bMaskLWord, TempVal);
1228 }
1229
1230
1231 }
1232 #ifndef RTL8190P
1233 static void dm_CCKTxPowerAdjust_ThermalMeter(struct net_device *dev, bool bInCH14)
1234 {
1235 u32 TempVal;
1236 struct r8192_priv *priv = ieee80211_priv(dev);
1237
1238 TempVal = 0;
1239 if(!bInCH14)
1240 {
1241 //Write 0xa22 0xa23
1242 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][0] +
1243 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][1]<<8) ;
1244 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1245 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1246 rCCK0_TxFilter1, TempVal);
1247 //Write 0xa24 ~ 0xa27
1248 TempVal = 0;
1249 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][2] +
1250 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][3]<<8) +
1251 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][4]<<16 )+
1252 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][5]<<24);
1253 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1254 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1255 rCCK0_TxFilter2, TempVal);
1256 //Write 0xa28 0xa29
1257 TempVal = 0;
1258 TempVal = CCKSwingTable_Ch1_Ch13[priv->CCK_index][6] +
1259 (CCKSwingTable_Ch1_Ch13[priv->CCK_index][7]<<8) ;
1260
1261 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1262 RT_TRACE(COMP_POWER_TRACKING, "CCK not chnl 14, reg 0x%x = 0x%x\n",
1263 rCCK0_DebugPort, TempVal);
1264 }
1265 else
1266 {
1267 // priv->CCKTxPowerAdjustCntNotCh14++; //cosa add for debug.
1268 //Write 0xa22 0xa23
1269 TempVal = CCKSwingTable_Ch14[priv->CCK_index][0] +
1270 (CCKSwingTable_Ch14[priv->CCK_index][1]<<8) ;
1271
1272 rtl8192_setBBreg(dev, rCCK0_TxFilter1, bMaskHWord, TempVal);
1273 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1274 rCCK0_TxFilter1, TempVal);
1275 //Write 0xa24 ~ 0xa27
1276 TempVal = 0;
1277 TempVal = CCKSwingTable_Ch14[priv->CCK_index][2] +
1278 (CCKSwingTable_Ch14[priv->CCK_index][3]<<8) +
1279 (CCKSwingTable_Ch14[priv->CCK_index][4]<<16 )+
1280 (CCKSwingTable_Ch14[priv->CCK_index][5]<<24);
1281 rtl8192_setBBreg(dev, rCCK0_TxFilter2, bMaskDWord, TempVal);
1282 RT_TRACE(COMP_POWER_TRACKING, "CCK chnl 14, reg 0x%x = 0x%x\n",
1283 rCCK0_TxFilter2, TempVal);
1284 //Write 0xa28 0xa29
1285 TempVal = 0;
1286 TempVal = CCKSwingTable_Ch14[priv->CCK_index][6] +
1287 (CCKSwingTable_Ch14[priv->CCK_index][7]<<8) ;
1288
1289 rtl8192_setBBreg(dev, rCCK0_DebugPort, bMaskLWord, TempVal);
1290 RT_TRACE(COMP_POWER_TRACKING,"CCK chnl 14, reg 0x%x = 0x%x\n",
1291 rCCK0_DebugPort, TempVal);
1292 }
1293 }
1294 #endif
1295
1296
1297 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14)
1298 {
1299 #ifndef RTL8190P
1300 struct r8192_priv *priv = ieee80211_priv(dev);
1301 #endif
1302 #ifdef RTL8190P
1303 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1304 #else
1305 if(priv->IC_Cut >= IC_VersionCut_D)
1306 dm_CCKTxPowerAdjust_TSSI(dev, binch14);
1307 else
1308 dm_CCKTxPowerAdjust_ThermalMeter(dev, binch14);
1309 #endif
1310 }
1311
1312
1313 #ifndef RTL8192U
1314 static void dm_txpower_reset_recovery(
1315 struct net_device *dev
1316 )
1317 {
1318 struct r8192_priv *priv = ieee80211_priv(dev);
1319
1320 RT_TRACE(COMP_POWER_TRACKING, "Start Reset Recovery ==>\n");
1321 rtl8192_setBBreg(dev, rOFDM0_XATxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1322 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc80 is %08x\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbbgain_value);
1323 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFA_txPowerTrackingIndex is %x\n",priv->rfa_txpowertrackingindex);
1324 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF A I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfa_txpowertrackingindex].txbb_iq_amplifygain);
1325 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: CCK Attenuation is %d dB\n",priv->CCKPresentAttentuation);
1326 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
1327
1328 rtl8192_setBBreg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord, priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1329 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in 0xc90 is %08x\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbbgain_value);
1330 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery: Fill in RFC_txPowerTrackingIndex is %x\n",priv->rfc_txpowertrackingindex);
1331 RT_TRACE(COMP_POWER_TRACKING, "Reset Recovery : RF C I/Q Amplify Gain is %ld\n",priv->txbbgain_table[priv->rfc_txpowertrackingindex].txbb_iq_amplifygain);
1332
1333 }
1334
1335 void dm_restore_dynamic_mechanism_state(struct net_device *dev)
1336 {
1337 struct r8192_priv *priv = ieee80211_priv(dev);
1338 u32 reg_ratr = priv->rate_adaptive.last_ratr;
1339
1340 if(!priv->up)
1341 {
1342 RT_TRACE(COMP_RATE, "<---- dm_restore_dynamic_mechanism_state(): driver is going to unload\n");
1343 return;
1344 }
1345
1346 //
1347 // Restore previous state for rate adaptive
1348 //
1349 if(priv->rate_adaptive.rate_adaptive_disabled)
1350 return;
1351 // TODO: Only 11n mode is implemented currently,
1352 if( !(priv->ieee80211->mode==WIRELESS_MODE_N_24G ||
1353 priv->ieee80211->mode==WIRELESS_MODE_N_5G))
1354 return;
1355 {
1356 /* 2007/11/15 MH Copy from 8190PCI. */
1357 u32 ratr_value;
1358 ratr_value = reg_ratr;
1359 if(priv->rf_type == RF_1T2R) // 1T2R, Spatial Stream 2 should be disabled
1360 {
1361 ratr_value &=~ (RATE_ALL_OFDM_2SS);
1362 }
1363 write_nic_dword(dev, RATR0, ratr_value);
1364 write_nic_byte(dev, UFWP, 1);
1365 }
1366 //Resore TX Power Tracking Index
1367 if(priv->btxpower_trackingInit && priv->btxpower_tracking){
1368 dm_txpower_reset_recovery(dev);
1369 }
1370
1371 //
1372 //Restore BB Initial Gain
1373 //
1374 dm_bb_initialgain_restore(dev);
1375
1376 }
1377
1378 static void dm_bb_initialgain_restore(struct net_device *dev)
1379 {
1380 struct r8192_priv *priv = ieee80211_priv(dev);
1381 u32 bit_mask = 0x7f; //Bit0~ Bit6
1382
1383 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1384 return;
1385
1386 //Disable Initial Gain
1387 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1388 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1389 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bit_mask, (u32)priv->initgain_backup.xaagccore1);
1390 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bit_mask, (u32)priv->initgain_backup.xbagccore1);
1391 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bit_mask, (u32)priv->initgain_backup.xcagccore1);
1392 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bit_mask, (u32)priv->initgain_backup.xdagccore1);
1393 bit_mask = bMaskByte2;
1394 rtl8192_setBBreg(dev, rCCK0_CCA, bit_mask, (u32)priv->initgain_backup.cca);
1395
1396 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1397 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1398 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1399 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1400 RT_TRACE(COMP_DIG, "dm_BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
1401 //Enable Initial Gain
1402 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x100);
1403 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1404
1405 }
1406
1407
1408 void dm_backup_dynamic_mechanism_state(struct net_device *dev)
1409 {
1410 struct r8192_priv *priv = ieee80211_priv(dev);
1411
1412 // Fsync to avoid reset
1413 priv->bswitch_fsync = false;
1414 //Backup BB InitialGain
1415 dm_bb_initialgain_backup(dev);
1416
1417 }
1418
1419
1420 static void dm_bb_initialgain_backup(struct net_device *dev)
1421 {
1422 struct r8192_priv *priv = ieee80211_priv(dev);
1423 u32 bit_mask = bMaskByte0; //Bit0~ Bit6
1424
1425 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1426 return;
1427
1428 //PHY_SetBBReg(Adapter, UFWP, bMaskLWord, 0x800);
1429 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1430 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bit_mask);
1431 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bit_mask);
1432 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bit_mask);
1433 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bit_mask);
1434 bit_mask = bMaskByte2;
1435 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bit_mask);
1436
1437 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
1438 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
1439 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
1440 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
1441 RT_TRACE(COMP_DIG, "BBInitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
1442
1443 }
1444
1445 #endif
1446
1447 void dm_change_dynamic_initgain_thresh(struct net_device *dev, u32 dm_type, u32 dm_value)
1448 {
1449 if (dm_type == DIG_TYPE_THRESH_HIGH)
1450 {
1451 dm_digtable.rssi_high_thresh = dm_value;
1452 }
1453 else if (dm_type == DIG_TYPE_THRESH_LOW)
1454 {
1455 dm_digtable.rssi_low_thresh = dm_value;
1456 }
1457 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
1458 {
1459 dm_digtable.rssi_high_power_highthresh = dm_value;
1460 }
1461 else if (dm_type == DIG_TYPE_THRESH_HIGHPWR_HIGH)
1462 {
1463 dm_digtable.rssi_high_power_highthresh = dm_value;
1464 }
1465 else if (dm_type == DIG_TYPE_ENABLE)
1466 {
1467 dm_digtable.dig_state = DM_STA_DIG_MAX;
1468 dm_digtable.dig_enable_flag = true;
1469 }
1470 else if (dm_type == DIG_TYPE_DISABLE)
1471 {
1472 dm_digtable.dig_state = DM_STA_DIG_MAX;
1473 dm_digtable.dig_enable_flag = false;
1474 }
1475 else if (dm_type == DIG_TYPE_DBG_MODE)
1476 {
1477 if(dm_value >= DM_DBG_MAX)
1478 dm_value = DM_DBG_OFF;
1479 dm_digtable.dbg_mode = (u8)dm_value;
1480 }
1481 else if (dm_type == DIG_TYPE_RSSI)
1482 {
1483 if(dm_value > 100)
1484 dm_value = 30;
1485 dm_digtable.rssi_val = (long)dm_value;
1486 }
1487 else if (dm_type == DIG_TYPE_ALGORITHM)
1488 {
1489 if (dm_value >= DIG_ALGO_MAX)
1490 dm_value = DIG_ALGO_BY_FALSE_ALARM;
1491 if(dm_digtable.dig_algorithm != (u8)dm_value)
1492 dm_digtable.dig_algorithm_switch = 1;
1493 dm_digtable.dig_algorithm = (u8)dm_value;
1494 }
1495 else if (dm_type == DIG_TYPE_BACKOFF)
1496 {
1497 if(dm_value > 30)
1498 dm_value = 30;
1499 dm_digtable.backoff_val = (u8)dm_value;
1500 }
1501 else if(dm_type == DIG_TYPE_RX_GAIN_MIN)
1502 {
1503 if(dm_value == 0)
1504 dm_value = 0x1;
1505 dm_digtable.rx_gain_range_min = (u8)dm_value;
1506 }
1507 else if(dm_type == DIG_TYPE_RX_GAIN_MAX)
1508 {
1509 if(dm_value > 0x50)
1510 dm_value = 0x50;
1511 dm_digtable.rx_gain_range_max = (u8)dm_value;
1512 }
1513 }
1514
1515
1516 /* Set DIG scheme init value. */
1517 static void dm_dig_init(struct net_device *dev)
1518 {
1519 struct r8192_priv *priv = ieee80211_priv(dev);
1520 /* 2007/10/05 MH Disable DIG scheme now. Not tested. */
1521 dm_digtable.dig_enable_flag = true;
1522 dm_digtable.dig_algorithm = DIG_ALGO_BY_RSSI;
1523 dm_digtable.dbg_mode = DM_DBG_OFF; //off=by real rssi value, on=by DM_DigTable.Rssi_val for new dig
1524 dm_digtable.dig_algorithm_switch = 0;
1525
1526 /* 2007/10/04 MH Define init gain threshold. */
1527 dm_digtable.dig_state = DM_STA_DIG_MAX;
1528 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1529 dm_digtable.initialgain_lowerbound_state = false;
1530
1531 dm_digtable.rssi_low_thresh = DM_DIG_THRESH_LOW;
1532 dm_digtable.rssi_high_thresh = DM_DIG_THRESH_HIGH;
1533
1534 dm_digtable.rssi_high_power_lowthresh = DM_DIG_HIGH_PWR_THRESH_LOW;
1535 dm_digtable.rssi_high_power_highthresh = DM_DIG_HIGH_PWR_THRESH_HIGH;
1536
1537 dm_digtable.rssi_val = 50; //for new dig debug rssi value
1538 dm_digtable.backoff_val = DM_DIG_BACKOFF;
1539 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
1540 if(priv->CustomerID == RT_CID_819x_Netcore)
1541 dm_digtable.rx_gain_range_min = DM_DIG_MIN_Netcore;
1542 else
1543 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
1544
1545 }
1546
1547
1548 /*
1549 * Driver must monitor RSSI and notify firmware to change initial
1550 * gain according to different threshold. BB team provide the
1551 * suggested solution.
1552 */
1553 static void dm_ctrl_initgain_byrssi(struct net_device *dev)
1554 {
1555
1556 if (dm_digtable.dig_enable_flag == false)
1557 return;
1558
1559 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
1560 dm_ctrl_initgain_byrssi_by_fwfalse_alarm(dev);
1561 else if(dm_digtable.dig_algorithm == DIG_ALGO_BY_RSSI)
1562 dm_ctrl_initgain_byrssi_by_driverrssi(dev);
1563 }
1564
1565
1566 static void dm_ctrl_initgain_byrssi_by_driverrssi(
1567 struct net_device *dev)
1568 {
1569 struct r8192_priv *priv = ieee80211_priv(dev);
1570 u8 i;
1571 static u8 fw_dig=0;
1572
1573 if (dm_digtable.dig_enable_flag == false)
1574 return;
1575
1576 if(dm_digtable.dig_algorithm_switch) // if swithed algorithm, we have to disable FW Dig.
1577 fw_dig = 0;
1578 if(fw_dig <= 3) // execute several times to make sure the FW Dig is disabled
1579 {// FW DIG Off
1580 for(i=0; i<3; i++)
1581 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1582 fw_dig++;
1583 dm_digtable.dig_state = DM_STA_DIG_OFF; //fw dig off.
1584 }
1585
1586 if(priv->ieee80211->state == IEEE80211_LINKED)
1587 dm_digtable.cur_connect_state = DIG_CONNECT;
1588 else
1589 dm_digtable.cur_connect_state = DIG_DISCONNECT;
1590
1591 if(dm_digtable.dbg_mode == DM_DBG_OFF)
1592 dm_digtable.rssi_val = priv->undecorated_smoothed_pwdb;
1593
1594 dm_initial_gain(dev);
1595 dm_pd_th(dev);
1596 dm_cs_ratio(dev);
1597 if(dm_digtable.dig_algorithm_switch)
1598 dm_digtable.dig_algorithm_switch = 0;
1599 dm_digtable.pre_connect_state = dm_digtable.cur_connect_state;
1600
1601 }
1602
1603 static void dm_ctrl_initgain_byrssi_by_fwfalse_alarm(
1604 struct net_device *dev)
1605 {
1606 struct r8192_priv *priv = ieee80211_priv(dev);
1607 static u32 reset_cnt = 0;
1608 u8 i;
1609
1610 if (dm_digtable.dig_enable_flag == false)
1611 return;
1612
1613 if(dm_digtable.dig_algorithm_switch)
1614 {
1615 dm_digtable.dig_state = DM_STA_DIG_MAX;
1616 // Fw DIG On.
1617 for(i=0; i<3; i++)
1618 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1619 dm_digtable.dig_algorithm_switch = 0;
1620 }
1621
1622 if (priv->ieee80211->state != IEEE80211_LINKED)
1623 return;
1624
1625 // For smooth, we can not change DIG state.
1626 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_low_thresh) &&
1627 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_thresh))
1628 {
1629 return;
1630 }
1631
1632 /* 1. When RSSI decrease, We have to judge if it is smaller than a threshold
1633 and then execute below step. */
1634 if ((priv->undecorated_smoothed_pwdb <= dm_digtable.rssi_low_thresh))
1635 {
1636 /* 2008/02/05 MH When we execute silent reset, the DIG PHY parameters
1637 will be reset to init value. We must prevent the condition. */
1638 if (dm_digtable.dig_state == DM_STA_DIG_OFF &&
1639 (priv->reset_count == reset_cnt))
1640 {
1641 return;
1642 }
1643 else
1644 {
1645 reset_cnt = priv->reset_count;
1646 }
1647
1648 // If DIG is off, DIG high power state must reset.
1649 dm_digtable.dig_highpwr_state = DM_STA_DIG_MAX;
1650 dm_digtable.dig_state = DM_STA_DIG_OFF;
1651
1652 // 1.1 DIG Off.
1653 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // Only clear byte 1 and rewrite.
1654
1655 // 1.2 Set initial gain.
1656 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x17);
1657 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x17);
1658 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x17);
1659 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x17);
1660
1661 // 1.3 Lower PD_TH for OFDM.
1662 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1663 {
1664 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1665 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1666 #ifdef RTL8190P
1667 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
1668 #else
1669 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
1670 #endif
1671 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1672 write_nic_byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1673 */
1674 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1675
1676
1677 //else
1678 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x40);
1679 }
1680 else
1681 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1682
1683 // 1.4 Lower CS ratio for CCK.
1684 write_nic_byte(dev, 0xa0a, 0x08);
1685
1686 // 1.5 Higher EDCCA.
1687 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x325);
1688 return;
1689
1690 }
1691
1692 /* 2. When RSSI increase, We have to judge if it is larger than a threshold
1693 and then execute below step. */
1694 if ((priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh) )
1695 {
1696 u8 reset_flag = 0;
1697
1698 if (dm_digtable.dig_state == DM_STA_DIG_ON &&
1699 (priv->reset_count == reset_cnt))
1700 {
1701 dm_ctrl_initgain_byrssi_highpwr(dev);
1702 return;
1703 }
1704 else
1705 {
1706 if (priv->reset_count != reset_cnt)
1707 reset_flag = 1;
1708
1709 reset_cnt = priv->reset_count;
1710 }
1711
1712 dm_digtable.dig_state = DM_STA_DIG_ON;
1713
1714 // 2.1 Set initial gain.
1715 // 2008/02/26 MH SD3-Jerry suggest to prevent dirty environment.
1716 if (reset_flag == 1)
1717 {
1718 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x2c);
1719 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x2c);
1720 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x2c);
1721 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x2c);
1722 }
1723 else
1724 {
1725 write_nic_byte(dev, rOFDM0_XAAGCCore1, 0x20);
1726 write_nic_byte(dev, rOFDM0_XBAGCCore1, 0x20);
1727 write_nic_byte(dev, rOFDM0_XCAGCCore1, 0x20);
1728 write_nic_byte(dev, rOFDM0_XDAGCCore1, 0x20);
1729 }
1730
1731 // 2.2 Higher PD_TH for OFDM.
1732 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1733 {
1734 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1735 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1736 #ifdef RTL8190P
1737 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1738 #else
1739 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1740 #endif
1741 /*
1742 else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1743 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1744 */
1745 //else if (pAdapter->HardwareType == HARDWARE_TYPE_RTL8192E)
1746
1747 //else
1748 //PlatformEFIOWrite1Byte(pAdapter, rOFDM0_RxDetector1, 0x42);
1749 }
1750 else
1751 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1752
1753 // 2.3 Higher CS ratio for CCK.
1754 write_nic_byte(dev, 0xa0a, 0xcd);
1755
1756 // 2.4 Lower EDCCA.
1757 /* 2008/01/11 MH 90/92 series are the same. */
1758 //PlatformEFIOWrite4Byte(pAdapter, rOFDM0_ECCAThreshold, 0x346);
1759
1760 // 2.5 DIG On.
1761 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // Only clear byte 1 and rewrite.
1762
1763 }
1764
1765 dm_ctrl_initgain_byrssi_highpwr(dev);
1766
1767 }
1768
1769 static void dm_ctrl_initgain_byrssi_highpwr(
1770 struct net_device * dev)
1771 {
1772 struct r8192_priv *priv = ieee80211_priv(dev);
1773 static u32 reset_cnt_highpwr = 0;
1774
1775 // For smooth, we can not change high power DIG state in the range.
1776 if ((priv->undecorated_smoothed_pwdb > dm_digtable.rssi_high_power_lowthresh) &&
1777 (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_highthresh))
1778 {
1779 return;
1780 }
1781
1782 /* 3. When RSSI >75% or <70%, it is a high power issue. We have to judge if
1783 it is larger than a threshold and then execute below step. */
1784 // 2008/02/05 MH SD3-Jerry Modify PD_TH for high power issue.
1785 if (priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_power_highthresh)
1786 {
1787 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_ON &&
1788 (priv->reset_count == reset_cnt_highpwr))
1789 return;
1790 else
1791 dm_digtable.dig_highpwr_state = DM_STA_DIG_ON;
1792
1793 // 3.1 Higher PD_TH for OFDM for high power state.
1794 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1795 {
1796 #ifdef RTL8190P
1797 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
1798 #else
1799 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
1800 #endif
1801
1802 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1803 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
1804 */
1805
1806 }
1807 else
1808 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
1809 }
1810 else
1811 {
1812 if (dm_digtable.dig_highpwr_state == DM_STA_DIG_OFF&&
1813 (priv->reset_count == reset_cnt_highpwr))
1814 return;
1815 else
1816 dm_digtable.dig_highpwr_state = DM_STA_DIG_OFF;
1817
1818 if (priv->undecorated_smoothed_pwdb < dm_digtable.rssi_high_power_lowthresh &&
1819 priv->undecorated_smoothed_pwdb >= dm_digtable.rssi_high_thresh)
1820 {
1821 // 3.2 Recover PD_TH for OFDM for normal power region.
1822 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1823 {
1824 #ifdef RTL8190P
1825 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1826 #else
1827 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1828 #endif
1829 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1830 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1831 */
1832
1833 }
1834 else
1835 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1836 }
1837 }
1838
1839 reset_cnt_highpwr = priv->reset_count;
1840
1841 }
1842
1843
1844 static void dm_initial_gain(
1845 struct net_device * dev)
1846 {
1847 struct r8192_priv *priv = ieee80211_priv(dev);
1848 u8 initial_gain=0;
1849 static u8 initialized=0, force_write=0;
1850 static u32 reset_cnt=0;
1851
1852 if(dm_digtable.dig_algorithm_switch)
1853 {
1854 initialized = 0;
1855 reset_cnt = 0;
1856 }
1857
1858 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
1859 {
1860 if(dm_digtable.cur_connect_state == DIG_CONNECT)
1861 {
1862 if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) > dm_digtable.rx_gain_range_max)
1863 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_max;
1864 else if((dm_digtable.rssi_val+10-dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
1865 dm_digtable.cur_ig_value = dm_digtable.rx_gain_range_min;
1866 else
1867 dm_digtable.cur_ig_value = dm_digtable.rssi_val+10-dm_digtable.backoff_val;
1868 }
1869 else //current state is disconnected
1870 {
1871 if(dm_digtable.cur_ig_value == 0)
1872 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1873 else
1874 dm_digtable.cur_ig_value = dm_digtable.pre_ig_value;
1875 }
1876 }
1877 else // disconnected -> connected or connected -> disconnected
1878 {
1879 dm_digtable.cur_ig_value = priv->DefaultInitialGain[0];
1880 dm_digtable.pre_ig_value = 0;
1881 }
1882
1883 // if silent reset happened, we should rewrite the values back
1884 if(priv->reset_count != reset_cnt)
1885 {
1886 force_write = 1;
1887 reset_cnt = priv->reset_count;
1888 }
1889
1890 if(dm_digtable.pre_ig_value != read_nic_byte(dev, rOFDM0_XAAGCCore1))
1891 force_write = 1;
1892
1893 {
1894 if((dm_digtable.pre_ig_value != dm_digtable.cur_ig_value)
1895 || !initialized || force_write)
1896 {
1897 initial_gain = (u8)dm_digtable.cur_ig_value;
1898 // Set initial gain.
1899 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
1900 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
1901 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
1902 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
1903 dm_digtable.pre_ig_value = dm_digtable.cur_ig_value;
1904 initialized = 1;
1905 force_write = 0;
1906 }
1907 }
1908 }
1909
1910 static void dm_pd_th(
1911 struct net_device * dev)
1912 {
1913 struct r8192_priv *priv = ieee80211_priv(dev);
1914 static u8 initialized=0, force_write=0;
1915 static u32 reset_cnt = 0;
1916
1917 if(dm_digtable.dig_algorithm_switch)
1918 {
1919 initialized = 0;
1920 reset_cnt = 0;
1921 }
1922
1923 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
1924 {
1925 if(dm_digtable.cur_connect_state == DIG_CONNECT)
1926 {
1927 if (dm_digtable.rssi_val >= dm_digtable.rssi_high_power_highthresh)
1928 dm_digtable.curpd_thstate = DIG_PD_AT_HIGH_POWER;
1929 else if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
1930 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1931 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) &&
1932 (dm_digtable.rssi_val < dm_digtable.rssi_high_power_lowthresh))
1933 dm_digtable.curpd_thstate = DIG_PD_AT_NORMAL_POWER;
1934 else
1935 dm_digtable.curpd_thstate = dm_digtable.prepd_thstate;
1936 }
1937 else
1938 {
1939 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1940 }
1941 }
1942 else // disconnected -> connected or connected -> disconnected
1943 {
1944 dm_digtable.curpd_thstate = DIG_PD_AT_LOW_POWER;
1945 }
1946
1947 // if silent reset happened, we should rewrite the values back
1948 if(priv->reset_count != reset_cnt)
1949 {
1950 force_write = 1;
1951 reset_cnt = priv->reset_count;
1952 }
1953
1954 {
1955 if((dm_digtable.prepd_thstate != dm_digtable.curpd_thstate) ||
1956 (initialized<=3) || force_write)
1957 {
1958 if(dm_digtable.curpd_thstate == DIG_PD_AT_LOW_POWER)
1959 {
1960 // Lower PD_TH for OFDM.
1961 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1962 {
1963 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1964 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1965 #ifdef RTL8190P
1966 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
1967 #else
1968 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x00);
1969 #endif
1970 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1971 write_nic_byte(dev, rOFDM0_RxDetector1, 0x40);
1972 */
1973 }
1974 else
1975 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1976 }
1977 else if(dm_digtable.curpd_thstate == DIG_PD_AT_NORMAL_POWER)
1978 {
1979 // Higher PD_TH for OFDM.
1980 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
1981 {
1982 /* 2008/01/11 MH 40MHZ 90/92 register are not the same. */
1983 // 2008/02/05 MH SD3-Jerry 92U/92E PD_TH are the same.
1984 #ifdef RTL8190P
1985 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1986 #else
1987 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x20);
1988 #endif
1989 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
1990 write_nic_byte(dev, rOFDM0_RxDetector1, 0x42);
1991 */
1992 }
1993 else
1994 write_nic_byte(dev, rOFDM0_RxDetector1, 0x44);
1995 }
1996 else if(dm_digtable.curpd_thstate == DIG_PD_AT_HIGH_POWER)
1997 {
1998 // Higher PD_TH for OFDM for high power state.
1999 if (priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20)
2000 {
2001 #ifdef RTL8190P
2002 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2003 #else
2004 write_nic_byte(dev, (rOFDM0_XATxAFE+3), 0x10);
2005 #endif
2006 /*else if (priv->card_8192 == HARDWARE_TYPE_RTL8190P)
2007 write_nic_byte(dev, rOFDM0_RxDetector1, 0x41);
2008 */
2009 }
2010 else
2011 write_nic_byte(dev, rOFDM0_RxDetector1, 0x43);
2012 }
2013 dm_digtable.prepd_thstate = dm_digtable.curpd_thstate;
2014 if(initialized <= 3)
2015 initialized++;
2016 force_write = 0;
2017 }
2018 }
2019 }
2020
2021 static void dm_cs_ratio(
2022 struct net_device * dev)
2023 {
2024 struct r8192_priv *priv = ieee80211_priv(dev);
2025 static u8 initialized=0,force_write=0;
2026 static u32 reset_cnt = 0;
2027
2028 if(dm_digtable.dig_algorithm_switch)
2029 {
2030 initialized = 0;
2031 reset_cnt = 0;
2032 }
2033
2034 if(dm_digtable.pre_connect_state == dm_digtable.cur_connect_state)
2035 {
2036 if(dm_digtable.cur_connect_state == DIG_CONNECT)
2037 {
2038 if ((dm_digtable.rssi_val <= dm_digtable.rssi_low_thresh))
2039 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2040 else if ((dm_digtable.rssi_val >= dm_digtable.rssi_high_thresh) )
2041 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_HIGHER;
2042 else
2043 dm_digtable.curcs_ratio_state = dm_digtable.precs_ratio_state;
2044 }
2045 else
2046 {
2047 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2048 }
2049 }
2050 else // disconnected -> connected or connected -> disconnected
2051 {
2052 dm_digtable.curcs_ratio_state = DIG_CS_RATIO_LOWER;
2053 }
2054
2055 // if silent reset happened, we should rewrite the values back
2056 if(priv->reset_count != reset_cnt)
2057 {
2058 force_write = 1;
2059 reset_cnt = priv->reset_count;
2060 }
2061
2062
2063 if((dm_digtable.precs_ratio_state != dm_digtable.curcs_ratio_state) ||
2064 !initialized || force_write)
2065 {
2066 if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_LOWER)
2067 {
2068 // Lower CS ratio for CCK.
2069 write_nic_byte(dev, 0xa0a, 0x08);
2070 }
2071 else if(dm_digtable.curcs_ratio_state == DIG_CS_RATIO_HIGHER)
2072 {
2073 // Higher CS ratio for CCK.
2074 write_nic_byte(dev, 0xa0a, 0xcd);
2075 }
2076 dm_digtable.precs_ratio_state = dm_digtable.curcs_ratio_state;
2077 initialized = 1;
2078 force_write = 0;
2079 }
2080 }
2081
2082 void dm_init_edca_turbo(struct net_device *dev)
2083 {
2084 struct r8192_priv *priv = ieee80211_priv(dev);
2085
2086 priv->bcurrent_turbo_EDCA = false;
2087 priv->ieee80211->bis_any_nonbepkts = false;
2088 priv->bis_cur_rdlstate = false;
2089 }
2090
2091 #if 1
2092 static void dm_check_edca_turbo(
2093 struct net_device * dev)
2094 {
2095 struct r8192_priv *priv = ieee80211_priv(dev);
2096 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2097 //PSTA_QOS pStaQos = pMgntInfo->pStaQos;
2098
2099 // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
2100 static unsigned long lastTxOkCnt = 0;
2101 static unsigned long lastRxOkCnt = 0;
2102 unsigned long curTxOkCnt = 0;
2103 unsigned long curRxOkCnt = 0;
2104
2105 //
2106 // Do not be Turbo if it's under WiFi config and Qos Enabled, because the EDCA parameters
2107 // should follow the settings from QAP. By Bruce, 2007-12-07.
2108 //
2109 #if 1
2110 if(priv->ieee80211->state != IEEE80211_LINKED)
2111 goto dm_CheckEdcaTurbo_EXIT;
2112 #endif
2113 // We do not turn on EDCA turbo mode for some AP that has IOT issue
2114 if(priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO)
2115 goto dm_CheckEdcaTurbo_EXIT;
2116
2117 // Check the status for current condition.
2118 if(!priv->ieee80211->bis_any_nonbepkts)
2119 {
2120 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2121 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2122 // For RT-AP, we needs to turn it on when Rx>Tx
2123 if(curRxOkCnt > 4*curTxOkCnt)
2124 {
2125 if(!priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2126 {
2127 write_nic_dword(dev, EDCAPARA_BE, edca_setting_DL[pHTInfo->IOTPeer]);
2128 priv->bis_cur_rdlstate = true;
2129 }
2130 }
2131 else
2132 {
2133 if(priv->bis_cur_rdlstate || !priv->bcurrent_turbo_EDCA)
2134 {
2135 write_nic_dword(dev, EDCAPARA_BE, edca_setting_UL[pHTInfo->IOTPeer]);
2136 priv->bis_cur_rdlstate = false;
2137 }
2138
2139 }
2140
2141 priv->bcurrent_turbo_EDCA = true;
2142 }
2143 else
2144 {
2145 //
2146 // Turn Off EDCA turbo here.
2147 // Restore original EDCA according to the declaration of AP.
2148 //
2149 if(priv->bcurrent_turbo_EDCA)
2150 {
2151
2152 {
2153 u8 u1bAIFS;
2154 u32 u4bAcParam;
2155 struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters;
2156 u8 mode = priv->ieee80211->mode;
2157
2158 // For Each time updating EDCA parameter, reset EDCA turbo mode status.
2159 dm_init_edca_turbo(dev);
2160 u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ?9:20) + aSifsTime;
2161 u4bAcParam = ((((u32)(qos_parameters->tx_op_limit[0]))<< AC_PARAM_TXOP_LIMIT_OFFSET)|
2162 (((u32)(qos_parameters->cw_max[0]))<< AC_PARAM_ECW_MAX_OFFSET)|
2163 (((u32)(qos_parameters->cw_min[0]))<< AC_PARAM_ECW_MIN_OFFSET)|
2164 ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET));
2165 printk("===>u4bAcParam:%x, ", u4bAcParam);
2166 //write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);
2167 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
2168
2169 // Check ACM bit.
2170 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
2171 {
2172 // TODO: Modified this part and try to set acm control in only 1 IO processing!!
2173
2174 PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]);
2175 u8 AcmCtrl = read_nic_byte( dev, AcmHwCtrl );
2176 if( pAciAifsn->f.ACM )
2177 { // ACM bit is 1.
2178 AcmCtrl |= AcmHw_BeqEn;
2179 }
2180 else
2181 { // ACM bit is 0.
2182 AcmCtrl &= (~AcmHw_BeqEn);
2183 }
2184
2185 RT_TRACE( COMP_QOS,"SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ) ;
2186 write_nic_byte(dev, AcmHwCtrl, AcmCtrl );
2187 }
2188 }
2189 priv->bcurrent_turbo_EDCA = false;
2190 }
2191 }
2192
2193
2194 dm_CheckEdcaTurbo_EXIT:
2195 // Set variables for next time.
2196 priv->ieee80211->bis_any_nonbepkts = false;
2197 lastTxOkCnt = priv->stats.txbytesunicast;
2198 lastRxOkCnt = priv->stats.rxbytesunicast;
2199 }
2200 #endif
2201
2202 static void dm_init_ctstoself(struct net_device * dev)
2203 {
2204 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2205
2206 priv->ieee80211->bCTSToSelfEnable = TRUE;
2207 priv->ieee80211->CTSToSelfTH = CTSToSelfTHVal;
2208 }
2209
2210 static void dm_ctstoself(struct net_device *dev)
2211 {
2212 struct r8192_priv *priv = ieee80211_priv((struct net_device *)dev);
2213 PRT_HIGH_THROUGHPUT pHTInfo = priv->ieee80211->pHTInfo;
2214 static unsigned long lastTxOkCnt = 0;
2215 static unsigned long lastRxOkCnt = 0;
2216 unsigned long curTxOkCnt = 0;
2217 unsigned long curRxOkCnt = 0;
2218
2219 if(priv->ieee80211->bCTSToSelfEnable != TRUE)
2220 {
2221 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2222 return;
2223 }
2224 /*
2225 1. Uplink
2226 2. Linksys350/Linksys300N
2227 3. <50 disable, >55 enable
2228 */
2229
2230 if(pHTInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
2231 {
2232 curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt;
2233 curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt;
2234 if(curRxOkCnt > 4*curTxOkCnt) //downlink, disable CTS to self
2235 {
2236 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2237 }
2238 else //uplink
2239 {
2240 #if 1
2241 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2242 #else
2243 if(priv->undecorated_smoothed_pwdb < priv->ieee80211->CTSToSelfTH) // disable CTS to self
2244 {
2245 pHTInfo->IOTAction &= ~HT_IOT_ACT_FORCED_CTS2SELF;
2246 }
2247 else if(priv->undecorated_smoothed_pwdb >= (priv->ieee80211->CTSToSelfTH+5)) // enable CTS to self
2248 {
2249 pHTInfo->IOTAction |= HT_IOT_ACT_FORCED_CTS2SELF;
2250 }
2251 #endif
2252 }
2253
2254 lastTxOkCnt = priv->stats.txbytesunicast;
2255 lastRxOkCnt = priv->stats.rxbytesunicast;
2256 }
2257 }
2258
2259
2260
2261 /* Copy 8187B template for 9xseries */
2262 #if 1
2263 static void dm_check_rfctrl_gpio(struct net_device * dev)
2264 {
2265 #ifdef RTL8192E
2266 struct r8192_priv *priv = ieee80211_priv(dev);
2267 #endif
2268
2269 // Walk around for DTM test, we will not enable HW - radio on/off because r/w
2270 // page 1 register before Lextra bus is enabled cause system fails when resuming
2271 // from S4. 20080218, Emily
2272
2273 // Stop to execute workitem to prevent S3/S4 bug.
2274 #ifdef RTL8190P
2275 return;
2276 #endif
2277 #ifdef RTL8192U
2278 return;
2279 #endif
2280 #ifdef RTL8192E
2281 queue_delayed_work(priv->priv_wq,&priv->gpio_change_rf_wq,0);
2282 #endif
2283
2284 }
2285
2286 #endif
2287 /* Check if PBC button is pressed. */
2288 static void dm_check_pbc_gpio(struct net_device *dev)
2289 {
2290 #ifdef RTL8192U
2291 struct r8192_priv *priv = ieee80211_priv(dev);
2292 u8 tmp1byte;
2293
2294
2295 tmp1byte = read_nic_byte(dev,GPI);
2296 if(tmp1byte == 0xff)
2297 return;
2298
2299 if (tmp1byte&BIT6 || tmp1byte&BIT0)
2300 {
2301 // Here we only set bPbcPressed to TRUE
2302 // After trigger PBC, the variable will be set to FALSE
2303 RT_TRACE(COMP_IO, "CheckPbcGPIO - PBC is pressed\n");
2304 }
2305 #endif
2306
2307 }
2308
2309 #ifdef RTL8192E
2310
2311 /* PCI will not support workitem call back HW radio on-off control. */
2312 void dm_gpio_change_rf_callback(struct work_struct *work)
2313 {
2314 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
2315 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,gpio_change_rf_wq);
2316 struct net_device *dev = priv->ieee80211->dev;
2317 u8 tmp1byte;
2318 RT_RF_POWER_STATE eRfPowerStateToSet;
2319 bool bActuallySet = false;
2320
2321 if (!priv->up) {
2322 RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF),"dm_gpio_change_rf_callback(): Callback function breaks out!!\n");
2323 } else {
2324 // 0x108 GPIO input register is read only
2325 //set 0x108 B1= 1: RF-ON; 0: RF-OFF.
2326 tmp1byte = read_nic_byte(dev,GPI);
2327
2328 eRfPowerStateToSet = (tmp1byte&BIT1) ? eRfOn : eRfOff;
2329
2330 if (priv->bHwRadioOff && (eRfPowerStateToSet == eRfOn)) {
2331 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio ON\n");
2332
2333 priv->bHwRadioOff = false;
2334 bActuallySet = true;
2335 } else if ((!priv->bHwRadioOff) && (eRfPowerStateToSet == eRfOff)) {
2336 RT_TRACE(COMP_RF, "gpiochangeRF - HW Radio OFF\n");
2337 priv->bHwRadioOff = true;
2338 bActuallySet = true;
2339 }
2340
2341 if (bActuallySet) {
2342 priv->bHwRfOffAction = 1;
2343 MgntActSet_RF_State(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW);
2344 //DrvIFIndicateCurrentPhyStatus(pAdapter);
2345 } else {
2346 msleep(2000);
2347 }
2348 }
2349 }
2350
2351 #endif
2352
2353 /* Check if Current RF RX path is enabled */
2354 void dm_rf_pathcheck_workitemcallback(struct work_struct *work)
2355 {
2356 struct delayed_work *dwork = container_of(work,struct delayed_work,work);
2357 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,rfpath_check_wq);
2358 struct net_device *dev =priv->ieee80211->dev;
2359 //bool bactually_set = false;
2360 u8 rfpath = 0, i;
2361
2362
2363 /* 2008/01/30 MH After discussing with SD3 Jerry, 0xc04/0xd04 register will
2364 always be the same. We only read 0xc04 now. */
2365 rfpath = read_nic_byte(dev, 0xc04);
2366
2367 // Check Bit 0-3, it means if RF A-D is enabled.
2368 for (i = 0; i < RF90_PATH_MAX; i++)
2369 {
2370 if (rfpath & (0x01<<i))
2371 priv->brfpath_rxenable[i] = 1;
2372 else
2373 priv->brfpath_rxenable[i] = 0;
2374 }
2375 if(!DM_RxPathSelTable.Enable)
2376 return;
2377
2378 dm_rxpath_sel_byrssi(dev);
2379 }
2380
2381 static void dm_init_rxpath_selection(struct net_device * dev)
2382 {
2383 u8 i;
2384 struct r8192_priv *priv = ieee80211_priv(dev);
2385 DM_RxPathSelTable.Enable = 1; //default enabled
2386 DM_RxPathSelTable.SS_TH_low = RxPathSelection_SS_TH_low;
2387 DM_RxPathSelTable.diff_TH = RxPathSelection_diff_TH;
2388 if(priv->CustomerID == RT_CID_819x_Netcore)
2389 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2;
2390 else
2391 DM_RxPathSelTable.cck_method = CCK_Rx_Version_1;
2392 DM_RxPathSelTable.DbgMode = DM_DBG_OFF;
2393 DM_RxPathSelTable.disabledRF = 0;
2394 for(i=0; i<4; i++)
2395 {
2396 DM_RxPathSelTable.rf_rssi[i] = 50;
2397 DM_RxPathSelTable.cck_pwdb_sta[i] = -64;
2398 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2399 }
2400 }
2401
2402 static void dm_rxpath_sel_byrssi(struct net_device * dev)
2403 {
2404 struct r8192_priv *priv = ieee80211_priv(dev);
2405 u8 i, max_rssi_index=0, min_rssi_index=0, sec_rssi_index=0, rf_num=0;
2406 u8 tmp_max_rssi=0, tmp_min_rssi=0, tmp_sec_rssi=0;
2407 u8 cck_default_Rx=0x2; //RF-C
2408 u8 cck_optional_Rx=0x3;//RF-D
2409 long tmp_cck_max_pwdb=0, tmp_cck_min_pwdb=0, tmp_cck_sec_pwdb=0;
2410 u8 cck_rx_ver2_max_index=0, cck_rx_ver2_min_index=0, cck_rx_ver2_sec_index=0;
2411 u8 cur_rf_rssi;
2412 long cur_cck_pwdb;
2413 static u8 disabled_rf_cnt=0, cck_Rx_Path_initialized=0;
2414 u8 update_cck_rx_path;
2415
2416 if(priv->rf_type != RF_2T4R)
2417 return;
2418
2419 if(!cck_Rx_Path_initialized)
2420 {
2421 DM_RxPathSelTable.cck_Rx_path = (read_nic_byte(dev, 0xa07)&0xf);
2422 cck_Rx_Path_initialized = 1;
2423 }
2424
2425 DM_RxPathSelTable.disabledRF = 0xf;
2426 DM_RxPathSelTable.disabledRF &=~ (read_nic_byte(dev, 0xc04));
2427
2428 if(priv->ieee80211->mode == WIRELESS_MODE_B)
2429 {
2430 DM_RxPathSelTable.cck_method = CCK_Rx_Version_2; //pure B mode, fixed cck version2
2431 }
2432
2433 //decide max/sec/min rssi index
2434 for (i=0; i<RF90_PATH_MAX; i++)
2435 {
2436 if(!DM_RxPathSelTable.DbgMode)
2437 DM_RxPathSelTable.rf_rssi[i] = priv->stats.rx_rssi_percentage[i];
2438
2439 if(priv->brfpath_rxenable[i])
2440 {
2441 rf_num++;
2442 cur_rf_rssi = DM_RxPathSelTable.rf_rssi[i];
2443
2444 if(rf_num == 1) // find first enabled rf path and the rssi values
2445 { //initialize, set all rssi index to the same one
2446 max_rssi_index = min_rssi_index = sec_rssi_index = i;
2447 tmp_max_rssi = tmp_min_rssi = tmp_sec_rssi = cur_rf_rssi;
2448 }
2449 else if(rf_num == 2)
2450 { // we pick up the max index first, and let sec and min to be the same one
2451 if(cur_rf_rssi >= tmp_max_rssi)
2452 {
2453 tmp_max_rssi = cur_rf_rssi;
2454 max_rssi_index = i;
2455 }
2456 else
2457 {
2458 tmp_sec_rssi = tmp_min_rssi = cur_rf_rssi;
2459 sec_rssi_index = min_rssi_index = i;
2460 }
2461 }
2462 else
2463 {
2464 if(cur_rf_rssi > tmp_max_rssi)
2465 {
2466 tmp_sec_rssi = tmp_max_rssi;
2467 sec_rssi_index = max_rssi_index;
2468 tmp_max_rssi = cur_rf_rssi;
2469 max_rssi_index = i;
2470 }
2471 else if(cur_rf_rssi == tmp_max_rssi)
2472 { // let sec and min point to the different index
2473 tmp_sec_rssi = cur_rf_rssi;
2474 sec_rssi_index = i;
2475 }
2476 else if((cur_rf_rssi < tmp_max_rssi) &&(cur_rf_rssi > tmp_sec_rssi))
2477 {
2478 tmp_sec_rssi = cur_rf_rssi;
2479 sec_rssi_index = i;
2480 }
2481 else if(cur_rf_rssi == tmp_sec_rssi)
2482 {
2483 if(tmp_sec_rssi == tmp_min_rssi)
2484 { // let sec and min point to the different index
2485 tmp_sec_rssi = cur_rf_rssi;
2486 sec_rssi_index = i;
2487 }
2488 else
2489 {
2490 // This case we don't need to set any index
2491 }
2492 }
2493 else if((cur_rf_rssi < tmp_sec_rssi) && (cur_rf_rssi > tmp_min_rssi))
2494 {
2495 // This case we don't need to set any index
2496 }
2497 else if(cur_rf_rssi == tmp_min_rssi)
2498 {
2499 if(tmp_sec_rssi == tmp_min_rssi)
2500 { // let sec and min point to the different index
2501 tmp_min_rssi = cur_rf_rssi;
2502 min_rssi_index = i;
2503 }
2504 else
2505 {
2506 // This case we don't need to set any index
2507 }
2508 }
2509 else if(cur_rf_rssi < tmp_min_rssi)
2510 {
2511 tmp_min_rssi = cur_rf_rssi;
2512 min_rssi_index = i;
2513 }
2514 }
2515 }
2516 }
2517
2518 rf_num = 0;
2519 // decide max/sec/min cck pwdb index
2520 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
2521 {
2522 for (i=0; i<RF90_PATH_MAX; i++)
2523 {
2524 if(priv->brfpath_rxenable[i])
2525 {
2526 rf_num++;
2527 cur_cck_pwdb = DM_RxPathSelTable.cck_pwdb_sta[i];
2528
2529 if(rf_num == 1) // find first enabled rf path and the rssi values
2530 { //initialize, set all rssi index to the same one
2531 cck_rx_ver2_max_index = cck_rx_ver2_min_index = cck_rx_ver2_sec_index = i;
2532 tmp_cck_max_pwdb = tmp_cck_min_pwdb = tmp_cck_sec_pwdb = cur_cck_pwdb;
2533 }
2534 else if(rf_num == 2)
2535 { // we pick up the max index first, and let sec and min to be the same one
2536 if(cur_cck_pwdb >= tmp_cck_max_pwdb)
2537 {
2538 tmp_cck_max_pwdb = cur_cck_pwdb;
2539 cck_rx_ver2_max_index = i;
2540 }
2541 else
2542 {
2543 tmp_cck_sec_pwdb = tmp_cck_min_pwdb = cur_cck_pwdb;
2544 cck_rx_ver2_sec_index = cck_rx_ver2_min_index = i;
2545 }
2546 }
2547 else
2548 {
2549 if(cur_cck_pwdb > tmp_cck_max_pwdb)
2550 {
2551 tmp_cck_sec_pwdb = tmp_cck_max_pwdb;
2552 cck_rx_ver2_sec_index = cck_rx_ver2_max_index;
2553 tmp_cck_max_pwdb = cur_cck_pwdb;
2554 cck_rx_ver2_max_index = i;
2555 }
2556 else if(cur_cck_pwdb == tmp_cck_max_pwdb)
2557 { // let sec and min point to the different index
2558 tmp_cck_sec_pwdb = cur_cck_pwdb;
2559 cck_rx_ver2_sec_index = i;
2560 }
2561 else if((cur_cck_pwdb < tmp_cck_max_pwdb) &&(cur_cck_pwdb > tmp_cck_sec_pwdb))
2562 {
2563 tmp_cck_sec_pwdb = cur_cck_pwdb;
2564 cck_rx_ver2_sec_index = i;
2565 }
2566 else if(cur_cck_pwdb == tmp_cck_sec_pwdb)
2567 {
2568 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
2569 { // let sec and min point to the different index
2570 tmp_cck_sec_pwdb = cur_cck_pwdb;
2571 cck_rx_ver2_sec_index = i;
2572 }
2573 else
2574 {
2575 // This case we don't need to set any index
2576 }
2577 }
2578 else if((cur_cck_pwdb < tmp_cck_sec_pwdb) && (cur_cck_pwdb > tmp_cck_min_pwdb))
2579 {
2580 // This case we don't need to set any index
2581 }
2582 else if(cur_cck_pwdb == tmp_cck_min_pwdb)
2583 {
2584 if(tmp_cck_sec_pwdb == tmp_cck_min_pwdb)
2585 { // let sec and min point to the different index
2586 tmp_cck_min_pwdb = cur_cck_pwdb;
2587 cck_rx_ver2_min_index = i;
2588 }
2589 else
2590 {
2591 // This case we don't need to set any index
2592 }
2593 }
2594 else if(cur_cck_pwdb < tmp_cck_min_pwdb)
2595 {
2596 tmp_cck_min_pwdb = cur_cck_pwdb;
2597 cck_rx_ver2_min_index = i;
2598 }
2599 }
2600
2601 }
2602 }
2603 }
2604
2605
2606 // Set CCK Rx path
2607 // reg0xA07[3:2]=cck default rx path, reg0xa07[1:0]=cck optional rx path.
2608 update_cck_rx_path = 0;
2609 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_2)
2610 {
2611 cck_default_Rx = cck_rx_ver2_max_index;
2612 cck_optional_Rx = cck_rx_ver2_sec_index;
2613 if(tmp_cck_max_pwdb != -64)
2614 update_cck_rx_path = 1;
2615 }
2616
2617 if(tmp_min_rssi < DM_RxPathSelTable.SS_TH_low && disabled_rf_cnt < 2)
2618 {
2619 if((tmp_max_rssi - tmp_min_rssi) >= DM_RxPathSelTable.diff_TH)
2620 {
2621 //record the enabled rssi threshold
2622 DM_RxPathSelTable.rf_enable_rssi_th[min_rssi_index] = tmp_max_rssi+5;
2623 //disable the BB Rx path, OFDM
2624 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xc04[3:0]
2625 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<min_rssi_index, 0x0); // 0xd04[3:0]
2626 disabled_rf_cnt++;
2627 }
2628 if(DM_RxPathSelTable.cck_method == CCK_Rx_Version_1)
2629 {
2630 cck_default_Rx = max_rssi_index;
2631 cck_optional_Rx = sec_rssi_index;
2632 if(tmp_max_rssi)
2633 update_cck_rx_path = 1;
2634 }
2635 }
2636
2637 if(update_cck_rx_path)
2638 {
2639 DM_RxPathSelTable.cck_Rx_path = (cck_default_Rx<<2)|(cck_optional_Rx);
2640 rtl8192_setBBreg(dev, rCCK0_AFESetting, 0x0f000000, DM_RxPathSelTable.cck_Rx_path);
2641 }
2642
2643 if(DM_RxPathSelTable.disabledRF)
2644 {
2645 for(i=0; i<4; i++)
2646 {
2647 if((DM_RxPathSelTable.disabledRF>>i) & 0x1) //disabled rf
2648 {
2649 if(tmp_max_rssi >= DM_RxPathSelTable.rf_enable_rssi_th[i])
2650 {
2651 //enable the BB Rx path
2652 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x1<<i, 0x1); // 0xc04[3:0]
2653 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x1<<i, 0x1); // 0xd04[3:0]
2654 DM_RxPathSelTable.rf_enable_rssi_th[i] = 100;
2655 disabled_rf_cnt--;
2656 }
2657 }
2658 }
2659 }
2660 }
2661
2662 /*
2663 * Call a workitem to check current RXRF path and Rx Path selection by RSSI.
2664 */
2665 static void dm_check_rx_path_selection(struct net_device *dev)
2666 {
2667 struct r8192_priv *priv = ieee80211_priv(dev);
2668 queue_delayed_work(priv->priv_wq,&priv->rfpath_check_wq,0);
2669 }
2670
2671 static void dm_init_fsync (struct net_device *dev)
2672 {
2673 struct r8192_priv *priv = ieee80211_priv(dev);
2674
2675 priv->ieee80211->fsync_time_interval = 500;
2676 priv->ieee80211->fsync_rate_bitmap = 0x0f000800;
2677 priv->ieee80211->fsync_rssi_threshold = 30;
2678 #ifdef RTL8190P
2679 priv->ieee80211->bfsync_enable = true;
2680 #else
2681 priv->ieee80211->bfsync_enable = false;
2682 #endif
2683 priv->ieee80211->fsync_multiple_timeinterval = 3;
2684 priv->ieee80211->fsync_firstdiff_ratethreshold= 100;
2685 priv->ieee80211->fsync_seconddiff_ratethreshold= 200;
2686 priv->ieee80211->fsync_state = Default_Fsync;
2687 priv->framesyncMonitor = 1; // current default 0xc38 monitor on
2688
2689 init_timer(&priv->fsync_timer);
2690 priv->fsync_timer.data = (unsigned long)dev;
2691 priv->fsync_timer.function = dm_fsync_timer_callback;
2692 }
2693
2694
2695 static void dm_deInit_fsync(struct net_device *dev)
2696 {
2697 struct r8192_priv *priv = ieee80211_priv(dev);
2698 del_timer_sync(&priv->fsync_timer);
2699 }
2700
2701 void dm_fsync_timer_callback(unsigned long data)
2702 {
2703 struct net_device *dev = (struct net_device *)data;
2704 struct r8192_priv *priv = ieee80211_priv((struct net_device *)data);
2705 u32 rate_index, rate_count = 0, rate_count_diff=0;
2706 bool bSwitchFromCountDiff = false;
2707 bool bDoubleTimeInterval = false;
2708
2709 if( priv->ieee80211->state == IEEE80211_LINKED &&
2710 priv->ieee80211->bfsync_enable &&
2711 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
2712 {
2713 // Count rate 54, MCS [7], [12, 13, 14, 15]
2714 u32 rate_bitmap;
2715 for(rate_index = 0; rate_index <= 27; rate_index++)
2716 {
2717 rate_bitmap = 1 << rate_index;
2718 if(priv->ieee80211->fsync_rate_bitmap & rate_bitmap)
2719 rate_count+= priv->stats.received_rate_histogram[1][rate_index];
2720 }
2721
2722 if(rate_count < priv->rate_record)
2723 rate_count_diff = 0xffffffff - rate_count + priv->rate_record;
2724 else
2725 rate_count_diff = rate_count - priv->rate_record;
2726 if(rate_count_diff < priv->rateCountDiffRecord)
2727 {
2728
2729 u32 DiffNum = priv->rateCountDiffRecord - rate_count_diff;
2730 // Contiune count
2731 if(DiffNum >= priv->ieee80211->fsync_seconddiff_ratethreshold)
2732 priv->ContiuneDiffCount++;
2733 else
2734 priv->ContiuneDiffCount = 0;
2735
2736 // Contiune count over
2737 if(priv->ContiuneDiffCount >=2)
2738 {
2739 bSwitchFromCountDiff = true;
2740 priv->ContiuneDiffCount = 0;
2741 }
2742 }
2743 else
2744 {
2745 // Stop contiune count
2746 priv->ContiuneDiffCount = 0;
2747 }
2748
2749 //If Count diff <= FsyncRateCountThreshold
2750 if(rate_count_diff <= priv->ieee80211->fsync_firstdiff_ratethreshold)
2751 {
2752 bSwitchFromCountDiff = true;
2753 priv->ContiuneDiffCount = 0;
2754 }
2755 priv->rate_record = rate_count;
2756 priv->rateCountDiffRecord = rate_count_diff;
2757 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
2758 // if we never receive those mcs rate and rssi > 30 % then switch fsyn
2759 if(priv->undecorated_smoothed_pwdb > priv->ieee80211->fsync_rssi_threshold && bSwitchFromCountDiff)
2760 {
2761 bDoubleTimeInterval = true;
2762 priv->bswitch_fsync = !priv->bswitch_fsync;
2763 if(priv->bswitch_fsync)
2764 {
2765 #ifdef RTL8190P
2766 write_nic_byte(dev,0xC36, 0x00);
2767 #else
2768 write_nic_byte(dev,0xC36, 0x1c);
2769 #endif
2770 write_nic_byte(dev, 0xC3e, 0x90);
2771 }
2772 else
2773 {
2774 #ifdef RTL8190P
2775 write_nic_byte(dev, 0xC36, 0x40);
2776 #else
2777 write_nic_byte(dev, 0xC36, 0x5c);
2778 #endif
2779 write_nic_byte(dev, 0xC3e, 0x96);
2780 }
2781 }
2782 else if(priv->undecorated_smoothed_pwdb <= priv->ieee80211->fsync_rssi_threshold)
2783 {
2784 if(priv->bswitch_fsync)
2785 {
2786 priv->bswitch_fsync = false;
2787 #ifdef RTL8190P
2788 write_nic_byte(dev, 0xC36, 0x40);
2789 #else
2790 write_nic_byte(dev, 0xC36, 0x5c);
2791 #endif
2792 write_nic_byte(dev, 0xC3e, 0x96);
2793 }
2794 }
2795 if(bDoubleTimeInterval){
2796 if(timer_pending(&priv->fsync_timer))
2797 del_timer_sync(&priv->fsync_timer);
2798 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval*priv->ieee80211->fsync_multiple_timeinterval);
2799 add_timer(&priv->fsync_timer);
2800 }
2801 else{
2802 if(timer_pending(&priv->fsync_timer))
2803 del_timer_sync(&priv->fsync_timer);
2804 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
2805 add_timer(&priv->fsync_timer);
2806 }
2807 }
2808 else
2809 {
2810 // Let Register return to default value;
2811 if(priv->bswitch_fsync)
2812 {
2813 priv->bswitch_fsync = false;
2814 #ifdef RTL8190P
2815 write_nic_byte(dev, 0xC36, 0x40);
2816 #else
2817 write_nic_byte(dev, 0xC36, 0x5c);
2818 #endif
2819 write_nic_byte(dev, 0xC3e, 0x96);
2820 }
2821 priv->ContiuneDiffCount = 0;
2822 #ifdef RTL8190P
2823 write_nic_dword(dev, rOFDM0_RxDetector2, 0x164052cd);
2824 #else
2825 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2826 #endif
2827 }
2828 RT_TRACE(COMP_HALDM, "ContiuneDiffCount %d\n", priv->ContiuneDiffCount);
2829 RT_TRACE(COMP_HALDM, "rateRecord %d rateCount %d, rateCountdiff %d bSwitchFsync %d\n", priv->rate_record, rate_count, rate_count_diff , priv->bswitch_fsync);
2830 }
2831
2832 static void dm_StartHWFsync(struct net_device *dev)
2833 {
2834 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
2835 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cf);
2836 write_nic_byte(dev, 0xc3b, 0x41);
2837 }
2838
2839 static void dm_EndSWFsync(struct net_device *dev)
2840 {
2841 struct r8192_priv *priv = ieee80211_priv(dev);
2842
2843 RT_TRACE(COMP_HALDM, "%s\n", __FUNCTION__);
2844 del_timer_sync(&(priv->fsync_timer));
2845
2846 // Let Register return to default value;
2847 if(priv->bswitch_fsync)
2848 {
2849 priv->bswitch_fsync = false;
2850
2851 #ifdef RTL8190P
2852 write_nic_byte(dev, 0xC36, 0x40);
2853 #else
2854 write_nic_byte(dev, 0xC36, 0x5c);
2855 #endif
2856
2857 write_nic_byte(dev, 0xC3e, 0x96);
2858 }
2859
2860 priv->ContiuneDiffCount = 0;
2861 #ifndef RTL8190P
2862 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2863 #endif
2864
2865 }
2866
2867 static void dm_StartSWFsync(struct net_device *dev)
2868 {
2869 struct r8192_priv *priv = ieee80211_priv(dev);
2870 u32 rateIndex;
2871 u32 rateBitmap;
2872
2873 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
2874 // Initial rate record to zero, start to record.
2875 priv->rate_record = 0;
2876 // Initial contiune diff count to zero, start to record.
2877 priv->ContiuneDiffCount = 0;
2878 priv->rateCountDiffRecord = 0;
2879 priv->bswitch_fsync = false;
2880
2881 if(priv->ieee80211->mode == WIRELESS_MODE_N_24G)
2882 {
2883 priv->ieee80211->fsync_firstdiff_ratethreshold= 600;
2884 priv->ieee80211->fsync_seconddiff_ratethreshold = 0xffff;
2885 }
2886 else
2887 {
2888 priv->ieee80211->fsync_firstdiff_ratethreshold= 200;
2889 priv->ieee80211->fsync_seconddiff_ratethreshold = 200;
2890 }
2891 for(rateIndex = 0; rateIndex <= 27; rateIndex++)
2892 {
2893 rateBitmap = 1 << rateIndex;
2894 if(priv->ieee80211->fsync_rate_bitmap & rateBitmap)
2895 priv->rate_record += priv->stats.received_rate_histogram[1][rateIndex];
2896 }
2897 if(timer_pending(&priv->fsync_timer))
2898 del_timer_sync(&priv->fsync_timer);
2899 priv->fsync_timer.expires = jiffies + MSECS(priv->ieee80211->fsync_time_interval);
2900 add_timer(&priv->fsync_timer);
2901
2902 #ifndef RTL8190P
2903 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c12cd);
2904 #endif
2905
2906 }
2907
2908 static void dm_EndHWFsync(struct net_device *dev)
2909 {
2910 RT_TRACE(COMP_HALDM,"%s\n", __FUNCTION__);
2911 write_nic_dword(dev, rOFDM0_RxDetector2, 0x465c52cd);
2912 write_nic_byte(dev, 0xc3b, 0x49);
2913
2914 }
2915
2916 void dm_check_fsync(struct net_device *dev)
2917 {
2918 #define RegC38_Default 0
2919 #define RegC38_NonFsync_Other_AP 1
2920 #define RegC38_Fsync_AP_BCM 2
2921 struct r8192_priv *priv = ieee80211_priv(dev);
2922 //u32 framesyncC34;
2923 static u8 reg_c38_State=RegC38_Default;
2924 static u32 reset_cnt=0;
2925
2926 RT_TRACE(COMP_HALDM, "RSSI %d TimeInterval %d MultipleTimeInterval %d\n", priv->ieee80211->fsync_rssi_threshold, priv->ieee80211->fsync_time_interval, priv->ieee80211->fsync_multiple_timeinterval);
2927 RT_TRACE(COMP_HALDM, "RateBitmap 0x%x FirstDiffRateThreshold %d SecondDiffRateThreshold %d\n", priv->ieee80211->fsync_rate_bitmap, priv->ieee80211->fsync_firstdiff_ratethreshold, priv->ieee80211->fsync_seconddiff_ratethreshold);
2928
2929 if( priv->ieee80211->state == IEEE80211_LINKED &&
2930 (priv->ieee80211->pHTInfo->IOTAction & HT_IOT_ACT_CDD_FSYNC))
2931 {
2932 if(priv->ieee80211->bfsync_enable == 0)
2933 {
2934 switch(priv->ieee80211->fsync_state)
2935 {
2936 case Default_Fsync:
2937 dm_StartHWFsync(dev);
2938 priv->ieee80211->fsync_state = HW_Fsync;
2939 break;
2940 case SW_Fsync:
2941 dm_EndSWFsync(dev);
2942 dm_StartHWFsync(dev);
2943 priv->ieee80211->fsync_state = HW_Fsync;
2944 break;
2945 case HW_Fsync:
2946 default:
2947 break;
2948 }
2949 }
2950 else
2951 {
2952 switch(priv->ieee80211->fsync_state)
2953 {
2954 case Default_Fsync:
2955 dm_StartSWFsync(dev);
2956 priv->ieee80211->fsync_state = SW_Fsync;
2957 break;
2958 case HW_Fsync:
2959 dm_EndHWFsync(dev);
2960 dm_StartSWFsync(dev);
2961 priv->ieee80211->fsync_state = SW_Fsync;
2962 break;
2963 case SW_Fsync:
2964 default:
2965 break;
2966
2967 }
2968 }
2969 if(priv->framesyncMonitor)
2970 {
2971 if(reg_c38_State != RegC38_Fsync_AP_BCM)
2972 { //For broadcom AP we write different default value
2973 #ifdef RTL8190P
2974 write_nic_byte(dev, rOFDM0_RxDetector3, 0x15);
2975 #else
2976 write_nic_byte(dev, rOFDM0_RxDetector3, 0x95);
2977 #endif
2978
2979 reg_c38_State = RegC38_Fsync_AP_BCM;
2980 }
2981 }
2982 }
2983 else
2984 {
2985 switch(priv->ieee80211->fsync_state)
2986 {
2987 case HW_Fsync:
2988 dm_EndHWFsync(dev);
2989 priv->ieee80211->fsync_state = Default_Fsync;
2990 break;
2991 case SW_Fsync:
2992 dm_EndSWFsync(dev);
2993 priv->ieee80211->fsync_state = Default_Fsync;
2994 break;
2995 case Default_Fsync:
2996 default:
2997 break;
2998 }
2999
3000 if(priv->framesyncMonitor)
3001 {
3002 if(priv->ieee80211->state == IEEE80211_LINKED)
3003 {
3004 if(priv->undecorated_smoothed_pwdb <= RegC38_TH)
3005 {
3006 if(reg_c38_State != RegC38_NonFsync_Other_AP)
3007 {
3008 #ifdef RTL8190P
3009 write_nic_byte(dev, rOFDM0_RxDetector3, 0x10);
3010 #else
3011 write_nic_byte(dev, rOFDM0_RxDetector3, 0x90);
3012 #endif
3013
3014 reg_c38_State = RegC38_NonFsync_Other_AP;
3015 }
3016 }
3017 else if(priv->undecorated_smoothed_pwdb >= (RegC38_TH+5))
3018 {
3019 if(reg_c38_State)
3020 {
3021 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3022 reg_c38_State = RegC38_Default;
3023 }
3024 }
3025 }
3026 else
3027 {
3028 if(reg_c38_State)
3029 {
3030 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3031 reg_c38_State = RegC38_Default;
3032 }
3033 }
3034 }
3035 }
3036 if(priv->framesyncMonitor)
3037 {
3038 if(priv->reset_count != reset_cnt)
3039 { //After silent reset, the reg_c38_State will be returned to default value
3040 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3041 reg_c38_State = RegC38_Default;
3042 reset_cnt = priv->reset_count;
3043 }
3044 }
3045 else
3046 {
3047 if(reg_c38_State)
3048 {
3049 write_nic_byte(dev, rOFDM0_RxDetector3, priv->framesync);
3050 reg_c38_State = RegC38_Default;
3051 }
3052 }
3053 }
3054
3055 /*
3056 * Detect Signal strength to control TX Registry
3057 * Tx Power Control For Near/Far Range
3058 */
3059 static void dm_init_dynamic_txpower(struct net_device *dev)
3060 {
3061 struct r8192_priv *priv = ieee80211_priv(dev);
3062
3063 //Initial TX Power Control for near/far range , add by amy 2008/05/15, porting from windows code.
3064 priv->ieee80211->bdynamic_txpower_enable = true; //Default to enable Tx Power Control
3065 priv->bLastDTPFlag_High = false;
3066 priv->bLastDTPFlag_Low = false;
3067 priv->bDynamicTxHighPower = false;
3068 priv->bDynamicTxLowPower = false;
3069 }
3070
3071 static void dm_dynamic_txpower(struct net_device *dev)
3072 {
3073 struct r8192_priv *priv = ieee80211_priv(dev);
3074 unsigned int txhipower_threshhold=0;
3075 unsigned int txlowpower_threshold=0;
3076 if(priv->ieee80211->bdynamic_txpower_enable != true)
3077 {
3078 priv->bDynamicTxHighPower = false;
3079 priv->bDynamicTxLowPower = false;
3080 return;
3081 }
3082 if((priv->ieee80211->current_network.atheros_cap_exist ) && (priv->ieee80211->mode == IEEE_G)){
3083 txhipower_threshhold = TX_POWER_ATHEROAP_THRESH_HIGH;
3084 txlowpower_threshold = TX_POWER_ATHEROAP_THRESH_LOW;
3085 }
3086 else
3087 {
3088 txhipower_threshhold = TX_POWER_NEAR_FIELD_THRESH_HIGH;
3089 txlowpower_threshold = TX_POWER_NEAR_FIELD_THRESH_LOW;
3090 }
3091
3092 RT_TRACE(COMP_TXAGC,"priv->undecorated_smoothed_pwdb = %ld \n" , priv->undecorated_smoothed_pwdb);
3093
3094 if(priv->ieee80211->state == IEEE80211_LINKED)
3095 {
3096 if(priv->undecorated_smoothed_pwdb >= txhipower_threshhold)
3097 {
3098 priv->bDynamicTxHighPower = true;
3099 priv->bDynamicTxLowPower = false;
3100 }
3101 else
3102 {
3103 // high power state check
3104 if(priv->undecorated_smoothed_pwdb < txlowpower_threshold && priv->bDynamicTxHighPower == true)
3105 {
3106 priv->bDynamicTxHighPower = false;
3107 }
3108 // low power state check
3109 if(priv->undecorated_smoothed_pwdb < 35)
3110 {
3111 priv->bDynamicTxLowPower = true;
3112 }
3113 else if(priv->undecorated_smoothed_pwdb >= 40)
3114 {
3115 priv->bDynamicTxLowPower = false;
3116 }
3117 }
3118 }
3119 else
3120 {
3121 //pHalData->bTXPowerCtrlforNearFarRange = !pHalData->bTXPowerCtrlforNearFarRange;
3122 priv->bDynamicTxHighPower = false;
3123 priv->bDynamicTxLowPower = false;
3124 }
3125
3126 if( (priv->bDynamicTxHighPower != priv->bLastDTPFlag_High ) ||
3127 (priv->bDynamicTxLowPower != priv->bLastDTPFlag_Low ) )
3128 {
3129 RT_TRACE(COMP_TXAGC,"SetTxPowerLevel8190() channel = %d \n" , priv->ieee80211->current_network.channel);
3130
3131
3132 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
3133
3134 }
3135 priv->bLastDTPFlag_High = priv->bDynamicTxHighPower;
3136 priv->bLastDTPFlag_Low = priv->bDynamicTxLowPower;
3137
3138 }
3139
3140 //added by vivi, for read tx rate and retrycount
3141 static void dm_check_txrateandretrycount(struct net_device * dev)
3142 {
3143 struct r8192_priv *priv = ieee80211_priv(dev);
3144 struct ieee80211_device* ieee = priv->ieee80211;
3145 //for initial tx rate
3146 ieee->softmac_stats.last_packet_rate = read_nic_byte(dev ,Initial_Tx_Rate_Reg);
3147 //for tx tx retry count
3148 ieee->softmac_stats.txretrycount = read_nic_dword(dev, Tx_Retry_Count_Reg);
3149 }
3150
3151 static void dm_send_rssi_tofw(struct net_device *dev)
3152 {
3153 DCMD_TXCMD_T tx_cmd;
3154 struct r8192_priv *priv = ieee80211_priv(dev);
3155
3156 // If we test chariot, we should stop the TX command ?
3157 // Because 92E will always silent reset when we send tx command. We use register
3158 // 0x1e0(byte) to botify driver.
3159 write_nic_byte(dev, DRIVER_RSSI, (u8)priv->undecorated_smoothed_pwdb);
3160 return;
3161 #if 1
3162 tx_cmd.Op = TXCMD_SET_RX_RSSI;
3163 tx_cmd.Length = 4;
3164 tx_cmd.Value = priv->undecorated_smoothed_pwdb;
3165
3166 cmpk_message_handle_tx(dev, (u8*)&tx_cmd,
3167 DESC_PACKET_TYPE_INIT, sizeof(DCMD_TXCMD_T));
3168 #endif
3169 }
3170
Linux kernel - Deliverables
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