projects / deliverable / linux.git / blob
? search:


a1312d8f7511ee1ada1997277c46c28146c62c9e
[deliverable/linux.git] / drivers / staging / rtl8192e / r819xE_phy.c
1 #include "r8192E.h"
2 #include "r8192E_hw.h"
3 #include "r819xE_phyreg.h"
4 #include "r8190_rtl8256.h"
5 #include "r819xE_phy.h"
6 #include "r8192E_dm.h"
7 #ifdef ENABLE_DOT11D
8 #include "ieee80211/dot11d.h"
9 #endif
10 static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
11 0,
12 0x085c, //2412 1
13 0x08dc, //2417 2
14 0x095c, //2422 3
15 0x09dc, //2427 4
16 0x0a5c, //2432 5
17 0x0adc, //2437 6
18 0x0b5c, //2442 7
19 0x0bdc, //2447 8
20 0x0c5c, //2452 9
21 0x0cdc, //2457 10
22 0x0d5c, //2462 11
23 0x0ddc, //2467 12
24 0x0e5c, //2472 13
25 0x0f72, //2484
26 };
27
28 static u32 Rtl8192PciEMACPHY_Array[] = {
29 0x03c,0xffff0000,0x00000f0f,
30 0x340,0xffffffff,0x161a1a1a,
31 0x344,0xffffffff,0x12121416,
32 0x348,0x0000ffff,0x00001818,
33 0x12c,0xffffffff,0x04000802,
34 0x318,0x00000fff,0x00000100,
35 };
36 static u32 Rtl8192PciEMACPHY_Array_PG[] = {
37 0x03c,0xffff0000,0x00000f0f,
38 0xe00,0xffffffff,0x06090909,
39 0xe04,0xffffffff,0x00030306,
40 0xe08,0x0000ff00,0x00000000,
41 0xe10,0xffffffff,0x0a0c0d0f,
42 0xe14,0xffffffff,0x06070809,
43 0xe18,0xffffffff,0x0a0c0d0f,
44 0xe1c,0xffffffff,0x06070809,
45 0x12c,0xffffffff,0x04000802,
46 0x318,0x00000fff,0x00000800,
47 };
48 static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = {
49 0xc78,0x7d000001,
50 0xc78,0x7d010001,
51 0xc78,0x7d020001,
52 0xc78,0x7d030001,
53 0xc78,0x7d040001,
54 0xc78,0x7d050001,
55 0xc78,0x7c060001,
56 0xc78,0x7b070001,
57 0xc78,0x7a080001,
58 0xc78,0x79090001,
59 0xc78,0x780a0001,
60 0xc78,0x770b0001,
61 0xc78,0x760c0001,
62 0xc78,0x750d0001,
63 0xc78,0x740e0001,
64 0xc78,0x730f0001,
65 0xc78,0x72100001,
66 0xc78,0x71110001,
67 0xc78,0x70120001,
68 0xc78,0x6f130001,
69 0xc78,0x6e140001,
70 0xc78,0x6d150001,
71 0xc78,0x6c160001,
72 0xc78,0x6b170001,
73 0xc78,0x6a180001,
74 0xc78,0x69190001,
75 0xc78,0x681a0001,
76 0xc78,0x671b0001,
77 0xc78,0x661c0001,
78 0xc78,0x651d0001,
79 0xc78,0x641e0001,
80 0xc78,0x491f0001,
81 0xc78,0x48200001,
82 0xc78,0x47210001,
83 0xc78,0x46220001,
84 0xc78,0x45230001,
85 0xc78,0x44240001,
86 0xc78,0x43250001,
87 0xc78,0x28260001,
88 0xc78,0x27270001,
89 0xc78,0x26280001,
90 0xc78,0x25290001,
91 0xc78,0x242a0001,
92 0xc78,0x232b0001,
93 0xc78,0x222c0001,
94 0xc78,0x212d0001,
95 0xc78,0x202e0001,
96 0xc78,0x0a2f0001,
97 0xc78,0x08300001,
98 0xc78,0x06310001,
99 0xc78,0x05320001,
100 0xc78,0x04330001,
101 0xc78,0x03340001,
102 0xc78,0x02350001,
103 0xc78,0x01360001,
104 0xc78,0x00370001,
105 0xc78,0x00380001,
106 0xc78,0x00390001,
107 0xc78,0x003a0001,
108 0xc78,0x003b0001,
109 0xc78,0x003c0001,
110 0xc78,0x003d0001,
111 0xc78,0x003e0001,
112 0xc78,0x003f0001,
113 0xc78,0x7d400001,
114 0xc78,0x7d410001,
115 0xc78,0x7d420001,
116 0xc78,0x7d430001,
117 0xc78,0x7d440001,
118 0xc78,0x7d450001,
119 0xc78,0x7c460001,
120 0xc78,0x7b470001,
121 0xc78,0x7a480001,
122 0xc78,0x79490001,
123 0xc78,0x784a0001,
124 0xc78,0x774b0001,
125 0xc78,0x764c0001,
126 0xc78,0x754d0001,
127 0xc78,0x744e0001,
128 0xc78,0x734f0001,
129 0xc78,0x72500001,
130 0xc78,0x71510001,
131 0xc78,0x70520001,
132 0xc78,0x6f530001,
133 0xc78,0x6e540001,
134 0xc78,0x6d550001,
135 0xc78,0x6c560001,
136 0xc78,0x6b570001,
137 0xc78,0x6a580001,
138 0xc78,0x69590001,
139 0xc78,0x685a0001,
140 0xc78,0x675b0001,
141 0xc78,0x665c0001,
142 0xc78,0x655d0001,
143 0xc78,0x645e0001,
144 0xc78,0x495f0001,
145 0xc78,0x48600001,
146 0xc78,0x47610001,
147 0xc78,0x46620001,
148 0xc78,0x45630001,
149 0xc78,0x44640001,
150 0xc78,0x43650001,
151 0xc78,0x28660001,
152 0xc78,0x27670001,
153 0xc78,0x26680001,
154 0xc78,0x25690001,
155 0xc78,0x246a0001,
156 0xc78,0x236b0001,
157 0xc78,0x226c0001,
158 0xc78,0x216d0001,
159 0xc78,0x206e0001,
160 0xc78,0x0a6f0001,
161 0xc78,0x08700001,
162 0xc78,0x06710001,
163 0xc78,0x05720001,
164 0xc78,0x04730001,
165 0xc78,0x03740001,
166 0xc78,0x02750001,
167 0xc78,0x01760001,
168 0xc78,0x00770001,
169 0xc78,0x00780001,
170 0xc78,0x00790001,
171 0xc78,0x007a0001,
172 0xc78,0x007b0001,
173 0xc78,0x007c0001,
174 0xc78,0x007d0001,
175 0xc78,0x007e0001,
176 0xc78,0x007f0001,
177 0xc78,0x2e00001e,
178 0xc78,0x2e01001e,
179 0xc78,0x2e02001e,
180 0xc78,0x2e03001e,
181 0xc78,0x2e04001e,
182 0xc78,0x2e05001e,
183 0xc78,0x3006001e,
184 0xc78,0x3407001e,
185 0xc78,0x3908001e,
186 0xc78,0x3c09001e,
187 0xc78,0x3f0a001e,
188 0xc78,0x420b001e,
189 0xc78,0x440c001e,
190 0xc78,0x450d001e,
191 0xc78,0x460e001e,
192 0xc78,0x460f001e,
193 0xc78,0x4710001e,
194 0xc78,0x4811001e,
195 0xc78,0x4912001e,
196 0xc78,0x4a13001e,
197 0xc78,0x4b14001e,
198 0xc78,0x4b15001e,
199 0xc78,0x4c16001e,
200 0xc78,0x4d17001e,
201 0xc78,0x4e18001e,
202 0xc78,0x4f19001e,
203 0xc78,0x4f1a001e,
204 0xc78,0x501b001e,
205 0xc78,0x511c001e,
206 0xc78,0x521d001e,
207 0xc78,0x521e001e,
208 0xc78,0x531f001e,
209 0xc78,0x5320001e,
210 0xc78,0x5421001e,
211 0xc78,0x5522001e,
212 0xc78,0x5523001e,
213 0xc78,0x5624001e,
214 0xc78,0x5725001e,
215 0xc78,0x5726001e,
216 0xc78,0x5827001e,
217 0xc78,0x5828001e,
218 0xc78,0x5929001e,
219 0xc78,0x592a001e,
220 0xc78,0x5a2b001e,
221 0xc78,0x5b2c001e,
222 0xc78,0x5c2d001e,
223 0xc78,0x5c2e001e,
224 0xc78,0x5d2f001e,
225 0xc78,0x5e30001e,
226 0xc78,0x5f31001e,
227 0xc78,0x6032001e,
228 0xc78,0x6033001e,
229 0xc78,0x6134001e,
230 0xc78,0x6235001e,
231 0xc78,0x6336001e,
232 0xc78,0x6437001e,
233 0xc78,0x6438001e,
234 0xc78,0x6539001e,
235 0xc78,0x663a001e,
236 0xc78,0x673b001e,
237 0xc78,0x673c001e,
238 0xc78,0x683d001e,
239 0xc78,0x693e001e,
240 0xc78,0x6a3f001e,
241 };
242 static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = {
243 0x0, };
244 static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
245 0x800,0x00000000,
246 0x804,0x00000001,
247 0x808,0x0000fc00,
248 0x80c,0x0000001c,
249 0x810,0x801010aa,
250 0x814,0x008514d0,
251 0x818,0x00000040,
252 0x81c,0x00000000,
253 0x820,0x00000004,
254 0x824,0x00690000,
255 0x828,0x00000004,
256 0x82c,0x00e90000,
257 0x830,0x00000004,
258 0x834,0x00690000,
259 0x838,0x00000004,
260 0x83c,0x00e90000,
261 0x840,0x00000000,
262 0x844,0x00000000,
263 0x848,0x00000000,
264 0x84c,0x00000000,
265 0x850,0x00000000,
266 0x854,0x00000000,
267 0x858,0x65a965a9,
268 0x85c,0x65a965a9,
269 0x860,0x001f0010,
270 0x864,0x007f0010,
271 0x868,0x001f0010,
272 0x86c,0x007f0010,
273 0x870,0x0f100f70,
274 0x874,0x0f100f70,
275 0x878,0x00000000,
276 0x87c,0x00000000,
277 0x880,0x6870e36c,
278 0x884,0xe3573600,
279 0x888,0x4260c340,
280 0x88c,0x0000ff00,
281 0x890,0x00000000,
282 0x894,0xfffffffe,
283 0x898,0x4c42382f,
284 0x89c,0x00656056,
285 0x8b0,0x00000000,
286 0x8e0,0x00000000,
287 0x8e4,0x00000000,
288 0x900,0x00000000,
289 0x904,0x00000023,
290 0x908,0x00000000,
291 0x90c,0x31121311,
292 0xa00,0x00d0c7d8,
293 0xa04,0x811f0008,
294 0xa08,0x80cd8300,
295 0xa0c,0x2e62740f,
296 0xa10,0x95009b78,
297 0xa14,0x11145008,
298 0xa18,0x00881117,
299 0xa1c,0x89140fa0,
300 0xa20,0x1a1b0000,
301 0xa24,0x090e1317,
302 0xa28,0x00000204,
303 0xa2c,0x00000000,
304 0xc00,0x00000040,
305 0xc04,0x00005433,
306 0xc08,0x000000e4,
307 0xc0c,0x6c6c6c6c,
308 0xc10,0x08800000,
309 0xc14,0x40000100,
310 0xc18,0x08000000,
311 0xc1c,0x40000100,
312 0xc20,0x08000000,
313 0xc24,0x40000100,
314 0xc28,0x08000000,
315 0xc2c,0x40000100,
316 0xc30,0x6de9ac44,
317 0xc34,0x465c52cd,
318 0xc38,0x497f5994,
319 0xc3c,0x0a969764,
320 0xc40,0x1f7c403f,
321 0xc44,0x000100b7,
322 0xc48,0xec020000,
323 0xc4c,0x00000300,
324 0xc50,0x69543420,
325 0xc54,0x433c0094,
326 0xc58,0x69543420,
327 0xc5c,0x433c0094,
328 0xc60,0x69543420,
329 0xc64,0x433c0094,
330 0xc68,0x69543420,
331 0xc6c,0x433c0094,
332 0xc70,0x2c7f000d,
333 0xc74,0x0186175b,
334 0xc78,0x0000001f,
335 0xc7c,0x00b91612,
336 0xc80,0x40000100,
337 0xc84,0x20000000,
338 0xc88,0x40000100,
339 0xc8c,0x20200000,
340 0xc90,0x40000100,
341 0xc94,0x00000000,
342 0xc98,0x40000100,
343 0xc9c,0x00000000,
344 0xca0,0x00492492,
345 0xca4,0x00000000,
346 0xca8,0x00000000,
347 0xcac,0x00000000,
348 0xcb0,0x00000000,
349 0xcb4,0x00000000,
350 0xcb8,0x00000000,
351 0xcbc,0x00492492,
352 0xcc0,0x00000000,
353 0xcc4,0x00000000,
354 0xcc8,0x00000000,
355 0xccc,0x00000000,
356 0xcd0,0x00000000,
357 0xcd4,0x00000000,
358 0xcd8,0x64b22427,
359 0xcdc,0x00766932,
360 0xce0,0x00222222,
361 0xd00,0x00000750,
362 0xd04,0x00000403,
363 0xd08,0x0000907f,
364 0xd0c,0x00000001,
365 0xd10,0xa0633333,
366 0xd14,0x33333c63,
367 0xd18,0x6a8f5b6b,
368 0xd1c,0x00000000,
369 0xd20,0x00000000,
370 0xd24,0x00000000,
371 0xd28,0x00000000,
372 0xd2c,0xcc979975,
373 0xd30,0x00000000,
374 0xd34,0x00000000,
375 0xd38,0x00000000,
376 0xd3c,0x00027293,
377 0xd40,0x00000000,
378 0xd44,0x00000000,
379 0xd48,0x00000000,
380 0xd4c,0x00000000,
381 0xd50,0x6437140a,
382 0xd54,0x024dbd02,
383 0xd58,0x00000000,
384 0xd5c,0x04032064,
385 0xe00,0x161a1a1a,
386 0xe04,0x12121416,
387 0xe08,0x00001800,
388 0xe0c,0x00000000,
389 0xe10,0x161a1a1a,
390 0xe14,0x12121416,
391 0xe18,0x161a1a1a,
392 0xe1c,0x12121416,
393 };
394 static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = {
395 0x019,0x00000003,
396 0x000,0x000000bf,
397 0x001,0x00000ee0,
398 0x002,0x0000004c,
399 0x003,0x000007f1,
400 0x004,0x00000975,
401 0x005,0x00000c58,
402 0x006,0x00000ae6,
403 0x007,0x000000ca,
404 0x008,0x00000e1c,
405 0x009,0x000007f0,
406 0x00a,0x000009d0,
407 0x00b,0x000001ba,
408 0x00c,0x00000240,
409 0x00e,0x00000020,
410 0x00f,0x00000990,
411 0x012,0x00000806,
412 0x014,0x000005ab,
413 0x015,0x00000f80,
414 0x016,0x00000020,
415 0x017,0x00000597,
416 0x018,0x0000050a,
417 0x01a,0x00000f80,
418 0x01b,0x00000f5e,
419 0x01c,0x00000008,
420 0x01d,0x00000607,
421 0x01e,0x000006cc,
422 0x01f,0x00000000,
423 0x020,0x000001a5,
424 0x01f,0x00000001,
425 0x020,0x00000165,
426 0x01f,0x00000002,
427 0x020,0x000000c6,
428 0x01f,0x00000003,
429 0x020,0x00000086,
430 0x01f,0x00000004,
431 0x020,0x00000046,
432 0x01f,0x00000005,
433 0x020,0x000001e6,
434 0x01f,0x00000006,
435 0x020,0x000001a6,
436 0x01f,0x00000007,
437 0x020,0x00000166,
438 0x01f,0x00000008,
439 0x020,0x000000c7,
440 0x01f,0x00000009,
441 0x020,0x00000087,
442 0x01f,0x0000000a,
443 0x020,0x000000f7,
444 0x01f,0x0000000b,
445 0x020,0x000000d7,
446 0x01f,0x0000000c,
447 0x020,0x000000b7,
448 0x01f,0x0000000d,
449 0x020,0x00000097,
450 0x01f,0x0000000e,
451 0x020,0x00000077,
452 0x01f,0x0000000f,
453 0x020,0x00000057,
454 0x01f,0x00000010,
455 0x020,0x00000037,
456 0x01f,0x00000011,
457 0x020,0x000000fb,
458 0x01f,0x00000012,
459 0x020,0x000000db,
460 0x01f,0x00000013,
461 0x020,0x000000bb,
462 0x01f,0x00000014,
463 0x020,0x000000ff,
464 0x01f,0x00000015,
465 0x020,0x000000e3,
466 0x01f,0x00000016,
467 0x020,0x000000c3,
468 0x01f,0x00000017,
469 0x020,0x000000a3,
470 0x01f,0x00000018,
471 0x020,0x00000083,
472 0x01f,0x00000019,
473 0x020,0x00000063,
474 0x01f,0x0000001a,
475 0x020,0x00000043,
476 0x01f,0x0000001b,
477 0x020,0x00000023,
478 0x01f,0x0000001c,
479 0x020,0x00000003,
480 0x01f,0x0000001d,
481 0x020,0x000001e3,
482 0x01f,0x0000001e,
483 0x020,0x000001c3,
484 0x01f,0x0000001f,
485 0x020,0x000001a3,
486 0x01f,0x00000020,
487 0x020,0x00000183,
488 0x01f,0x00000021,
489 0x020,0x00000163,
490 0x01f,0x00000022,
491 0x020,0x00000143,
492 0x01f,0x00000023,
493 0x020,0x00000123,
494 0x01f,0x00000024,
495 0x020,0x00000103,
496 0x023,0x00000203,
497 0x024,0x00000100,
498 0x00b,0x000001ba,
499 0x02c,0x000003d7,
500 0x02d,0x00000ff0,
501 0x000,0x00000037,
502 0x004,0x00000160,
503 0x007,0x00000080,
504 0x002,0x0000088d,
505 0x0fe,0x00000000,
506 0x0fe,0x00000000,
507 0x016,0x00000200,
508 0x016,0x00000380,
509 0x016,0x00000020,
510 0x016,0x000001a0,
511 0x000,0x000000bf,
512 0x00d,0x0000001f,
513 0x00d,0x00000c9f,
514 0x002,0x0000004d,
515 0x000,0x00000cbf,
516 0x004,0x00000975,
517 0x007,0x00000700,
518 };
519 static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = {
520 0x019,0x00000003,
521 0x000,0x000000bf,
522 0x001,0x000006e0,
523 0x002,0x0000004c,
524 0x003,0x000007f1,
525 0x004,0x00000975,
526 0x005,0x00000c58,
527 0x006,0x00000ae6,
528 0x007,0x000000ca,
529 0x008,0x00000e1c,
530 0x000,0x000000b7,
531 0x00a,0x00000850,
532 0x000,0x000000bf,
533 0x00b,0x000001ba,
534 0x00c,0x00000240,
535 0x00e,0x00000020,
536 0x015,0x00000f80,
537 0x016,0x00000020,
538 0x017,0x00000597,
539 0x018,0x0000050a,
540 0x01a,0x00000e00,
541 0x01b,0x00000f5e,
542 0x01d,0x00000607,
543 0x01e,0x000006cc,
544 0x00b,0x000001ba,
545 0x023,0x00000203,
546 0x024,0x00000100,
547 0x000,0x00000037,
548 0x004,0x00000160,
549 0x016,0x00000200,
550 0x016,0x00000380,
551 0x016,0x00000020,
552 0x016,0x000001a0,
553 0x00d,0x00000ccc,
554 0x000,0x000000bf,
555 0x002,0x0000004d,
556 0x000,0x00000cbf,
557 0x004,0x00000975,
558 0x007,0x00000700,
559 };
560 static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
561 0x0, };
562 static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
563 0x0, };
564
565 /*************************Define local function prototype**********************/
566
567 static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
568 static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data);
569 /*************************Define local function prototype**********************/
570 /******************************************************************************
571 *function: This function read BB parameters from Header file we gen,
572 * and do register read/write
573 * input: u32 dwBitMask //taget bit pos in the addr to be modified
574 * output: none
575 * return: u32 return the shift bit bit position of the mask
576 * ****************************************************************************/
577 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
578 {
579 u32 i;
580 for (i=0; i<=31; i++)
581 {
582 if (((dwBitMask>>i)&0x1) == 1)
583 break;
584 }
585 return i;
586 }
587 /******************************************************************************
588 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
589 * input: none
590 * output: none
591 * return: 0(illegal, false), 1(legal,true)
592 * ***************************************************************************/
593 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
594 {
595 u8 ret = 1;
596 struct r8192_priv *priv = ieee80211_priv(dev);
597
598 if (priv->rf_type == RF_2T4R)
599 ret = 0;
600 else if (priv->rf_type == RF_1T2R)
601 {
602 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
603 ret = 1;
604 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
605 ret = 0;
606 }
607
608 return ret;
609 }
610 /******************************************************************************
611 *function: This function set specific bits to BB register
612 * input: net_device dev
613 * u32 dwRegAddr //target addr to be modified
614 * u32 dwBitMask //taget bit pos in the addr to be modified
615 * u32 dwData //value to be write
616 * output: none
617 * return: none
618 * notice:
619 * ****************************************************************************/
620 void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
621 {
622 struct r8192_priv *priv = ieee80211_priv(dev);
623 u32 OriginalValue, BitShift, NewValue;
624
625 if(dwBitMask!= bMaskDWord)
626 {//if not "double word" write
627 OriginalValue = read_nic_dword(priv, dwRegAddr);
628 BitShift = rtl8192_CalculateBitShift(dwBitMask);
629 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
630 write_nic_dword(priv, dwRegAddr, NewValue);
631 }else
632 write_nic_dword(priv, dwRegAddr, dwData);
633 }
634 /******************************************************************************
635 *function: This function reads specific bits from BB register
636 * input: net_device dev
637 * u32 dwRegAddr //target addr to be readback
638 * u32 dwBitMask //taget bit pos in the addr to be readback
639 * output: none
640 * return: u32 Data //the readback register value
641 * notice:
642 * ****************************************************************************/
643 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
644 {
645 struct r8192_priv *priv = ieee80211_priv(dev);
646 u32 OriginalValue, BitShift;
647
648 OriginalValue = read_nic_dword(priv, dwRegAddr);
649 BitShift = rtl8192_CalculateBitShift(dwBitMask);
650 return (OriginalValue & dwBitMask) >> BitShift;
651 }
652 /******************************************************************************
653 *function: This function read register from RF chip
654 * input: net_device dev
655 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
656 * u32 Offset //target address to be read
657 * output: none
658 * return: u32 readback value
659 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
660 * ****************************************************************************/
661 static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
662 {
663 struct r8192_priv *priv = ieee80211_priv(dev);
664 u32 ret = 0;
665 u32 NewOffset = 0;
666 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
667 //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
668 //make sure RF register offset is correct
669 Offset &= 0x3f;
670
671 //switch page for 8256 RF IC
672 if (priv->rf_chip == RF_8256)
673 {
674 //analog to digital off, for protection
675 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
676 if (Offset >= 31)
677 {
678 priv->RfReg0Value[eRFPath] |= 0x140;
679 //Switch to Reg_Mode2 for Reg 31-45
680 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
681 //modify offset
682 NewOffset = Offset -30;
683 }
684 else if (Offset >= 16)
685 {
686 priv->RfReg0Value[eRFPath] |= 0x100;
687 priv->RfReg0Value[eRFPath] &= (~0x40);
688 //Switch to Reg_Mode 1 for Reg16-30
689 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
690
691 NewOffset = Offset - 15;
692 }
693 else
694 NewOffset = Offset;
695 }
696 else
697 {
698 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
699 NewOffset = Offset;
700 }
701 //put desired read addr to LSSI control Register
702 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
703 //Issue a posedge trigger
704 //
705 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
706 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
707
708
709 // TODO: we should not delay such a long time. Ask help from SD3
710 msleep(1);
711
712 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
713
714
715 // Switch back to Reg_Mode0;
716 if(priv->rf_chip == RF_8256)
717 {
718 priv->RfReg0Value[eRFPath] &= 0xebf;
719
720 rtl8192_setBBreg(
721 dev,
722 pPhyReg->rf3wireOffset,
723 bMaskDWord,
724 (priv->RfReg0Value[eRFPath] << 16));
725
726 //analog to digital on
727 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
728 }
729
730
731 return ret;
732
733 }
734
735 /******************************************************************************
736 *function: This function write data to RF register
737 * input: net_device dev
738 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
739 * u32 Offset //target address to be written
740 * u32 Data //The new register data to be written
741 * output: none
742 * return: none
743 * notice: For RF8256 only.
744 ===========================================================
745 *Reg Mode RegCTL[1] RegCTL[0] Note
746 * (Reg00[12]) (Reg00[10])
747 *===========================================================
748 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
749 *------------------------------------------------------------------
750 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
751 *------------------------------------------------------------------
752 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
753 *------------------------------------------------------------------
754 * ****************************************************************************/
755 static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
756 {
757 struct r8192_priv *priv = ieee80211_priv(dev);
758 u32 DataAndAddr = 0, NewOffset = 0;
759 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
760
761 Offset &= 0x3f;
762 if (priv->rf_chip == RF_8256)
763 {
764
765 //analog to digital off, for protection
766 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
767
768 if (Offset >= 31)
769 {
770 priv->RfReg0Value[eRFPath] |= 0x140;
771 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
772 NewOffset = Offset - 30;
773 }
774 else if (Offset >= 16)
775 {
776 priv->RfReg0Value[eRFPath] |= 0x100;
777 priv->RfReg0Value[eRFPath] &= (~0x40);
778 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
779 NewOffset = Offset - 15;
780 }
781 else
782 NewOffset = Offset;
783 }
784 else
785 {
786 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
787 NewOffset = Offset;
788 }
789
790 // Put write addr in [5:0] and write data in [31:16]
791 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
792
793 // Write Operation
794 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
795
796
797 if(Offset==0x0)
798 priv->RfReg0Value[eRFPath] = Data;
799
800 // Switch back to Reg_Mode0;
801 if(priv->rf_chip == RF_8256)
802 {
803 if(Offset != 0)
804 {
805 priv->RfReg0Value[eRFPath] &= 0xebf;
806 rtl8192_setBBreg(
807 dev,
808 pPhyReg->rf3wireOffset,
809 bMaskDWord,
810 (priv->RfReg0Value[eRFPath] << 16));
811 }
812 //analog to digital on
813 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
814 }
815 }
816
817 /******************************************************************************
818 *function: This function set specific bits to RF register
819 * input: net_device dev
820 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
821 * u32 RegAddr //target addr to be modified
822 * u32 BitMask //taget bit pos in the addr to be modified
823 * u32 Data //value to be write
824 * output: none
825 * return: none
826 * notice:
827 * ****************************************************************************/
828 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
829 {
830 struct r8192_priv *priv = ieee80211_priv(dev);
831 u32 Original_Value, BitShift, New_Value;
832 // u8 time = 0;
833
834 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
835 return;
836 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
837 return;
838 //down(&priv->rf_sem);
839
840 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
841 if (priv->Rf_Mode == RF_OP_By_FW)
842 {
843 if (BitMask != bMask12Bits) // RF data is 12 bits only
844 {
845 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
846 BitShift = rtl8192_CalculateBitShift(BitMask);
847 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
848
849 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
850 }else
851 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
852 udelay(200);
853
854 }
855 else
856 {
857 if (BitMask != bMask12Bits) // RF data is 12 bits only
858 {
859 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
860 BitShift = rtl8192_CalculateBitShift(BitMask);
861 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
862
863 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
864 }else
865 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
866 }
867 //up(&priv->rf_sem);
868 }
869
870 /******************************************************************************
871 *function: This function reads specific bits from RF register
872 * input: net_device dev
873 * u32 RegAddr //target addr to be readback
874 * u32 BitMask //taget bit pos in the addr to be readback
875 * output: none
876 * return: u32 Data //the readback register value
877 * notice:
878 * ****************************************************************************/
879 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
880 {
881 u32 Original_Value, Readback_Value, BitShift;
882 struct r8192_priv *priv = ieee80211_priv(dev);
883 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
884 return 0;
885 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
886 return 0;
887 down(&priv->rf_sem);
888 if (priv->Rf_Mode == RF_OP_By_FW)
889 {
890 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
891 udelay(200);
892 }
893 else
894 {
895 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
896
897 }
898 BitShift = rtl8192_CalculateBitShift(BitMask);
899 Readback_Value = (Original_Value & BitMask) >> BitShift;
900 up(&priv->rf_sem);
901 // udelay(200);
902 return Readback_Value;
903 }
904
905 /******************************************************************************
906 *function: We support firmware to execute RF-R/W.
907 * input: dev
908 * output: none
909 * return: none
910 * notice:
911 * ***************************************************************************/
912 static u32 phy_FwRFSerialRead(
913 struct net_device* dev,
914 RF90_RADIO_PATH_E eRFPath,
915 u32 Offset )
916 {
917 struct r8192_priv *priv = ieee80211_priv(dev);
918 u32 Data = 0;
919 u8 time = 0;
920 //DbgPrint("FW RF CTRL\n\r");
921 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
922 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
923 much time. This is only for site survey. */
924 // 1. Read operation need not insert data. bit 0-11
925 //Data &= bMask12Bits;
926 // 2. Write RF register address. Bit 12-19
927 Data |= ((Offset&0xFF)<<12);
928 // 3. Write RF path. bit 20-21
929 Data |= ((eRFPath&0x3)<<20);
930 // 4. Set RF read indicator. bit 22=0
931 //Data |= 0x00000;
932 // 5. Trigger Fw to operate the command. bit 31
933 Data |= 0x80000000;
934 // 6. We can not execute read operation if bit 31 is 1.
935 while (read_nic_dword(priv, QPNR)&0x80000000)
936 {
937 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
938 if (time++ < 100)
939 {
940 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
941 udelay(10);
942 }
943 else
944 break;
945 }
946 // 7. Execute read operation.
947 write_nic_dword(priv, QPNR, Data);
948 // 8. Check if firmawre send back RF content.
949 while (read_nic_dword(priv, QPNR)&0x80000000)
950 {
951 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
952 if (time++ < 100)
953 {
954 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
955 udelay(10);
956 }
957 else
958 return 0;
959 }
960 return read_nic_dword(priv, RF_DATA);
961 }
962
963 /******************************************************************************
964 *function: We support firmware to execute RF-R/W.
965 * input: dev
966 * output: none
967 * return: none
968 * notice:
969 * ***************************************************************************/
970 static void
971 phy_FwRFSerialWrite(
972 struct net_device* dev,
973 RF90_RADIO_PATH_E eRFPath,
974 u32 Offset,
975 u32 Data )
976 {
977 struct r8192_priv *priv = ieee80211_priv(dev);
978 u8 time = 0;
979
980 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
981 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
982 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
983 much time. This is only for site survey. */
984
985 // 1. Set driver write bit and 12 bit data. bit 0-11
986 //Data &= bMask12Bits; // Done by uper layer.
987 // 2. Write RF register address. bit 12-19
988 Data |= ((Offset&0xFF)<<12);
989 // 3. Write RF path. bit 20-21
990 Data |= ((eRFPath&0x3)<<20);
991 // 4. Set RF write indicator. bit 22=1
992 Data |= 0x400000;
993 // 5. Trigger Fw to operate the command. bit 31=1
994 Data |= 0x80000000;
995
996 // 6. Write operation. We can not write if bit 31 is 1.
997 while (read_nic_dword(priv, QPNR)&0x80000000)
998 {
999 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1000 if (time++ < 100)
1001 {
1002 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1003 udelay(10);
1004 }
1005 else
1006 break;
1007 }
1008 // 7. No matter check bit. We always force the write. Because FW will
1009 // not accept the command.
1010 write_nic_dword(priv, QPNR, Data);
1011 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
1012 to finish RF write operation. */
1013 /* 2008/01/17 MH We support delay in firmware side now. */
1014 //delay_us(20);
1015
1016 }
1017
1018
1019 /******************************************************************************
1020 *function: This function read BB parameters from Header file we gen,
1021 * and do register read/write
1022 * input: dev
1023 * output: none
1024 * return: none
1025 * notice: BB parameters may change all the time, so please make
1026 * sure it has been synced with the newest.
1027 * ***************************************************************************/
1028 void rtl8192_phy_configmac(struct net_device* dev)
1029 {
1030 u32 dwArrayLen = 0, i = 0;
1031 u32* pdwArray = NULL;
1032 struct r8192_priv *priv = ieee80211_priv(dev);
1033 #ifdef TO_DO_LIST
1034 if(Adapter->bInHctTest)
1035 {
1036 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
1037 dwArrayLen = MACPHY_ArrayLengthDTM;
1038 pdwArray = Rtl819XMACPHY_ArrayDTM;
1039 }
1040 else if(priv->bTXPowerDataReadFromEEPORM)
1041 #endif
1042 if(priv->bTXPowerDataReadFromEEPORM)
1043 {
1044 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
1045 dwArrayLen = MACPHY_Array_PGLength;
1046 pdwArray = Rtl819XMACPHY_Array_PG;
1047
1048 }
1049 else
1050 {
1051 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
1052 dwArrayLen = MACPHY_ArrayLength;
1053 pdwArray = Rtl819XMACPHY_Array;
1054 }
1055 for(i = 0; i<dwArrayLen; i=i+3){
1056 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
1057 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1058 if(pdwArray[i] == 0x318)
1059 {
1060 pdwArray[i+2] = 0x00000800;
1061 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1062 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1063 }
1064 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1065 }
1066 }
1067
1068 /******************************************************************************
1069 *function: This function do dirty work
1070 * input: dev
1071 * output: none
1072 * return: none
1073 * notice: BB parameters may change all the time, so please make
1074 * sure it has been synced with the newest.
1075 * ***************************************************************************/
1076
1077 void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1078 {
1079 int i;
1080 //u8 ArrayLength;
1081 u32* Rtl819XPHY_REGArray_Table = NULL;
1082 u32* Rtl819XAGCTAB_Array_Table = NULL;
1083 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1084 struct r8192_priv *priv = ieee80211_priv(dev);
1085 #ifdef TO_DO_LIST
1086 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1087 if(Adapter->bInHctTest)
1088 {
1089 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1090 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1091
1092 if(priv->RF_Type == RF_2T4R)
1093 {
1094 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1095 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1096 }
1097 else if (priv->RF_Type == RF_1T2R)
1098 {
1099 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1100 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1101 }
1102 }
1103 else
1104 #endif
1105 {
1106 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
1107 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
1108 if(priv->rf_type == RF_2T4R)
1109 {
1110 PHY_REGArrayLen = PHY_REGArrayLength;
1111 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
1112 }
1113 else if (priv->rf_type == RF_1T2R)
1114 {
1115 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
1116 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
1117 }
1118 }
1119
1120 if (ConfigType == BaseBand_Config_PHY_REG)
1121 {
1122 for (i=0; i<PHY_REGArrayLen; i+=2)
1123 {
1124 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1125 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
1126 }
1127 }
1128 else if (ConfigType == BaseBand_Config_AGC_TAB)
1129 {
1130 for (i=0; i<AGCTAB_ArrayLen; i+=2)
1131 {
1132 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1133 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
1134 }
1135 }
1136 }
1137 /******************************************************************************
1138 *function: This function initialize Register definition offset for Radio Path
1139 * A/B/C/D
1140 * input: net_device dev
1141 * output: none
1142 * return: none
1143 * notice: Initialization value here is constant and it should never be changed
1144 * ***************************************************************************/
1145 static void rtl8192_InitBBRFRegDef(struct net_device* dev)
1146 {
1147 struct r8192_priv *priv = ieee80211_priv(dev);
1148 // RF Interface Sowrtware Control
1149 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
1150 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
1151 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
1152 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
1153
1154 // RF Interface Readback Value
1155 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
1156 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
1157 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
1158 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
1159
1160 // RF Interface Output (and Enable)
1161 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
1162 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
1163 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
1164 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
1165
1166 // RF Interface (Output and) Enable
1167 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
1168 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
1169 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
1170 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
1171
1172 //Addr of LSSI. Wirte RF register by driver
1173 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
1174 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
1175 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
1176 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
1177
1178 // RF parameter
1179 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
1180 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
1181 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1182 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
1183
1184 // Tx AGC Gain Stage (same for all path. Should we remove this?)
1185 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1186 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1187 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1188 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
1189
1190 // Tranceiver A~D HSSI Parameter-1
1191 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
1192 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
1193 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
1194 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
1195
1196 // Tranceiver A~D HSSI Parameter-2
1197 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
1198 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
1199 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
1200 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
1201
1202 // RF switch Control
1203 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
1204 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
1205 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1206 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
1207
1208 // AGC control 1
1209 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
1210 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
1211 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
1212 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
1213
1214 // AGC control 2
1215 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
1216 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
1217 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
1218 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
1219
1220 // RX AFE control 1
1221 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
1222 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
1223 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
1224 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
1225
1226 // RX AFE control 1
1227 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
1228 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
1229 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
1230 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
1231
1232 // Tx AFE control 1
1233 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
1234 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
1235 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
1236 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
1237
1238 // Tx AFE control 2
1239 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
1240 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
1241 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
1242 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
1243
1244 // Tranceiver LSSI Readback
1245 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
1246 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
1247 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
1248 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
1249
1250 }
1251 /******************************************************************************
1252 *function: This function is to write register and then readback to make sure whether BB and RF is OK
1253 * input: net_device dev
1254 * HW90_BLOCK_E CheckBlock
1255 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
1256 * output: none
1257 * return: return whether BB and RF is ok(0:OK; 1:Fail)
1258 * notice: This function may be removed in the ASIC
1259 * ***************************************************************************/
1260 RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
1261 {
1262 struct r8192_priv *priv = ieee80211_priv(dev);
1263 // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1264 RT_STATUS ret = RT_STATUS_SUCCESS;
1265 u32 i, CheckTimes = 4, dwRegRead = 0;
1266 u32 WriteAddr[4];
1267 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
1268 // Initialize register address offset to be checked
1269 WriteAddr[HW90_BLOCK_MAC] = 0x100;
1270 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
1271 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
1272 WriteAddr[HW90_BLOCK_RF] = 0x3;
1273 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
1274 for(i=0 ; i < CheckTimes ; i++)
1275 {
1276
1277 //
1278 // Write Data to register and readback
1279 //
1280 switch(CheckBlock)
1281 {
1282 case HW90_BLOCK_MAC:
1283 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
1284 break;
1285
1286 case HW90_BLOCK_PHY0:
1287 case HW90_BLOCK_PHY1:
1288 write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]);
1289 dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]);
1290 break;
1291
1292 case HW90_BLOCK_RF:
1293 WriteData[i] &= 0xfff;
1294 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
1295 // TODO: we should not delay for such a long time. Ask SD3
1296 mdelay(10);
1297 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
1298 mdelay(10);
1299 break;
1300
1301 default:
1302 ret = RT_STATUS_FAILURE;
1303 break;
1304 }
1305
1306
1307 //
1308 // Check whether readback data is correct
1309 //
1310 if(dwRegRead != WriteData[i])
1311 {
1312 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
1313 ret = RT_STATUS_FAILURE;
1314 break;
1315 }
1316 }
1317
1318 return ret;
1319 }
1320
1321
1322 /******************************************************************************
1323 *function: This function initialize BB&RF
1324 * input: net_device dev
1325 * output: none
1326 * return: none
1327 * notice: Initialization value may change all the time, so please make
1328 * sure it has been synced with the newest.
1329 * ***************************************************************************/
1330 static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
1331 {
1332 struct r8192_priv *priv = ieee80211_priv(dev);
1333 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1334 u8 bRegValue = 0, eCheckItem = 0;
1335 u32 dwRegValue = 0;
1336 /**************************************
1337 //<1>Initialize BaseBand
1338 **************************************/
1339
1340 /*--set BB Global Reset--*/
1341 bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET);
1342 write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
1343
1344 /*---set BB reset Active---*/
1345 dwRegValue = read_nic_dword(priv, CPU_GEN);
1346 write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
1347
1348 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
1349 // TODO: this function should be removed on ASIC , Emily 2007.2.2
1350 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
1351 {
1352 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
1353 if(rtStatus != RT_STATUS_SUCCESS)
1354 {
1355 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
1356 return rtStatus;
1357 }
1358 }
1359 /*---- Set CCK and OFDM Block "OFF"----*/
1360 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
1361 /*----BB Register Initilazation----*/
1362 //==m==>Set PHY REG From Header<==m==
1363 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
1364
1365 /*----Set BB reset de-Active----*/
1366 dwRegValue = read_nic_dword(priv, CPU_GEN);
1367 write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
1368
1369 /*----BB AGC table Initialization----*/
1370 //==m==>Set PHY REG From Header<==m==
1371 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
1372
1373 if (priv->card_8192_version > VERSION_8190_BD)
1374 {
1375 if(priv->rf_type == RF_2T4R)
1376 {
1377 // Antenna gain offset from B/C/D to A
1378 dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 |
1379 priv->AntennaTxPwDiff[1]<<4 |
1380 priv->AntennaTxPwDiff[0]);
1381 }
1382 else
1383 dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R.
1384 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
1385 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
1386
1387
1388 //XSTALLCap
1389 dwRegValue = priv->CrystalCap;
1390 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
1391 }
1392
1393 // Check if the CCK HighPower is turned ON.
1394 // This is used to calculate PWDB.
1395 // priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
1396 return rtStatus;
1397 }
1398 /******************************************************************************
1399 *function: This function initialize BB&RF
1400 * input: net_device dev
1401 * output: none
1402 * return: none
1403 * notice: Initialization value may change all the time, so please make
1404 * sure it has been synced with the newest.
1405 * ***************************************************************************/
1406 RT_STATUS rtl8192_BBConfig(struct net_device* dev)
1407 {
1408 rtl8192_InitBBRFRegDef(dev);
1409 //config BB&RF. As hardCode based initialization has not been well
1410 //implemented, so use file first.FIXME:should implement it for hardcode?
1411 return rtl8192_BB_Config_ParaFile(dev);
1412 }
1413
1414 /******************************************************************************
1415 *function: This function obtains the initialization value of Tx power Level offset
1416 * input: net_device dev
1417 * output: none
1418 * return: none
1419 * ***************************************************************************/
1420 void rtl8192_phy_getTxPower(struct net_device* dev)
1421 {
1422 struct r8192_priv *priv = ieee80211_priv(dev);
1423
1424 priv->MCSTxPowerLevelOriginalOffset[0] =
1425 read_nic_dword(priv, rTxAGC_Rate18_06);
1426 priv->MCSTxPowerLevelOriginalOffset[1] =
1427 read_nic_dword(priv, rTxAGC_Rate54_24);
1428 priv->MCSTxPowerLevelOriginalOffset[2] =
1429 read_nic_dword(priv, rTxAGC_Mcs03_Mcs00);
1430 priv->MCSTxPowerLevelOriginalOffset[3] =
1431 read_nic_dword(priv, rTxAGC_Mcs07_Mcs04);
1432 priv->MCSTxPowerLevelOriginalOffset[4] =
1433 read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
1434 priv->MCSTxPowerLevelOriginalOffset[5] =
1435 read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
1436
1437 // read rx initial gain
1438 priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
1439 priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1);
1440 priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1);
1441 priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1);
1442 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
1443 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
1444 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
1445
1446 // read framesync
1447 priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3);
1448 priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2);
1449 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
1450 rOFDM0_RxDetector3, priv->framesync);
1451 // read SIFS (save the value read fome MACPHY_REG.txt)
1452 priv->SifsTime = read_nic_word(priv, SIFS);
1453 }
1454
1455 /******************************************************************************
1456 *function: This function obtains the initialization value of Tx power Level offset
1457 * input: net_device dev
1458 * output: none
1459 * return: none
1460 * ***************************************************************************/
1461 void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
1462 {
1463 struct r8192_priv *priv = ieee80211_priv(dev);
1464 u8 powerlevel = 0,powerlevelOFDM24G = 0;
1465 char ant_pwr_diff;
1466 u32 u4RegValue;
1467
1468 if(priv->epromtype == EPROM_93c46)
1469 {
1470 powerlevel = priv->TxPowerLevelCCK[channel-1];
1471 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1472 }
1473 else if(priv->epromtype == EPROM_93c56)
1474 {
1475 if(priv->rf_type == RF_1T2R)
1476 {
1477 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
1478 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
1479 }
1480 else if(priv->rf_type == RF_2T4R)
1481 {
1482 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx
1483 // Power must be calculated by the antenna diff.
1484 // So we have to rewrite Antenna gain offset register here.
1485 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
1486 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
1487
1488 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
1489 -priv->TxPowerLevelOFDM24G_A[channel-1];
1490 ant_pwr_diff &= 0xf;
1491 //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff));
1492 priv->RF_C_TxPwDiff = ant_pwr_diff;
1493
1494 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
1495 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C
1496 priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care
1497
1498 // Antenna gain offset from B/C/D to A
1499 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
1500 priv->AntennaTxPwDiff[1]<<4 |
1501 priv->AntennaTxPwDiff[0]);
1502
1503 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
1504 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
1505 }
1506 }
1507 #ifdef TODO
1508 //
1509 // CCX 2 S31, AP control of client transmit power:
1510 // 1. We shall not exceed Cell Power Limit as possible as we can.
1511 // 2. Tolerance is +/- 5dB.
1512 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
1513 //
1514 // TODO:
1515 // 1. 802.11h power contraint
1516 //
1517 // 071011, by rcnjko.
1518 //
1519 if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
1520 pMgntInfo->bWithCcxCellPwr &&
1521 channel == pMgntInfo->dot11CurrentChannelNumber)
1522 {
1523 u8 CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
1524 u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
1525 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
1526
1527 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1528 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1529 pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
1530 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1531 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
1532 channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1533
1534 // CCK
1535 if(powerlevel > CckCellPwrIdx)
1536 powerlevel = CckCellPwrIdx;
1537 // Legacy OFDM, HT OFDM
1538 if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
1539 {
1540 if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
1541 {
1542 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
1543 }
1544 else
1545 {
1546 LegacyOfdmCellPwrIdx = 0;
1547 }
1548 }
1549
1550 RT_TRACE(COMP_TXAGC, DBG_LOUD,
1551 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
1552 powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
1553 }
1554
1555 pHalData->CurrentCckTxPwrIdx = powerlevel;
1556 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
1557 #endif
1558 switch(priv->rf_chip)
1559 {
1560 case RF_8225:
1561 // PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1562 // PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1563 break;
1564 case RF_8256:
1565 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
1566 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1567 break;
1568 case RF_8258:
1569 break;
1570 default:
1571 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __FUNCTION__);
1572 break;
1573 }
1574 }
1575
1576 /******************************************************************************
1577 *function: This function check Rf chip to do RF config
1578 * input: net_device dev
1579 * output: none
1580 * return: only 8256 is supported
1581 * ***************************************************************************/
1582 RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev)
1583 {
1584 struct r8192_priv *priv = ieee80211_priv(dev);
1585 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
1586 switch(priv->rf_chip)
1587 {
1588 case RF_8225:
1589 // rtStatus = PHY_RF8225_Config(Adapter);
1590 break;
1591 case RF_8256:
1592 rtStatus = PHY_RF8256_Config(dev);
1593 break;
1594
1595 case RF_8258:
1596 break;
1597 case RF_PSEUDO_11N:
1598 //rtStatus = PHY_RF8225_Config(Adapter);
1599 break;
1600
1601 default:
1602 RT_TRACE(COMP_ERR, "error chip id\n");
1603 break;
1604 }
1605 return rtStatus;
1606 }
1607
1608 /******************************************************************************
1609 *function: This function update Initial gain
1610 * input: net_device dev
1611 * output: none
1612 * return: As Windows has not implemented this, wait for complement
1613 * ***************************************************************************/
1614 void rtl8192_phy_updateInitGain(struct net_device* dev)
1615 {
1616 }
1617
1618 /******************************************************************************
1619 *function: This function read RF parameters from general head file, and do RF 3-wire
1620 * input: net_device dev
1621 * output: none
1622 * return: return code show if RF configuration is successful(0:pass, 1:fail)
1623 * Note: Delay may be required for RF configuration
1624 * ***************************************************************************/
1625 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
1626 {
1627
1628 int i;
1629 //u32* pRFArray;
1630 u8 ret = 0;
1631
1632 switch(eRFPath){
1633 case RF90_PATH_A:
1634 for(i = 0;i<RadioA_ArrayLength; i=i+2){
1635
1636 if(Rtl819XRadioA_Array[i] == 0xfe){
1637 msleep(100);
1638 continue;
1639 }
1640 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
1641 //msleep(1);
1642
1643 }
1644 break;
1645 case RF90_PATH_B:
1646 for(i = 0;i<RadioB_ArrayLength; i=i+2){
1647
1648 if(Rtl819XRadioB_Array[i] == 0xfe){
1649 msleep(100);
1650 continue;
1651 }
1652 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
1653 //msleep(1);
1654
1655 }
1656 break;
1657 case RF90_PATH_C:
1658 for(i = 0;i<RadioC_ArrayLength; i=i+2){
1659
1660 if(Rtl819XRadioC_Array[i] == 0xfe){
1661 msleep(100);
1662 continue;
1663 }
1664 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
1665 //msleep(1);
1666
1667 }
1668 break;
1669 case RF90_PATH_D:
1670 for(i = 0;i<RadioD_ArrayLength; i=i+2){
1671
1672 if(Rtl819XRadioD_Array[i] == 0xfe){
1673 msleep(100);
1674 continue;
1675 }
1676 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
1677 //msleep(1);
1678
1679 }
1680 break;
1681 default:
1682 break;
1683 }
1684
1685 return ret;
1686
1687 }
1688 /******************************************************************************
1689 *function: This function set Tx Power of the channel
1690 * input: struct net_device *dev
1691 * u8 channel
1692 * output: none
1693 * return: none
1694 * Note:
1695 * ***************************************************************************/
1696 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
1697 {
1698 struct r8192_priv *priv = ieee80211_priv(dev);
1699 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
1700 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
1701
1702 switch(priv->rf_chip)
1703 {
1704 case RF_8225:
1705 #ifdef TO_DO_LIST
1706 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
1707 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
1708 #endif
1709 break;
1710
1711 case RF_8256:
1712 PHY_SetRF8256CCKTxPower(dev, powerlevel);
1713 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
1714 break;
1715
1716 case RF_8258:
1717 break;
1718 default:
1719 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
1720 break;
1721 }
1722 }
1723 /****************************************************************************************
1724 *function: This function set command table variable(struct SwChnlCmd).
1725 * input: SwChnlCmd* CmdTable //table to be set.
1726 * u32 CmdTableIdx //variable index in table to be set
1727 * u32 CmdTableSz //table size.
1728 * SwChnlCmdID CmdID //command ID to set.
1729 * u32 Para1
1730 * u32 Para2
1731 * u32 msDelay
1732 * output:
1733 * return: true if finished, false otherwise
1734 * Note:
1735 * ************************************************************************************/
1736 static u8 rtl8192_phy_SetSwChnlCmdArray(
1737 SwChnlCmd* CmdTable,
1738 u32 CmdTableIdx,
1739 u32 CmdTableSz,
1740 SwChnlCmdID CmdID,
1741 u32 Para1,
1742 u32 Para2,
1743 u32 msDelay
1744 )
1745 {
1746 SwChnlCmd* pCmd;
1747
1748 if(CmdTable == NULL)
1749 {
1750 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
1751 return false;
1752 }
1753 if(CmdTableIdx >= CmdTableSz)
1754 {
1755 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1756 CmdTableIdx, CmdTableSz);
1757 return false;
1758 }
1759
1760 pCmd = CmdTable + CmdTableIdx;
1761 pCmd->CmdID = CmdID;
1762 pCmd->Para1 = Para1;
1763 pCmd->Para2 = Para2;
1764 pCmd->msDelay = msDelay;
1765
1766 return true;
1767 }
1768 /******************************************************************************
1769 *function: This function set channel step by step
1770 * input: struct net_device *dev
1771 * u8 channel
1772 * u8* stage //3 stages
1773 * u8* step //
1774 * u32* delay //whether need to delay
1775 * output: store new stage, step and delay for next step(combine with function above)
1776 * return: true if finished, false otherwise
1777 * Note: Wait for simpler function to replace it //wb
1778 * ***************************************************************************/
1779 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
1780 {
1781 struct r8192_priv *priv = ieee80211_priv(dev);
1782 // PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
1783 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
1784 u32 PreCommonCmdCnt;
1785 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
1786 u32 PostCommonCmdCnt;
1787 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
1788 u32 RfDependCmdCnt;
1789 SwChnlCmd *CurrentCmd = NULL;
1790 //RF90_RADIO_PATH_E eRFPath;
1791 u8 eRFPath;
1792 // u32 RfRetVal;
1793 // u8 RetryCnt;
1794
1795 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
1796 // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
1797
1798 #ifdef ENABLE_DOT11D
1799 if (!IsLegalChannel(priv->ieee80211, channel))
1800 {
1801 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
1802 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
1803 }
1804 #endif
1805
1806 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
1807 //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
1808 {
1809 //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1810 // return false;
1811 // <1> Fill up pre common command.
1812 PreCommonCmdCnt = 0;
1813 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1814 CmdID_SetTxPowerLevel, 0, 0, 0);
1815 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
1816 CmdID_End, 0, 0, 0);
1817
1818 // <2> Fill up post common command.
1819 PostCommonCmdCnt = 0;
1820
1821 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
1822 CmdID_End, 0, 0, 0);
1823
1824 // <3> Fill up RF dependent command.
1825 RfDependCmdCnt = 0;
1826 switch( priv->rf_chip )
1827 {
1828 case RF_8225:
1829 if (!(channel >= 1 && channel <= 14))
1830 {
1831 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
1832 return false;
1833 }
1834 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1835 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
1836 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1837 CmdID_End, 0, 0, 0);
1838 break;
1839
1840 case RF_8256:
1841 // TEST!! This is not the table for 8256!!
1842 if (!(channel >= 1 && channel <= 14))
1843 {
1844 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
1845 return false;
1846 }
1847 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1848 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
1849 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
1850 CmdID_End, 0, 0, 0);
1851 break;
1852
1853 case RF_8258:
1854 break;
1855
1856 default:
1857 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
1858 return false;
1859 break;
1860 }
1861
1862
1863 do{
1864 switch(*stage)
1865 {
1866 case 0:
1867 CurrentCmd=&PreCommonCmd[*step];
1868 break;
1869 case 1:
1870 CurrentCmd=&RfDependCmd[*step];
1871 break;
1872 case 2:
1873 CurrentCmd=&PostCommonCmd[*step];
1874 break;
1875 }
1876
1877 if(CurrentCmd->CmdID==CmdID_End)
1878 {
1879 if((*stage)==2)
1880 {
1881 return true;
1882 }
1883 else
1884 {
1885 (*stage)++;
1886 (*step)=0;
1887 continue;
1888 }
1889 }
1890
1891 switch(CurrentCmd->CmdID)
1892 {
1893 case CmdID_SetTxPowerLevel:
1894 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
1895 rtl8192_SetTxPowerLevel(dev,channel);
1896 break;
1897 case CmdID_WritePortUlong:
1898 write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2);
1899 break;
1900 case CmdID_WritePortUshort:
1901 write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
1902 break;
1903 case CmdID_WritePortUchar:
1904 write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
1905 break;
1906 case CmdID_RF_WriteReg:
1907 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
1908 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
1909 break;
1910 default:
1911 break;
1912 }
1913
1914 break;
1915 }while(true);
1916 }/*for(Number of RF paths)*/
1917
1918 (*delay)=CurrentCmd->msDelay;
1919 (*step)++;
1920 return false;
1921 }
1922
1923 /******************************************************************************
1924 *function: This function does acturally set channel work
1925 * input: struct net_device *dev
1926 * u8 channel
1927 * output: none
1928 * return: noin
1929 * Note: We should not call this function directly
1930 * ***************************************************************************/
1931 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
1932 {
1933 struct r8192_priv *priv = ieee80211_priv(dev);
1934 u32 delay = 0;
1935
1936 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
1937 {
1938 if(delay>0)
1939 msleep(delay);//or mdelay? need further consideration
1940 if(!priv->up)
1941 break;
1942 }
1943 }
1944 /******************************************************************************
1945 *function: Callback routine of the work item for switch channel.
1946 * input:
1947 *
1948 * output: none
1949 * return: noin
1950 * ***************************************************************************/
1951 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
1952 {
1953
1954 struct r8192_priv *priv = ieee80211_priv(dev);
1955
1956 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
1957
1958 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
1959
1960 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
1961
1962 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
1963 }
1964
1965 /******************************************************************************
1966 *function: This function scheduled actural workitem to set channel
1967 * input: net_device dev
1968 * u8 channel //channel to set
1969 * output: none
1970 * return: return code show if workitem is scheduled(1:pass, 0:fail)
1971 * Note: Delay may be required for RF configuration
1972 * ***************************************************************************/
1973 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
1974 {
1975 struct r8192_priv *priv = ieee80211_priv(dev);
1976 RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__);
1977 if(!priv->up)
1978 return false;
1979 if(priv->SwChnlInProgress)
1980 return false;
1981
1982 // if(pHalData->SetBWModeInProgress)
1983 // return;
1984
1985 //--------------------------------------------
1986 switch(priv->ieee80211->mode)
1987 {
1988 case WIRELESS_MODE_A:
1989 case WIRELESS_MODE_N_5G:
1990 if (channel<=14){
1991 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
1992 return false;
1993 }
1994 break;
1995 case WIRELESS_MODE_B:
1996 if (channel>14){
1997 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
1998 return false;
1999 }
2000 break;
2001 case WIRELESS_MODE_G:
2002 case WIRELESS_MODE_N_24G:
2003 if (channel>14){
2004 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2005 return false;
2006 }
2007 break;
2008 }
2009 //--------------------------------------------
2010
2011 priv->SwChnlInProgress = true;
2012 if(channel == 0)
2013 channel = 1;
2014
2015 priv->chan=channel;
2016
2017 priv->SwChnlStage=0;
2018 priv->SwChnlStep=0;
2019 // schedule_work(&(priv->SwChnlWorkItem));
2020 // rtl8192_SwChnl_WorkItem(dev);
2021 if(priv->up) {
2022 // queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
2023 rtl8192_SwChnl_WorkItem(dev);
2024 }
2025 priv->SwChnlInProgress = false;
2026 return true;
2027 }
2028
2029 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
2030 {
2031 struct r8192_priv *priv = ieee80211_priv(dev);
2032
2033 switch(priv->CurrentChannelBW)
2034 {
2035 /* 20 MHz channel*/
2036 case HT_CHANNEL_WIDTH_20:
2037 //added by vivi, cck,tx power track, 20080703
2038 priv->CCKPresentAttentuation =
2039 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
2040
2041 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2042 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2043 if(priv->CCKPresentAttentuation < 0)
2044 priv->CCKPresentAttentuation = 0;
2045
2046 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2047
2048 if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14)
2049 {
2050 priv->bcck_in_ch14 = TRUE;
2051 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2052 }
2053 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2054 {
2055 priv->bcck_in_ch14 = FALSE;
2056 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2057 }
2058 else
2059 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2060 break;
2061
2062 /* 40 MHz channel*/
2063 case HT_CHANNEL_WIDTH_20_40:
2064 //added by vivi, cck,tx power track, 20080703
2065 priv->CCKPresentAttentuation =
2066 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
2067
2068 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2069 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2070 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2071 if(priv->CCKPresentAttentuation < 0)
2072 priv->CCKPresentAttentuation = 0;
2073
2074 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
2075 {
2076 priv->bcck_in_ch14 = TRUE;
2077 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2078 }
2079 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2080 {
2081 priv->bcck_in_ch14 = FALSE;
2082 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2083 }
2084 else
2085 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2086 break;
2087 }
2088 }
2089
2090 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
2091 {
2092 struct r8192_priv *priv = ieee80211_priv(dev);
2093
2094 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
2095 priv->bcck_in_ch14 = TRUE;
2096 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2097 priv->bcck_in_ch14 = FALSE;
2098
2099 //write to default index and tx power track will be done in dm.
2100 switch(priv->CurrentChannelBW)
2101 {
2102 /* 20 MHz channel*/
2103 case HT_CHANNEL_WIDTH_20:
2104 if(priv->Record_CCK_20Mindex == 0)
2105 priv->Record_CCK_20Mindex = 6; //set default value.
2106 priv->CCK_index = priv->Record_CCK_20Mindex;//6;
2107 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
2108 break;
2109
2110 /* 40 MHz channel*/
2111 case HT_CHANNEL_WIDTH_20_40:
2112 priv->CCK_index = priv->Record_CCK_40Mindex;//0;
2113 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
2114 break;
2115 }
2116 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
2117 }
2118
2119 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
2120 {
2121 struct r8192_priv *priv = ieee80211_priv(dev);
2122
2123 //if(pHalData->bDcut == TRUE)
2124 if(priv->IC_Cut >= IC_VersionCut_D)
2125 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
2126 else
2127 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
2128 }
2129
2130
2131 //
2132 /******************************************************************************
2133 *function: Callback routine of the work item for set bandwidth mode.
2134 * input: struct net_device *dev
2135 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
2136 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
2137 * output: none
2138 * return: none
2139 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
2140 * test whether current work in the queue or not.//do I?
2141 * ***************************************************************************/
2142 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
2143 {
2144
2145 struct r8192_priv *priv = ieee80211_priv(dev);
2146 u8 regBwOpMode;
2147
2148 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n",
2149 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
2150
2151
2152 if(priv->rf_chip== RF_PSEUDO_11N)
2153 {
2154 priv->SetBWModeInProgress= false;
2155 return;
2156 }
2157 if(!priv->up)
2158 {
2159 priv->SetBWModeInProgress= false;
2160 return;
2161 }
2162 //<1>Set MAC register
2163 regBwOpMode = read_nic_byte(priv, BW_OPMODE);
2164
2165 switch(priv->CurrentChannelBW)
2166 {
2167 case HT_CHANNEL_WIDTH_20:
2168 regBwOpMode |= BW_OPMODE_20MHZ;
2169 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2170 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
2171 break;
2172
2173 case HT_CHANNEL_WIDTH_20_40:
2174 regBwOpMode &= ~BW_OPMODE_20MHZ;
2175 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2176 write_nic_byte(priv, BW_OPMODE, regBwOpMode);
2177 break;
2178
2179 default:
2180 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
2181 break;
2182 }
2183
2184 //<2>Set PHY related register
2185 switch(priv->CurrentChannelBW)
2186 {
2187 case HT_CHANNEL_WIDTH_20:
2188 // Add by Vivi 20071119
2189 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
2190 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
2191 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
2192
2193 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
2194 // write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
2195 // write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
2196 // write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
2197 if(!priv->btxpower_tracking)
2198 {
2199 write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000);
2200 write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317);
2201 write_nic_dword(priv, rCCK0_DebugPort, 0x00000204);
2202 }
2203 else
2204 CCK_Tx_Power_Track_BW_Switch(dev);
2205
2206 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
2207 break;
2208 case HT_CHANNEL_WIDTH_20_40:
2209 // Add by Vivi 20071119
2210 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
2211 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
2212 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2213 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
2214 //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2215
2216 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
2217 //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
2218 //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
2219 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
2220 if(!priv->btxpower_tracking)
2221 {
2222 write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000);
2223 write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e);
2224 write_nic_dword(priv, rCCK0_DebugPort, 0x00000409);
2225 }
2226 else
2227 CCK_Tx_Power_Track_BW_Switch(dev);
2228
2229 // Set Control channel to upper or lower. These settings are required only for 40MHz
2230 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
2231 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
2232
2233
2234 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
2235 break;
2236 default:
2237 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
2238 break;
2239
2240 }
2241 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2242
2243 //<3>Set RF related register
2244 switch( priv->rf_chip )
2245 {
2246 case RF_8225:
2247 #ifdef TO_DO_LIST
2248 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
2249 #endif
2250 break;
2251
2252 case RF_8256:
2253 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
2254 break;
2255
2256 case RF_8258:
2257 // PHY_SetRF8258Bandwidth();
2258 break;
2259
2260 case RF_PSEUDO_11N:
2261 // Do Nothing
2262 break;
2263
2264 default:
2265 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
2266 break;
2267 }
2268
2269 atomic_dec(&(priv->ieee80211->atm_swbw));
2270 priv->SetBWModeInProgress= false;
2271
2272 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
2273 }
2274
2275 /******************************************************************************
2276 *function: This function schedules bandwith switch work.
2277 * input: struct net_device *dev
2278 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
2279 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
2280 * output: none
2281 * return: none
2282 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
2283 * test whether current work in the queue or not.//do I?
2284 * ***************************************************************************/
2285 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
2286 {
2287 struct r8192_priv *priv = ieee80211_priv(dev);
2288
2289
2290 if(priv->SetBWModeInProgress)
2291 return;
2292
2293 atomic_inc(&(priv->ieee80211->atm_swbw));
2294 priv->SetBWModeInProgress= true;
2295
2296 priv->CurrentChannelBW = Bandwidth;
2297
2298 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2299 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2300 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2301 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2302 else
2303 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2304
2305 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
2306 // schedule_work(&(priv->SetBWModeWorkItem));
2307 rtl8192_SetBWModeWorkItem(dev);
2308
2309 }
2310
2311
2312 void InitialGain819xPci(struct net_device *dev, u8 Operation)
2313 {
2314 #define SCAN_RX_INITIAL_GAIN 0x17
2315 #define POWER_DETECTION_TH 0x08
2316 struct r8192_priv *priv = ieee80211_priv(dev);
2317 u32 BitMask;
2318 u8 initial_gain;
2319
2320 if(priv->up)
2321 {
2322 switch(Operation)
2323 {
2324 case IG_Backup:
2325 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
2326 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
2327 BitMask = bMaskByte0;
2328 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2329 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
2330 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
2331 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
2332 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
2333 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
2334 BitMask = bMaskByte2;
2335 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
2336
2337 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2338 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2339 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2340 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2341 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
2342
2343 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
2344 write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
2345 write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
2346 write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
2347 write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
2348 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
2349 write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH);
2350 break;
2351 case IG_Restore:
2352 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
2353 BitMask = 0x7f; //Bit0~ Bit6
2354 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2355 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
2356
2357 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
2358 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
2359 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
2360 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
2361 BitMask = bMaskByte2;
2362 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
2363
2364 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
2365 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
2366 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
2367 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
2368 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
2369
2370 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
2371
2372
2373 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
2374 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
2375 break;
2376 default:
2377 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
2378 break;
2379 }
2380 }
2381 }
2382
Linux kernel - Deliverables
This page took 0.080175 seconds and 4 git commands to generate.