1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 * Based on the r8180 driver, which is:
5 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 * The full GNU General Public License is included in this distribution in the
20 * file called LICENSE.
22 * Contact Information:
23 * wlanfae <wlanfae@realtek.com>
24 ******************************************************************************/
26 #include "r8192E_phy.h"
27 #include "r8192E_phyreg.h"
28 #include "r8190P_rtl8256.h"
29 #include "r8192E_cmdpkt.h"
33 static int WDCAPARA_ADD
[] = {EDCAPARA_BE
, EDCAPARA_BK
, EDCAPARA_VI
,
36 void rtl92e_start_beacon(struct net_device
*dev
)
38 struct r8192_priv
*priv
= (struct r8192_priv
*)rtllib_priv(dev
);
39 struct rtllib_network
*net
= &priv
->rtllib
->current_network
;
44 rtl92e_irq_disable(dev
);
46 write_nic_word(dev
, ATIMWND
, 2);
48 write_nic_word(dev
, BCN_INTERVAL
, net
->beacon_interval
);
49 write_nic_word(dev
, BCN_DRV_EARLY_INT
, 10);
50 write_nic_word(dev
, BCN_DMATIME
, 256);
52 write_nic_byte(dev
, BCN_ERR_THRESH
, 100);
54 BcnTimeCfg
|= BcnCW
<<BCN_TCFG_CW_SHIFT
;
55 BcnTimeCfg
|= BcnIFS
<<BCN_TCFG_IFS
;
56 write_nic_word(dev
, BCN_TCFG
, BcnTimeCfg
);
57 rtl92e_irq_enable(dev
);
60 static void rtl8192e_update_msr(struct net_device
*dev
)
62 struct r8192_priv
*priv
= rtllib_priv(dev
);
64 enum led_ctl_mode LedAction
= LED_CTL_NO_LINK
;
66 msr
= rtl92e_readb(dev
, MSR
);
67 msr
&= ~MSR_LINK_MASK
;
69 switch (priv
->rtllib
->iw_mode
) {
71 if (priv
->rtllib
->state
== RTLLIB_LINKED
)
72 msr
|= (MSR_LINK_MANAGED
<< MSR_LINK_SHIFT
);
74 msr
|= (MSR_LINK_NONE
<< MSR_LINK_SHIFT
);
75 LedAction
= LED_CTL_LINK
;
78 if (priv
->rtllib
->state
== RTLLIB_LINKED
)
79 msr
|= (MSR_LINK_ADHOC
<< MSR_LINK_SHIFT
);
81 msr
|= (MSR_LINK_NONE
<< MSR_LINK_SHIFT
);
84 if (priv
->rtllib
->state
== RTLLIB_LINKED
)
85 msr
|= (MSR_LINK_MASTER
<< MSR_LINK_SHIFT
);
87 msr
|= (MSR_LINK_NONE
<< MSR_LINK_SHIFT
);
93 write_nic_byte(dev
, MSR
, msr
);
94 if (priv
->rtllib
->LedControlHandler
)
95 priv
->rtllib
->LedControlHandler(dev
, LedAction
);
98 void rtl92e_set_reg(struct net_device
*dev
, u8 variable
, u8
*val
)
100 struct r8192_priv
*priv
= rtllib_priv(dev
);
104 write_nic_dword(dev
, BSSIDR
, ((u32
*)(val
))[0]);
105 write_nic_word(dev
, BSSIDR
+2, ((u16
*)(val
+2))[0]);
108 case HW_VAR_MEDIA_STATUS
:
110 enum rt_op_mode OpMode
= *((enum rt_op_mode
*)(val
));
111 enum led_ctl_mode LedAction
= LED_CTL_NO_LINK
;
112 u8 btMsr
= rtl92e_readb(dev
, MSR
);
117 case RT_OP_MODE_INFRASTRUCTURE
:
119 LedAction
= LED_CTL_LINK
;
122 case RT_OP_MODE_IBSS
:
128 LedAction
= LED_CTL_LINK
;
136 write_nic_byte(dev
, MSR
, btMsr
);
141 case HW_VAR_CECHK_BSSID
:
145 Type
= ((u8
*)(val
))[0];
146 RegRCR
= rtl92e_readl(dev
, RCR
);
147 priv
->ReceiveConfig
= RegRCR
;
150 RegRCR
|= (RCR_CBSSID
);
151 else if (Type
== false)
152 RegRCR
&= (~RCR_CBSSID
);
154 write_nic_dword(dev
, RCR
, RegRCR
);
155 priv
->ReceiveConfig
= RegRCR
;
160 case HW_VAR_SLOT_TIME
:
162 priv
->slot_time
= val
[0];
163 write_nic_byte(dev
, SLOT_TIME
, val
[0]);
167 case HW_VAR_ACK_PREAMBLE
:
171 priv
->short_preamble
= (bool)(*(u8
*)val
);
172 regTmp
= priv
->basic_rate
;
173 if (priv
->short_preamble
)
174 regTmp
|= BRSR_AckShortPmb
;
175 write_nic_dword(dev
, RRSR
, regTmp
);
180 write_nic_dword(dev
, CPU_GEN
, ((u32
*)(val
))[0]);
183 case HW_VAR_AC_PARAM
:
185 u8 pAcParam
= *((u8
*)val
);
189 u8 mode
= priv
->rtllib
->mode
;
190 struct rtllib_qos_parameters
*qop
=
191 &priv
->rtllib
->current_network
.qos_data
.parameters
;
193 u1bAIFS
= qop
->aifs
[pAcParam
] *
194 ((mode
&(IEEE_G
|IEEE_N_24G
)) ? 9 : 20) + aSifsTime
;
196 dm_init_edca_turbo(dev
);
198 u4bAcParam
= (le16_to_cpu(qop
->tx_op_limit
[pAcParam
]) <<
199 AC_PARAM_TXOP_LIMIT_OFFSET
) |
200 ((le16_to_cpu(qop
->cw_max
[pAcParam
])) <<
201 AC_PARAM_ECW_MAX_OFFSET
) |
202 ((le16_to_cpu(qop
->cw_min
[pAcParam
])) <<
203 AC_PARAM_ECW_MIN_OFFSET
) |
204 (((u32
)u1bAIFS
) << AC_PARAM_AIFS_OFFSET
);
206 RT_TRACE(COMP_DBG
, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
207 __func__
, eACI
, u4bAcParam
);
210 write_nic_dword(dev
, EDCAPARA_BK
, u4bAcParam
);
214 write_nic_dword(dev
, EDCAPARA_BE
, u4bAcParam
);
218 write_nic_dword(dev
, EDCAPARA_VI
, u4bAcParam
);
222 write_nic_dword(dev
, EDCAPARA_VO
, u4bAcParam
);
226 netdev_info(dev
, "SetHwReg8185(): invalid ACI: %d !\n",
230 priv
->rtllib
->SetHwRegHandler(dev
, HW_VAR_ACM_CTRL
,
235 case HW_VAR_ACM_CTRL
:
237 struct rtllib_qos_parameters
*qos_parameters
=
238 &priv
->rtllib
->current_network
.qos_data
.parameters
;
239 u8 pAcParam
= *((u8
*)val
);
241 union aci_aifsn
*pAciAifsn
= (union aci_aifsn
*) &
242 (qos_parameters
->aifs
[0]);
243 u8 acm
= pAciAifsn
->f
.acm
;
244 u8 AcmCtrl
= rtl92e_readb(dev
, AcmHwCtrl
);
246 RT_TRACE(COMP_DBG
, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
248 AcmCtrl
= AcmCtrl
| ((priv
->AcmMethod
== 2) ? 0x0 : 0x1);
253 AcmCtrl
|= AcmHw_BeqEn
;
257 AcmCtrl
|= AcmHw_ViqEn
;
261 AcmCtrl
|= AcmHw_VoqEn
;
266 "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
273 AcmCtrl
&= (~AcmHw_BeqEn
);
277 AcmCtrl
&= (~AcmHw_ViqEn
);
281 AcmCtrl
&= (~AcmHw_BeqEn
);
290 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
292 write_nic_byte(dev
, AcmHwCtrl
, AcmCtrl
);
297 write_nic_byte(dev
, SIFS
, val
[0]);
298 write_nic_byte(dev
, SIFS
+1, val
[0]);
301 case HW_VAR_RF_TIMING
:
303 u8 Rf_Timing
= *((u8
*)val
);
305 write_nic_byte(dev
, rFPGA0_RFTiming1
, Rf_Timing
);
315 static void rtl8192_read_eeprom_info(struct net_device
*dev
)
317 struct r8192_priv
*priv
= rtllib_priv(dev
);
318 const u8 bMac_Tmp_Addr
[ETH_ALEN
] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
320 u8 ICVer8192
, ICVer8256
;
321 u16 i
, usValue
, IC_Version
;
324 RT_TRACE(COMP_INIT
, "====> rtl8192_read_eeprom_info\n");
326 EEPROMId
= eprom_read(dev
, 0);
327 if (EEPROMId
!= RTL8190_EEPROM_ID
) {
328 netdev_err(dev
, "%s(): Invalid EEPROM ID: %x\n", __func__
,
330 priv
->AutoloadFailFlag
= true;
332 priv
->AutoloadFailFlag
= false;
335 if (!priv
->AutoloadFailFlag
) {
336 priv
->eeprom_vid
= eprom_read(dev
, EEPROM_VID
>> 1);
337 priv
->eeprom_did
= eprom_read(dev
, EEPROM_DID
>> 1);
339 usValue
= eprom_read(dev
, (u16
)(EEPROM_Customer_ID
>>1)) >> 8;
340 priv
->eeprom_CustomerID
= (u8
)(usValue
& 0xff);
341 usValue
= eprom_read(dev
, EEPROM_ICVersion_ChannelPlan
>>1);
342 priv
->eeprom_ChannelPlan
= usValue
&0xff;
343 IC_Version
= (usValue
& 0xff00)>>8;
345 ICVer8192
= (IC_Version
&0xf);
346 ICVer8256
= (IC_Version
& 0xf0)>>4;
347 RT_TRACE(COMP_INIT
, "\nICVer8192 = 0x%x\n", ICVer8192
);
348 RT_TRACE(COMP_INIT
, "\nICVer8256 = 0x%x\n", ICVer8256
);
349 if (ICVer8192
== 0x2) {
350 if (ICVer8256
== 0x5)
351 priv
->card_8192_version
= VERSION_8190_BE
;
353 switch (priv
->card_8192_version
) {
354 case VERSION_8190_BD
:
355 case VERSION_8190_BE
:
358 priv
->card_8192_version
= VERSION_8190_BD
;
361 RT_TRACE(COMP_INIT
, "\nIC Version = 0x%x\n",
362 priv
->card_8192_version
);
364 priv
->card_8192_version
= VERSION_8190_BD
;
365 priv
->eeprom_vid
= 0;
366 priv
->eeprom_did
= 0;
367 priv
->eeprom_CustomerID
= 0;
368 priv
->eeprom_ChannelPlan
= 0;
369 RT_TRACE(COMP_INIT
, "\nIC Version = 0x%x\n", 0xff);
372 RT_TRACE(COMP_INIT
, "EEPROM VID = 0x%4x\n", priv
->eeprom_vid
);
373 RT_TRACE(COMP_INIT
, "EEPROM DID = 0x%4x\n", priv
->eeprom_did
);
374 RT_TRACE(COMP_INIT
, "EEPROM Customer ID: 0x%2x\n",
375 priv
->eeprom_CustomerID
);
377 if (!priv
->AutoloadFailFlag
) {
378 for (i
= 0; i
< 6; i
+= 2) {
379 usValue
= eprom_read(dev
,
380 (u16
)((EEPROM_NODE_ADDRESS_BYTE_0
+ i
) >> 1));
381 *(u16
*)(&dev
->dev_addr
[i
]) = usValue
;
384 ether_addr_copy(dev
->dev_addr
, bMac_Tmp_Addr
);
387 RT_TRACE(COMP_INIT
, "Permanent Address = %pM\n",
390 if (priv
->card_8192_version
> VERSION_8190_BD
)
391 priv
->bTXPowerDataReadFromEEPORM
= true;
393 priv
->bTXPowerDataReadFromEEPORM
= false;
395 priv
->rf_type
= RTL819X_DEFAULT_RF_TYPE
;
397 if (priv
->card_8192_version
> VERSION_8190_BD
) {
398 if (!priv
->AutoloadFailFlag
) {
399 tempval
= (eprom_read(dev
, (EEPROM_RFInd_PowerDiff
>>
401 priv
->EEPROMLegacyHTTxPowerDiff
= tempval
& 0xf;
404 priv
->rf_type
= RF_1T2R
;
406 priv
->rf_type
= RF_2T4R
;
408 priv
->EEPROMLegacyHTTxPowerDiff
= 0x04;
410 RT_TRACE(COMP_INIT
, "EEPROMLegacyHTTxPowerDiff = %d\n",
411 priv
->EEPROMLegacyHTTxPowerDiff
);
413 if (!priv
->AutoloadFailFlag
)
414 priv
->EEPROMThermalMeter
= (u8
)(((eprom_read(dev
,
415 (EEPROM_ThermalMeter
>>1))) &
418 priv
->EEPROMThermalMeter
= EEPROM_Default_ThermalMeter
;
419 RT_TRACE(COMP_INIT
, "ThermalMeter = %d\n",
420 priv
->EEPROMThermalMeter
);
421 priv
->TSSI_13dBm
= priv
->EEPROMThermalMeter
* 100;
423 if (priv
->epromtype
== EEPROM_93C46
) {
424 if (!priv
->AutoloadFailFlag
) {
425 usValue
= eprom_read(dev
,
426 EEPROM_TxPwDiff_CrystalCap
>> 1);
427 priv
->EEPROMAntPwDiff
= (usValue
&0x0fff);
428 priv
->EEPROMCrystalCap
= (u8
)((usValue
& 0xf000)
431 priv
->EEPROMAntPwDiff
=
432 EEPROM_Default_AntTxPowerDiff
;
433 priv
->EEPROMCrystalCap
=
434 EEPROM_Default_TxPwDiff_CrystalCap
;
436 RT_TRACE(COMP_INIT
, "EEPROMAntPwDiff = %d\n",
437 priv
->EEPROMAntPwDiff
);
438 RT_TRACE(COMP_INIT
, "EEPROMCrystalCap = %d\n",
439 priv
->EEPROMCrystalCap
);
441 for (i
= 0; i
< 14; i
+= 2) {
442 if (!priv
->AutoloadFailFlag
)
443 usValue
= eprom_read(dev
,
444 (u16
)((EEPROM_TxPwIndex_CCK
+
447 usValue
= EEPROM_Default_TxPower
;
448 *((u16
*)(&priv
->EEPROMTxPowerLevelCCK
[i
])) =
451 "CCK Tx Power Level, Index %d = 0x%02x\n",
452 i
, priv
->EEPROMTxPowerLevelCCK
[i
]);
454 "CCK Tx Power Level, Index %d = 0x%02x\n",
455 i
+1, priv
->EEPROMTxPowerLevelCCK
[i
+1]);
457 for (i
= 0; i
< 14; i
+= 2) {
458 if (!priv
->AutoloadFailFlag
)
459 usValue
= eprom_read(dev
,
460 (u16
)((EEPROM_TxPwIndex_OFDM_24G
463 usValue
= EEPROM_Default_TxPower
;
464 *((u16
*)(&priv
->EEPROMTxPowerLevelOFDM24G
[i
]))
467 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
468 i
, priv
->EEPROMTxPowerLevelOFDM24G
[i
]);
470 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
472 priv
->EEPROMTxPowerLevelOFDM24G
[i
+1]);
475 if (priv
->epromtype
== EEPROM_93C46
) {
476 for (i
= 0; i
< 14; i
++) {
477 priv
->TxPowerLevelCCK
[i
] =
478 priv
->EEPROMTxPowerLevelCCK
[i
];
479 priv
->TxPowerLevelOFDM24G
[i
] =
480 priv
->EEPROMTxPowerLevelOFDM24G
[i
];
482 priv
->LegacyHTTxPowerDiff
=
483 priv
->EEPROMLegacyHTTxPowerDiff
;
484 priv
->AntennaTxPwDiff
[0] = (priv
->EEPROMAntPwDiff
&
486 priv
->AntennaTxPwDiff
[1] = (priv
->EEPROMAntPwDiff
&
488 priv
->AntennaTxPwDiff
[2] = (priv
->EEPROMAntPwDiff
&
490 priv
->CrystalCap
= priv
->EEPROMCrystalCap
;
491 priv
->ThermalMeter
[0] = (priv
->EEPROMThermalMeter
&
493 priv
->ThermalMeter
[1] = (priv
->EEPROMThermalMeter
&
495 } else if (priv
->epromtype
== EEPROM_93C56
) {
497 for (i
= 0; i
< 3; i
++) {
498 priv
->TxPowerLevelCCK_A
[i
] =
499 priv
->EEPROMRfACCKChnl1TxPwLevel
[0];
500 priv
->TxPowerLevelOFDM24G_A
[i
] =
501 priv
->EEPROMRfAOfdmChnlTxPwLevel
[0];
502 priv
->TxPowerLevelCCK_C
[i
] =
503 priv
->EEPROMRfCCCKChnl1TxPwLevel
[0];
504 priv
->TxPowerLevelOFDM24G_C
[i
] =
505 priv
->EEPROMRfCOfdmChnlTxPwLevel
[0];
507 for (i
= 3; i
< 9; i
++) {
508 priv
->TxPowerLevelCCK_A
[i
] =
509 priv
->EEPROMRfACCKChnl1TxPwLevel
[1];
510 priv
->TxPowerLevelOFDM24G_A
[i
] =
511 priv
->EEPROMRfAOfdmChnlTxPwLevel
[1];
512 priv
->TxPowerLevelCCK_C
[i
] =
513 priv
->EEPROMRfCCCKChnl1TxPwLevel
[1];
514 priv
->TxPowerLevelOFDM24G_C
[i
] =
515 priv
->EEPROMRfCOfdmChnlTxPwLevel
[1];
517 for (i
= 9; i
< 14; i
++) {
518 priv
->TxPowerLevelCCK_A
[i
] =
519 priv
->EEPROMRfACCKChnl1TxPwLevel
[2];
520 priv
->TxPowerLevelOFDM24G_A
[i
] =
521 priv
->EEPROMRfAOfdmChnlTxPwLevel
[2];
522 priv
->TxPowerLevelCCK_C
[i
] =
523 priv
->EEPROMRfCCCKChnl1TxPwLevel
[2];
524 priv
->TxPowerLevelOFDM24G_C
[i
] =
525 priv
->EEPROMRfCOfdmChnlTxPwLevel
[2];
527 for (i
= 0; i
< 14; i
++)
529 "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
530 i
, priv
->TxPowerLevelCCK_A
[i
]);
531 for (i
= 0; i
< 14; i
++)
533 "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
534 i
, priv
->TxPowerLevelOFDM24G_A
[i
]);
535 for (i
= 0; i
< 14; i
++)
537 "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
538 i
, priv
->TxPowerLevelCCK_C
[i
]);
539 for (i
= 0; i
< 14; i
++)
541 "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
542 i
, priv
->TxPowerLevelOFDM24G_C
[i
]);
543 priv
->LegacyHTTxPowerDiff
=
544 priv
->EEPROMLegacyHTTxPowerDiff
;
545 priv
->AntennaTxPwDiff
[0] = 0;
546 priv
->AntennaTxPwDiff
[1] = 0;
547 priv
->AntennaTxPwDiff
[2] = 0;
548 priv
->CrystalCap
= priv
->EEPROMCrystalCap
;
549 priv
->ThermalMeter
[0] = (priv
->EEPROMThermalMeter
&
551 priv
->ThermalMeter
[1] = (priv
->EEPROMThermalMeter
&
556 if (priv
->rf_type
== RF_1T2R
) {
557 /* no matter what checkpatch says, the braces are needed */
558 RT_TRACE(COMP_INIT
, "\n1T2R config\n");
559 } else if (priv
->rf_type
== RF_2T4R
) {
560 RT_TRACE(COMP_INIT
, "\n2T4R config\n");
563 init_rate_adaptive(dev
);
565 priv
->rf_chip
= RF_8256
;
567 if (priv
->RegChannelPlan
== 0xf)
568 priv
->ChannelPlan
= priv
->eeprom_ChannelPlan
;
570 priv
->ChannelPlan
= priv
->RegChannelPlan
;
572 if (priv
->eeprom_vid
== 0x1186 && priv
->eeprom_did
== 0x3304)
573 priv
->CustomerID
= RT_CID_DLINK
;
575 switch (priv
->eeprom_CustomerID
) {
576 case EEPROM_CID_DEFAULT
:
577 priv
->CustomerID
= RT_CID_DEFAULT
;
579 case EEPROM_CID_CAMEO
:
580 priv
->CustomerID
= RT_CID_819x_CAMEO
;
582 case EEPROM_CID_RUNTOP
:
583 priv
->CustomerID
= RT_CID_819x_RUNTOP
;
585 case EEPROM_CID_NetCore
:
586 priv
->CustomerID
= RT_CID_819x_Netcore
;
588 case EEPROM_CID_TOSHIBA
:
589 priv
->CustomerID
= RT_CID_TOSHIBA
;
590 if (priv
->eeprom_ChannelPlan
&0x80)
591 priv
->ChannelPlan
= priv
->eeprom_ChannelPlan
&0x7f;
593 priv
->ChannelPlan
= 0x0;
594 RT_TRACE(COMP_INIT
, "Toshiba ChannelPlan = 0x%x\n",
597 case EEPROM_CID_Nettronix
:
598 priv
->ScanDelay
= 100;
599 priv
->CustomerID
= RT_CID_Nettronix
;
601 case EEPROM_CID_Pronet
:
602 priv
->CustomerID
= RT_CID_PRONET
;
604 case EEPROM_CID_DLINK
:
605 priv
->CustomerID
= RT_CID_DLINK
;
608 case EEPROM_CID_WHQL
:
614 if (priv
->ChannelPlan
> CHANNEL_PLAN_LEN
- 1)
615 priv
->ChannelPlan
= 0;
616 priv
->ChannelPlan
= COUNTRY_CODE_WORLD_WIDE_13
;
618 if (priv
->eeprom_vid
== 0x1186 && priv
->eeprom_did
== 0x3304)
619 priv
->rtllib
->bSupportRemoteWakeUp
= true;
621 priv
->rtllib
->bSupportRemoteWakeUp
= false;
623 RT_TRACE(COMP_INIT
, "RegChannelPlan(%d)\n", priv
->RegChannelPlan
);
624 RT_TRACE(COMP_INIT
, "ChannelPlan = %d\n", priv
->ChannelPlan
);
625 RT_TRACE(COMP_TRACE
, "<==== ReadAdapterInfo\n");
628 void rtl92e_get_eeprom_size(struct net_device
*dev
)
631 struct r8192_priv
*priv
= rtllib_priv(dev
);
633 RT_TRACE(COMP_INIT
, "===========>%s()\n", __func__
);
634 curCR
= rtl92e_readl(dev
, EPROM_CMD
);
635 RT_TRACE(COMP_INIT
, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD
,
637 priv
->epromtype
= (curCR
& EPROM_CMD_9356SEL
) ? EEPROM_93C56
:
639 RT_TRACE(COMP_INIT
, "<===========%s(), epromtype:%d\n", __func__
,
641 rtl8192_read_eeprom_info(dev
);
644 static void rtl8192_hwconfig(struct net_device
*dev
)
646 u32 regRATR
= 0, regRRSR
= 0;
647 u8 regBwOpMode
= 0, regTmp
= 0;
648 struct r8192_priv
*priv
= rtllib_priv(dev
);
650 switch (priv
->rtllib
->mode
) {
651 case WIRELESS_MODE_B
:
652 regBwOpMode
= BW_OPMODE_20MHZ
;
653 regRATR
= RATE_ALL_CCK
;
654 regRRSR
= RATE_ALL_CCK
;
656 case WIRELESS_MODE_A
:
657 regBwOpMode
= BW_OPMODE_5G
| BW_OPMODE_20MHZ
;
658 regRATR
= RATE_ALL_OFDM_AG
;
659 regRRSR
= RATE_ALL_OFDM_AG
;
661 case WIRELESS_MODE_G
:
662 regBwOpMode
= BW_OPMODE_20MHZ
;
663 regRATR
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
664 regRRSR
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
666 case WIRELESS_MODE_AUTO
:
667 case WIRELESS_MODE_N_24G
:
668 regBwOpMode
= BW_OPMODE_20MHZ
;
669 regRATR
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
|
670 RATE_ALL_OFDM_1SS
| RATE_ALL_OFDM_2SS
;
671 regRRSR
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
673 case WIRELESS_MODE_N_5G
:
674 regBwOpMode
= BW_OPMODE_5G
;
675 regRATR
= RATE_ALL_OFDM_AG
| RATE_ALL_OFDM_1SS
|
677 regRRSR
= RATE_ALL_OFDM_AG
;
680 regBwOpMode
= BW_OPMODE_20MHZ
;
681 regRATR
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
682 regRRSR
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
686 write_nic_byte(dev
, BW_OPMODE
, regBwOpMode
);
690 ratr_value
= regRATR
;
691 if (priv
->rf_type
== RF_1T2R
)
692 ratr_value
&= ~(RATE_ALL_OFDM_2SS
);
693 write_nic_dword(dev
, RATR0
, ratr_value
);
694 write_nic_byte(dev
, UFWP
, 1);
696 regTmp
= rtl92e_readb(dev
, 0x313);
697 regRRSR
= ((regTmp
) << 24) | (regRRSR
& 0x00ffffff);
698 write_nic_dword(dev
, RRSR
, regRRSR
);
700 write_nic_word(dev
, RETRY_LIMIT
,
701 priv
->ShortRetryLimit
<< RETRY_LIMIT_SHORT_SHIFT
|
702 priv
->LongRetryLimit
<< RETRY_LIMIT_LONG_SHIFT
);
705 bool rtl92e_start_adapter(struct net_device
*dev
)
707 struct r8192_priv
*priv
= rtllib_priv(dev
);
709 bool rtStatus
= true;
711 u8 ICVersion
, SwitchingRegulatorOutput
;
712 bool bfirmwareok
= true;
713 u32 tmpRegA
, tmpRegC
, TempCCk
;
717 RT_TRACE(COMP_INIT
, "====>%s()\n", __func__
);
718 priv
->being_init_adapter
= true;
721 rtl92e_reset_desc_ring(dev
);
722 priv
->Rf_Mode
= RF_OP_By_SW_3wire
;
723 if (priv
->ResetProgress
== RESET_TYPE_NORESET
) {
724 write_nic_byte(dev
, ANAPAR
, 0x37);
727 priv
->pFirmware
->firmware_status
= FW_STATUS_0_INIT
;
730 priv
->rtllib
->eRFPowerState
= eRfOff
;
732 ulRegRead
= rtl92e_readl(dev
, CPU_GEN
);
733 if (priv
->pFirmware
->firmware_status
== FW_STATUS_0_INIT
)
734 ulRegRead
|= CPU_GEN_SYSTEM_RESET
;
735 else if (priv
->pFirmware
->firmware_status
== FW_STATUS_5_READY
)
736 ulRegRead
|= CPU_GEN_FIRMWARE_RESET
;
738 netdev_err(dev
, "%s(): undefined firmware state: %d.\n",
739 __func__
, priv
->pFirmware
->firmware_status
);
741 write_nic_dword(dev
, CPU_GEN
, ulRegRead
);
743 ICVersion
= rtl92e_readb(dev
, IC_VERRSION
);
744 if (ICVersion
>= 0x4) {
745 SwitchingRegulatorOutput
= rtl92e_readb(dev
, SWREGULATOR
);
746 if (SwitchingRegulatorOutput
!= 0xb8) {
747 write_nic_byte(dev
, SWREGULATOR
, 0xa8);
749 write_nic_byte(dev
, SWREGULATOR
, 0xb8);
752 RT_TRACE(COMP_INIT
, "BB Config Start!\n");
753 rtStatus
= rtl92e_config_bb(dev
);
755 netdev_warn(dev
, "%s(): Failed to configure BB\n", __func__
);
758 RT_TRACE(COMP_INIT
, "BB Config Finished!\n");
760 priv
->LoopbackMode
= RTL819X_NO_LOOPBACK
;
761 if (priv
->ResetProgress
== RESET_TYPE_NORESET
) {
762 ulRegRead
= rtl92e_readl(dev
, CPU_GEN
);
763 if (priv
->LoopbackMode
== RTL819X_NO_LOOPBACK
)
764 ulRegRead
= ((ulRegRead
& CPU_GEN_NO_LOOPBACK_MSK
) |
765 CPU_GEN_NO_LOOPBACK_SET
);
766 else if (priv
->LoopbackMode
== RTL819X_MAC_LOOPBACK
)
767 ulRegRead
|= CPU_CCK_LOOPBACK
;
769 netdev_err(dev
, "%s: Invalid loopback mode setting.\n",
772 write_nic_dword(dev
, CPU_GEN
, ulRegRead
);
776 rtl8192_hwconfig(dev
);
777 write_nic_byte(dev
, CMDR
, CR_RE
| CR_TE
);
779 write_nic_byte(dev
, PCIF
, ((MXDMA2_NoLimit
<<MXDMA2_RX_SHIFT
) |
780 (MXDMA2_NoLimit
<<MXDMA2_TX_SHIFT
)));
781 write_nic_dword(dev
, MAC0
, ((u32
*)dev
->dev_addr
)[0]);
782 write_nic_word(dev
, MAC4
, ((u16
*)(dev
->dev_addr
+ 4))[0]);
783 write_nic_dword(dev
, RCR
, priv
->ReceiveConfig
);
785 write_nic_dword(dev
, RQPN1
, NUM_OF_PAGE_IN_FW_QUEUE_BK
<<
786 RSVD_FW_QUEUE_PAGE_BK_SHIFT
|
787 NUM_OF_PAGE_IN_FW_QUEUE_BE
<<
788 RSVD_FW_QUEUE_PAGE_BE_SHIFT
|
789 NUM_OF_PAGE_IN_FW_QUEUE_VI
<<
790 RSVD_FW_QUEUE_PAGE_VI_SHIFT
|
791 NUM_OF_PAGE_IN_FW_QUEUE_VO
<<
792 RSVD_FW_QUEUE_PAGE_VO_SHIFT
);
793 write_nic_dword(dev
, RQPN2
, NUM_OF_PAGE_IN_FW_QUEUE_MGNT
<<
794 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT
);
795 write_nic_dword(dev
, RQPN3
, APPLIED_RESERVED_QUEUE_IN_FW
|
796 NUM_OF_PAGE_IN_FW_QUEUE_BCN
<<
797 RSVD_FW_QUEUE_PAGE_BCN_SHIFT
|
798 NUM_OF_PAGE_IN_FW_QUEUE_PUB
<<
799 RSVD_FW_QUEUE_PAGE_PUB_SHIFT
);
801 rtl92e_tx_enable(dev
);
802 rtl92e_rx_enable(dev
);
803 ulRegRead
= (0xFFF00000 & rtl92e_readl(dev
, RRSR
)) |
804 RATE_ALL_OFDM_AG
| RATE_ALL_CCK
;
805 write_nic_dword(dev
, RRSR
, ulRegRead
);
806 write_nic_dword(dev
, RATR0
+4*7, (RATE_ALL_OFDM_AG
| RATE_ALL_CCK
));
808 write_nic_byte(dev
, ACK_TIMEOUT
, 0x30);
810 if (priv
->ResetProgress
== RESET_TYPE_NORESET
)
811 rtl92e_set_wireless_mode(dev
, priv
->rtllib
->mode
);
812 rtl92e_cam_reset(dev
);
816 SECR_value
|= SCR_TxEncEnable
;
817 SECR_value
|= SCR_RxDecEnable
;
818 SECR_value
|= SCR_NoSKMC
;
819 write_nic_byte(dev
, SECR
, SECR_value
);
821 write_nic_word(dev
, ATIMWND
, 2);
822 write_nic_word(dev
, BCN_INTERVAL
, 100);
826 for (i
= 0; i
< QOS_QUEUE_NUM
; i
++)
827 write_nic_dword(dev
, WDCAPARA_ADD
[i
], 0x005e4332);
829 write_nic_byte(dev
, 0xbe, 0xc0);
831 rtl92e_config_mac(dev
);
833 if (priv
->card_8192_version
> (u8
) VERSION_8190_BD
) {
834 rtl92e_get_tx_power(dev
);
835 rtl92e_set_tx_power(dev
, priv
->chan
);
838 tmpvalue
= rtl92e_readb(dev
, IC_VERRSION
);
839 priv
->IC_Cut
= tmpvalue
;
840 RT_TRACE(COMP_INIT
, "priv->IC_Cut= 0x%x\n", priv
->IC_Cut
);
841 if (priv
->IC_Cut
>= IC_VersionCut_D
) {
842 if (priv
->IC_Cut
== IC_VersionCut_D
) {
843 /* no matter what checkpatch says, braces are needed */
844 RT_TRACE(COMP_INIT
, "D-cut\n");
845 } else if (priv
->IC_Cut
== IC_VersionCut_E
) {
846 RT_TRACE(COMP_INIT
, "E-cut\n");
849 RT_TRACE(COMP_INIT
, "Before C-cut\n");
852 RT_TRACE(COMP_INIT
, "Load Firmware!\n");
853 bfirmwareok
= init_firmware(dev
);
855 if (retry_times
< 10) {
863 RT_TRACE(COMP_INIT
, "Load Firmware finished!\n");
864 if (priv
->ResetProgress
== RESET_TYPE_NORESET
) {
865 RT_TRACE(COMP_INIT
, "RF Config Started!\n");
866 rtStatus
= rtl92e_config_phy(dev
);
868 netdev_info(dev
, "RF Config failed\n");
871 RT_TRACE(COMP_INIT
, "RF Config Finished!\n");
873 rtl8192_phy_updateInitGain(dev
);
875 rtl92e_set_bb_reg(dev
, rFPGA0_RFMOD
, bCCKEn
, 0x1);
876 rtl92e_set_bb_reg(dev
, rFPGA0_RFMOD
, bOFDMEn
, 0x1);
878 write_nic_byte(dev
, 0x87, 0x0);
880 if (priv
->RegRfOff
) {
881 RT_TRACE((COMP_INIT
| COMP_RF
| COMP_POWER
),
882 "%s(): Turn off RF for RegRfOff ----------\n",
884 rtl92e_set_rf_state(dev
, eRfOff
, RF_CHANGE_BY_SW
, true);
885 } else if (priv
->rtllib
->RfOffReason
> RF_CHANGE_BY_PS
) {
886 RT_TRACE((COMP_INIT
|COMP_RF
|COMP_POWER
),
887 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
888 __func__
, priv
->rtllib
->RfOffReason
);
889 rtl92e_set_rf_state(dev
, eRfOff
, priv
->rtllib
->RfOffReason
,
891 } else if (priv
->rtllib
->RfOffReason
>= RF_CHANGE_BY_IPS
) {
892 RT_TRACE((COMP_INIT
|COMP_RF
|COMP_POWER
),
893 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
894 __func__
, priv
->rtllib
->RfOffReason
);
895 rtl92e_set_rf_state(dev
, eRfOff
, priv
->rtllib
->RfOffReason
,
898 RT_TRACE((COMP_INIT
|COMP_RF
|COMP_POWER
), "%s(): RF-ON\n",
900 priv
->rtllib
->eRFPowerState
= eRfOn
;
901 priv
->rtllib
->RfOffReason
= 0;
904 if (priv
->rtllib
->FwRWRF
)
905 priv
->Rf_Mode
= RF_OP_By_FW
;
907 priv
->Rf_Mode
= RF_OP_By_SW_3wire
;
909 if (priv
->ResetProgress
== RESET_TYPE_NORESET
) {
910 dm_initialize_txpower_tracking(dev
);
912 if (priv
->IC_Cut
>= IC_VersionCut_D
) {
913 tmpRegA
= rtl92e_get_bb_reg(dev
, rOFDM0_XATxIQImbalance
,
915 tmpRegC
= rtl92e_get_bb_reg(dev
, rOFDM0_XCTxIQImbalance
,
917 for (i
= 0; i
< TxBBGainTableLength
; i
++) {
918 if (tmpRegA
== dm_tx_bb_gain
[i
]) {
919 priv
->rfa_txpowertrackingindex
= (u8
)i
;
920 priv
->rfa_txpowertrackingindex_real
=
922 priv
->rfa_txpowertracking_default
=
923 priv
->rfa_txpowertrackingindex
;
928 TempCCk
= rtl92e_get_bb_reg(dev
, rCCK0_TxFilter1
,
931 for (i
= 0; i
< CCKTxBBGainTableLength
; i
++) {
932 if (TempCCk
== dm_cck_tx_bb_gain
[i
][0]) {
933 priv
->CCKPresentAttentuation_20Mdefault
= (u8
)i
;
937 priv
->CCKPresentAttentuation_40Mdefault
= 0;
938 priv
->CCKPresentAttentuation_difference
= 0;
939 priv
->CCKPresentAttentuation
=
940 priv
->CCKPresentAttentuation_20Mdefault
;
941 RT_TRACE(COMP_POWER_TRACKING
,
942 "priv->rfa_txpowertrackingindex_initial = %d\n",
943 priv
->rfa_txpowertrackingindex
);
944 RT_TRACE(COMP_POWER_TRACKING
,
945 "priv->rfa_txpowertrackingindex_real__initial = %d\n",
946 priv
->rfa_txpowertrackingindex_real
);
947 RT_TRACE(COMP_POWER_TRACKING
,
948 "priv->CCKPresentAttentuation_difference_initial = %d\n",
949 priv
->CCKPresentAttentuation_difference
);
950 RT_TRACE(COMP_POWER_TRACKING
,
951 "priv->CCKPresentAttentuation_initial = %d\n",
952 priv
->CCKPresentAttentuation
);
953 priv
->btxpower_tracking
= false;
956 rtl92e_irq_enable(dev
);
958 priv
->being_init_adapter
= false;
962 static void rtl8192_net_update(struct net_device
*dev
)
965 struct r8192_priv
*priv
= rtllib_priv(dev
);
966 struct rtllib_network
*net
;
967 u16 BcnTimeCfg
= 0, BcnCW
= 6, BcnIFS
= 0xf;
970 net
= &priv
->rtllib
->current_network
;
971 rtl92e_config_rate(dev
, &rate_config
);
972 priv
->dot11CurrentPreambleMode
= PREAMBLE_AUTO
;
973 priv
->basic_rate
= rate_config
&= 0x15f;
974 write_nic_dword(dev
, BSSIDR
, ((u32
*)net
->bssid
)[0]);
975 write_nic_word(dev
, BSSIDR
+4, ((u16
*)net
->bssid
)[2]);
977 if (priv
->rtllib
->iw_mode
== IW_MODE_ADHOC
) {
978 write_nic_word(dev
, ATIMWND
, 2);
979 write_nic_word(dev
, BCN_DMATIME
, 256);
980 write_nic_word(dev
, BCN_INTERVAL
, net
->beacon_interval
);
981 write_nic_word(dev
, BCN_DRV_EARLY_INT
, 10);
982 write_nic_byte(dev
, BCN_ERR_THRESH
, 100);
984 BcnTimeCfg
|= (BcnCW
<<BCN_TCFG_CW_SHIFT
);
985 BcnTimeCfg
|= BcnIFS
<<BCN_TCFG_IFS
;
987 write_nic_word(dev
, BCN_TCFG
, BcnTimeCfg
);
991 void rtl92e_link_change(struct net_device
*dev
)
993 struct r8192_priv
*priv
= rtllib_priv(dev
);
994 struct rtllib_device
*ieee
= priv
->rtllib
;
999 if (ieee
->state
== RTLLIB_LINKED
) {
1000 rtl8192_net_update(dev
);
1001 priv
->ops
->update_ratr_table(dev
);
1002 if ((KEY_TYPE_WEP40
== ieee
->pairwise_key_type
) ||
1003 (KEY_TYPE_WEP104
== ieee
->pairwise_key_type
))
1004 rtl92e_enable_hw_security_config(dev
);
1006 write_nic_byte(dev
, 0x173, 0);
1008 rtl8192e_update_msr(dev
);
1010 if (ieee
->iw_mode
== IW_MODE_INFRA
|| ieee
->iw_mode
== IW_MODE_ADHOC
) {
1013 reg
= rtl92e_readl(dev
, RCR
);
1014 if (priv
->rtllib
->state
== RTLLIB_LINKED
) {
1015 if (ieee
->IntelPromiscuousModeInfo
.bPromiscuousOn
)
1018 priv
->ReceiveConfig
= reg
|= RCR_CBSSID
;
1020 priv
->ReceiveConfig
= reg
&= ~RCR_CBSSID
;
1022 write_nic_dword(dev
, RCR
, reg
);
1026 void rtl92e_set_monitor_mode(struct net_device
*dev
, bool bAllowAllDA
,
1029 struct r8192_priv
*priv
= rtllib_priv(dev
);
1032 priv
->ReceiveConfig
|= RCR_AAP
;
1034 priv
->ReceiveConfig
&= ~RCR_AAP
;
1037 write_nic_dword(dev
, RCR
, priv
->ReceiveConfig
);
1040 static u8
MRateToHwRate8190Pci(u8 rate
)
1042 u8 ret
= DESC90_RATE1M
;
1046 ret
= DESC90_RATE1M
;
1049 ret
= DESC90_RATE2M
;
1052 ret
= DESC90_RATE5_5M
;
1055 ret
= DESC90_RATE11M
;
1058 ret
= DESC90_RATE6M
;
1061 ret
= DESC90_RATE9M
;
1064 ret
= DESC90_RATE12M
;
1067 ret
= DESC90_RATE18M
;
1070 ret
= DESC90_RATE24M
;
1073 ret
= DESC90_RATE36M
;
1076 ret
= DESC90_RATE48M
;
1079 ret
= DESC90_RATE54M
;
1082 ret
= DESC90_RATEMCS0
;
1085 ret
= DESC90_RATEMCS1
;
1088 ret
= DESC90_RATEMCS2
;
1091 ret
= DESC90_RATEMCS3
;
1094 ret
= DESC90_RATEMCS4
;
1097 ret
= DESC90_RATEMCS5
;
1100 ret
= DESC90_RATEMCS6
;
1103 ret
= DESC90_RATEMCS7
;
1106 ret
= DESC90_RATEMCS8
;
1109 ret
= DESC90_RATEMCS9
;
1112 ret
= DESC90_RATEMCS10
;
1115 ret
= DESC90_RATEMCS11
;
1118 ret
= DESC90_RATEMCS12
;
1121 ret
= DESC90_RATEMCS13
;
1124 ret
= DESC90_RATEMCS14
;
1127 ret
= DESC90_RATEMCS15
;
1130 ret
= DESC90_RATEMCS32
;
1138 static u8
rtl8192_MapHwQueueToFirmwareQueue(struct net_device
*dev
, u8 QueueID
,
1141 u8 QueueSelect
= 0x0;
1145 QueueSelect
= QSLT_BE
;
1149 QueueSelect
= QSLT_BK
;
1153 QueueSelect
= QSLT_VO
;
1157 QueueSelect
= QSLT_VI
;
1160 QueueSelect
= QSLT_MGNT
;
1163 QueueSelect
= QSLT_BEACON
;
1166 QueueSelect
= QSLT_CMD
;
1169 QueueSelect
= QSLT_HIGH
;
1172 netdev_warn(dev
, "%s(): Impossible Queue Selection: %d\n",
1179 static u8
rtl8192_QueryIsShort(u8 TxHT
, u8 TxRate
, struct cb_desc
*tcb_desc
)
1183 tmp_Short
= (TxHT
== 1) ? ((tcb_desc
->bUseShortGI
) ? 1 : 0) :
1184 ((tcb_desc
->bUseShortPreamble
) ? 1 : 0);
1185 if (TxHT
== 1 && TxRate
!= DESC90_RATEMCS15
)
1191 void rtl92e_fill_tx_desc(struct net_device
*dev
, struct tx_desc
*pdesc
,
1192 struct cb_desc
*cb_desc
, struct sk_buff
*skb
)
1194 struct r8192_priv
*priv
= rtllib_priv(dev
);
1195 dma_addr_t mapping
= pci_map_single(priv
->pdev
, skb
->data
, skb
->len
,
1197 struct tx_fwinfo_8190pci
*pTxFwInfo
= NULL
;
1199 pTxFwInfo
= (struct tx_fwinfo_8190pci
*)skb
->data
;
1200 memset(pTxFwInfo
, 0, sizeof(struct tx_fwinfo_8190pci
));
1201 pTxFwInfo
->TxHT
= (cb_desc
->data_rate
& 0x80) ? 1 : 0;
1202 pTxFwInfo
->TxRate
= MRateToHwRate8190Pci((u8
)cb_desc
->data_rate
);
1203 pTxFwInfo
->EnableCPUDur
= cb_desc
->bTxEnableFwCalcDur
;
1204 pTxFwInfo
->Short
= rtl8192_QueryIsShort(pTxFwInfo
->TxHT
,
1208 if (pci_dma_mapping_error(priv
->pdev
, mapping
))
1209 netdev_err(dev
, "%s(): DMA Mapping error\n", __func__
);
1210 if (cb_desc
->bAMPDUEnable
) {
1211 pTxFwInfo
->AllowAggregation
= 1;
1212 pTxFwInfo
->RxMF
= cb_desc
->ampdu_factor
;
1213 pTxFwInfo
->RxAMD
= cb_desc
->ampdu_density
;
1215 pTxFwInfo
->AllowAggregation
= 0;
1216 pTxFwInfo
->RxMF
= 0;
1217 pTxFwInfo
->RxAMD
= 0;
1220 pTxFwInfo
->RtsEnable
= (cb_desc
->bRTSEnable
) ? 1 : 0;
1221 pTxFwInfo
->CtsEnable
= (cb_desc
->bCTSEnable
) ? 1 : 0;
1222 pTxFwInfo
->RtsSTBC
= (cb_desc
->bRTSSTBC
) ? 1 : 0;
1223 pTxFwInfo
->RtsHT
= (cb_desc
->rts_rate
&0x80) ? 1 : 0;
1224 pTxFwInfo
->RtsRate
= MRateToHwRate8190Pci((u8
)cb_desc
->rts_rate
);
1225 pTxFwInfo
->RtsBandwidth
= 0;
1226 pTxFwInfo
->RtsSubcarrier
= cb_desc
->RTSSC
;
1227 pTxFwInfo
->RtsShort
= (pTxFwInfo
->RtsHT
== 0) ?
1228 (cb_desc
->bRTSUseShortPreamble
? 1 : 0) :
1229 (cb_desc
->bRTSUseShortGI
? 1 : 0);
1230 if (priv
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20_40
) {
1231 if (cb_desc
->bPacketBW
) {
1232 pTxFwInfo
->TxBandwidth
= 1;
1233 pTxFwInfo
->TxSubCarrier
= 0;
1235 pTxFwInfo
->TxBandwidth
= 0;
1236 pTxFwInfo
->TxSubCarrier
= priv
->nCur40MhzPrimeSC
;
1239 pTxFwInfo
->TxBandwidth
= 0;
1240 pTxFwInfo
->TxSubCarrier
= 0;
1243 memset((u8
*)pdesc
, 0, 12);
1246 pdesc
->Offset
= sizeof(struct tx_fwinfo_8190pci
) + 8;
1247 pdesc
->PktSize
= (u16
)skb
->len
-sizeof(struct tx_fwinfo_8190pci
);
1249 pdesc
->SecCAMID
= 0;
1250 pdesc
->RATid
= cb_desc
->RATRIndex
;
1254 pdesc
->SecType
= 0x0;
1255 if (cb_desc
->bHwSec
) {
1259 RT_TRACE(COMP_DBG
, "==>================hw sec\n");
1262 switch (priv
->rtllib
->pairwise_key_type
) {
1263 case KEY_TYPE_WEP40
:
1264 case KEY_TYPE_WEP104
:
1265 pdesc
->SecType
= 0x1;
1269 pdesc
->SecType
= 0x2;
1273 pdesc
->SecType
= 0x3;
1277 pdesc
->SecType
= 0x0;
1285 pdesc
->QueueSelect
= rtl8192_MapHwQueueToFirmwareQueue(dev
,
1286 cb_desc
->queue_index
,
1288 pdesc
->TxFWInfoSize
= sizeof(struct tx_fwinfo_8190pci
);
1290 pdesc
->DISFB
= cb_desc
->bTxDisableRateFallBack
;
1291 pdesc
->USERATE
= cb_desc
->bTxUseDriverAssingedRate
;
1293 pdesc
->FirstSeg
= 1;
1295 pdesc
->TxBufferSize
= skb
->len
;
1297 pdesc
->TxBuffAddr
= mapping
;
1300 void rtl92e_fill_tx_cmd_desc(struct net_device
*dev
, struct tx_desc_cmd
*entry
,
1301 struct cb_desc
*cb_desc
, struct sk_buff
*skb
)
1303 struct r8192_priv
*priv
= rtllib_priv(dev
);
1304 dma_addr_t mapping
= pci_map_single(priv
->pdev
, skb
->data
, skb
->len
,
1307 if (pci_dma_mapping_error(priv
->pdev
, mapping
))
1308 netdev_err(dev
, "%s(): DMA Mapping error\n", __func__
);
1309 memset(entry
, 0, 12);
1310 entry
->LINIP
= cb_desc
->bLastIniPkt
;
1311 entry
->FirstSeg
= 1;
1313 if (cb_desc
->bCmdOrInit
== DESC_PACKET_TYPE_INIT
) {
1314 entry
->CmdInit
= DESC_PACKET_TYPE_INIT
;
1316 struct tx_desc
*entry_tmp
= (struct tx_desc
*)entry
;
1318 entry_tmp
->CmdInit
= DESC_PACKET_TYPE_NORMAL
;
1319 entry_tmp
->Offset
= sizeof(struct tx_fwinfo_8190pci
) + 8;
1320 entry_tmp
->PktSize
= (u16
)(cb_desc
->pkt_size
+
1322 entry_tmp
->QueueSelect
= QSLT_CMD
;
1323 entry_tmp
->TxFWInfoSize
= 0x08;
1324 entry_tmp
->RATid
= (u8
)DESC_PACKET_TYPE_INIT
;
1326 entry
->TxBufferSize
= skb
->len
;
1327 entry
->TxBuffAddr
= mapping
;
1331 static u8
HwRateToMRate90(bool bIsHT
, u8 rate
)
1343 case DESC90_RATE5_5M
:
1344 ret_rate
= MGN_5_5M
;
1346 case DESC90_RATE11M
:
1355 case DESC90_RATE12M
:
1358 case DESC90_RATE18M
:
1361 case DESC90_RATE24M
:
1364 case DESC90_RATE36M
:
1367 case DESC90_RATE48M
:
1370 case DESC90_RATE54M
:
1376 "HwRateToMRate90(): Non supportedRate [%x], bIsHT = %d!!!\n",
1383 case DESC90_RATEMCS0
:
1384 ret_rate
= MGN_MCS0
;
1386 case DESC90_RATEMCS1
:
1387 ret_rate
= MGN_MCS1
;
1389 case DESC90_RATEMCS2
:
1390 ret_rate
= MGN_MCS2
;
1392 case DESC90_RATEMCS3
:
1393 ret_rate
= MGN_MCS3
;
1395 case DESC90_RATEMCS4
:
1396 ret_rate
= MGN_MCS4
;
1398 case DESC90_RATEMCS5
:
1399 ret_rate
= MGN_MCS5
;
1401 case DESC90_RATEMCS6
:
1402 ret_rate
= MGN_MCS6
;
1404 case DESC90_RATEMCS7
:
1405 ret_rate
= MGN_MCS7
;
1407 case DESC90_RATEMCS8
:
1408 ret_rate
= MGN_MCS8
;
1410 case DESC90_RATEMCS9
:
1411 ret_rate
= MGN_MCS9
;
1413 case DESC90_RATEMCS10
:
1414 ret_rate
= MGN_MCS10
;
1416 case DESC90_RATEMCS11
:
1417 ret_rate
= MGN_MCS11
;
1419 case DESC90_RATEMCS12
:
1420 ret_rate
= MGN_MCS12
;
1422 case DESC90_RATEMCS13
:
1423 ret_rate
= MGN_MCS13
;
1425 case DESC90_RATEMCS14
:
1426 ret_rate
= MGN_MCS14
;
1428 case DESC90_RATEMCS15
:
1429 ret_rate
= MGN_MCS15
;
1431 case DESC90_RATEMCS32
:
1432 ret_rate
= (0x80|0x20);
1437 "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",
1446 static long rtl8192_signal_scale_mapping(struct r8192_priv
*priv
, long currsig
)
1450 if (currsig
>= 61 && currsig
<= 100)
1451 retsig
= 90 + ((currsig
- 60) / 4);
1452 else if (currsig
>= 41 && currsig
<= 60)
1453 retsig
= 78 + ((currsig
- 40) / 2);
1454 else if (currsig
>= 31 && currsig
<= 40)
1455 retsig
= 66 + (currsig
- 30);
1456 else if (currsig
>= 21 && currsig
<= 30)
1457 retsig
= 54 + (currsig
- 20);
1458 else if (currsig
>= 5 && currsig
<= 20)
1459 retsig
= 42 + (((currsig
- 5) * 2) / 3);
1460 else if (currsig
== 4)
1462 else if (currsig
== 3)
1464 else if (currsig
== 2)
1466 else if (currsig
== 1)
1475 #define rx_hal_is_cck_rate(_pdrvinfo)\
1476 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1477 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1478 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1479 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1482 static void rtl8192_query_rxphystatus(
1483 struct r8192_priv
*priv
,
1484 struct rtllib_rx_stats
*pstats
,
1485 struct rx_desc
*pdesc
,
1486 struct rx_fwinfo
*pdrvinfo
,
1487 struct rtllib_rx_stats
*precord_stats
,
1488 bool bpacket_match_bssid
,
1489 bool bpacket_toself
,
1494 struct phy_sts_ofdm_819xpci
*pofdm_buf
;
1495 struct phy_sts_cck_819xpci
*pcck_buf
;
1496 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag
*prxsc
;
1498 u8 i
, max_spatial_stream
, tmp_rxsnr
, tmp_rxevm
, rxsc_sgien_exflg
;
1499 char rx_pwr
[4], rx_pwr_all
= 0;
1500 char rx_snrX
, rx_evmX
;
1502 u32 RSSI
, total_rssi
= 0;
1505 static u8 check_reg824
;
1506 static u32 reg824_bit9
;
1508 priv
->stats
.numqry_phystatus
++;
1510 is_cck_rate
= rx_hal_is_cck_rate(pdrvinfo
);
1511 memset(precord_stats
, 0, sizeof(struct rtllib_rx_stats
));
1512 pstats
->bPacketMatchBSSID
= precord_stats
->bPacketMatchBSSID
=
1513 bpacket_match_bssid
;
1514 pstats
->bPacketToSelf
= precord_stats
->bPacketToSelf
= bpacket_toself
;
1515 pstats
->bIsCCK
= precord_stats
->bIsCCK
= is_cck_rate
;
1516 pstats
->bPacketBeacon
= precord_stats
->bPacketBeacon
= bPacketBeacon
;
1517 pstats
->bToSelfBA
= precord_stats
->bToSelfBA
= bToSelfBA
;
1518 if (check_reg824
== 0) {
1519 reg824_bit9
= rtl92e_get_bb_reg(priv
->rtllib
->dev
,
1520 rFPGA0_XA_HSSIParameter2
,
1526 prxpkt
= (u8
*)pdrvinfo
;
1528 prxpkt
+= sizeof(struct rx_fwinfo
);
1530 pcck_buf
= (struct phy_sts_cck_819xpci
*)prxpkt
;
1531 pofdm_buf
= (struct phy_sts_ofdm_819xpci
*)prxpkt
;
1533 pstats
->RxMIMOSignalQuality
[0] = -1;
1534 pstats
->RxMIMOSignalQuality
[1] = -1;
1535 precord_stats
->RxMIMOSignalQuality
[0] = -1;
1536 precord_stats
->RxMIMOSignalQuality
[1] = -1;
1541 priv
->stats
.numqry_phystatusCCK
++;
1543 report
= pcck_buf
->cck_agc_rpt
& 0xc0;
1547 rx_pwr_all
= -35 - (pcck_buf
->cck_agc_rpt
&
1551 rx_pwr_all
= -23 - (pcck_buf
->cck_agc_rpt
&
1555 rx_pwr_all
= -11 - (pcck_buf
->cck_agc_rpt
&
1559 rx_pwr_all
= 8 - (pcck_buf
->cck_agc_rpt
& 0x3e);
1563 report
= pcck_buf
->cck_agc_rpt
& 0x60;
1568 ((pcck_buf
->cck_agc_rpt
&
1573 ((pcck_buf
->cck_agc_rpt
&
1578 ((pcck_buf
->cck_agc_rpt
&
1583 ((pcck_buf
->cck_agc_rpt
&
1589 pwdb_all
= rtl819x_query_rxpwrpercentage(rx_pwr_all
);
1590 pstats
->RxPWDBAll
= precord_stats
->RxPWDBAll
= pwdb_all
;
1591 pstats
->RecvSignalPower
= rx_pwr_all
;
1593 if (bpacket_match_bssid
) {
1596 if (pstats
->RxPWDBAll
> 40) {
1599 sq
= pcck_buf
->sq_rpt
;
1601 if (pcck_buf
->sq_rpt
> 64)
1603 else if (pcck_buf
->sq_rpt
< 20)
1606 sq
= ((64-sq
) * 100) / 44;
1608 pstats
->SignalQuality
= sq
;
1609 precord_stats
->SignalQuality
= sq
;
1610 pstats
->RxMIMOSignalQuality
[0] = sq
;
1611 precord_stats
->RxMIMOSignalQuality
[0] = sq
;
1612 pstats
->RxMIMOSignalQuality
[1] = -1;
1613 precord_stats
->RxMIMOSignalQuality
[1] = -1;
1616 priv
->stats
.numqry_phystatusHT
++;
1617 for (i
= RF90_PATH_A
; i
< RF90_PATH_MAX
; i
++) {
1618 if (priv
->brfpath_rxenable
[i
])
1621 rx_pwr
[i
] = ((pofdm_buf
->trsw_gain_X
[i
] & 0x3F) *
1624 tmp_rxsnr
= pofdm_buf
->rxsnr_X
[i
];
1625 rx_snrX
= (char)(tmp_rxsnr
);
1627 priv
->stats
.rxSNRdB
[i
] = (long)rx_snrX
;
1629 RSSI
= rtl819x_query_rxpwrpercentage(rx_pwr
[i
]);
1630 if (priv
->brfpath_rxenable
[i
])
1633 if (bpacket_match_bssid
) {
1634 pstats
->RxMIMOSignalStrength
[i
] = (u8
) RSSI
;
1635 precord_stats
->RxMIMOSignalStrength
[i
] =
1641 rx_pwr_all
= (((pofdm_buf
->pwdb_all
) >> 1) & 0x7f) - 106;
1642 pwdb_all
= rtl819x_query_rxpwrpercentage(rx_pwr_all
);
1644 pstats
->RxPWDBAll
= precord_stats
->RxPWDBAll
= pwdb_all
;
1645 pstats
->RxPower
= precord_stats
->RxPower
= rx_pwr_all
;
1646 pstats
->RecvSignalPower
= rx_pwr_all
;
1647 if (pdrvinfo
->RxHT
&& pdrvinfo
->RxRate
>= DESC90_RATEMCS8
&&
1648 pdrvinfo
->RxRate
<= DESC90_RATEMCS15
)
1649 max_spatial_stream
= 2;
1651 max_spatial_stream
= 1;
1653 for (i
= 0; i
< max_spatial_stream
; i
++) {
1654 tmp_rxevm
= pofdm_buf
->rxevm_X
[i
];
1655 rx_evmX
= (char)(tmp_rxevm
);
1659 evm
= rtl92e_evm_db_to_percent(rx_evmX
);
1660 if (bpacket_match_bssid
) {
1662 pstats
->SignalQuality
= (u8
)(evm
&
1664 precord_stats
->SignalQuality
= (u8
)(evm
1667 pstats
->RxMIMOSignalQuality
[i
] = (u8
)(evm
&
1669 precord_stats
->RxMIMOSignalQuality
[i
] = (u8
)(evm
1675 rxsc_sgien_exflg
= pofdm_buf
->rxsc_sgien_exflg
;
1676 prxsc
= (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag
*)
1679 priv
->stats
.received_bwtype
[1+prxsc
->rxsc
]++;
1681 priv
->stats
.received_bwtype
[0]++;
1685 pstats
->SignalStrength
= precord_stats
->SignalStrength
=
1686 (u8
)(rtl8192_signal_scale_mapping(priv
,
1691 pstats
->SignalStrength
= precord_stats
->SignalStrength
=
1692 (u8
)(rtl8192_signal_scale_mapping(priv
,
1693 (long)(total_rssi
/= rf_rx_num
)));
1697 static void rtl8192_process_phyinfo(struct r8192_priv
*priv
, u8
*buffer
,
1698 struct rtllib_rx_stats
*prev_st
,
1699 struct rtllib_rx_stats
*curr_st
)
1701 bool bcheck
= false;
1704 static u32 slide_rssi_index
, slide_rssi_statistics
;
1705 static u32 slide_evm_index
, slide_evm_statistics
;
1706 static u32 last_rssi
, last_evm
;
1707 static u32 slide_beacon_adc_pwdb_index
;
1708 static u32 slide_beacon_adc_pwdb_statistics
;
1709 static u32 last_beacon_adc_pwdb
;
1710 struct rtllib_hdr_3addr
*hdr
;
1712 unsigned int frag
, seq
;
1714 hdr
= (struct rtllib_hdr_3addr
*)buffer
;
1715 sc
= le16_to_cpu(hdr
->seq_ctl
);
1716 frag
= WLAN_GET_SEQ_FRAG(sc
);
1717 seq
= WLAN_GET_SEQ_SEQ(sc
);
1718 curr_st
->Seq_Num
= seq
;
1719 if (!prev_st
->bIsAMPDU
)
1722 if (slide_rssi_statistics
++ >= PHY_RSSI_SLID_WIN_MAX
) {
1723 slide_rssi_statistics
= PHY_RSSI_SLID_WIN_MAX
;
1724 last_rssi
= priv
->stats
.slide_signal_strength
[slide_rssi_index
];
1725 priv
->stats
.slide_rssi_total
-= last_rssi
;
1727 priv
->stats
.slide_rssi_total
+= prev_st
->SignalStrength
;
1729 priv
->stats
.slide_signal_strength
[slide_rssi_index
++] =
1730 prev_st
->SignalStrength
;
1731 if (slide_rssi_index
>= PHY_RSSI_SLID_WIN_MAX
)
1732 slide_rssi_index
= 0;
1734 tmp_val
= priv
->stats
.slide_rssi_total
/slide_rssi_statistics
;
1735 priv
->stats
.signal_strength
= rtl819x_translate_todbm(priv
,
1737 curr_st
->rssi
= priv
->stats
.signal_strength
;
1738 if (!prev_st
->bPacketMatchBSSID
) {
1739 if (!prev_st
->bToSelfBA
)
1746 priv
->stats
.num_process_phyinfo
++;
1747 if (!prev_st
->bIsCCK
&& prev_st
->bPacketToSelf
) {
1748 for (rfpath
= RF90_PATH_A
; rfpath
< RF90_PATH_C
; rfpath
++) {
1749 if (!rtl92e_is_legal_rf_path(priv
->rtllib
->dev
, rfpath
))
1752 "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n",
1753 prev_st
->RxMIMOSignalStrength
[rfpath
]);
1754 if (priv
->stats
.rx_rssi_percentage
[rfpath
] == 0) {
1755 priv
->stats
.rx_rssi_percentage
[rfpath
] =
1756 prev_st
->RxMIMOSignalStrength
[rfpath
];
1758 if (prev_st
->RxMIMOSignalStrength
[rfpath
] >
1759 priv
->stats
.rx_rssi_percentage
[rfpath
]) {
1760 priv
->stats
.rx_rssi_percentage
[rfpath
] =
1761 ((priv
->stats
.rx_rssi_percentage
[rfpath
]
1762 * (RX_SMOOTH
- 1)) +
1763 (prev_st
->RxMIMOSignalStrength
1764 [rfpath
])) / (RX_SMOOTH
);
1765 priv
->stats
.rx_rssi_percentage
[rfpath
] =
1766 priv
->stats
.rx_rssi_percentage
[rfpath
]
1769 priv
->stats
.rx_rssi_percentage
[rfpath
] =
1770 ((priv
->stats
.rx_rssi_percentage
[rfpath
] *
1772 (prev_st
->RxMIMOSignalStrength
[rfpath
])) /
1776 "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath] = %d\n",
1777 priv
->stats
.rx_rssi_percentage
[rfpath
]);
1782 if (prev_st
->bPacketBeacon
) {
1783 if (slide_beacon_adc_pwdb_statistics
++ >=
1784 PHY_Beacon_RSSI_SLID_WIN_MAX
) {
1785 slide_beacon_adc_pwdb_statistics
=
1786 PHY_Beacon_RSSI_SLID_WIN_MAX
;
1787 last_beacon_adc_pwdb
= priv
->stats
.Slide_Beacon_pwdb
1788 [slide_beacon_adc_pwdb_index
];
1789 priv
->stats
.Slide_Beacon_Total
-= last_beacon_adc_pwdb
;
1791 priv
->stats
.Slide_Beacon_Total
+= prev_st
->RxPWDBAll
;
1792 priv
->stats
.Slide_Beacon_pwdb
[slide_beacon_adc_pwdb_index
] =
1794 slide_beacon_adc_pwdb_index
++;
1795 if (slide_beacon_adc_pwdb_index
>= PHY_Beacon_RSSI_SLID_WIN_MAX
)
1796 slide_beacon_adc_pwdb_index
= 0;
1797 prev_st
->RxPWDBAll
= priv
->stats
.Slide_Beacon_Total
/
1798 slide_beacon_adc_pwdb_statistics
;
1799 if (prev_st
->RxPWDBAll
>= 3)
1800 prev_st
->RxPWDBAll
-= 3;
1803 RT_TRACE(COMP_RXDESC
, "Smooth %s PWDB = %d\n",
1804 prev_st
->bIsCCK
? "CCK" : "OFDM",
1805 prev_st
->RxPWDBAll
);
1807 if (prev_st
->bPacketToSelf
|| prev_st
->bPacketBeacon
||
1808 prev_st
->bToSelfBA
) {
1809 if (priv
->undecorated_smoothed_pwdb
< 0)
1810 priv
->undecorated_smoothed_pwdb
= prev_st
->RxPWDBAll
;
1811 if (prev_st
->RxPWDBAll
> (u32
)priv
->undecorated_smoothed_pwdb
) {
1812 priv
->undecorated_smoothed_pwdb
=
1813 (((priv
->undecorated_smoothed_pwdb
) *
1815 (prev_st
->RxPWDBAll
)) / (RX_SMOOTH
);
1816 priv
->undecorated_smoothed_pwdb
=
1817 priv
->undecorated_smoothed_pwdb
+ 1;
1819 priv
->undecorated_smoothed_pwdb
=
1820 (((priv
->undecorated_smoothed_pwdb
) *
1822 (prev_st
->RxPWDBAll
)) / (RX_SMOOTH
);
1824 rtl819x_update_rxsignalstatistics8190pci(priv
, prev_st
);
1827 if (prev_st
->SignalQuality
!= 0) {
1828 if (prev_st
->bPacketToSelf
|| prev_st
->bPacketBeacon
||
1829 prev_st
->bToSelfBA
) {
1830 if (slide_evm_statistics
++ >= PHY_RSSI_SLID_WIN_MAX
) {
1831 slide_evm_statistics
= PHY_RSSI_SLID_WIN_MAX
;
1833 priv
->stats
.slide_evm
[slide_evm_index
];
1834 priv
->stats
.slide_evm_total
-= last_evm
;
1837 priv
->stats
.slide_evm_total
+= prev_st
->SignalQuality
;
1839 priv
->stats
.slide_evm
[slide_evm_index
++] =
1840 prev_st
->SignalQuality
;
1841 if (slide_evm_index
>= PHY_RSSI_SLID_WIN_MAX
)
1842 slide_evm_index
= 0;
1844 tmp_val
= priv
->stats
.slide_evm_total
/
1845 slide_evm_statistics
;
1846 priv
->stats
.signal_quality
= tmp_val
;
1847 priv
->stats
.last_signal_strength_inpercent
= tmp_val
;
1850 if (prev_st
->bPacketToSelf
||
1851 prev_st
->bPacketBeacon
||
1852 prev_st
->bToSelfBA
) {
1853 for (ij
= 0; ij
< 2; ij
++) {
1854 if (prev_st
->RxMIMOSignalQuality
[ij
] != -1) {
1855 if (priv
->stats
.rx_evm_percentage
[ij
] == 0)
1856 priv
->stats
.rx_evm_percentage
[ij
] =
1857 prev_st
->RxMIMOSignalQuality
[ij
];
1858 priv
->stats
.rx_evm_percentage
[ij
] =
1859 ((priv
->stats
.rx_evm_percentage
[ij
] *
1861 (prev_st
->RxMIMOSignalQuality
[ij
])) /
1869 static void rtl8192_TranslateRxSignalStuff(struct net_device
*dev
,
1870 struct sk_buff
*skb
,
1871 struct rtllib_rx_stats
*pstats
,
1872 struct rx_desc
*pdesc
,
1873 struct rx_fwinfo
*pdrvinfo
)
1875 struct r8192_priv
*priv
= (struct r8192_priv
*)rtllib_priv(dev
);
1876 bool bpacket_match_bssid
, bpacket_toself
;
1877 bool bPacketBeacon
= false;
1878 struct rtllib_hdr_3addr
*hdr
;
1879 bool bToSelfBA
= false;
1880 static struct rtllib_rx_stats previous_stats
;
1885 tmp_buf
= skb
->data
+ pstats
->RxDrvInfoSize
+ pstats
->RxBufShift
;
1887 hdr
= (struct rtllib_hdr_3addr
*)tmp_buf
;
1888 fc
= le16_to_cpu(hdr
->frame_ctl
);
1889 type
= WLAN_FC_GET_TYPE(fc
);
1890 praddr
= hdr
->addr1
;
1892 bpacket_match_bssid
=
1893 ((RTLLIB_FTYPE_CTL
!= type
) &&
1894 ether_addr_equal(priv
->rtllib
->current_network
.bssid
,
1895 (fc
& RTLLIB_FCTL_TODS
) ? hdr
->addr1
:
1896 (fc
& RTLLIB_FCTL_FROMDS
) ? hdr
->addr2
:
1898 (!pstats
->bHwError
) && (!pstats
->bCRC
) && (!pstats
->bICV
));
1899 bpacket_toself
= bpacket_match_bssid
&& /* check this */
1900 ether_addr_equal(praddr
, priv
->rtllib
->dev
->dev_addr
);
1901 if (WLAN_FC_GET_FRAMETYPE(fc
) == RTLLIB_STYPE_BEACON
)
1902 bPacketBeacon
= true;
1903 if (bpacket_match_bssid
)
1904 priv
->stats
.numpacket_matchbssid
++;
1906 priv
->stats
.numpacket_toself
++;
1907 rtl8192_process_phyinfo(priv
, tmp_buf
, &previous_stats
, pstats
);
1908 rtl8192_query_rxphystatus(priv
, pstats
, pdesc
, pdrvinfo
,
1909 &previous_stats
, bpacket_match_bssid
,
1910 bpacket_toself
, bPacketBeacon
, bToSelfBA
);
1911 rtl92e_copy_mpdu_stats(pstats
, &previous_stats
);
1914 static void rtl8192_UpdateReceivedRateHistogramStatistics(
1915 struct net_device
*dev
,
1916 struct rtllib_rx_stats
*pstats
)
1918 struct r8192_priv
*priv
= (struct r8192_priv
*)rtllib_priv(dev
);
1921 u32 preamble_guardinterval
;
1925 else if (pstats
->bICV
)
1928 if (pstats
->bShortPreamble
)
1929 preamble_guardinterval
= 1;
1931 preamble_guardinterval
= 0;
1933 switch (pstats
->rate
) {
2022 priv
->stats
.received_preamble_GI
[preamble_guardinterval
][rateIndex
]++;
2023 priv
->stats
.received_rate_histogram
[0][rateIndex
]++;
2024 priv
->stats
.received_rate_histogram
[rcvType
][rateIndex
]++;
2027 bool rtl92e_get_rx_stats(struct net_device
*dev
, struct rtllib_rx_stats
*stats
,
2028 struct rx_desc
*pdesc
, struct sk_buff
*skb
)
2030 struct r8192_priv
*priv
= rtllib_priv(dev
);
2031 struct rx_fwinfo
*pDrvInfo
= NULL
;
2033 stats
->bICV
= pdesc
->ICV
;
2034 stats
->bCRC
= pdesc
->CRC32
;
2035 stats
->bHwError
= pdesc
->CRC32
| pdesc
->ICV
;
2037 stats
->Length
= pdesc
->Length
;
2038 if (stats
->Length
< 24)
2039 stats
->bHwError
|= 1;
2041 if (stats
->bHwError
) {
2042 stats
->bShift
= false;
2045 if (pdesc
->Length
< 500)
2046 priv
->stats
.rxcrcerrmin
++;
2047 else if (pdesc
->Length
> 1000)
2048 priv
->stats
.rxcrcerrmax
++;
2050 priv
->stats
.rxcrcerrmid
++;
2055 stats
->RxDrvInfoSize
= pdesc
->RxDrvInfoSize
;
2056 stats
->RxBufShift
= ((pdesc
->Shift
)&0x03);
2057 stats
->Decrypted
= !pdesc
->SWDec
;
2059 pDrvInfo
= (struct rx_fwinfo
*)(skb
->data
+ stats
->RxBufShift
);
2061 stats
->rate
= HwRateToMRate90((bool)pDrvInfo
->RxHT
,
2062 (u8
)pDrvInfo
->RxRate
);
2063 stats
->bShortPreamble
= pDrvInfo
->SPLCP
;
2065 rtl8192_UpdateReceivedRateHistogramStatistics(dev
, stats
);
2067 stats
->bIsAMPDU
= (pDrvInfo
->PartAggr
== 1);
2068 stats
->bFirstMPDU
= (pDrvInfo
->PartAggr
== 1) &&
2069 (pDrvInfo
->FirstAGGR
== 1);
2071 stats
->TimeStampLow
= pDrvInfo
->TSFL
;
2072 stats
->TimeStampHigh
= rtl92e_readl(dev
, TSFR
+4);
2074 rtl819x_UpdateRxPktTimeStamp(dev
, stats
);
2076 if ((stats
->RxBufShift
+ stats
->RxDrvInfoSize
) > 0)
2079 stats
->RxIs40MHzPacket
= pDrvInfo
->BW
;
2081 rtl8192_TranslateRxSignalStuff(dev
, skb
, stats
, pdesc
,
2084 if (pDrvInfo
->FirstAGGR
== 1 || pDrvInfo
->PartAggr
== 1)
2085 RT_TRACE(COMP_RXDESC
,
2086 "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2087 pDrvInfo
->FirstAGGR
, pDrvInfo
->PartAggr
);
2088 skb_trim(skb
, skb
->len
- 4/*sCrcLng*/);
2091 stats
->packetlength
= stats
->Length
-4;
2092 stats
->fraglength
= stats
->packetlength
;
2093 stats
->fragoffset
= 0;
2094 stats
->ntotalfrag
= 1;
2098 void rtl92e_stop_adapter(struct net_device
*dev
, bool reset
)
2100 struct r8192_priv
*priv
= rtllib_priv(dev
);
2106 OpMode
= RT_OP_MODE_NO_LINK
;
2107 priv
->rtllib
->SetHwRegHandler(dev
, HW_VAR_MEDIA_STATUS
, &OpMode
);
2109 if (!priv
->rtllib
->bSupportRemoteWakeUp
) {
2111 write_nic_byte(dev
, CMDR
, u1bTmp
);
2119 priv
->bHwRfOffAction
= 2;
2121 if (!priv
->rtllib
->bSupportRemoteWakeUp
) {
2122 rtl92e_set_rf_off(dev
);
2123 ulRegRead
= rtl92e_readl(dev
, CPU_GEN
);
2124 ulRegRead
|= CPU_GEN_SYSTEM_RESET
;
2125 write_nic_dword(dev
, CPU_GEN
, ulRegRead
);
2127 write_nic_dword(dev
, WFCRC0
, 0xffffffff);
2128 write_nic_dword(dev
, WFCRC1
, 0xffffffff);
2129 write_nic_dword(dev
, WFCRC2
, 0xffffffff);
2132 write_nic_byte(dev
, PMR
, 0x5);
2133 write_nic_byte(dev
, MacBlkCtrl
, 0xa);
2137 for (i
= 0; i
< MAX_QUEUE_SIZE
; i
++)
2138 skb_queue_purge(&priv
->rtllib
->skb_waitQ
[i
]);
2139 for (i
= 0; i
< MAX_QUEUE_SIZE
; i
++)
2140 skb_queue_purge(&priv
->rtllib
->skb_aggQ
[i
]);
2142 skb_queue_purge(&priv
->skb_queue
);
2145 void rtl92e_update_ratr_table(struct net_device
*dev
)
2147 struct r8192_priv
*priv
= rtllib_priv(dev
);
2148 struct rtllib_device
*ieee
= priv
->rtllib
;
2149 u8
*pMcsRate
= ieee
->dot11HTOperationalRateSet
;
2151 u16 rate_config
= 0;
2154 rtl92e_config_rate(dev
, &rate_config
);
2155 ratr_value
= rate_config
| *pMcsRate
<< 12;
2156 switch (ieee
->mode
) {
2158 ratr_value
&= 0x00000FF0;
2161 ratr_value
&= 0x0000000F;
2165 ratr_value
&= 0x00000FF7;
2169 if (ieee
->pHTInfo
->PeerMimoPs
== 0) {
2170 ratr_value
&= 0x0007F007;
2172 if (priv
->rf_type
== RF_1T2R
)
2173 ratr_value
&= 0x000FF007;
2175 ratr_value
&= 0x0F81F007;
2181 ratr_value
&= 0x0FFFFFFF;
2182 if (ieee
->pHTInfo
->bCurTxBW40MHz
&&
2183 ieee
->pHTInfo
->bCurShortGI40MHz
)
2184 ratr_value
|= 0x80000000;
2185 else if (!ieee
->pHTInfo
->bCurTxBW40MHz
&&
2186 ieee
->pHTInfo
->bCurShortGI20MHz
)
2187 ratr_value
|= 0x80000000;
2188 write_nic_dword(dev
, RATR0
+rate_index
*4, ratr_value
);
2189 write_nic_byte(dev
, UFWP
, 1);
2193 rtl92e_init_variables(struct net_device
*dev
)
2195 struct r8192_priv
*priv
= rtllib_priv(dev
);
2197 strcpy(priv
->nick
, "rtl8192E");
2199 priv
->rtllib
->softmac_features
= IEEE_SOFTMAC_SCAN
|
2200 IEEE_SOFTMAC_ASSOCIATE
| IEEE_SOFTMAC_PROBERQ
|
2201 IEEE_SOFTMAC_PROBERS
| IEEE_SOFTMAC_TX_QUEUE
;
2203 priv
->rtllib
->tx_headroom
= sizeof(struct tx_fwinfo_8190pci
);
2205 priv
->ShortRetryLimit
= 0x30;
2206 priv
->LongRetryLimit
= 0x30;
2208 priv
->ReceiveConfig
= RCR_ADD3
|
2211 RCR_AB
| RCR_AM
| RCR_APM
|
2212 RCR_AAP
| ((u32
)7<<RCR_MXDMA_OFFSET
) |
2213 ((u32
)7 << RCR_FIFO_OFFSET
) | RCR_ONLYERLPKT
;
2215 priv
->irq_mask
[0] = (u32
)(IMR_ROK
| IMR_VODOK
| IMR_VIDOK
|
2216 IMR_BEDOK
| IMR_BKDOK
| IMR_HCCADOK
|
2217 IMR_MGNTDOK
| IMR_COMDOK
| IMR_HIGHDOK
|
2218 IMR_BDOK
| IMR_RXCMDOK
| IMR_TIMEOUT0
|
2219 IMR_RDU
| IMR_RXFOVW
| IMR_TXFOVW
|
2220 IMR_BcnInt
| IMR_TBDOK
| IMR_TBDER
);
2222 priv
->PwrDomainProtect
= false;
2224 priv
->bfirst_after_down
= false;
2227 void rtl92e_enable_irq(struct net_device
*dev
)
2229 struct r8192_priv
*priv
= (struct r8192_priv
*)rtllib_priv(dev
);
2231 priv
->irq_enabled
= 1;
2233 write_nic_dword(dev
, INTA_MASK
, priv
->irq_mask
[0]);
2237 void rtl92e_disable_irq(struct net_device
*dev
)
2239 struct r8192_priv
*priv
= (struct r8192_priv
*)rtllib_priv(dev
);
2241 write_nic_dword(dev
, INTA_MASK
, 0);
2243 priv
->irq_enabled
= 0;
2246 void rtl92e_clear_irq(struct net_device
*dev
)
2250 tmp
= rtl92e_readl(dev
, ISR
);
2251 write_nic_dword(dev
, ISR
, tmp
);
2255 void rtl92e_enable_rx(struct net_device
*dev
)
2257 struct r8192_priv
*priv
= (struct r8192_priv
*)rtllib_priv(dev
);
2259 write_nic_dword(dev
, RDQDA
, priv
->rx_ring_dma
[RX_MPDU_QUEUE
]);
2262 static const u32 TX_DESC_BASE
[] = {
2263 BKQDA
, BEQDA
, VIQDA
, VOQDA
, HCCAQDA
, CQDA
, MQDA
, HQDA
, BQDA
2266 void rtl92e_enable_tx(struct net_device
*dev
)
2268 struct r8192_priv
*priv
= (struct r8192_priv
*)rtllib_priv(dev
);
2271 for (i
= 0; i
< MAX_TX_QUEUE_COUNT
; i
++)
2272 write_nic_dword(dev
, TX_DESC_BASE
[i
], priv
->tx_ring
[i
].dma
);
2276 void rtl92e_ack_irq(struct net_device
*dev
, u32
*p_inta
, u32
*p_intb
)
2278 *p_inta
= rtl92e_readl(dev
, ISR
);
2279 write_nic_dword(dev
, ISR
, *p_inta
);
2282 bool rtl92e_is_rx_stuck(struct net_device
*dev
)
2284 struct r8192_priv
*priv
= rtllib_priv(dev
);
2285 u16 RegRxCounter
= rtl92e_readw(dev
, 0x130);
2286 bool bStuck
= false;
2287 static u8 rx_chk_cnt
;
2288 u32 SlotIndex
= 0, TotalRxStuckCount
= 0;
2290 u8 SilentResetRxSoltNum
= 4;
2292 RT_TRACE(COMP_RESET
, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2293 __func__
, RegRxCounter
, priv
->RxCounter
);
2296 if (priv
->undecorated_smoothed_pwdb
>= (RateAdaptiveTH_High
+5)) {
2298 } else if ((priv
->undecorated_smoothed_pwdb
< (RateAdaptiveTH_High
+ 5))
2299 && (((priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
) &&
2300 (priv
->undecorated_smoothed_pwdb
>= RateAdaptiveTH_Low_40M
))
2301 || ((priv
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
) &&
2302 (priv
->undecorated_smoothed_pwdb
>= RateAdaptiveTH_Low_20M
)))) {
2306 } else if ((((priv
->CurrentChannelBW
!= HT_CHANNEL_WIDTH_20
) &&
2307 (priv
->undecorated_smoothed_pwdb
< RateAdaptiveTH_Low_40M
)) ||
2308 ((priv
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
) &&
2309 (priv
->undecorated_smoothed_pwdb
< RateAdaptiveTH_Low_20M
))) &&
2310 priv
->undecorated_smoothed_pwdb
>= VeryLowRSSI
) {
2321 SlotIndex
= (priv
->SilentResetRxSlotIndex
++)%SilentResetRxSoltNum
;
2323 if (priv
->RxCounter
== RegRxCounter
) {
2324 priv
->SilentResetRxStuckEvent
[SlotIndex
] = 1;
2326 for (i
= 0; i
< SilentResetRxSoltNum
; i
++)
2327 TotalRxStuckCount
+= priv
->SilentResetRxStuckEvent
[i
];
2329 if (TotalRxStuckCount
== SilentResetRxSoltNum
) {
2331 for (i
= 0; i
< SilentResetRxSoltNum
; i
++)
2332 TotalRxStuckCount
+=
2333 priv
->SilentResetRxStuckEvent
[i
];
2338 priv
->SilentResetRxStuckEvent
[SlotIndex
] = 0;
2341 priv
->RxCounter
= RegRxCounter
;
2346 bool rtl92e_is_tx_stuck(struct net_device
*dev
)
2348 struct r8192_priv
*priv
= rtllib_priv(dev
);
2349 bool bStuck
= false;
2350 u16 RegTxCounter
= rtl92e_readw(dev
, 0x128);
2352 RT_TRACE(COMP_RESET
, "%s():RegTxCounter is %d,TxCounter is %d\n",
2353 __func__
, RegTxCounter
, priv
->TxCounter
);
2355 if (priv
->TxCounter
== RegTxCounter
)
2358 priv
->TxCounter
= RegTxCounter
;
2363 bool rtl92e_get_nmode_support_by_sec(struct net_device
*dev
)
2365 struct r8192_priv
*priv
= rtllib_priv(dev
);
2366 struct rtllib_device
*ieee
= priv
->rtllib
;
2368 if (ieee
->rtllib_ap_sec_type
&&
2369 (ieee
->rtllib_ap_sec_type(priv
->rtllib
)&(SEC_ALG_WEP
|
2377 bool rtl92e_is_halfn_supported_by_ap(struct net_device
*dev
)
2380 struct r8192_priv
*priv
= rtllib_priv(dev
);
2381 struct rtllib_device
*ieee
= priv
->rtllib
;
2383 if (ieee
->bHalfWirelessN24GMode
== true)
2391 void ActUpdateChannelAccessSetting(struct net_device
*dev
,
2392 enum wireless_mode WirelessMode
,
2393 struct channel_access_setting
*ChnlAccessSetting
)