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staging: rtl8192e: Rename rtl8192_phy_RFConfig
[deliverable/linux.git] / drivers / staging / rtl8192e / rtl8192e / r8192E_dev.c
1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * Based on the r8180 driver, which is:
5 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 *
19 * The full GNU General Public License is included in this distribution in the
20 * file called LICENSE.
21 *
22 * Contact Information:
23 * wlanfae <wlanfae@realtek.com>
24 ******************************************************************************/
25 #include "rtl_core.h"
26 #include "r8192E_phy.h"
27 #include "r8192E_phyreg.h"
28 #include "r8190P_rtl8256.h"
29 #include "r8192E_cmdpkt.h"
30 #include "rtl_dm.h"
31 #include "rtl_wx.h"
32
33 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
34 EDCAPARA_VO};
35
36 void rtl92e_start_beacon(struct net_device *dev)
37 {
38 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
39 struct rtllib_network *net = &priv->rtllib->current_network;
40 u16 BcnTimeCfg = 0;
41 u16 BcnCW = 6;
42 u16 BcnIFS = 0xf;
43
44 rtl8192_irq_disable(dev);
45
46 write_nic_word(dev, ATIMWND, 2);
47
48 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
49 write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
50 write_nic_word(dev, BCN_DMATIME, 256);
51
52 write_nic_byte(dev, BCN_ERR_THRESH, 100);
53
54 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
55 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
56 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
57 rtl8192_irq_enable(dev);
58 }
59
60 static void rtl8192e_update_msr(struct net_device *dev)
61 {
62 struct r8192_priv *priv = rtllib_priv(dev);
63 u8 msr;
64 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
65
66 msr = read_nic_byte(dev, MSR);
67 msr &= ~MSR_LINK_MASK;
68
69 switch (priv->rtllib->iw_mode) {
70 case IW_MODE_INFRA:
71 if (priv->rtllib->state == RTLLIB_LINKED)
72 msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
73 else
74 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
75 LedAction = LED_CTL_LINK;
76 break;
77 case IW_MODE_ADHOC:
78 if (priv->rtllib->state == RTLLIB_LINKED)
79 msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
80 else
81 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
82 break;
83 case IW_MODE_MASTER:
84 if (priv->rtllib->state == RTLLIB_LINKED)
85 msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
86 else
87 msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
88 break;
89 default:
90 break;
91 }
92
93 write_nic_byte(dev, MSR, msr);
94 if (priv->rtllib->LedControlHandler)
95 priv->rtllib->LedControlHandler(dev, LedAction);
96 }
97
98 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
99 {
100 struct r8192_priv *priv = rtllib_priv(dev);
101
102 switch (variable) {
103 case HW_VAR_BSSID:
104 write_nic_dword(dev, BSSIDR, ((u32 *)(val))[0]);
105 write_nic_word(dev, BSSIDR+2, ((u16 *)(val+2))[0]);
106 break;
107
108 case HW_VAR_MEDIA_STATUS:
109 {
110 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
111 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
112 u8 btMsr = read_nic_byte(dev, MSR);
113
114 btMsr &= 0xfc;
115
116 switch (OpMode) {
117 case RT_OP_MODE_INFRASTRUCTURE:
118 btMsr |= MSR_INFRA;
119 LedAction = LED_CTL_LINK;
120 break;
121
122 case RT_OP_MODE_IBSS:
123 btMsr |= MSR_ADHOC;
124 break;
125
126 case RT_OP_MODE_AP:
127 btMsr |= MSR_AP;
128 LedAction = LED_CTL_LINK;
129 break;
130
131 default:
132 btMsr |= MSR_NOLINK;
133 break;
134 }
135
136 write_nic_byte(dev, MSR, btMsr);
137
138 }
139 break;
140
141 case HW_VAR_CECHK_BSSID:
142 {
143 u32 RegRCR, Type;
144
145 Type = ((u8 *)(val))[0];
146 RegRCR = read_nic_dword(dev, RCR);
147 priv->ReceiveConfig = RegRCR;
148
149 if (Type == true)
150 RegRCR |= (RCR_CBSSID);
151 else if (Type == false)
152 RegRCR &= (~RCR_CBSSID);
153
154 write_nic_dword(dev, RCR, RegRCR);
155 priv->ReceiveConfig = RegRCR;
156
157 }
158 break;
159
160 case HW_VAR_SLOT_TIME:
161
162 priv->slot_time = val[0];
163 write_nic_byte(dev, SLOT_TIME, val[0]);
164
165 break;
166
167 case HW_VAR_ACK_PREAMBLE:
168 {
169 u32 regTmp;
170
171 priv->short_preamble = (bool)(*(u8 *)val);
172 regTmp = priv->basic_rate;
173 if (priv->short_preamble)
174 regTmp |= BRSR_AckShortPmb;
175 write_nic_dword(dev, RRSR, regTmp);
176 break;
177 }
178
179 case HW_VAR_CPU_RST:
180 write_nic_dword(dev, CPU_GEN, ((u32 *)(val))[0]);
181 break;
182
183 case HW_VAR_AC_PARAM:
184 {
185 u8 pAcParam = *((u8 *)val);
186 u32 eACI = pAcParam;
187 u8 u1bAIFS;
188 u32 u4bAcParam;
189 u8 mode = priv->rtllib->mode;
190 struct rtllib_qos_parameters *qop =
191 &priv->rtllib->current_network.qos_data.parameters;
192
193 u1bAIFS = qop->aifs[pAcParam] *
194 ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
195
196 dm_init_edca_turbo(dev);
197
198 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
199 AC_PARAM_TXOP_LIMIT_OFFSET) |
200 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
201 AC_PARAM_ECW_MAX_OFFSET) |
202 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
203 AC_PARAM_ECW_MIN_OFFSET) |
204 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
205
206 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
207 __func__, eACI, u4bAcParam);
208 switch (eACI) {
209 case AC1_BK:
210 write_nic_dword(dev, EDCAPARA_BK, u4bAcParam);
211 break;
212
213 case AC0_BE:
214 write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
215 break;
216
217 case AC2_VI:
218 write_nic_dword(dev, EDCAPARA_VI, u4bAcParam);
219 break;
220
221 case AC3_VO:
222 write_nic_dword(dev, EDCAPARA_VO, u4bAcParam);
223 break;
224
225 default:
226 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
227 eACI);
228 break;
229 }
230 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
231 (u8 *)(&pAcParam));
232 break;
233 }
234
235 case HW_VAR_ACM_CTRL:
236 {
237 struct rtllib_qos_parameters *qos_parameters =
238 &priv->rtllib->current_network.qos_data.parameters;
239 u8 pAcParam = *((u8 *)val);
240 u32 eACI = pAcParam;
241 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
242 (qos_parameters->aifs[0]);
243 u8 acm = pAciAifsn->f.acm;
244 u8 AcmCtrl = read_nic_byte(dev, AcmHwCtrl);
245
246 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
247 __func__, eACI);
248 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
249
250 if (acm) {
251 switch (eACI) {
252 case AC0_BE:
253 AcmCtrl |= AcmHw_BeqEn;
254 break;
255
256 case AC2_VI:
257 AcmCtrl |= AcmHw_ViqEn;
258 break;
259
260 case AC3_VO:
261 AcmCtrl |= AcmHw_VoqEn;
262 break;
263
264 default:
265 RT_TRACE(COMP_QOS,
266 "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
267 eACI);
268 break;
269 }
270 } else {
271 switch (eACI) {
272 case AC0_BE:
273 AcmCtrl &= (~AcmHw_BeqEn);
274 break;
275
276 case AC2_VI:
277 AcmCtrl &= (~AcmHw_ViqEn);
278 break;
279
280 case AC3_VO:
281 AcmCtrl &= (~AcmHw_BeqEn);
282 break;
283
284 default:
285 break;
286 }
287 }
288
289 RT_TRACE(COMP_QOS,
290 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
291 AcmCtrl);
292 write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
293 break;
294 }
295
296 case HW_VAR_SIFS:
297 write_nic_byte(dev, SIFS, val[0]);
298 write_nic_byte(dev, SIFS+1, val[0]);
299 break;
300
301 case HW_VAR_RF_TIMING:
302 {
303 u8 Rf_Timing = *((u8 *)val);
304
305 write_nic_byte(dev, rFPGA0_RFTiming1, Rf_Timing);
306 break;
307 }
308
309 default:
310 break;
311 }
312
313 }
314
315 static void rtl8192_read_eeprom_info(struct net_device *dev)
316 {
317 struct r8192_priv *priv = rtllib_priv(dev);
318 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
319 u8 tempval;
320 u8 ICVer8192, ICVer8256;
321 u16 i, usValue, IC_Version;
322 u16 EEPROMId;
323
324 RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
325
326 EEPROMId = eprom_read(dev, 0);
327 if (EEPROMId != RTL8190_EEPROM_ID) {
328 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
329 EEPROMId);
330 priv->AutoloadFailFlag = true;
331 } else {
332 priv->AutoloadFailFlag = false;
333 }
334
335 if (!priv->AutoloadFailFlag) {
336 priv->eeprom_vid = eprom_read(dev, EEPROM_VID >> 1);
337 priv->eeprom_did = eprom_read(dev, EEPROM_DID >> 1);
338
339 usValue = eprom_read(dev, (u16)(EEPROM_Customer_ID>>1)) >> 8;
340 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
341 usValue = eprom_read(dev, EEPROM_ICVersion_ChannelPlan>>1);
342 priv->eeprom_ChannelPlan = usValue&0xff;
343 IC_Version = (usValue & 0xff00)>>8;
344
345 ICVer8192 = (IC_Version&0xf);
346 ICVer8256 = (IC_Version & 0xf0)>>4;
347 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
348 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
349 if (ICVer8192 == 0x2) {
350 if (ICVer8256 == 0x5)
351 priv->card_8192_version = VERSION_8190_BE;
352 }
353 switch (priv->card_8192_version) {
354 case VERSION_8190_BD:
355 case VERSION_8190_BE:
356 break;
357 default:
358 priv->card_8192_version = VERSION_8190_BD;
359 break;
360 }
361 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
362 priv->card_8192_version);
363 } else {
364 priv->card_8192_version = VERSION_8190_BD;
365 priv->eeprom_vid = 0;
366 priv->eeprom_did = 0;
367 priv->eeprom_CustomerID = 0;
368 priv->eeprom_ChannelPlan = 0;
369 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
370 }
371
372 RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
373 RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
374 RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
375 priv->eeprom_CustomerID);
376
377 if (!priv->AutoloadFailFlag) {
378 for (i = 0; i < 6; i += 2) {
379 usValue = eprom_read(dev,
380 (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1));
381 *(u16 *)(&dev->dev_addr[i]) = usValue;
382 }
383 } else {
384 ether_addr_copy(dev->dev_addr, bMac_Tmp_Addr);
385 }
386
387 RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
388 dev->dev_addr);
389
390 if (priv->card_8192_version > VERSION_8190_BD)
391 priv->bTXPowerDataReadFromEEPORM = true;
392 else
393 priv->bTXPowerDataReadFromEEPORM = false;
394
395 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
396
397 if (priv->card_8192_version > VERSION_8190_BD) {
398 if (!priv->AutoloadFailFlag) {
399 tempval = (eprom_read(dev, (EEPROM_RFInd_PowerDiff >>
400 1))) & 0xff;
401 priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
402
403 if (tempval&0x80)
404 priv->rf_type = RF_1T2R;
405 else
406 priv->rf_type = RF_2T4R;
407 } else {
408 priv->EEPROMLegacyHTTxPowerDiff = 0x04;
409 }
410 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
411 priv->EEPROMLegacyHTTxPowerDiff);
412
413 if (!priv->AutoloadFailFlag)
414 priv->EEPROMThermalMeter = (u8)(((eprom_read(dev,
415 (EEPROM_ThermalMeter>>1))) &
416 0xff00)>>8);
417 else
418 priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
419 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
420 priv->EEPROMThermalMeter);
421 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
422
423 if (priv->epromtype == EEPROM_93C46) {
424 if (!priv->AutoloadFailFlag) {
425 usValue = eprom_read(dev,
426 EEPROM_TxPwDiff_CrystalCap >> 1);
427 priv->EEPROMAntPwDiff = (usValue&0x0fff);
428 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
429 >> 12);
430 } else {
431 priv->EEPROMAntPwDiff =
432 EEPROM_Default_AntTxPowerDiff;
433 priv->EEPROMCrystalCap =
434 EEPROM_Default_TxPwDiff_CrystalCap;
435 }
436 RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
437 priv->EEPROMAntPwDiff);
438 RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
439 priv->EEPROMCrystalCap);
440
441 for (i = 0; i < 14; i += 2) {
442 if (!priv->AutoloadFailFlag)
443 usValue = eprom_read(dev,
444 (u16)((EEPROM_TxPwIndex_CCK +
445 i) >> 1));
446 else
447 usValue = EEPROM_Default_TxPower;
448 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
449 usValue;
450 RT_TRACE(COMP_INIT,
451 "CCK Tx Power Level, Index %d = 0x%02x\n",
452 i, priv->EEPROMTxPowerLevelCCK[i]);
453 RT_TRACE(COMP_INIT,
454 "CCK Tx Power Level, Index %d = 0x%02x\n",
455 i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
456 }
457 for (i = 0; i < 14; i += 2) {
458 if (!priv->AutoloadFailFlag)
459 usValue = eprom_read(dev,
460 (u16)((EEPROM_TxPwIndex_OFDM_24G
461 + i) >> 1));
462 else
463 usValue = EEPROM_Default_TxPower;
464 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
465 = usValue;
466 RT_TRACE(COMP_INIT,
467 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
468 i, priv->EEPROMTxPowerLevelOFDM24G[i]);
469 RT_TRACE(COMP_INIT,
470 "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
471 i + 1,
472 priv->EEPROMTxPowerLevelOFDM24G[i+1]);
473 }
474 }
475 if (priv->epromtype == EEPROM_93C46) {
476 for (i = 0; i < 14; i++) {
477 priv->TxPowerLevelCCK[i] =
478 priv->EEPROMTxPowerLevelCCK[i];
479 priv->TxPowerLevelOFDM24G[i] =
480 priv->EEPROMTxPowerLevelOFDM24G[i];
481 }
482 priv->LegacyHTTxPowerDiff =
483 priv->EEPROMLegacyHTTxPowerDiff;
484 priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
485 0xf);
486 priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
487 0xf0) >> 4;
488 priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
489 0xf00) >> 8;
490 priv->CrystalCap = priv->EEPROMCrystalCap;
491 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
492 0xf);
493 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
494 0xf0) >> 4;
495 } else if (priv->epromtype == EEPROM_93C56) {
496
497 for (i = 0; i < 3; i++) {
498 priv->TxPowerLevelCCK_A[i] =
499 priv->EEPROMRfACCKChnl1TxPwLevel[0];
500 priv->TxPowerLevelOFDM24G_A[i] =
501 priv->EEPROMRfAOfdmChnlTxPwLevel[0];
502 priv->TxPowerLevelCCK_C[i] =
503 priv->EEPROMRfCCCKChnl1TxPwLevel[0];
504 priv->TxPowerLevelOFDM24G_C[i] =
505 priv->EEPROMRfCOfdmChnlTxPwLevel[0];
506 }
507 for (i = 3; i < 9; i++) {
508 priv->TxPowerLevelCCK_A[i] =
509 priv->EEPROMRfACCKChnl1TxPwLevel[1];
510 priv->TxPowerLevelOFDM24G_A[i] =
511 priv->EEPROMRfAOfdmChnlTxPwLevel[1];
512 priv->TxPowerLevelCCK_C[i] =
513 priv->EEPROMRfCCCKChnl1TxPwLevel[1];
514 priv->TxPowerLevelOFDM24G_C[i] =
515 priv->EEPROMRfCOfdmChnlTxPwLevel[1];
516 }
517 for (i = 9; i < 14; i++) {
518 priv->TxPowerLevelCCK_A[i] =
519 priv->EEPROMRfACCKChnl1TxPwLevel[2];
520 priv->TxPowerLevelOFDM24G_A[i] =
521 priv->EEPROMRfAOfdmChnlTxPwLevel[2];
522 priv->TxPowerLevelCCK_C[i] =
523 priv->EEPROMRfCCCKChnl1TxPwLevel[2];
524 priv->TxPowerLevelOFDM24G_C[i] =
525 priv->EEPROMRfCOfdmChnlTxPwLevel[2];
526 }
527 for (i = 0; i < 14; i++)
528 RT_TRACE(COMP_INIT,
529 "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
530 i, priv->TxPowerLevelCCK_A[i]);
531 for (i = 0; i < 14; i++)
532 RT_TRACE(COMP_INIT,
533 "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
534 i, priv->TxPowerLevelOFDM24G_A[i]);
535 for (i = 0; i < 14; i++)
536 RT_TRACE(COMP_INIT,
537 "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
538 i, priv->TxPowerLevelCCK_C[i]);
539 for (i = 0; i < 14; i++)
540 RT_TRACE(COMP_INIT,
541 "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
542 i, priv->TxPowerLevelOFDM24G_C[i]);
543 priv->LegacyHTTxPowerDiff =
544 priv->EEPROMLegacyHTTxPowerDiff;
545 priv->AntennaTxPwDiff[0] = 0;
546 priv->AntennaTxPwDiff[1] = 0;
547 priv->AntennaTxPwDiff[2] = 0;
548 priv->CrystalCap = priv->EEPROMCrystalCap;
549 priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
550 0xf);
551 priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
552 0xf0) >> 4;
553 }
554 }
555
556 if (priv->rf_type == RF_1T2R) {
557 /* no matter what checkpatch says, the braces are needed */
558 RT_TRACE(COMP_INIT, "\n1T2R config\n");
559 } else if (priv->rf_type == RF_2T4R) {
560 RT_TRACE(COMP_INIT, "\n2T4R config\n");
561 }
562
563 init_rate_adaptive(dev);
564
565 priv->rf_chip = RF_8256;
566
567 if (priv->RegChannelPlan == 0xf)
568 priv->ChannelPlan = priv->eeprom_ChannelPlan;
569 else
570 priv->ChannelPlan = priv->RegChannelPlan;
571
572 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
573 priv->CustomerID = RT_CID_DLINK;
574
575 switch (priv->eeprom_CustomerID) {
576 case EEPROM_CID_DEFAULT:
577 priv->CustomerID = RT_CID_DEFAULT;
578 break;
579 case EEPROM_CID_CAMEO:
580 priv->CustomerID = RT_CID_819x_CAMEO;
581 break;
582 case EEPROM_CID_RUNTOP:
583 priv->CustomerID = RT_CID_819x_RUNTOP;
584 break;
585 case EEPROM_CID_NetCore:
586 priv->CustomerID = RT_CID_819x_Netcore;
587 break;
588 case EEPROM_CID_TOSHIBA:
589 priv->CustomerID = RT_CID_TOSHIBA;
590 if (priv->eeprom_ChannelPlan&0x80)
591 priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
592 else
593 priv->ChannelPlan = 0x0;
594 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
595 priv->ChannelPlan);
596 break;
597 case EEPROM_CID_Nettronix:
598 priv->ScanDelay = 100;
599 priv->CustomerID = RT_CID_Nettronix;
600 break;
601 case EEPROM_CID_Pronet:
602 priv->CustomerID = RT_CID_PRONET;
603 break;
604 case EEPROM_CID_DLINK:
605 priv->CustomerID = RT_CID_DLINK;
606 break;
607
608 case EEPROM_CID_WHQL:
609 break;
610 default:
611 break;
612 }
613
614 if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
615 priv->ChannelPlan = 0;
616 priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
617
618 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
619 priv->rtllib->bSupportRemoteWakeUp = true;
620 else
621 priv->rtllib->bSupportRemoteWakeUp = false;
622
623 RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
624 RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
625 RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
626 }
627
628 void rtl92e_get_eeprom_size(struct net_device *dev)
629 {
630 u16 curCR;
631 struct r8192_priv *priv = rtllib_priv(dev);
632
633 RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
634 curCR = read_nic_dword(dev, EPROM_CMD);
635 RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
636 curCR);
637 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
638 EEPROM_93C46;
639 RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
640 priv->epromtype);
641 rtl8192_read_eeprom_info(dev);
642 }
643
644 static void rtl8192_hwconfig(struct net_device *dev)
645 {
646 u32 regRATR = 0, regRRSR = 0;
647 u8 regBwOpMode = 0, regTmp = 0;
648 struct r8192_priv *priv = rtllib_priv(dev);
649
650 switch (priv->rtllib->mode) {
651 case WIRELESS_MODE_B:
652 regBwOpMode = BW_OPMODE_20MHZ;
653 regRATR = RATE_ALL_CCK;
654 regRRSR = RATE_ALL_CCK;
655 break;
656 case WIRELESS_MODE_A:
657 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
658 regRATR = RATE_ALL_OFDM_AG;
659 regRRSR = RATE_ALL_OFDM_AG;
660 break;
661 case WIRELESS_MODE_G:
662 regBwOpMode = BW_OPMODE_20MHZ;
663 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
664 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
665 break;
666 case WIRELESS_MODE_AUTO:
667 case WIRELESS_MODE_N_24G:
668 regBwOpMode = BW_OPMODE_20MHZ;
669 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
670 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
671 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
672 break;
673 case WIRELESS_MODE_N_5G:
674 regBwOpMode = BW_OPMODE_5G;
675 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
676 RATE_ALL_OFDM_2SS;
677 regRRSR = RATE_ALL_OFDM_AG;
678 break;
679 default:
680 regBwOpMode = BW_OPMODE_20MHZ;
681 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
682 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
683 break;
684 }
685
686 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
687 {
688 u32 ratr_value = 0;
689
690 ratr_value = regRATR;
691 if (priv->rf_type == RF_1T2R)
692 ratr_value &= ~(RATE_ALL_OFDM_2SS);
693 write_nic_dword(dev, RATR0, ratr_value);
694 write_nic_byte(dev, UFWP, 1);
695 }
696 regTmp = read_nic_byte(dev, 0x313);
697 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
698 write_nic_dword(dev, RRSR, regRRSR);
699
700 write_nic_word(dev, RETRY_LIMIT,
701 priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
702 priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
703 }
704
705 bool rtl92e_start_adapter(struct net_device *dev)
706 {
707 struct r8192_priv *priv = rtllib_priv(dev);
708 u32 ulRegRead;
709 bool rtStatus = true;
710 u8 tmpvalue;
711 u8 ICVersion, SwitchingRegulatorOutput;
712 bool bfirmwareok = true;
713 u32 tmpRegA, tmpRegC, TempCCk;
714 int i = 0;
715 u32 retry_times = 0;
716
717 RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
718 priv->being_init_adapter = true;
719
720 start:
721 rtl8192_pci_resetdescring(dev);
722 priv->Rf_Mode = RF_OP_By_SW_3wire;
723 if (priv->ResetProgress == RESET_TYPE_NORESET) {
724 write_nic_byte(dev, ANAPAR, 0x37);
725 mdelay(500);
726 }
727 priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
728
729 if (priv->RegRfOff)
730 priv->rtllib->eRFPowerState = eRfOff;
731
732 ulRegRead = read_nic_dword(dev, CPU_GEN);
733 if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
734 ulRegRead |= CPU_GEN_SYSTEM_RESET;
735 else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
736 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
737 else
738 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
739 __func__, priv->pFirmware->firmware_status);
740
741 write_nic_dword(dev, CPU_GEN, ulRegRead);
742
743 ICVersion = read_nic_byte(dev, IC_VERRSION);
744 if (ICVersion >= 0x4) {
745 SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR);
746 if (SwitchingRegulatorOutput != 0xb8) {
747 write_nic_byte(dev, SWREGULATOR, 0xa8);
748 mdelay(1);
749 write_nic_byte(dev, SWREGULATOR, 0xb8);
750 }
751 }
752 RT_TRACE(COMP_INIT, "BB Config Start!\n");
753 rtStatus = rtl92e_config_bb(dev);
754 if (!rtStatus) {
755 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
756 return rtStatus;
757 }
758 RT_TRACE(COMP_INIT, "BB Config Finished!\n");
759
760 priv->LoopbackMode = RTL819X_NO_LOOPBACK;
761 if (priv->ResetProgress == RESET_TYPE_NORESET) {
762 ulRegRead = read_nic_dword(dev, CPU_GEN);
763 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
764 ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
765 CPU_GEN_NO_LOOPBACK_SET);
766 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
767 ulRegRead |= CPU_CCK_LOOPBACK;
768 else
769 netdev_err(dev, "%s: Invalid loopback mode setting.\n",
770 __func__);
771
772 write_nic_dword(dev, CPU_GEN, ulRegRead);
773
774 udelay(500);
775 }
776 rtl8192_hwconfig(dev);
777 write_nic_byte(dev, CMDR, CR_RE | CR_TE);
778
779 write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
780 (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
781 write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
782 write_nic_word(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
783 write_nic_dword(dev, RCR, priv->ReceiveConfig);
784
785 write_nic_dword(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
786 RSVD_FW_QUEUE_PAGE_BK_SHIFT |
787 NUM_OF_PAGE_IN_FW_QUEUE_BE <<
788 RSVD_FW_QUEUE_PAGE_BE_SHIFT |
789 NUM_OF_PAGE_IN_FW_QUEUE_VI <<
790 RSVD_FW_QUEUE_PAGE_VI_SHIFT |
791 NUM_OF_PAGE_IN_FW_QUEUE_VO <<
792 RSVD_FW_QUEUE_PAGE_VO_SHIFT);
793 write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
794 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
795 write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
796 NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
797 RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
798 NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
799 RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
800
801 rtl8192_tx_enable(dev);
802 rtl8192_rx_enable(dev);
803 ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR)) |
804 RATE_ALL_OFDM_AG | RATE_ALL_CCK;
805 write_nic_dword(dev, RRSR, ulRegRead);
806 write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
807
808 write_nic_byte(dev, ACK_TIMEOUT, 0x30);
809
810 if (priv->ResetProgress == RESET_TYPE_NORESET)
811 rtl8192_SetWirelessMode(dev, priv->rtllib->mode);
812 CamResetAllEntry(dev);
813 {
814 u8 SECR_value = 0x0;
815
816 SECR_value |= SCR_TxEncEnable;
817 SECR_value |= SCR_RxDecEnable;
818 SECR_value |= SCR_NoSKMC;
819 write_nic_byte(dev, SECR, SECR_value);
820 }
821 write_nic_word(dev, ATIMWND, 2);
822 write_nic_word(dev, BCN_INTERVAL, 100);
823 {
824 int i;
825
826 for (i = 0; i < QOS_QUEUE_NUM; i++)
827 write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
828 }
829 write_nic_byte(dev, 0xbe, 0xc0);
830
831 rtl92e_config_mac(dev);
832
833 if (priv->card_8192_version > (u8) VERSION_8190_BD) {
834 rtl92e_get_tx_power(dev);
835 rtl8192_phy_setTxPower(dev, priv->chan);
836 }
837
838 tmpvalue = read_nic_byte(dev, IC_VERRSION);
839 priv->IC_Cut = tmpvalue;
840 RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
841 if (priv->IC_Cut >= IC_VersionCut_D) {
842 if (priv->IC_Cut == IC_VersionCut_D) {
843 /* no matter what checkpatch says, braces are needed */
844 RT_TRACE(COMP_INIT, "D-cut\n");
845 } else if (priv->IC_Cut == IC_VersionCut_E) {
846 RT_TRACE(COMP_INIT, "E-cut\n");
847 }
848 } else {
849 RT_TRACE(COMP_INIT, "Before C-cut\n");
850 }
851
852 RT_TRACE(COMP_INIT, "Load Firmware!\n");
853 bfirmwareok = init_firmware(dev);
854 if (!bfirmwareok) {
855 if (retry_times < 10) {
856 retry_times++;
857 goto start;
858 } else {
859 rtStatus = false;
860 goto end;
861 }
862 }
863 RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
864 if (priv->ResetProgress == RESET_TYPE_NORESET) {
865 RT_TRACE(COMP_INIT, "RF Config Started!\n");
866 rtStatus = rtl92e_config_phy(dev);
867 if (!rtStatus) {
868 netdev_info(dev, "RF Config failed\n");
869 return rtStatus;
870 }
871 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
872 }
873 rtl8192_phy_updateInitGain(dev);
874
875 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
876 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
877
878 write_nic_byte(dev, 0x87, 0x0);
879
880 if (priv->RegRfOff) {
881 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
882 "%s(): Turn off RF for RegRfOff ----------\n",
883 __func__);
884 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW, true);
885 } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
886 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
887 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
888 __func__, priv->rtllib->RfOffReason);
889 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
890 true);
891 } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
892 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
893 "%s(): Turn off RF for RfOffReason(%d) ----------\n",
894 __func__, priv->rtllib->RfOffReason);
895 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
896 true);
897 } else {
898 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
899 __func__);
900 priv->rtllib->eRFPowerState = eRfOn;
901 priv->rtllib->RfOffReason = 0;
902 }
903
904 if (priv->rtllib->FwRWRF)
905 priv->Rf_Mode = RF_OP_By_FW;
906 else
907 priv->Rf_Mode = RF_OP_By_SW_3wire;
908
909 if (priv->ResetProgress == RESET_TYPE_NORESET) {
910 dm_initialize_txpower_tracking(dev);
911
912 if (priv->IC_Cut >= IC_VersionCut_D) {
913 tmpRegA = rtl8192_QueryBBReg(dev,
914 rOFDM0_XATxIQImbalance, bMaskDWord);
915 tmpRegC = rtl8192_QueryBBReg(dev,
916 rOFDM0_XCTxIQImbalance, bMaskDWord);
917 for (i = 0; i < TxBBGainTableLength; i++) {
918 if (tmpRegA == dm_tx_bb_gain[i]) {
919 priv->rfa_txpowertrackingindex = (u8)i;
920 priv->rfa_txpowertrackingindex_real =
921 (u8)i;
922 priv->rfa_txpowertracking_default =
923 priv->rfa_txpowertrackingindex;
924 break;
925 }
926 }
927
928 TempCCk = rtl8192_QueryBBReg(dev,
929 rCCK0_TxFilter1, bMaskByte2);
930
931 for (i = 0; i < CCKTxBBGainTableLength; i++) {
932 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
933 priv->CCKPresentAttentuation_20Mdefault = (u8)i;
934 break;
935 }
936 }
937 priv->CCKPresentAttentuation_40Mdefault = 0;
938 priv->CCKPresentAttentuation_difference = 0;
939 priv->CCKPresentAttentuation =
940 priv->CCKPresentAttentuation_20Mdefault;
941 RT_TRACE(COMP_POWER_TRACKING,
942 "priv->rfa_txpowertrackingindex_initial = %d\n",
943 priv->rfa_txpowertrackingindex);
944 RT_TRACE(COMP_POWER_TRACKING,
945 "priv->rfa_txpowertrackingindex_real__initial = %d\n",
946 priv->rfa_txpowertrackingindex_real);
947 RT_TRACE(COMP_POWER_TRACKING,
948 "priv->CCKPresentAttentuation_difference_initial = %d\n",
949 priv->CCKPresentAttentuation_difference);
950 RT_TRACE(COMP_POWER_TRACKING,
951 "priv->CCKPresentAttentuation_initial = %d\n",
952 priv->CCKPresentAttentuation);
953 priv->btxpower_tracking = false;
954 }
955 }
956 rtl8192_irq_enable(dev);
957 end:
958 priv->being_init_adapter = false;
959 return rtStatus;
960 }
961
962 static void rtl8192_net_update(struct net_device *dev)
963 {
964
965 struct r8192_priv *priv = rtllib_priv(dev);
966 struct rtllib_network *net;
967 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
968 u16 rate_config = 0;
969
970 net = &priv->rtllib->current_network;
971 rtl8192_config_rate(dev, &rate_config);
972 priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
973 priv->basic_rate = rate_config &= 0x15f;
974 write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]);
975 write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
976
977 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
978 write_nic_word(dev, ATIMWND, 2);
979 write_nic_word(dev, BCN_DMATIME, 256);
980 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
981 write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
982 write_nic_byte(dev, BCN_ERR_THRESH, 100);
983
984 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
985 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
986
987 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
988 }
989 }
990
991 void rtl92e_link_change(struct net_device *dev)
992 {
993 struct r8192_priv *priv = rtllib_priv(dev);
994 struct rtllib_device *ieee = priv->rtllib;
995
996 if (!priv->up)
997 return;
998
999 if (ieee->state == RTLLIB_LINKED) {
1000 rtl8192_net_update(dev);
1001 priv->ops->update_ratr_table(dev);
1002 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
1003 (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
1004 EnableHWSecurityConfig8192(dev);
1005 } else {
1006 write_nic_byte(dev, 0x173, 0);
1007 }
1008 rtl8192e_update_msr(dev);
1009
1010 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1011 u32 reg = 0;
1012
1013 reg = read_nic_dword(dev, RCR);
1014 if (priv->rtllib->state == RTLLIB_LINKED) {
1015 if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1016 ;
1017 else
1018 priv->ReceiveConfig = reg |= RCR_CBSSID;
1019 } else
1020 priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1021
1022 write_nic_dword(dev, RCR, reg);
1023 }
1024 }
1025
1026 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
1027 bool WriteIntoReg)
1028 {
1029 struct r8192_priv *priv = rtllib_priv(dev);
1030
1031 if (bAllowAllDA)
1032 priv->ReceiveConfig |= RCR_AAP;
1033 else
1034 priv->ReceiveConfig &= ~RCR_AAP;
1035
1036 if (WriteIntoReg)
1037 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1038 }
1039
1040 static u8 MRateToHwRate8190Pci(u8 rate)
1041 {
1042 u8 ret = DESC90_RATE1M;
1043
1044 switch (rate) {
1045 case MGN_1M:
1046 ret = DESC90_RATE1M;
1047 break;
1048 case MGN_2M:
1049 ret = DESC90_RATE2M;
1050 break;
1051 case MGN_5_5M:
1052 ret = DESC90_RATE5_5M;
1053 break;
1054 case MGN_11M:
1055 ret = DESC90_RATE11M;
1056 break;
1057 case MGN_6M:
1058 ret = DESC90_RATE6M;
1059 break;
1060 case MGN_9M:
1061 ret = DESC90_RATE9M;
1062 break;
1063 case MGN_12M:
1064 ret = DESC90_RATE12M;
1065 break;
1066 case MGN_18M:
1067 ret = DESC90_RATE18M;
1068 break;
1069 case MGN_24M:
1070 ret = DESC90_RATE24M;
1071 break;
1072 case MGN_36M:
1073 ret = DESC90_RATE36M;
1074 break;
1075 case MGN_48M:
1076 ret = DESC90_RATE48M;
1077 break;
1078 case MGN_54M:
1079 ret = DESC90_RATE54M;
1080 break;
1081 case MGN_MCS0:
1082 ret = DESC90_RATEMCS0;
1083 break;
1084 case MGN_MCS1:
1085 ret = DESC90_RATEMCS1;
1086 break;
1087 case MGN_MCS2:
1088 ret = DESC90_RATEMCS2;
1089 break;
1090 case MGN_MCS3:
1091 ret = DESC90_RATEMCS3;
1092 break;
1093 case MGN_MCS4:
1094 ret = DESC90_RATEMCS4;
1095 break;
1096 case MGN_MCS5:
1097 ret = DESC90_RATEMCS5;
1098 break;
1099 case MGN_MCS6:
1100 ret = DESC90_RATEMCS6;
1101 break;
1102 case MGN_MCS7:
1103 ret = DESC90_RATEMCS7;
1104 break;
1105 case MGN_MCS8:
1106 ret = DESC90_RATEMCS8;
1107 break;
1108 case MGN_MCS9:
1109 ret = DESC90_RATEMCS9;
1110 break;
1111 case MGN_MCS10:
1112 ret = DESC90_RATEMCS10;
1113 break;
1114 case MGN_MCS11:
1115 ret = DESC90_RATEMCS11;
1116 break;
1117 case MGN_MCS12:
1118 ret = DESC90_RATEMCS12;
1119 break;
1120 case MGN_MCS13:
1121 ret = DESC90_RATEMCS13;
1122 break;
1123 case MGN_MCS14:
1124 ret = DESC90_RATEMCS14;
1125 break;
1126 case MGN_MCS15:
1127 ret = DESC90_RATEMCS15;
1128 break;
1129 case (0x80|0x20):
1130 ret = DESC90_RATEMCS32;
1131 break;
1132 default:
1133 break;
1134 }
1135 return ret;
1136 }
1137
1138 static u8 rtl8192_MapHwQueueToFirmwareQueue(struct net_device *dev, u8 QueueID,
1139 u8 priority)
1140 {
1141 u8 QueueSelect = 0x0;
1142
1143 switch (QueueID) {
1144 case BE_QUEUE:
1145 QueueSelect = QSLT_BE;
1146 break;
1147
1148 case BK_QUEUE:
1149 QueueSelect = QSLT_BK;
1150 break;
1151
1152 case VO_QUEUE:
1153 QueueSelect = QSLT_VO;
1154 break;
1155
1156 case VI_QUEUE:
1157 QueueSelect = QSLT_VI;
1158 break;
1159 case MGNT_QUEUE:
1160 QueueSelect = QSLT_MGNT;
1161 break;
1162 case BEACON_QUEUE:
1163 QueueSelect = QSLT_BEACON;
1164 break;
1165 case TXCMD_QUEUE:
1166 QueueSelect = QSLT_CMD;
1167 break;
1168 case HIGH_QUEUE:
1169 QueueSelect = QSLT_HIGH;
1170 break;
1171 default:
1172 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
1173 __func__, QueueID);
1174 break;
1175 }
1176 return QueueSelect;
1177 }
1178
1179 static u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
1180 {
1181 u8 tmp_Short;
1182
1183 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
1184 ((tcb_desc->bUseShortPreamble) ? 1 : 0);
1185 if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
1186 tmp_Short = 0;
1187
1188 return tmp_Short;
1189 }
1190
1191 void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
1192 struct cb_desc *cb_desc, struct sk_buff *skb)
1193 {
1194 struct r8192_priv *priv = rtllib_priv(dev);
1195 dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1196 PCI_DMA_TODEVICE);
1197 struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
1198
1199 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1200 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1201 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1202 pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)cb_desc->data_rate);
1203 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1204 pTxFwInfo->Short = rtl8192_QueryIsShort(pTxFwInfo->TxHT,
1205 pTxFwInfo->TxRate,
1206 cb_desc);
1207
1208 if (pci_dma_mapping_error(priv->pdev, mapping))
1209 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1210 if (cb_desc->bAMPDUEnable) {
1211 pTxFwInfo->AllowAggregation = 1;
1212 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1213 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1214 } else {
1215 pTxFwInfo->AllowAggregation = 0;
1216 pTxFwInfo->RxMF = 0;
1217 pTxFwInfo->RxAMD = 0;
1218 }
1219
1220 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0;
1221 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1222 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1223 pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1224 pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)cb_desc->rts_rate);
1225 pTxFwInfo->RtsBandwidth = 0;
1226 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1227 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1228 (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1229 (cb_desc->bRTSUseShortGI ? 1 : 0);
1230 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1231 if (cb_desc->bPacketBW) {
1232 pTxFwInfo->TxBandwidth = 1;
1233 pTxFwInfo->TxSubCarrier = 0;
1234 } else {
1235 pTxFwInfo->TxBandwidth = 0;
1236 pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1237 }
1238 } else {
1239 pTxFwInfo->TxBandwidth = 0;
1240 pTxFwInfo->TxSubCarrier = 0;
1241 }
1242
1243 memset((u8 *)pdesc, 0, 12);
1244 pdesc->LINIP = 0;
1245 pdesc->CmdInit = 1;
1246 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1247 pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1248
1249 pdesc->SecCAMID = 0;
1250 pdesc->RATid = cb_desc->RATRIndex;
1251
1252
1253 pdesc->NoEnc = 1;
1254 pdesc->SecType = 0x0;
1255 if (cb_desc->bHwSec) {
1256 static u8 tmp;
1257
1258 if (!tmp) {
1259 RT_TRACE(COMP_DBG, "==>================hw sec\n");
1260 tmp = 1;
1261 }
1262 switch (priv->rtllib->pairwise_key_type) {
1263 case KEY_TYPE_WEP40:
1264 case KEY_TYPE_WEP104:
1265 pdesc->SecType = 0x1;
1266 pdesc->NoEnc = 0;
1267 break;
1268 case KEY_TYPE_TKIP:
1269 pdesc->SecType = 0x2;
1270 pdesc->NoEnc = 0;
1271 break;
1272 case KEY_TYPE_CCMP:
1273 pdesc->SecType = 0x3;
1274 pdesc->NoEnc = 0;
1275 break;
1276 case KEY_TYPE_NA:
1277 pdesc->SecType = 0x0;
1278 pdesc->NoEnc = 1;
1279 break;
1280 }
1281 }
1282
1283 pdesc->PktId = 0x0;
1284
1285 pdesc->QueueSelect = rtl8192_MapHwQueueToFirmwareQueue(dev,
1286 cb_desc->queue_index,
1287 cb_desc->priority);
1288 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1289
1290 pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1291 pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1292
1293 pdesc->FirstSeg = 1;
1294 pdesc->LastSeg = 1;
1295 pdesc->TxBufferSize = skb->len;
1296
1297 pdesc->TxBuffAddr = mapping;
1298 }
1299
1300 void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1301 struct cb_desc *cb_desc, struct sk_buff *skb)
1302 {
1303 struct r8192_priv *priv = rtllib_priv(dev);
1304 dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1305 PCI_DMA_TODEVICE);
1306
1307 if (pci_dma_mapping_error(priv->pdev, mapping))
1308 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1309 memset(entry, 0, 12);
1310 entry->LINIP = cb_desc->bLastIniPkt;
1311 entry->FirstSeg = 1;
1312 entry->LastSeg = 1;
1313 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1314 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1315 } else {
1316 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1317
1318 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1319 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1320 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1321 entry_tmp->Offset);
1322 entry_tmp->QueueSelect = QSLT_CMD;
1323 entry_tmp->TxFWInfoSize = 0x08;
1324 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1325 }
1326 entry->TxBufferSize = skb->len;
1327 entry->TxBuffAddr = mapping;
1328 entry->OWN = 1;
1329 }
1330
1331 static u8 HwRateToMRate90(bool bIsHT, u8 rate)
1332 {
1333 u8 ret_rate = 0x02;
1334
1335 if (!bIsHT) {
1336 switch (rate) {
1337 case DESC90_RATE1M:
1338 ret_rate = MGN_1M;
1339 break;
1340 case DESC90_RATE2M:
1341 ret_rate = MGN_2M;
1342 break;
1343 case DESC90_RATE5_5M:
1344 ret_rate = MGN_5_5M;
1345 break;
1346 case DESC90_RATE11M:
1347 ret_rate = MGN_11M;
1348 break;
1349 case DESC90_RATE6M:
1350 ret_rate = MGN_6M;
1351 break;
1352 case DESC90_RATE9M:
1353 ret_rate = MGN_9M;
1354 break;
1355 case DESC90_RATE12M:
1356 ret_rate = MGN_12M;
1357 break;
1358 case DESC90_RATE18M:
1359 ret_rate = MGN_18M;
1360 break;
1361 case DESC90_RATE24M:
1362 ret_rate = MGN_24M;
1363 break;
1364 case DESC90_RATE36M:
1365 ret_rate = MGN_36M;
1366 break;
1367 case DESC90_RATE48M:
1368 ret_rate = MGN_48M;
1369 break;
1370 case DESC90_RATE54M:
1371 ret_rate = MGN_54M;
1372 break;
1373
1374 default:
1375 RT_TRACE(COMP_RECV,
1376 "HwRateToMRate90(): Non supportedRate [%x], bIsHT = %d!!!\n",
1377 rate, bIsHT);
1378 break;
1379 }
1380
1381 } else {
1382 switch (rate) {
1383 case DESC90_RATEMCS0:
1384 ret_rate = MGN_MCS0;
1385 break;
1386 case DESC90_RATEMCS1:
1387 ret_rate = MGN_MCS1;
1388 break;
1389 case DESC90_RATEMCS2:
1390 ret_rate = MGN_MCS2;
1391 break;
1392 case DESC90_RATEMCS3:
1393 ret_rate = MGN_MCS3;
1394 break;
1395 case DESC90_RATEMCS4:
1396 ret_rate = MGN_MCS4;
1397 break;
1398 case DESC90_RATEMCS5:
1399 ret_rate = MGN_MCS5;
1400 break;
1401 case DESC90_RATEMCS6:
1402 ret_rate = MGN_MCS6;
1403 break;
1404 case DESC90_RATEMCS7:
1405 ret_rate = MGN_MCS7;
1406 break;
1407 case DESC90_RATEMCS8:
1408 ret_rate = MGN_MCS8;
1409 break;
1410 case DESC90_RATEMCS9:
1411 ret_rate = MGN_MCS9;
1412 break;
1413 case DESC90_RATEMCS10:
1414 ret_rate = MGN_MCS10;
1415 break;
1416 case DESC90_RATEMCS11:
1417 ret_rate = MGN_MCS11;
1418 break;
1419 case DESC90_RATEMCS12:
1420 ret_rate = MGN_MCS12;
1421 break;
1422 case DESC90_RATEMCS13:
1423 ret_rate = MGN_MCS13;
1424 break;
1425 case DESC90_RATEMCS14:
1426 ret_rate = MGN_MCS14;
1427 break;
1428 case DESC90_RATEMCS15:
1429 ret_rate = MGN_MCS15;
1430 break;
1431 case DESC90_RATEMCS32:
1432 ret_rate = (0x80|0x20);
1433 break;
1434
1435 default:
1436 RT_TRACE(COMP_RECV,
1437 "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",
1438 rate, bIsHT);
1439 break;
1440 }
1441 }
1442
1443 return ret_rate;
1444 }
1445
1446 static long rtl8192_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1447 {
1448 long retsig;
1449
1450 if (currsig >= 61 && currsig <= 100)
1451 retsig = 90 + ((currsig - 60) / 4);
1452 else if (currsig >= 41 && currsig <= 60)
1453 retsig = 78 + ((currsig - 40) / 2);
1454 else if (currsig >= 31 && currsig <= 40)
1455 retsig = 66 + (currsig - 30);
1456 else if (currsig >= 21 && currsig <= 30)
1457 retsig = 54 + (currsig - 20);
1458 else if (currsig >= 5 && currsig <= 20)
1459 retsig = 42 + (((currsig - 5) * 2) / 3);
1460 else if (currsig == 4)
1461 retsig = 36;
1462 else if (currsig == 3)
1463 retsig = 27;
1464 else if (currsig == 2)
1465 retsig = 18;
1466 else if (currsig == 1)
1467 retsig = 9;
1468 else
1469 retsig = currsig;
1470
1471 return retsig;
1472 }
1473
1474
1475 #define rx_hal_is_cck_rate(_pdrvinfo)\
1476 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1477 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1478 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1479 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1480 !_pdrvinfo->RxHT)
1481
1482 static void rtl8192_query_rxphystatus(
1483 struct r8192_priv *priv,
1484 struct rtllib_rx_stats *pstats,
1485 struct rx_desc *pdesc,
1486 struct rx_fwinfo *pdrvinfo,
1487 struct rtllib_rx_stats *precord_stats,
1488 bool bpacket_match_bssid,
1489 bool bpacket_toself,
1490 bool bPacketBeacon,
1491 bool bToSelfBA
1492 )
1493 {
1494 struct phy_sts_ofdm_819xpci *pofdm_buf;
1495 struct phy_sts_cck_819xpci *pcck_buf;
1496 struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1497 u8 *prxpkt;
1498 u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1499 char rx_pwr[4], rx_pwr_all = 0;
1500 char rx_snrX, rx_evmX;
1501 u8 evm, pwdb_all;
1502 u32 RSSI, total_rssi = 0;
1503 u8 is_cck_rate = 0;
1504 u8 rf_rx_num = 0;
1505 static u8 check_reg824;
1506 static u32 reg824_bit9;
1507
1508 priv->stats.numqry_phystatus++;
1509
1510 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1511 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1512 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1513 bpacket_match_bssid;
1514 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1515 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1516 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1517 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1518 if (check_reg824 == 0) {
1519 reg824_bit9 = rtl8192_QueryBBReg(priv->rtllib->dev,
1520 rFPGA0_XA_HSSIParameter2, 0x200);
1521 check_reg824 = 1;
1522 }
1523
1524
1525 prxpkt = (u8 *)pdrvinfo;
1526
1527 prxpkt += sizeof(struct rx_fwinfo);
1528
1529 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1530 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1531
1532 pstats->RxMIMOSignalQuality[0] = -1;
1533 pstats->RxMIMOSignalQuality[1] = -1;
1534 precord_stats->RxMIMOSignalQuality[0] = -1;
1535 precord_stats->RxMIMOSignalQuality[1] = -1;
1536
1537 if (is_cck_rate) {
1538 u8 report;
1539
1540 priv->stats.numqry_phystatusCCK++;
1541 if (!reg824_bit9) {
1542 report = pcck_buf->cck_agc_rpt & 0xc0;
1543 report >>= 6;
1544 switch (report) {
1545 case 0x3:
1546 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1547 0x3e);
1548 break;
1549 case 0x2:
1550 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1551 0x3e);
1552 break;
1553 case 0x1:
1554 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1555 0x3e);
1556 break;
1557 case 0x0:
1558 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1559 break;
1560 }
1561 } else {
1562 report = pcck_buf->cck_agc_rpt & 0x60;
1563 report >>= 5;
1564 switch (report) {
1565 case 0x3:
1566 rx_pwr_all = -35 -
1567 ((pcck_buf->cck_agc_rpt &
1568 0x1f) << 1);
1569 break;
1570 case 0x2:
1571 rx_pwr_all = -23 -
1572 ((pcck_buf->cck_agc_rpt &
1573 0x1f) << 1);
1574 break;
1575 case 0x1:
1576 rx_pwr_all = -11 -
1577 ((pcck_buf->cck_agc_rpt &
1578 0x1f) << 1);
1579 break;
1580 case 0x0:
1581 rx_pwr_all = -8 -
1582 ((pcck_buf->cck_agc_rpt &
1583 0x1f) << 1);
1584 break;
1585 }
1586 }
1587
1588 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1589 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1590 pstats->RecvSignalPower = rx_pwr_all;
1591
1592 if (bpacket_match_bssid) {
1593 u8 sq;
1594
1595 if (pstats->RxPWDBAll > 40) {
1596 sq = 100;
1597 } else {
1598 sq = pcck_buf->sq_rpt;
1599
1600 if (pcck_buf->sq_rpt > 64)
1601 sq = 0;
1602 else if (pcck_buf->sq_rpt < 20)
1603 sq = 100;
1604 else
1605 sq = ((64-sq) * 100) / 44;
1606 }
1607 pstats->SignalQuality = sq;
1608 precord_stats->SignalQuality = sq;
1609 pstats->RxMIMOSignalQuality[0] = sq;
1610 precord_stats->RxMIMOSignalQuality[0] = sq;
1611 pstats->RxMIMOSignalQuality[1] = -1;
1612 precord_stats->RxMIMOSignalQuality[1] = -1;
1613 }
1614 } else {
1615 priv->stats.numqry_phystatusHT++;
1616 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1617 if (priv->brfpath_rxenable[i])
1618 rf_rx_num++;
1619
1620 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1621 2) - 110;
1622
1623 tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1624 rx_snrX = (char)(tmp_rxsnr);
1625 rx_snrX /= 2;
1626 priv->stats.rxSNRdB[i] = (long)rx_snrX;
1627
1628 RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
1629 if (priv->brfpath_rxenable[i])
1630 total_rssi += RSSI;
1631
1632 if (bpacket_match_bssid) {
1633 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1634 precord_stats->RxMIMOSignalStrength[i] =
1635 (u8) RSSI;
1636 }
1637 }
1638
1639
1640 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1641 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1642
1643 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1644 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
1645 pstats->RecvSignalPower = rx_pwr_all;
1646 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1647 pdrvinfo->RxRate <= DESC90_RATEMCS15)
1648 max_spatial_stream = 2;
1649 else
1650 max_spatial_stream = 1;
1651
1652 for (i = 0; i < max_spatial_stream; i++) {
1653 tmp_rxevm = pofdm_buf->rxevm_X[i];
1654 rx_evmX = (char)(tmp_rxevm);
1655
1656 rx_evmX /= 2;
1657
1658 evm = rtl819x_evm_dbtopercentage(rx_evmX);
1659 if (bpacket_match_bssid) {
1660 if (i == 0) {
1661 pstats->SignalQuality = (u8)(evm &
1662 0xff);
1663 precord_stats->SignalQuality = (u8)(evm
1664 & 0xff);
1665 }
1666 pstats->RxMIMOSignalQuality[i] = (u8)(evm &
1667 0xff);
1668 precord_stats->RxMIMOSignalQuality[i] = (u8)(evm
1669 & 0xff);
1670 }
1671 }
1672
1673
1674 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1675 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1676 &rxsc_sgien_exflg;
1677 if (pdrvinfo->BW)
1678 priv->stats.received_bwtype[1+prxsc->rxsc]++;
1679 else
1680 priv->stats.received_bwtype[0]++;
1681 }
1682
1683 if (is_cck_rate) {
1684 pstats->SignalStrength = precord_stats->SignalStrength =
1685 (u8)(rtl8192_signal_scale_mapping(priv,
1686 (long)pwdb_all));
1687
1688 } else {
1689 if (rf_rx_num != 0)
1690 pstats->SignalStrength = precord_stats->SignalStrength =
1691 (u8)(rtl8192_signal_scale_mapping(priv,
1692 (long)(total_rssi /= rf_rx_num)));
1693 }
1694 }
1695
1696 static void rtl8192_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1697 struct rtllib_rx_stats *prev_st,
1698 struct rtllib_rx_stats *curr_st)
1699 {
1700 bool bcheck = false;
1701 u8 rfpath;
1702 u32 ij, tmp_val;
1703 static u32 slide_rssi_index, slide_rssi_statistics;
1704 static u32 slide_evm_index, slide_evm_statistics;
1705 static u32 last_rssi, last_evm;
1706 static u32 slide_beacon_adc_pwdb_index;
1707 static u32 slide_beacon_adc_pwdb_statistics;
1708 static u32 last_beacon_adc_pwdb;
1709 struct rtllib_hdr_3addr *hdr;
1710 u16 sc;
1711 unsigned int frag, seq;
1712
1713 hdr = (struct rtllib_hdr_3addr *)buffer;
1714 sc = le16_to_cpu(hdr->seq_ctl);
1715 frag = WLAN_GET_SEQ_FRAG(sc);
1716 seq = WLAN_GET_SEQ_SEQ(sc);
1717 curr_st->Seq_Num = seq;
1718 if (!prev_st->bIsAMPDU)
1719 bcheck = true;
1720
1721 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1722 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1723 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1724 priv->stats.slide_rssi_total -= last_rssi;
1725 }
1726 priv->stats.slide_rssi_total += prev_st->SignalStrength;
1727
1728 priv->stats.slide_signal_strength[slide_rssi_index++] =
1729 prev_st->SignalStrength;
1730 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1731 slide_rssi_index = 0;
1732
1733 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1734 priv->stats.signal_strength = rtl819x_translate_todbm(priv,
1735 (u8)tmp_val);
1736 curr_st->rssi = priv->stats.signal_strength;
1737 if (!prev_st->bPacketMatchBSSID) {
1738 if (!prev_st->bToSelfBA)
1739 return;
1740 }
1741
1742 if (!bcheck)
1743 return;
1744
1745 priv->stats.num_process_phyinfo++;
1746 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1747 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1748 if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
1749 continue;
1750 RT_TRACE(COMP_DBG,
1751 "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath] = %d\n",
1752 prev_st->RxMIMOSignalStrength[rfpath]);
1753 if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1754 priv->stats.rx_rssi_percentage[rfpath] =
1755 prev_st->RxMIMOSignalStrength[rfpath];
1756 }
1757 if (prev_st->RxMIMOSignalStrength[rfpath] >
1758 priv->stats.rx_rssi_percentage[rfpath]) {
1759 priv->stats.rx_rssi_percentage[rfpath] =
1760 ((priv->stats.rx_rssi_percentage[rfpath]
1761 * (RX_SMOOTH - 1)) +
1762 (prev_st->RxMIMOSignalStrength
1763 [rfpath])) / (RX_SMOOTH);
1764 priv->stats.rx_rssi_percentage[rfpath] =
1765 priv->stats.rx_rssi_percentage[rfpath]
1766 + 1;
1767 } else {
1768 priv->stats.rx_rssi_percentage[rfpath] =
1769 ((priv->stats.rx_rssi_percentage[rfpath] *
1770 (RX_SMOOTH-1)) +
1771 (prev_st->RxMIMOSignalStrength[rfpath])) /
1772 (RX_SMOOTH);
1773 }
1774 RT_TRACE(COMP_DBG,
1775 "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath] = %d\n",
1776 priv->stats.rx_rssi_percentage[rfpath]);
1777 }
1778 }
1779
1780
1781 if (prev_st->bPacketBeacon) {
1782 if (slide_beacon_adc_pwdb_statistics++ >=
1783 PHY_Beacon_RSSI_SLID_WIN_MAX) {
1784 slide_beacon_adc_pwdb_statistics =
1785 PHY_Beacon_RSSI_SLID_WIN_MAX;
1786 last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1787 [slide_beacon_adc_pwdb_index];
1788 priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1789 }
1790 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1791 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1792 prev_st->RxPWDBAll;
1793 slide_beacon_adc_pwdb_index++;
1794 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1795 slide_beacon_adc_pwdb_index = 0;
1796 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1797 slide_beacon_adc_pwdb_statistics;
1798 if (prev_st->RxPWDBAll >= 3)
1799 prev_st->RxPWDBAll -= 3;
1800 }
1801
1802 RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1803 prev_st->bIsCCK ? "CCK" : "OFDM",
1804 prev_st->RxPWDBAll);
1805
1806 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1807 prev_st->bToSelfBA) {
1808 if (priv->undecorated_smoothed_pwdb < 0)
1809 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1810 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1811 priv->undecorated_smoothed_pwdb =
1812 (((priv->undecorated_smoothed_pwdb) *
1813 (RX_SMOOTH-1)) +
1814 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1815 priv->undecorated_smoothed_pwdb =
1816 priv->undecorated_smoothed_pwdb + 1;
1817 } else {
1818 priv->undecorated_smoothed_pwdb =
1819 (((priv->undecorated_smoothed_pwdb) *
1820 (RX_SMOOTH-1)) +
1821 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1822 }
1823 rtl819x_update_rxsignalstatistics8190pci(priv, prev_st);
1824 }
1825
1826 if (prev_st->SignalQuality != 0) {
1827 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1828 prev_st->bToSelfBA) {
1829 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1830 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1831 last_evm =
1832 priv->stats.slide_evm[slide_evm_index];
1833 priv->stats.slide_evm_total -= last_evm;
1834 }
1835
1836 priv->stats.slide_evm_total += prev_st->SignalQuality;
1837
1838 priv->stats.slide_evm[slide_evm_index++] =
1839 prev_st->SignalQuality;
1840 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1841 slide_evm_index = 0;
1842
1843 tmp_val = priv->stats.slide_evm_total /
1844 slide_evm_statistics;
1845 priv->stats.signal_quality = tmp_val;
1846 priv->stats.last_signal_strength_inpercent = tmp_val;
1847 }
1848
1849 if (prev_st->bPacketToSelf ||
1850 prev_st->bPacketBeacon ||
1851 prev_st->bToSelfBA) {
1852 for (ij = 0; ij < 2; ij++) {
1853 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1854 if (priv->stats.rx_evm_percentage[ij] == 0)
1855 priv->stats.rx_evm_percentage[ij] =
1856 prev_st->RxMIMOSignalQuality[ij];
1857 priv->stats.rx_evm_percentage[ij] =
1858 ((priv->stats.rx_evm_percentage[ij] *
1859 (RX_SMOOTH - 1)) +
1860 (prev_st->RxMIMOSignalQuality[ij])) /
1861 (RX_SMOOTH);
1862 }
1863 }
1864 }
1865 }
1866 }
1867
1868 static void rtl8192_TranslateRxSignalStuff(struct net_device *dev,
1869 struct sk_buff *skb,
1870 struct rtllib_rx_stats *pstats,
1871 struct rx_desc *pdesc,
1872 struct rx_fwinfo *pdrvinfo)
1873 {
1874 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1875 bool bpacket_match_bssid, bpacket_toself;
1876 bool bPacketBeacon = false;
1877 struct rtllib_hdr_3addr *hdr;
1878 bool bToSelfBA = false;
1879 static struct rtllib_rx_stats previous_stats;
1880 u16 fc, type;
1881 u8 *tmp_buf;
1882 u8 *praddr;
1883
1884 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1885
1886 hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1887 fc = le16_to_cpu(hdr->frame_ctl);
1888 type = WLAN_FC_GET_TYPE(fc);
1889 praddr = hdr->addr1;
1890
1891 bpacket_match_bssid =
1892 ((RTLLIB_FTYPE_CTL != type) &&
1893 ether_addr_equal(priv->rtllib->current_network.bssid,
1894 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1895 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1896 hdr->addr3) &&
1897 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1898 bpacket_toself = bpacket_match_bssid && /* check this */
1899 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1900 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1901 bPacketBeacon = true;
1902 if (bpacket_match_bssid)
1903 priv->stats.numpacket_matchbssid++;
1904 if (bpacket_toself)
1905 priv->stats.numpacket_toself++;
1906 rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1907 rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1908 &previous_stats, bpacket_match_bssid,
1909 bpacket_toself, bPacketBeacon, bToSelfBA);
1910 rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
1911 }
1912
1913 static void rtl8192_UpdateReceivedRateHistogramStatistics(
1914 struct net_device *dev,
1915 struct rtllib_rx_stats *pstats)
1916 {
1917 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1918 u32 rcvType = 1;
1919 u32 rateIndex;
1920 u32 preamble_guardinterval;
1921
1922 if (pstats->bCRC)
1923 rcvType = 2;
1924 else if (pstats->bICV)
1925 rcvType = 3;
1926
1927 if (pstats->bShortPreamble)
1928 preamble_guardinterval = 1;
1929 else
1930 preamble_guardinterval = 0;
1931
1932 switch (pstats->rate) {
1933 case MGN_1M:
1934 rateIndex = 0;
1935 break;
1936 case MGN_2M:
1937 rateIndex = 1;
1938 break;
1939 case MGN_5_5M:
1940 rateIndex = 2;
1941 break;
1942 case MGN_11M:
1943 rateIndex = 3;
1944 break;
1945 case MGN_6M:
1946 rateIndex = 4;
1947 break;
1948 case MGN_9M:
1949 rateIndex = 5;
1950 break;
1951 case MGN_12M:
1952 rateIndex = 6;
1953 break;
1954 case MGN_18M:
1955 rateIndex = 7;
1956 break;
1957 case MGN_24M:
1958 rateIndex = 8;
1959 break;
1960 case MGN_36M:
1961 rateIndex = 9;
1962 break;
1963 case MGN_48M:
1964 rateIndex = 10;
1965 break;
1966 case MGN_54M:
1967 rateIndex = 11;
1968 break;
1969 case MGN_MCS0:
1970 rateIndex = 12;
1971 break;
1972 case MGN_MCS1:
1973 rateIndex = 13;
1974 break;
1975 case MGN_MCS2:
1976 rateIndex = 14;
1977 break;
1978 case MGN_MCS3:
1979 rateIndex = 15;
1980 break;
1981 case MGN_MCS4:
1982 rateIndex = 16;
1983 break;
1984 case MGN_MCS5:
1985 rateIndex = 17;
1986 break;
1987 case MGN_MCS6:
1988 rateIndex = 18;
1989 break;
1990 case MGN_MCS7:
1991 rateIndex = 19;
1992 break;
1993 case MGN_MCS8:
1994 rateIndex = 20;
1995 break;
1996 case MGN_MCS9:
1997 rateIndex = 21;
1998 break;
1999 case MGN_MCS10:
2000 rateIndex = 22;
2001 break;
2002 case MGN_MCS11:
2003 rateIndex = 23;
2004 break;
2005 case MGN_MCS12:
2006 rateIndex = 24;
2007 break;
2008 case MGN_MCS13:
2009 rateIndex = 25;
2010 break;
2011 case MGN_MCS14:
2012 rateIndex = 26;
2013 break;
2014 case MGN_MCS15:
2015 rateIndex = 27;
2016 break;
2017 default:
2018 rateIndex = 28;
2019 break;
2020 }
2021 priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2022 priv->stats.received_rate_histogram[0][rateIndex]++;
2023 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2024 }
2025
2026 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
2027 struct rx_desc *pdesc, struct sk_buff *skb)
2028 {
2029 struct r8192_priv *priv = rtllib_priv(dev);
2030 struct rx_fwinfo *pDrvInfo = NULL;
2031
2032 stats->bICV = pdesc->ICV;
2033 stats->bCRC = pdesc->CRC32;
2034 stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2035
2036 stats->Length = pdesc->Length;
2037 if (stats->Length < 24)
2038 stats->bHwError |= 1;
2039
2040 if (stats->bHwError) {
2041 stats->bShift = false;
2042
2043 if (pdesc->CRC32) {
2044 if (pdesc->Length < 500)
2045 priv->stats.rxcrcerrmin++;
2046 else if (pdesc->Length > 1000)
2047 priv->stats.rxcrcerrmax++;
2048 else
2049 priv->stats.rxcrcerrmid++;
2050 }
2051 return false;
2052 }
2053
2054 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2055 stats->RxBufShift = ((pdesc->Shift)&0x03);
2056 stats->Decrypted = !pdesc->SWDec;
2057
2058 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2059
2060 stats->rate = HwRateToMRate90((bool)pDrvInfo->RxHT,
2061 (u8)pDrvInfo->RxRate);
2062 stats->bShortPreamble = pDrvInfo->SPLCP;
2063
2064 rtl8192_UpdateReceivedRateHistogramStatistics(dev, stats);
2065
2066 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2067 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2068 (pDrvInfo->FirstAGGR == 1);
2069
2070 stats->TimeStampLow = pDrvInfo->TSFL;
2071 stats->TimeStampHigh = read_nic_dword(dev, TSFR+4);
2072
2073 rtl819x_UpdateRxPktTimeStamp(dev, stats);
2074
2075 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2076 stats->bShift = 1;
2077
2078 stats->RxIs40MHzPacket = pDrvInfo->BW;
2079
2080 rtl8192_TranslateRxSignalStuff(dev, skb, stats, pdesc,
2081 pDrvInfo);
2082
2083 if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2084 RT_TRACE(COMP_RXDESC,
2085 "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2086 pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2087 skb_trim(skb, skb->len - 4/*sCrcLng*/);
2088
2089
2090 stats->packetlength = stats->Length-4;
2091 stats->fraglength = stats->packetlength;
2092 stats->fragoffset = 0;
2093 stats->ntotalfrag = 1;
2094 return true;
2095 }
2096
2097 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
2098 {
2099 struct r8192_priv *priv = rtllib_priv(dev);
2100 int i;
2101 u8 OpMode;
2102 u8 u1bTmp;
2103 u32 ulRegRead;
2104
2105 OpMode = RT_OP_MODE_NO_LINK;
2106 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2107
2108 if (!priv->rtllib->bSupportRemoteWakeUp) {
2109 u1bTmp = 0x0;
2110 write_nic_byte(dev, CMDR, u1bTmp);
2111 }
2112
2113 mdelay(20);
2114
2115 if (!reset) {
2116 mdelay(150);
2117
2118 priv->bHwRfOffAction = 2;
2119
2120 if (!priv->rtllib->bSupportRemoteWakeUp) {
2121 rtl92e_set_rf_off(dev);
2122 ulRegRead = read_nic_dword(dev, CPU_GEN);
2123 ulRegRead |= CPU_GEN_SYSTEM_RESET;
2124 write_nic_dword(dev, CPU_GEN, ulRegRead);
2125 } else {
2126 write_nic_dword(dev, WFCRC0, 0xffffffff);
2127 write_nic_dword(dev, WFCRC1, 0xffffffff);
2128 write_nic_dword(dev, WFCRC2, 0xffffffff);
2129
2130
2131 write_nic_byte(dev, PMR, 0x5);
2132 write_nic_byte(dev, MacBlkCtrl, 0xa);
2133 }
2134 }
2135
2136 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2137 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2138 for (i = 0; i < MAX_QUEUE_SIZE; i++)
2139 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2140
2141 skb_queue_purge(&priv->skb_queue);
2142 }
2143
2144 void rtl92e_update_ratr_table(struct net_device *dev)
2145 {
2146 struct r8192_priv *priv = rtllib_priv(dev);
2147 struct rtllib_device *ieee = priv->rtllib;
2148 u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2149 u32 ratr_value = 0;
2150 u16 rate_config = 0;
2151 u8 rate_index = 0;
2152
2153 rtl8192_config_rate(dev, &rate_config);
2154 ratr_value = rate_config | *pMcsRate << 12;
2155 switch (ieee->mode) {
2156 case IEEE_A:
2157 ratr_value &= 0x00000FF0;
2158 break;
2159 case IEEE_B:
2160 ratr_value &= 0x0000000F;
2161 break;
2162 case IEEE_G:
2163 case IEEE_G|IEEE_B:
2164 ratr_value &= 0x00000FF7;
2165 break;
2166 case IEEE_N_24G:
2167 case IEEE_N_5G:
2168 if (ieee->pHTInfo->PeerMimoPs == 0) {
2169 ratr_value &= 0x0007F007;
2170 } else {
2171 if (priv->rf_type == RF_1T2R)
2172 ratr_value &= 0x000FF007;
2173 else
2174 ratr_value &= 0x0F81F007;
2175 }
2176 break;
2177 default:
2178 break;
2179 }
2180 ratr_value &= 0x0FFFFFFF;
2181 if (ieee->pHTInfo->bCurTxBW40MHz &&
2182 ieee->pHTInfo->bCurShortGI40MHz)
2183 ratr_value |= 0x80000000;
2184 else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2185 ieee->pHTInfo->bCurShortGI20MHz)
2186 ratr_value |= 0x80000000;
2187 write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
2188 write_nic_byte(dev, UFWP, 1);
2189 }
2190
2191 void
2192 rtl92e_init_variables(struct net_device *dev)
2193 {
2194 struct r8192_priv *priv = rtllib_priv(dev);
2195
2196 strcpy(priv->nick, "rtl8192E");
2197
2198 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN |
2199 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2200 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2201
2202 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2203
2204 priv->ShortRetryLimit = 0x30;
2205 priv->LongRetryLimit = 0x30;
2206
2207 priv->ReceiveConfig = RCR_ADD3 |
2208 RCR_AMF | RCR_ADF |
2209 RCR_AICV |
2210 RCR_AB | RCR_AM | RCR_APM |
2211 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2212 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2213
2214 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2215 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2216 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2217 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2218 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2219 IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2220
2221 priv->PwrDomainProtect = false;
2222
2223 priv->bfirst_after_down = false;
2224 }
2225
2226 void rtl92e_enable_irq(struct net_device *dev)
2227 {
2228 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2229
2230 priv->irq_enabled = 1;
2231
2232 write_nic_dword(dev, INTA_MASK, priv->irq_mask[0]);
2233
2234 }
2235
2236 void rtl92e_disable_irq(struct net_device *dev)
2237 {
2238 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2239
2240 write_nic_dword(dev, INTA_MASK, 0);
2241
2242 priv->irq_enabled = 0;
2243 }
2244
2245 void rtl92e_clear_irq(struct net_device *dev)
2246 {
2247 u32 tmp = 0;
2248
2249 tmp = read_nic_dword(dev, ISR);
2250 write_nic_dword(dev, ISR, tmp);
2251 }
2252
2253
2254 void rtl92e_enable_rx(struct net_device *dev)
2255 {
2256 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2257
2258 write_nic_dword(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2259 }
2260
2261 static const u32 TX_DESC_BASE[] = {
2262 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2263 };
2264
2265 void rtl92e_enable_tx(struct net_device *dev)
2266 {
2267 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2268 u32 i;
2269
2270 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2271 write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2272 }
2273
2274
2275 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb)
2276 {
2277 *p_inta = read_nic_dword(dev, ISR);
2278 write_nic_dword(dev, ISR, *p_inta);
2279 }
2280
2281 bool rtl92e_is_rx_stuck(struct net_device *dev)
2282 {
2283 struct r8192_priv *priv = rtllib_priv(dev);
2284 u16 RegRxCounter = read_nic_word(dev, 0x130);
2285 bool bStuck = false;
2286 static u8 rx_chk_cnt;
2287 u32 SlotIndex = 0, TotalRxStuckCount = 0;
2288 u8 i;
2289 u8 SilentResetRxSoltNum = 4;
2290
2291 RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2292 __func__, RegRxCounter, priv->RxCounter);
2293
2294 rx_chk_cnt++;
2295 if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2296 rx_chk_cnt = 0;
2297 } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2298 && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2299 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2300 || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2301 (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2302 if (rx_chk_cnt < 2)
2303 return bStuck;
2304 rx_chk_cnt = 0;
2305 } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2306 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2307 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2308 (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2309 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2310 if (rx_chk_cnt < 4)
2311 return bStuck;
2312 rx_chk_cnt = 0;
2313 } else {
2314 if (rx_chk_cnt < 8)
2315 return bStuck;
2316 rx_chk_cnt = 0;
2317 }
2318
2319
2320 SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2321
2322 if (priv->RxCounter == RegRxCounter) {
2323 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2324
2325 for (i = 0; i < SilentResetRxSoltNum; i++)
2326 TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2327
2328 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2329 bStuck = true;
2330 for (i = 0; i < SilentResetRxSoltNum; i++)
2331 TotalRxStuckCount +=
2332 priv->SilentResetRxStuckEvent[i];
2333 }
2334
2335
2336 } else {
2337 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2338 }
2339
2340 priv->RxCounter = RegRxCounter;
2341
2342 return bStuck;
2343 }
2344
2345 bool rtl92e_is_tx_stuck(struct net_device *dev)
2346 {
2347 struct r8192_priv *priv = rtllib_priv(dev);
2348 bool bStuck = false;
2349 u16 RegTxCounter = read_nic_word(dev, 0x128);
2350
2351 RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2352 __func__, RegTxCounter, priv->TxCounter);
2353
2354 if (priv->TxCounter == RegTxCounter)
2355 bStuck = true;
2356
2357 priv->TxCounter = RegTxCounter;
2358
2359 return bStuck;
2360 }
2361
2362 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
2363 {
2364 struct r8192_priv *priv = rtllib_priv(dev);
2365 struct rtllib_device *ieee = priv->rtllib;
2366
2367 if (ieee->rtllib_ap_sec_type &&
2368 (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2369 SEC_ALG_TKIP))) {
2370 return false;
2371 } else {
2372 return true;
2373 }
2374 }
2375
2376 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
2377 {
2378 bool Reval;
2379 struct r8192_priv *priv = rtllib_priv(dev);
2380 struct rtllib_device *ieee = priv->rtllib;
2381
2382 if (ieee->bHalfWirelessN24GMode == true)
2383 Reval = true;
2384 else
2385 Reval = false;
2386
2387 return Reval;
2388 }
2389
2390 void ActUpdateChannelAccessSetting(struct net_device *dev,
2391 enum wireless_mode WirelessMode,
2392 struct channel_access_setting *ChnlAccessSetting)
2393 {
2394 }
Linux kernel - Deliverables
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