drivers/staging/rtl8192u/r819xU_cmdpkt.h

   1 #ifndef R819XUSB_CMDPKT_H
   2 #define R819XUSB_CMDPKT_H
   3 /* Different command packet have dedicated message length and definition. */
   4 #define         CMPK_RX_TX_FB_SIZE                                      sizeof(cmpk_txfb_t)             //20
   5 #define         CMPK_TX_SET_CONFIG_SIZE                         sizeof(cmpk_set_cfg_t)  //16
   6 #define         CMPK_BOTH_QUERY_CONFIG_SIZE                     sizeof(cmpk_set_cfg_t)  //16
   7 #define         CMPK_RX_TX_STS_SIZE                                     sizeof(cmpk_tx_status_t)//
   8 #define         CMPK_RX_DBG_MSG_SIZE                    sizeof(cmpk_rx_dbginfo_t)//
   9 #define         CMPK_TX_RAHIS_SIZE                      sizeof(cmpk_tx_rahis_t)
  10
  11 /* 2008/05/08 amy For USB constant. */
  12 #define ISR_TxBcnOk                                     BIT27                   // Transmit Beacon OK
  13 #define ISR_TxBcnErr                            BIT26                   // Transmit Beacon Error
  14 #define ISR_BcnTimerIntr                        BIT13                   // Beacon Timer Interrupt
  15
  16
  17 /* Define element ID of command packet. */
  18
  19 /*------------------------------Define structure----------------------------*/
  20 /* Define different command packet structure. */
  21 /* 1. RX side: TX feedback packet. */
  22 typedef struct tag_cmd_pkt_tx_feedback {
  23         // DWORD 0
  24         u8      element_id;                     /* Command packet type. */
  25         u8      length;                         /* Command packet length. */
  26         /* 2007/07/05 MH Change tx feedback info field. */
  27         /*------TX Feedback Info Field */
  28         u8      TID:4;                          /* */
  29         u8      fail_reason:3;          /* */
  30         u8      tok:1;                          /* Transmit ok. */
  31         u8      reserve1:4;                     /* */
  32         u8      pkt_type:2;             /* */
  33         u8      bandwidth:1;            /* */
  34         u8      qos_pkt:1;                      /* */
  35
  36         // DWORD 1
  37         u8      reserve2;                       /* */
  38         /*------TX Feedback Info Field */
  39         u8      retry_cnt;                      /* */
  40         u16     pkt_id;                         /* */
  41
  42         // DWORD 3
  43         u16     seq_num;                        /* */
  44         u8      s_rate;                         /* Start rate. */
  45         u8      f_rate;                         /* Final rate. */
  46
  47         // DWORD 4
  48         u8      s_rts_rate;                     /* */
  49         u8      f_rts_rate;                     /* */
  50         u16     pkt_length;                     /* */
  51
  52         // DWORD 5
  53         u16     reserve3;                       /* */
  54         u16     duration;                       /* */
  55 }cmpk_txfb_t;
  56
  57 /* 2. RX side: Interrupt status packet. It includes Beacon State,
  58           Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */
  59 typedef struct tag_cmd_pkt_interrupt_status {
  60         u8      element_id;                     /* Command packet type. */
  61         u8      length;                         /* Command packet length. */
  62         u16     reserve;
  63         u32     interrupt_status;                               /* Interrupt Status. */
  64 }cmpk_intr_sta_t;
  65
  66
  67 /* 3. TX side: Set configuration packet. */
  68 typedef struct tag_cmd_pkt_set_configuration {
  69         u8      element_id;                     /* Command packet type. */
  70         u8      length;                         /* Command packet length. */
  71         u16     reserve1;                       /* */
  72         u8      cfg_reserve1:3;
  73         u8      cfg_size:2;                     /* Configuration info. */
  74         u8      cfg_type:2;                     /* Configuration info. */
  75         u8      cfg_action:1;           /* Configuration info. */
  76         u8      cfg_reserve2;           /* Configuration info. */
  77         u8      cfg_page:4;                     /* Configuration info. */
  78         u8      cfg_reserve3:4;         /* Configuration info. */
  79         u8      cfg_offset;                     /* Configuration info. */
  80         u32     value;                          /* */
  81         u32     mask;                           /* */
  82 }cmpk_set_cfg_t;
  83
  84 /* 4. Both side : TX/RX query configuraton packet. The query structure is the
  85       same as set configuration. */
  86 #define         cmpk_query_cfg_t        cmpk_set_cfg_t
  87
  88 /* 5. Multi packet feedback status. */
  89 typedef struct tag_tx_stats_feedback { // PJ quick rxcmd 09042007
  90         // For endian transfer --> Driver will not the same as firmware structure.
  91         // DW 0
  92         u16     reserve1;
  93         u8      length;                         // Command packet length
  94         u8      element_id;                     // Command packet type
  95
  96         // DW 1
  97         u16     txfail;                         // Tx Fail count
  98         u16     txok;                           // Tx ok count
  99
 100         // DW 2
 101         u16     txmcok;                         // tx multicast
 102         u16     txretry;                        // Tx Retry count
 103
 104         // DW 3
 105         u16  txucok;                            // tx unicast
 106         u16     txbcok;                         // tx broadcast
 107
 108         // DW 4
 109         u16     txbcfail;                       //
 110         u16     txmcfail;                       //
 111
 112         // DW 5
 113         u16     reserve2;                       //
 114         u16     txucfail;                       //
 115
 116         // DW 6-8
 117         u32     txmclength;
 118         u32     txbclength;
 119         u32     txuclength;
 120
 121         // DW 9
 122         u16     reserve3_23;
 123         u8      reserve3_1;
 124         u8      rate;
 125 }__attribute__((packed)) cmpk_tx_status_t;
 126
 127 /* 6. Debug feedback message. */
 128 /* 2007/10/23 MH Define RX debug message  */
 129 typedef struct tag_rx_debug_message_feedback {
 130         // For endian transfer --> for driver
 131         // DW 0
 132         u16     reserve1;
 133         u8      length;                         // Command packet length
 134         u8      element_id;                     // Command packet type
 135
 136         // DW 1-??
 137         // Variable debug message.
 138
 139 }cmpk_rx_dbginfo_t;
 140
 141 /* 2008/03/20 MH Define transmit rate history. For big endian format. */
 142 typedef struct tag_tx_rate_history {
 143         // For endian transfer --> for driver
 144         // DW 0
 145         u8      element_id;                     // Command packet type
 146         u8      length;                         // Command packet length
 147         u16     reserved1;
 148
 149         // DW 1-2       CCK rate counter
 150         u16     cck[4];
 151
 152         // DW 3-6
 153         u16     ofdm[8];
 154
 155         // DW 7-14
 156         //UINT16        MCS_BW0_SG0[16];
 157
 158         // DW 15-22
 159         //UINT16        MCS_BW1_SG0[16];
 160
 161         // DW 23-30
 162         //UINT16        MCS_BW0_SG1[16];
 163
 164         // DW 31-38
 165         //UINT16        MCS_BW1_SG1[16];
 166
 167         // DW 7-14      BW=0 SG=0
 168         // DW 15-22     BW=1 SG=0
 169         // DW 23-30     BW=0 SG=1
 170         // DW 31-38     BW=1 SG=1
 171         u16     ht_mcs[4][16];
 172
 173 }__attribute__((packed)) cmpk_tx_rahis_t;
 174
 175 typedef enum tag_command_packet_directories
 176 {
 177     RX_TX_FEEDBACK = 0,
 178     RX_INTERRUPT_STATUS         = 1,
 179     TX_SET_CONFIG                               = 2,
 180     BOTH_QUERY_CONFIG                   = 3,
 181     RX_TX_STATUS                                = 4,
 182     RX_DBGINFO_FEEDBACK         = 5,
 183     RX_TX_PER_PKT_FEEDBACK              = 6,
 184     RX_TX_RATE_HISTORY          = 7,
 185     RX_CMD_ELE_MAX
 186 }cmpk_element_e;
 187
 188 typedef enum _rt_status{
 189         RT_STATUS_SUCCESS,
 190         RT_STATUS_FAILURE,
 191         RT_STATUS_PENDING,
 192         RT_STATUS_RESOURCE
 193 }rt_status,*prt_status;
 194
 195 extern rt_status cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
 196
 197 extern  u32 cmpk_message_handle_rx(struct net_device *dev, struct ieee80211_rx_stats * pstats);
 198 extern rt_status SendTxCommandPacket( struct net_device *dev, void* pData, u32 DataLen);
 199
 200
 201 #endif