drivers/staging/rtl8192u/r819xU_cmdpkt.h

   1 #ifndef R819XUSB_CMDPKT_H
   2 #define R819XUSB_CMDPKT_H
   3 /* Different command packet have dedicated message length and definition. */
   4 #define         CMPK_RX_TX_FB_SIZE              sizeof(cmpk_txfb_t)     /* 20 */
   5 #define         CMPK_TX_SET_CONFIG_SIZE         sizeof(cmpk_set_cfg_t)  /* 16 */
   6 #define         CMPK_BOTH_QUERY_CONFIG_SIZE     sizeof(cmpk_set_cfg_t)  /* 16 */
   7 #define         CMPK_RX_TX_STS_SIZE             sizeof(cmpk_tx_status_t)
   8 #define         CMPK_RX_DBG_MSG_SIZE            sizeof(cmpk_rx_dbginfo_t)
   9 #define         CMPK_TX_RAHIS_SIZE              sizeof(cmpk_tx_rahis_t)
  10
  11 /* 2008/05/08 amy For USB constant. */
  12 #define ISR_TxBcnOk             BIT(27)         /* Transmit Beacon OK */
  13 #define ISR_TxBcnErr            BIT(26)         /* Transmit Beacon Error */
  14 #define ISR_BcnTimerIntr        BIT(13)         /* Beacon Timer Interrupt */
  15
  16
  17 /* Define element ID of command packet. */
  18
  19 /*------------------------------Define structure----------------------------*/
  20 /* Define different command packet structure. */
  21 /* 1. RX side: TX feedback packet. */
  22 typedef struct tag_cmd_pkt_tx_feedback {
  23         /* DWORD 0 */
  24         u8      element_id;                     /* Command packet type. */
  25         u8      length;                         /* Command packet length. */
  26         /* Change tx feedback info field. */
  27         /*------TX Feedback Info Field */
  28         u8      TID:4;
  29         u8      fail_reason:3;
  30         u8      tok:1;                          /* Transmit ok. */
  31         u8      reserve1:4;
  32         u8      pkt_type:2;
  33         u8      bandwidth:1;
  34         u8      qos_pkt:1;
  35
  36         /* DWORD 1 */
  37         u8      reserve2;
  38         /*------TX Feedback Info Field */
  39         u8      retry_cnt;
  40         u16     pkt_id;
  41
  42         /* DWORD 3 */
  43         u16     seq_num;
  44         u8      s_rate;                         /* Start rate. */
  45         u8      f_rate;                         /* Final rate. */
  46
  47         /* DWORD 4 */
  48         u8      s_rts_rate;
  49         u8      f_rts_rate;
  50         u16     pkt_length;
  51
  52         /* DWORD 5 */
  53         u16     reserve3;
  54         u16     duration;
  55 } cmpk_txfb_t;
  56
  57 /* 2. RX side: Interrupt status packet. It includes Beacon State,
  58  * Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */
  59 typedef struct tag_cmd_pkt_interrupt_status {
  60         u8      element_id;                     /* Command packet type. */
  61         u8      length;                         /* Command packet length. */
  62         u16     reserve;
  63         u32     interrupt_status;               /* Interrupt Status. */
  64 } cmpk_intr_sta_t;
  65
  66
  67 /* 3. TX side: Set configuration packet. */
  68 typedef struct tag_cmd_pkt_set_configuration {
  69         u8      element_id;                     /* Command packet type. */
  70         u8      length;                         /* Command packet length. */
  71         u16     reserve1;
  72         /* Configuration info. */
  73         u8      cfg_reserve1:3;
  74         u8      cfg_size:2;
  75         u8      cfg_type:2;
  76         u8      cfg_action:1;
  77         u8      cfg_reserve2;
  78         u8      cfg_page:4;
  79         u8      cfg_reserve3:4;
  80         u8      cfg_offset;
  81         u32     value;
  82         u32     mask;
  83 } cmpk_set_cfg_t;
  84
  85 /* 4. Both side : TX/RX query configuraton packet. The query structure is the
  86       same as set configuration. */
  87 #define         cmpk_query_cfg_t        cmpk_set_cfg_t
  88
  89 /* 5. Multi packet feedback status. */
  90 typedef struct tag_tx_stats_feedback {
  91         /* For endian transfer --> Driver will not the same as
  92            firmware structure. */
  93         /* DW 0 */
  94         u16     reserve1;
  95         u8      length;                         /* Command packet length */
  96         u8      element_id;                     /* Command packet type */
  97
  98         /* DW 1 */
  99         u16     txfail;                         /* Tx fail count */
 100         u16     txok;                           /* Tx ok count */
 101
 102         /* DW 2 */
 103         u16     txmcok;                         /* Tx multicast */
 104         u16     txretry;                        /* Tx retry count */
 105
 106         /* DW 3 */
 107         u16     txucok;                         /* Tx unicast */
 108         u16     txbcok;                         /* Tx broadcast */
 109
 110         /* DW 4 */
 111         u16     txbcfail;
 112         u16     txmcfail;
 113
 114         /* DW 5 */
 115         u16     reserve2;
 116         u16     txucfail;
 117
 118         /* DW 6-8 */
 119         u32     txmclength;
 120         u32     txbclength;
 121         u32     txuclength;
 122
 123         /* DW 9 */
 124         u16     reserve3_23;
 125         u8      reserve3_1;
 126         u8      rate;
 127 } __packed cmpk_tx_status_t;
 128
 129 /* 6. Debug feedback message. */
 130 /* Define RX debug message  */
 131 typedef struct tag_rx_debug_message_feedback {
 132         /* For endian transfer --> for driver */
 133         /* DW 0 */
 134         u16     reserve1;
 135         u8      length;                         /* Command packet length */
 136         u8      element_id;                     /* Command packet type */
 137
 138         /* DW 1-?? */
 139         /* Variable debug message. */
 140
 141 } cmpk_rx_dbginfo_t;
 142
 143 /* Define transmit rate history. For big endian format. */
 144 typedef struct tag_tx_rate_history {
 145         /* For endian transfer --> for driver */
 146         /* DW 0 */
 147         u8      element_id;                     /* Command packet type */
 148         u8      length;                         /* Command packet length */
 149         u16     reserved1;
 150
 151         /* DW 1-2       CCK rate counter */
 152         u16     cck[4];
 153
 154         /* DW 3-6 */
 155         u16     ofdm[8];
 156
 157         /* DW 7-14      BW=0 SG=0
 158          * DW 15-22     BW=1 SG=0
 159          * DW 23-30     BW=0 SG=1
 160          * DW 31-38     BW=1 SG=1
 161          */
 162         u16     ht_mcs[4][16];
 163
 164 } __packed cmpk_tx_rahis_t;
 165
 166 typedef enum tag_command_packet_directories {
 167         RX_TX_FEEDBACK                  = 0,
 168         RX_INTERRUPT_STATUS             = 1,
 169         TX_SET_CONFIG                   = 2,
 170         BOTH_QUERY_CONFIG               = 3,
 171         RX_TX_STATUS                    = 4,
 172         RX_DBGINFO_FEEDBACK             = 5,
 173         RX_TX_PER_PKT_FEEDBACK          = 6,
 174         RX_TX_RATE_HISTORY              = 7,
 175         RX_CMD_ELE_MAX
 176 } cmpk_element_e;
 177
 178 typedef enum _rt_status {
 179         RT_STATUS_SUCCESS,
 180         RT_STATUS_FAILURE,
 181         RT_STATUS_PENDING,
 182         RT_STATUS_RESOURCE
 183 } rt_status, *prt_status;
 184
 185 u32 cmpk_message_handle_rx(struct net_device *dev,
 186                            struct ieee80211_rx_stats *pstats);
 187 rt_status SendTxCommandPacket(struct net_device *dev,
 188                               void *pData, u32 DataLen);
 189
 190
 191 #endif