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drm/radeon: make sure vertical front porch is at least 1
[deliverable/linux.git] / drivers / staging / rts5208 / ms.c
1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/vmalloc.h>
27
28 #include "rtsx.h"
29 #include "ms.h"
30
31 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code)
32 {
33 struct ms_info *ms_card = &chip->ms_card;
34
35 ms_card->err_code = err_code;
36 }
37
38 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code)
39 {
40 struct ms_info *ms_card = &chip->ms_card;
41
42 return (ms_card->err_code == err_code);
43 }
44
45 static int ms_parse_err_code(struct rtsx_chip *chip)
46 {
47 rtsx_trace(chip);
48 return STATUS_FAIL;
49 }
50
51 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode,
52 u8 tpc, u8 cnt, u8 cfg)
53 {
54 struct ms_info *ms_card = &chip->ms_card;
55 int retval;
56 u8 *ptr;
57
58 dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc);
59
60 rtsx_init_cmd(chip);
61
62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
65 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
66 0x01, PINGPONG_BUFFER);
67
68 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER,
69 0xFF, MS_TRANSFER_START | trans_mode);
70 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
71 MS_TRANSFER_END, MS_TRANSFER_END);
72
73 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
74
75 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
76 if (retval < 0) {
77 rtsx_clear_ms_error(chip);
78 ms_set_err_code(chip, MS_TO_ERROR);
79 rtsx_trace(chip);
80 return ms_parse_err_code(chip);
81 }
82
83 ptr = rtsx_get_cmd_data(chip) + 1;
84
85 if (!(tpc & 0x08)) { /* Read Packet */
86 if (*ptr & MS_CRC16_ERR) {
87 ms_set_err_code(chip, MS_CRC16_ERROR);
88 rtsx_trace(chip);
89 return ms_parse_err_code(chip);
90 }
91 } else { /* Write Packet */
92 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) {
93 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) {
94 ms_set_err_code(chip, MS_CMD_NK);
95 rtsx_trace(chip);
96 return ms_parse_err_code(chip);
97 }
98 }
99 }
100
101 if (*ptr & MS_RDY_TIMEOUT) {
102 rtsx_clear_ms_error(chip);
103 ms_set_err_code(chip, MS_TO_ERROR);
104 rtsx_trace(chip);
105 return ms_parse_err_code(chip);
106 }
107
108 return STATUS_SUCCESS;
109 }
110
111 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode,
112 u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k,
113 int use_sg, void *buf, int buf_len)
114 {
115 int retval;
116 u8 val, err_code = 0;
117 enum dma_data_direction dir;
118
119 if (!buf || !buf_len) {
120 rtsx_trace(chip);
121 return STATUS_FAIL;
122 }
123
124 if (trans_mode == MS_TM_AUTO_READ) {
125 dir = DMA_FROM_DEVICE;
126 err_code = MS_FLASH_READ_ERROR;
127 } else if (trans_mode == MS_TM_AUTO_WRITE) {
128 dir = DMA_TO_DEVICE;
129 err_code = MS_FLASH_WRITE_ERROR;
130 } else {
131 rtsx_trace(chip);
132 return STATUS_FAIL;
133 }
134
135 rtsx_init_cmd(chip);
136
137 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
138 rtsx_add_cmd(chip, WRITE_REG_CMD,
139 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8));
140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt);
141 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
142
143 if (mode_2k) {
144 rtsx_add_cmd(chip, WRITE_REG_CMD,
145 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE);
146 } else {
147 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0);
148 }
149
150 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
151
152 rtsx_add_cmd(chip, WRITE_REG_CMD,
153 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
154 rtsx_add_cmd(chip, CHECK_REG_CMD,
155 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
156
157 rtsx_send_cmd_no_wait(chip);
158
159 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len,
160 use_sg, dir, chip->mspro_timeout);
161 if (retval < 0) {
162 ms_set_err_code(chip, err_code);
163 if (retval == -ETIMEDOUT)
164 retval = STATUS_TIMEDOUT;
165 else
166 retval = STATUS_FAIL;
167
168 rtsx_trace(chip);
169 return retval;
170 }
171
172 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
173 if (retval) {
174 rtsx_trace(chip);
175 return retval;
176 }
177 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
178 rtsx_trace(chip);
179 return STATUS_FAIL;
180 }
181
182 return STATUS_SUCCESS;
183 }
184
185 static int ms_write_bytes(struct rtsx_chip *chip,
186 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
187 {
188 struct ms_info *ms_card = &chip->ms_card;
189 int retval, i;
190
191 if (!data || (data_len < cnt)) {
192 rtsx_trace(chip);
193 return STATUS_ERROR;
194 }
195
196 rtsx_init_cmd(chip);
197
198 for (i = 0; i < cnt; i++) {
199 rtsx_add_cmd(chip, WRITE_REG_CMD,
200 PPBUF_BASE2 + i, 0xFF, data[i]);
201 }
202 if (cnt % 2)
203 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF);
204
205 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
206 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
207 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
208 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
209 0x01, PINGPONG_BUFFER);
210
211 rtsx_add_cmd(chip, WRITE_REG_CMD,
212 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
213 rtsx_add_cmd(chip, CHECK_REG_CMD,
214 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
215
216 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
217 if (retval < 0) {
218 u8 val = 0;
219
220 rtsx_read_register(chip, MS_TRANS_CFG, &val);
221 dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val);
222
223 rtsx_clear_ms_error(chip);
224
225 if (!(tpc & 0x08)) {
226 if (val & MS_CRC16_ERR) {
227 ms_set_err_code(chip, MS_CRC16_ERROR);
228 rtsx_trace(chip);
229 return ms_parse_err_code(chip);
230 }
231 } else {
232 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
233 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
234 ms_set_err_code(chip, MS_CMD_NK);
235 rtsx_trace(chip);
236 return ms_parse_err_code(chip);
237 }
238 }
239 }
240
241 if (val & MS_RDY_TIMEOUT) {
242 ms_set_err_code(chip, MS_TO_ERROR);
243 rtsx_trace(chip);
244 return ms_parse_err_code(chip);
245 }
246
247 ms_set_err_code(chip, MS_TO_ERROR);
248 rtsx_trace(chip);
249 return ms_parse_err_code(chip);
250 }
251
252 return STATUS_SUCCESS;
253 }
254
255 static int ms_read_bytes(struct rtsx_chip *chip,
256 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
257 {
258 struct ms_info *ms_card = &chip->ms_card;
259 int retval, i;
260 u8 *ptr;
261
262 if (!data) {
263 rtsx_trace(chip);
264 return STATUS_ERROR;
265 }
266
267 rtsx_init_cmd(chip);
268
269 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
270 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
271 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
272 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
273 0x01, PINGPONG_BUFFER);
274
275 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
276 MS_TRANSFER_START | MS_TM_READ_BYTES);
277 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
278 MS_TRANSFER_END, MS_TRANSFER_END);
279
280 for (i = 0; i < data_len - 1; i++)
281 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
282
283 if (data_len % 2)
284 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0);
285 else
286 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,
287 0, 0);
288
289 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
290 if (retval < 0) {
291 u8 val = 0;
292
293 rtsx_read_register(chip, MS_TRANS_CFG, &val);
294 rtsx_clear_ms_error(chip);
295
296 if (!(tpc & 0x08)) {
297 if (val & MS_CRC16_ERR) {
298 ms_set_err_code(chip, MS_CRC16_ERROR);
299 rtsx_trace(chip);
300 return ms_parse_err_code(chip);
301 }
302 } else {
303 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
304 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
305 ms_set_err_code(chip, MS_CMD_NK);
306 rtsx_trace(chip);
307 return ms_parse_err_code(chip);
308 }
309 }
310 }
311
312 if (val & MS_RDY_TIMEOUT) {
313 ms_set_err_code(chip, MS_TO_ERROR);
314 rtsx_trace(chip);
315 return ms_parse_err_code(chip);
316 }
317
318 ms_set_err_code(chip, MS_TO_ERROR);
319 rtsx_trace(chip);
320 return ms_parse_err_code(chip);
321 }
322
323 ptr = rtsx_get_cmd_data(chip) + 1;
324
325 for (i = 0; i < data_len; i++)
326 data[i] = ptr[i];
327
328 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) {
329 dev_dbg(rtsx_dev(chip), "Read format progress:\n");
330 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr,
331 cnt);
332 }
333
334 return STATUS_SUCCESS;
335 }
336
337 static int ms_set_rw_reg_addr(struct rtsx_chip *chip,
338 u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
339 {
340 int retval, i;
341 u8 data[4];
342
343 data[0] = read_start;
344 data[1] = read_cnt;
345 data[2] = write_start;
346 data[3] = write_cnt;
347
348 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
349 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4,
350 NO_WAIT_INT, data, 4);
351 if (retval == STATUS_SUCCESS)
352 return STATUS_SUCCESS;
353 rtsx_clear_ms_error(chip);
354 }
355
356 rtsx_trace(chip);
357 return STATUS_FAIL;
358 }
359
360 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg)
361 {
362 u8 data[2];
363
364 data[0] = cmd;
365 data[1] = 0;
366
367 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
368 }
369
370 static int ms_set_init_para(struct rtsx_chip *chip)
371 {
372 struct ms_info *ms_card = &chip->ms_card;
373 int retval;
374
375 if (CHK_HG8BIT(ms_card)) {
376 if (chip->asic_code)
377 ms_card->ms_clock = chip->asic_ms_hg_clk;
378 else
379 ms_card->ms_clock = chip->fpga_ms_hg_clk;
380
381 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
382 if (chip->asic_code)
383 ms_card->ms_clock = chip->asic_ms_4bit_clk;
384 else
385 ms_card->ms_clock = chip->fpga_ms_4bit_clk;
386
387 } else {
388 if (chip->asic_code)
389 ms_card->ms_clock = chip->asic_ms_1bit_clk;
390 else
391 ms_card->ms_clock = chip->fpga_ms_1bit_clk;
392 }
393
394 retval = switch_clock(chip, ms_card->ms_clock);
395 if (retval != STATUS_SUCCESS) {
396 rtsx_trace(chip);
397 return STATUS_FAIL;
398 }
399
400 retval = select_card(chip, MS_CARD);
401 if (retval != STATUS_SUCCESS) {
402 rtsx_trace(chip);
403 return STATUS_FAIL;
404 }
405
406 return STATUS_SUCCESS;
407 }
408
409 static int ms_switch_clock(struct rtsx_chip *chip)
410 {
411 struct ms_info *ms_card = &chip->ms_card;
412 int retval;
413
414 retval = select_card(chip, MS_CARD);
415 if (retval != STATUS_SUCCESS) {
416 rtsx_trace(chip);
417 return STATUS_FAIL;
418 }
419
420 retval = switch_clock(chip, ms_card->ms_clock);
421 if (retval != STATUS_SUCCESS) {
422 rtsx_trace(chip);
423 return STATUS_FAIL;
424 }
425
426 return STATUS_SUCCESS;
427 }
428
429 static int ms_pull_ctl_disable(struct rtsx_chip *chip)
430 {
431 int retval;
432
433 if (CHECK_PID(chip, 0x5208)) {
434 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
435 MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD);
436 if (retval) {
437 rtsx_trace(chip);
438 return retval;
439 }
440 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
441 MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD);
442 if (retval) {
443 rtsx_trace(chip);
444 return retval;
445 }
446 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
447 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
448 if (retval) {
449 rtsx_trace(chip);
450 return retval;
451 }
452 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
453 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
454 if (retval) {
455 rtsx_trace(chip);
456 return retval;
457 }
458 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
459 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
460 if (retval) {
461 rtsx_trace(chip);
462 return retval;
463 }
464 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
465 MS_D5_PD | MS_D4_PD);
466 if (retval) {
467 rtsx_trace(chip);
468 return retval;
469 }
470 } else if (CHECK_PID(chip, 0x5288)) {
471 if (CHECK_BARO_PKG(chip, QFN)) {
472 retval = rtsx_write_register(chip, CARD_PULL_CTL1,
473 0xFF, 0x55);
474 if (retval) {
475 rtsx_trace(chip);
476 return retval;
477 }
478 retval = rtsx_write_register(chip, CARD_PULL_CTL2,
479 0xFF, 0x55);
480 if (retval) {
481 rtsx_trace(chip);
482 return retval;
483 }
484 retval = rtsx_write_register(chip, CARD_PULL_CTL3,
485 0xFF, 0x4B);
486 if (retval) {
487 rtsx_trace(chip);
488 return retval;
489 }
490 retval = rtsx_write_register(chip, CARD_PULL_CTL4,
491 0xFF, 0x69);
492 if (retval) {
493 rtsx_trace(chip);
494 return retval;
495 }
496 }
497 }
498
499 return STATUS_SUCCESS;
500 }
501
502 static int ms_pull_ctl_enable(struct rtsx_chip *chip)
503 {
504 int retval;
505
506 rtsx_init_cmd(chip);
507
508 if (CHECK_PID(chip, 0x5208)) {
509 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
510 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD);
511 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
512 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD);
513 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
514 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
515 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
516 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
517 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
518 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
519 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
520 MS_D5_PD | MS_D4_PD);
521 } else if (CHECK_PID(chip, 0x5288)) {
522 if (CHECK_BARO_PKG(chip, QFN)) {
523 rtsx_add_cmd(chip, WRITE_REG_CMD,
524 CARD_PULL_CTL1, 0xFF, 0x55);
525 rtsx_add_cmd(chip, WRITE_REG_CMD,
526 CARD_PULL_CTL2, 0xFF, 0x45);
527 rtsx_add_cmd(chip, WRITE_REG_CMD,
528 CARD_PULL_CTL3, 0xFF, 0x4B);
529 rtsx_add_cmd(chip, WRITE_REG_CMD,
530 CARD_PULL_CTL4, 0xFF, 0x29);
531 }
532 }
533
534 retval = rtsx_send_cmd(chip, MS_CARD, 100);
535 if (retval < 0) {
536 rtsx_trace(chip);
537 return STATUS_FAIL;
538 }
539
540 return STATUS_SUCCESS;
541 }
542
543 static int ms_prepare_reset(struct rtsx_chip *chip)
544 {
545 struct ms_info *ms_card = &chip->ms_card;
546 int retval;
547 u8 oc_mask = 0;
548
549 ms_card->ms_type = 0;
550 ms_card->check_ms_flow = 0;
551 ms_card->switch_8bit_fail = 0;
552 ms_card->delay_write.delay_write_flag = 0;
553
554 ms_card->pro_under_formatting = 0;
555
556 retval = ms_power_off_card3v3(chip);
557 if (retval != STATUS_SUCCESS) {
558 rtsx_trace(chip);
559 return STATUS_FAIL;
560 }
561
562 if (!chip->ft2_fast_mode)
563 wait_timeout(250);
564
565 retval = enable_card_clock(chip, MS_CARD);
566 if (retval != STATUS_SUCCESS) {
567 rtsx_trace(chip);
568 return STATUS_FAIL;
569 }
570
571 if (chip->asic_code) {
572 retval = ms_pull_ctl_enable(chip);
573 if (retval != STATUS_SUCCESS) {
574 rtsx_trace(chip);
575 return STATUS_FAIL;
576 }
577 } else {
578 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
579 FPGA_MS_PULL_CTL_BIT | 0x20, 0);
580 if (retval) {
581 rtsx_trace(chip);
582 return retval;
583 }
584 }
585
586 if (!chip->ft2_fast_mode) {
587 retval = card_power_on(chip, MS_CARD);
588 if (retval != STATUS_SUCCESS) {
589 rtsx_trace(chip);
590 return STATUS_FAIL;
591 }
592
593 wait_timeout(150);
594
595 #ifdef SUPPORT_OCP
596 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
597 oc_mask = MS_OC_NOW | MS_OC_EVER;
598 else
599 oc_mask = SD_OC_NOW | SD_OC_EVER;
600
601 if (chip->ocp_stat & oc_mask) {
602 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
603 chip->ocp_stat);
604 rtsx_trace(chip);
605 return STATUS_FAIL;
606 }
607 #endif
608 }
609
610 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN,
611 MS_OUTPUT_EN);
612 if (retval) {
613 rtsx_trace(chip);
614 return retval;
615 }
616
617 if (chip->asic_code) {
618 retval = rtsx_write_register(chip, MS_CFG, 0xFF,
619 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
620 if (retval) {
621 rtsx_trace(chip);
622 return retval;
623 }
624 } else {
625 retval = rtsx_write_register(chip, MS_CFG, 0xFF,
626 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
627 if (retval) {
628 rtsx_trace(chip);
629 return retval;
630 }
631 }
632 retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF,
633 NO_WAIT_INT | NO_AUTO_READ_INT_REG);
634 if (retval) {
635 rtsx_trace(chip);
636 return retval;
637 }
638 retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR,
639 MS_STOP | MS_CLR_ERR);
640 if (retval) {
641 rtsx_trace(chip);
642 return retval;
643 }
644
645 retval = ms_set_init_para(chip);
646 if (retval != STATUS_SUCCESS) {
647 rtsx_trace(chip);
648 return STATUS_FAIL;
649 }
650
651 return STATUS_SUCCESS;
652 }
653
654 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)
655 {
656 struct ms_info *ms_card = &chip->ms_card;
657 int retval, i;
658 u8 val;
659
660 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
661 if (retval != STATUS_SUCCESS) {
662 rtsx_trace(chip);
663 return STATUS_FAIL;
664 }
665
666 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
667 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG,
668 6, NO_WAIT_INT);
669 if (retval == STATUS_SUCCESS)
670 break;
671 }
672 if (i == MS_MAX_RETRY_COUNT) {
673 rtsx_trace(chip);
674 return STATUS_FAIL;
675 }
676
677 retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val);
678 if (retval) {
679 rtsx_trace(chip);
680 return retval;
681 }
682 dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val);
683 if (val != 0x01) {
684 if (val != 0x02)
685 ms_card->check_ms_flow = 1;
686
687 rtsx_trace(chip);
688 return STATUS_FAIL;
689 }
690
691 retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val);
692 if (retval) {
693 rtsx_trace(chip);
694 return retval;
695 }
696 dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val);
697 if (val != 0) {
698 ms_card->check_ms_flow = 1;
699 rtsx_trace(chip);
700 return STATUS_FAIL;
701 }
702
703 retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val);
704 if (retval) {
705 rtsx_trace(chip);
706 return retval;
707 }
708 dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val);
709 if (val == 0) {
710 retval = rtsx_read_register(chip, PPBUF_BASE2, &val);
711 if (retval) {
712 rtsx_trace(chip);
713 return retval;
714 }
715 if (val & WRT_PRTCT)
716 chip->card_wp |= MS_CARD;
717 else
718 chip->card_wp &= ~MS_CARD;
719
720 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
721 chip->card_wp |= MS_CARD;
722 } else {
723 ms_card->check_ms_flow = 1;
724 rtsx_trace(chip);
725 return STATUS_FAIL;
726 }
727
728 ms_card->ms_type |= TYPE_MSPRO;
729
730 retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val);
731 if (retval) {
732 rtsx_trace(chip);
733 return retval;
734 }
735 dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val);
736 if (val == 0) {
737 ms_card->ms_type &= 0x0F;
738 } else if (val == 7) {
739 if (switch_8bit_bus)
740 ms_card->ms_type |= MS_HG;
741 else
742 ms_card->ms_type &= 0x0F;
743
744 } else {
745 rtsx_trace(chip);
746 return STATUS_FAIL;
747 }
748
749 return STATUS_SUCCESS;
750 }
751
752 static int ms_confirm_cpu_startup(struct rtsx_chip *chip)
753 {
754 int retval, i, k;
755 u8 val;
756
757 /* Confirm CPU StartUp */
758 k = 0;
759 do {
760 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
761 ms_set_err_code(chip, MS_NO_CARD);
762 rtsx_trace(chip);
763 return STATUS_FAIL;
764 }
765
766 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
767 retval = ms_read_bytes(chip, GET_INT, 1,
768 NO_WAIT_INT, &val, 1);
769 if (retval == STATUS_SUCCESS)
770 break;
771 }
772 if (i == MS_MAX_RETRY_COUNT) {
773 rtsx_trace(chip);
774 return STATUS_FAIL;
775 }
776
777 if (k > 100) {
778 rtsx_trace(chip);
779 return STATUS_FAIL;
780 }
781
782 k++;
783 wait_timeout(100);
784 } while (!(val & INT_REG_CED));
785
786 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
787 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
788 if (retval == STATUS_SUCCESS)
789 break;
790 }
791 if (i == MS_MAX_RETRY_COUNT) {
792 rtsx_trace(chip);
793 return STATUS_FAIL;
794 }
795
796 if (val & INT_REG_ERR) {
797 if (val & INT_REG_CMDNK)
798 chip->card_wp |= (MS_CARD);
799 else {
800 rtsx_trace(chip);
801 return STATUS_FAIL;
802 }
803 }
804 /* -- end confirm CPU startup */
805
806 return STATUS_SUCCESS;
807 }
808
809 static int ms_switch_parallel_bus(struct rtsx_chip *chip)
810 {
811 int retval, i;
812 u8 data[2];
813
814 data[0] = PARALLEL_4BIT_IF;
815 data[1] = 0;
816 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
817 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT,
818 data, 2);
819 if (retval == STATUS_SUCCESS)
820 break;
821 }
822 if (retval != STATUS_SUCCESS) {
823 rtsx_trace(chip);
824 return STATUS_FAIL;
825 }
826
827 return STATUS_SUCCESS;
828 }
829
830 static int ms_switch_8bit_bus(struct rtsx_chip *chip)
831 {
832 struct ms_info *ms_card = &chip->ms_card;
833 int retval, i;
834 u8 data[2];
835
836 data[0] = PARALLEL_8BIT_IF;
837 data[1] = 0;
838 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
839 retval = ms_write_bytes(chip, WRITE_REG, 1,
840 NO_WAIT_INT, data, 2);
841 if (retval == STATUS_SUCCESS)
842 break;
843 }
844 if (retval != STATUS_SUCCESS) {
845 rtsx_trace(chip);
846 return STATUS_FAIL;
847 }
848
849 retval = rtsx_write_register(chip, MS_CFG, 0x98,
850 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
851 if (retval) {
852 rtsx_trace(chip);
853 return retval;
854 }
855 ms_card->ms_type |= MS_8BIT;
856 retval = ms_set_init_para(chip);
857 if (retval != STATUS_SUCCESS) {
858 rtsx_trace(chip);
859 return STATUS_FAIL;
860 }
861
862 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
863 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT,
864 1, NO_WAIT_INT);
865 if (retval != STATUS_SUCCESS) {
866 rtsx_trace(chip);
867 return STATUS_FAIL;
868 }
869 }
870
871 return STATUS_SUCCESS;
872 }
873
874 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus)
875 {
876 struct ms_info *ms_card = &chip->ms_card;
877 int retval, i;
878
879 for (i = 0; i < 3; i++) {
880 retval = ms_prepare_reset(chip);
881 if (retval != STATUS_SUCCESS) {
882 rtsx_trace(chip);
883 return STATUS_FAIL;
884 }
885
886 retval = ms_identify_media_type(chip, switch_8bit_bus);
887 if (retval != STATUS_SUCCESS) {
888 rtsx_trace(chip);
889 return STATUS_FAIL;
890 }
891
892 retval = ms_confirm_cpu_startup(chip);
893 if (retval != STATUS_SUCCESS) {
894 rtsx_trace(chip);
895 return STATUS_FAIL;
896 }
897
898 retval = ms_switch_parallel_bus(chip);
899 if (retval != STATUS_SUCCESS) {
900 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
901 ms_set_err_code(chip, MS_NO_CARD);
902 rtsx_trace(chip);
903 return STATUS_FAIL;
904 }
905 continue;
906 } else {
907 break;
908 }
909 }
910
911 if (retval != STATUS_SUCCESS) {
912 rtsx_trace(chip);
913 return STATUS_FAIL;
914 }
915
916 /* Switch MS-PRO into Parallel mode */
917 retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
918 if (retval) {
919 rtsx_trace(chip);
920 return retval;
921 }
922 retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD,
923 PUSH_TIME_ODD);
924 if (retval) {
925 rtsx_trace(chip);
926 return retval;
927 }
928
929 retval = ms_set_init_para(chip);
930 if (retval != STATUS_SUCCESS) {
931 rtsx_trace(chip);
932 return STATUS_FAIL;
933 }
934
935 /* If MSPro HG Card, We shall try to switch to 8-bit bus */
936 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) {
937 retval = ms_switch_8bit_bus(chip);
938 if (retval != STATUS_SUCCESS) {
939 ms_card->switch_8bit_fail = 1;
940 rtsx_trace(chip);
941 return STATUS_FAIL;
942 }
943 }
944
945 return STATUS_SUCCESS;
946 }
947
948 #ifdef XC_POWERCLASS
949 static int msxc_change_power(struct rtsx_chip *chip, u8 mode)
950 {
951 int retval;
952 u8 buf[6];
953
954 ms_cleanup_work(chip);
955
956 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
957 if (retval != STATUS_SUCCESS) {
958 rtsx_trace(chip);
959 return STATUS_FAIL;
960 }
961
962 buf[0] = 0;
963 buf[1] = mode;
964 buf[2] = 0;
965 buf[3] = 0;
966 buf[4] = 0;
967 buf[5] = 0;
968
969 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6);
970 if (retval != STATUS_SUCCESS) {
971 rtsx_trace(chip);
972 return STATUS_FAIL;
973 }
974
975 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
976 if (retval != STATUS_SUCCESS) {
977 rtsx_trace(chip);
978 return STATUS_FAIL;
979 }
980
981 retval = rtsx_read_register(chip, MS_TRANS_CFG, buf);
982 if (retval) {
983 rtsx_trace(chip);
984 return retval;
985 }
986 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) {
987 rtsx_trace(chip);
988 return STATUS_FAIL;
989 }
990
991 return STATUS_SUCCESS;
992 }
993 #endif
994
995 static int ms_read_attribute_info(struct rtsx_chip *chip)
996 {
997 struct ms_info *ms_card = &chip->ms_card;
998 int retval, i;
999 u8 val, *buf, class_code, device_type, sub_class, data[16];
1000 u16 total_blk = 0, blk_size = 0;
1001 #ifdef SUPPORT_MSXC
1002 u32 xc_total_blk = 0, xc_blk_size = 0;
1003 #endif
1004 u32 sys_info_addr = 0, sys_info_size;
1005 #ifdef SUPPORT_PCGL_1P18
1006 u32 model_name_addr = 0, model_name_size;
1007 int found_sys_info = 0, found_model_name = 0;
1008 #endif
1009
1010 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
1011 if (retval != STATUS_SUCCESS) {
1012 rtsx_trace(chip);
1013 return STATUS_FAIL;
1014 }
1015
1016 if (CHK_MS8BIT(ms_card))
1017 data[0] = PARALLEL_8BIT_IF;
1018 else
1019 data[0] = PARALLEL_4BIT_IF;
1020
1021 data[1] = 0;
1022
1023 data[2] = 0x40;
1024 data[3] = 0;
1025 data[4] = 0;
1026 data[5] = 0;
1027 data[6] = 0;
1028 data[7] = 0;
1029
1030 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1031 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT,
1032 data, 8);
1033 if (retval == STATUS_SUCCESS)
1034 break;
1035 }
1036 if (retval != STATUS_SUCCESS) {
1037 rtsx_trace(chip);
1038 return STATUS_FAIL;
1039 }
1040
1041 buf = kmalloc(64 * 512, GFP_KERNEL);
1042 if (!buf) {
1043 rtsx_trace(chip);
1044 return STATUS_ERROR;
1045 }
1046
1047 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1048 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
1049 if (retval != STATUS_SUCCESS)
1050 continue;
1051
1052 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
1053 if (retval != STATUS_SUCCESS) {
1054 kfree(buf);
1055 rtsx_trace(chip);
1056 return STATUS_FAIL;
1057 }
1058 if (!(val & MS_INT_BREQ)) {
1059 kfree(buf);
1060 rtsx_trace(chip);
1061 return STATUS_FAIL;
1062 }
1063 retval = ms_transfer_data(chip, MS_TM_AUTO_READ,
1064 PRO_READ_LONG_DATA, 0x40, WAIT_INT,
1065 0, 0, buf, 64 * 512);
1066 if (retval == STATUS_SUCCESS)
1067 break;
1068
1069 rtsx_clear_ms_error(chip);
1070 }
1071 if (retval != STATUS_SUCCESS) {
1072 kfree(buf);
1073 rtsx_trace(chip);
1074 return STATUS_FAIL;
1075 }
1076
1077 i = 0;
1078 do {
1079 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
1080 if (retval != STATUS_SUCCESS) {
1081 kfree(buf);
1082 rtsx_trace(chip);
1083 return STATUS_FAIL;
1084 }
1085
1086 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
1087 break;
1088
1089 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ,
1090 PRO_READ_LONG_DATA, 0, WAIT_INT);
1091 if (retval != STATUS_SUCCESS) {
1092 kfree(buf);
1093 rtsx_trace(chip);
1094 return STATUS_FAIL;
1095 }
1096
1097 i++;
1098 } while (i < 1024);
1099
1100 if (retval != STATUS_SUCCESS) {
1101 kfree(buf);
1102 rtsx_trace(chip);
1103 return STATUS_FAIL;
1104 }
1105
1106 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
1107 /* Signature code is wrong */
1108 kfree(buf);
1109 rtsx_trace(chip);
1110 return STATUS_FAIL;
1111 }
1112
1113 if ((buf[4] < 1) || (buf[4] > 12)) {
1114 kfree(buf);
1115 rtsx_trace(chip);
1116 return STATUS_FAIL;
1117 }
1118
1119 for (i = 0; i < buf[4]; i++) {
1120 int cur_addr_off = 16 + i * 12;
1121
1122 #ifdef SUPPORT_MSXC
1123 if ((buf[cur_addr_off + 8] == 0x10) ||
1124 (buf[cur_addr_off + 8] == 0x13)) {
1125 #else
1126 if (buf[cur_addr_off + 8] == 0x10) {
1127 #endif
1128 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
1129 ((u32)buf[cur_addr_off + 1] << 16) |
1130 ((u32)buf[cur_addr_off + 2] << 8) |
1131 buf[cur_addr_off + 3];
1132 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |
1133 ((u32)buf[cur_addr_off + 5] << 16) |
1134 ((u32)buf[cur_addr_off + 6] << 8) |
1135 buf[cur_addr_off + 7];
1136 dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
1137 sys_info_addr, sys_info_size);
1138 if (sys_info_size != 96) {
1139 kfree(buf);
1140 rtsx_trace(chip);
1141 return STATUS_FAIL;
1142 }
1143 if (sys_info_addr < 0x1A0) {
1144 kfree(buf);
1145 rtsx_trace(chip);
1146 return STATUS_FAIL;
1147 }
1148 if ((sys_info_size + sys_info_addr) > 0x8000) {
1149 kfree(buf);
1150 rtsx_trace(chip);
1151 return STATUS_FAIL;
1152 }
1153
1154 #ifdef SUPPORT_MSXC
1155 if (buf[cur_addr_off + 8] == 0x13)
1156 ms_card->ms_type |= MS_XC;
1157 #endif
1158 #ifdef SUPPORT_PCGL_1P18
1159 found_sys_info = 1;
1160 #else
1161 break;
1162 #endif
1163 }
1164 #ifdef SUPPORT_PCGL_1P18
1165 if (buf[cur_addr_off + 8] == 0x15) {
1166 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |
1167 ((u32)buf[cur_addr_off + 1] << 16) |
1168 ((u32)buf[cur_addr_off + 2] << 8) |
1169 buf[cur_addr_off + 3];
1170 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) |
1171 ((u32)buf[cur_addr_off + 5] << 16) |
1172 ((u32)buf[cur_addr_off + 6] << 8) |
1173 buf[cur_addr_off + 7];
1174 dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n",
1175 model_name_addr, model_name_size);
1176 if (model_name_size != 48) {
1177 kfree(buf);
1178 rtsx_trace(chip);
1179 return STATUS_FAIL;
1180 }
1181 if (model_name_addr < 0x1A0) {
1182 kfree(buf);
1183 rtsx_trace(chip);
1184 return STATUS_FAIL;
1185 }
1186 if ((model_name_size + model_name_addr) > 0x8000) {
1187 kfree(buf);
1188 rtsx_trace(chip);
1189 return STATUS_FAIL;
1190 }
1191
1192 found_model_name = 1;
1193 }
1194
1195 if (found_sys_info && found_model_name)
1196 break;
1197 #endif
1198 }
1199
1200 if (i == buf[4]) {
1201 kfree(buf);
1202 rtsx_trace(chip);
1203 return STATUS_FAIL;
1204 }
1205
1206 class_code = buf[sys_info_addr + 0];
1207 device_type = buf[sys_info_addr + 56];
1208 sub_class = buf[sys_info_addr + 46];
1209 #ifdef SUPPORT_MSXC
1210 if (CHK_MSXC(ms_card)) {
1211 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |
1212 ((u32)buf[sys_info_addr + 7] << 16) |
1213 ((u32)buf[sys_info_addr + 8] << 8) |
1214 buf[sys_info_addr + 9];
1215 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |
1216 ((u32)buf[sys_info_addr + 33] << 16) |
1217 ((u32)buf[sys_info_addr + 34] << 8) |
1218 buf[sys_info_addr + 35];
1219 dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n",
1220 xc_total_blk, xc_blk_size);
1221 } else {
1222 total_blk = ((u16)buf[sys_info_addr + 6] << 8) |
1223 buf[sys_info_addr + 7];
1224 blk_size = ((u16)buf[sys_info_addr + 2] << 8) |
1225 buf[sys_info_addr + 3];
1226 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
1227 total_blk, blk_size);
1228 }
1229 #else
1230 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
1231 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
1232 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n",
1233 total_blk, blk_size);
1234 #endif
1235
1236 dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n",
1237 class_code, device_type, sub_class);
1238
1239 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
1240 #ifdef SUPPORT_PCGL_1P18
1241 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
1242 #endif
1243
1244 kfree(buf);
1245
1246 #ifdef SUPPORT_MSXC
1247 if (CHK_MSXC(ms_card)) {
1248 if (class_code != 0x03) {
1249 rtsx_trace(chip);
1250 return STATUS_FAIL;
1251 }
1252 } else {
1253 if (class_code != 0x02) {
1254 rtsx_trace(chip);
1255 return STATUS_FAIL;
1256 }
1257 }
1258 #else
1259 if (class_code != 0x02) {
1260 rtsx_trace(chip);
1261 return STATUS_FAIL;
1262 }
1263 #endif
1264
1265 if (device_type != 0x00) {
1266 if ((device_type == 0x01) || (device_type == 0x02) ||
1267 (device_type == 0x03)) {
1268 chip->card_wp |= MS_CARD;
1269 } else {
1270 rtsx_trace(chip);
1271 return STATUS_FAIL;
1272 }
1273 }
1274
1275 if (sub_class & 0xC0) {
1276 rtsx_trace(chip);
1277 return STATUS_FAIL;
1278 }
1279
1280 dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
1281 class_code, device_type, sub_class);
1282
1283 #ifdef SUPPORT_MSXC
1284 if (CHK_MSXC(ms_card)) {
1285 chip->capacity[chip->card2lun[MS_CARD]] =
1286 ms_card->capacity = xc_total_blk * xc_blk_size;
1287 } else {
1288 chip->capacity[chip->card2lun[MS_CARD]] =
1289 ms_card->capacity = total_blk * blk_size;
1290 }
1291 #else
1292 ms_card->capacity = total_blk * blk_size;
1293 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
1294 #endif
1295
1296 return STATUS_SUCCESS;
1297 }
1298
1299 #ifdef SUPPORT_MAGIC_GATE
1300 static int mg_set_tpc_para_sub(struct rtsx_chip *chip,
1301 int type, u8 mg_entry_num);
1302 #endif
1303
1304 static int reset_ms_pro(struct rtsx_chip *chip)
1305 {
1306 struct ms_info *ms_card = &chip->ms_card;
1307 int retval;
1308 #ifdef XC_POWERCLASS
1309 u8 change_power_class;
1310
1311 if (chip->ms_power_class_en & 0x02)
1312 change_power_class = 2;
1313 else if (chip->ms_power_class_en & 0x01)
1314 change_power_class = 1;
1315 else
1316 change_power_class = 0;
1317 #endif
1318
1319 #ifdef XC_POWERCLASS
1320 Retry:
1321 #endif
1322 retval = ms_pro_reset_flow(chip, 1);
1323 if (retval != STATUS_SUCCESS) {
1324 if (ms_card->switch_8bit_fail) {
1325 retval = ms_pro_reset_flow(chip, 0);
1326 if (retval != STATUS_SUCCESS) {
1327 rtsx_trace(chip);
1328 return STATUS_FAIL;
1329 }
1330 } else {
1331 rtsx_trace(chip);
1332 return STATUS_FAIL;
1333 }
1334 }
1335
1336 retval = ms_read_attribute_info(chip);
1337 if (retval != STATUS_SUCCESS) {
1338 rtsx_trace(chip);
1339 return STATUS_FAIL;
1340 }
1341
1342 #ifdef XC_POWERCLASS
1343 if (CHK_HG8BIT(ms_card))
1344 change_power_class = 0;
1345
1346 if (change_power_class && CHK_MSXC(ms_card)) {
1347 u8 power_class_en = chip->ms_power_class_en;
1348
1349 dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n",
1350 power_class_en);
1351 dev_dbg(rtsx_dev(chip), "change_power_class = %d\n",
1352 change_power_class);
1353
1354 if (change_power_class)
1355 power_class_en &= (1 << (change_power_class - 1));
1356 else
1357 power_class_en = 0;
1358
1359 if (power_class_en) {
1360 u8 power_class_mode =
1361 (ms_card->raw_sys_info[46] & 0x18) >> 3;
1362 dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x",
1363 power_class_mode);
1364 if (change_power_class > power_class_mode)
1365 change_power_class = power_class_mode;
1366 if (change_power_class) {
1367 retval = msxc_change_power(chip,
1368 change_power_class);
1369 if (retval != STATUS_SUCCESS) {
1370 change_power_class--;
1371 goto Retry;
1372 }
1373 }
1374 }
1375 }
1376 #endif
1377
1378 #ifdef SUPPORT_MAGIC_GATE
1379 retval = mg_set_tpc_para_sub(chip, 0, 0);
1380 if (retval != STATUS_SUCCESS) {
1381 rtsx_trace(chip);
1382 return STATUS_FAIL;
1383 }
1384 #endif
1385
1386 if (CHK_HG8BIT(ms_card))
1387 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
1388 else
1389 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1390
1391 return STATUS_SUCCESS;
1392 }
1393
1394 static int ms_read_status_reg(struct rtsx_chip *chip)
1395 {
1396 int retval;
1397 u8 val[2];
1398
1399 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
1400 if (retval != STATUS_SUCCESS) {
1401 rtsx_trace(chip);
1402 return STATUS_FAIL;
1403 }
1404
1405 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1406 if (retval != STATUS_SUCCESS) {
1407 rtsx_trace(chip);
1408 return STATUS_FAIL;
1409 }
1410
1411 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
1412 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1413 rtsx_trace(chip);
1414 return STATUS_FAIL;
1415 }
1416
1417 return STATUS_SUCCESS;
1418 }
1419
1420
1421 static int ms_read_extra_data(struct rtsx_chip *chip,
1422 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1423 {
1424 struct ms_info *ms_card = &chip->ms_card;
1425 int retval, i;
1426 u8 val, data[10];
1427
1428 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1429 SystemParm, 6);
1430 if (retval != STATUS_SUCCESS) {
1431 rtsx_trace(chip);
1432 return STATUS_FAIL;
1433 }
1434
1435 if (CHK_MS4BIT(ms_card)) {
1436 /* Parallel interface */
1437 data[0] = 0x88;
1438 } else {
1439 /* Serial interface */
1440 data[0] = 0x80;
1441 }
1442 data[1] = 0;
1443 data[2] = (u8)(block_addr >> 8);
1444 data[3] = (u8)block_addr;
1445 data[4] = 0x40;
1446 data[5] = page_num;
1447
1448 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1449 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1450 data, 6);
1451 if (retval == STATUS_SUCCESS)
1452 break;
1453 }
1454 if (i == MS_MAX_RETRY_COUNT) {
1455 rtsx_trace(chip);
1456 return STATUS_FAIL;
1457 }
1458
1459 ms_set_err_code(chip, MS_NO_ERROR);
1460
1461 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1462 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1463 if (retval == STATUS_SUCCESS)
1464 break;
1465 }
1466 if (i == MS_MAX_RETRY_COUNT) {
1467 rtsx_trace(chip);
1468 return STATUS_FAIL;
1469 }
1470
1471 ms_set_err_code(chip, MS_NO_ERROR);
1472 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1473 if (retval != STATUS_SUCCESS) {
1474 rtsx_trace(chip);
1475 return STATUS_FAIL;
1476 }
1477
1478 if (val & INT_REG_CMDNK) {
1479 ms_set_err_code(chip, MS_CMD_NK);
1480 rtsx_trace(chip);
1481 return STATUS_FAIL;
1482 }
1483 if (val & INT_REG_CED) {
1484 if (val & INT_REG_ERR) {
1485 retval = ms_read_status_reg(chip);
1486 if (retval != STATUS_SUCCESS) {
1487 rtsx_trace(chip);
1488 return STATUS_FAIL;
1489 }
1490
1491 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1492 MS_EXTRA_SIZE, SystemParm, 6);
1493 if (retval != STATUS_SUCCESS) {
1494 rtsx_trace(chip);
1495 return STATUS_FAIL;
1496 }
1497 }
1498 }
1499
1500 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT,
1501 data, MS_EXTRA_SIZE);
1502 if (retval != STATUS_SUCCESS) {
1503 rtsx_trace(chip);
1504 return STATUS_FAIL;
1505 }
1506
1507 if (buf && buf_len) {
1508 if (buf_len > MS_EXTRA_SIZE)
1509 buf_len = MS_EXTRA_SIZE;
1510 memcpy(buf, data, buf_len);
1511 }
1512
1513 return STATUS_SUCCESS;
1514 }
1515
1516 static int ms_write_extra_data(struct rtsx_chip *chip,
1517 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1518 {
1519 struct ms_info *ms_card = &chip->ms_card;
1520 int retval, i;
1521 u8 val, data[16];
1522
1523 if (!buf || (buf_len < MS_EXTRA_SIZE)) {
1524 rtsx_trace(chip);
1525 return STATUS_FAIL;
1526 }
1527
1528 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1529 SystemParm, 6 + MS_EXTRA_SIZE);
1530 if (retval != STATUS_SUCCESS) {
1531 rtsx_trace(chip);
1532 return STATUS_FAIL;
1533 }
1534
1535 if (CHK_MS4BIT(ms_card))
1536 data[0] = 0x88;
1537 else
1538 data[0] = 0x80;
1539
1540 data[1] = 0;
1541 data[2] = (u8)(block_addr >> 8);
1542 data[3] = (u8)block_addr;
1543 data[4] = 0x40;
1544 data[5] = page_num;
1545
1546 for (i = 6; i < MS_EXTRA_SIZE + 6; i++)
1547 data[i] = buf[i - 6];
1548
1549 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1550 NO_WAIT_INT, data, 16);
1551 if (retval != STATUS_SUCCESS) {
1552 rtsx_trace(chip);
1553 return STATUS_FAIL;
1554 }
1555
1556 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1557 if (retval != STATUS_SUCCESS) {
1558 rtsx_trace(chip);
1559 return STATUS_FAIL;
1560 }
1561
1562 ms_set_err_code(chip, MS_NO_ERROR);
1563 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1564 if (retval != STATUS_SUCCESS) {
1565 rtsx_trace(chip);
1566 return STATUS_FAIL;
1567 }
1568
1569 if (val & INT_REG_CMDNK) {
1570 ms_set_err_code(chip, MS_CMD_NK);
1571 rtsx_trace(chip);
1572 return STATUS_FAIL;
1573 }
1574 if (val & INT_REG_CED) {
1575 if (val & INT_REG_ERR) {
1576 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1577 rtsx_trace(chip);
1578 return STATUS_FAIL;
1579 }
1580 }
1581
1582 return STATUS_SUCCESS;
1583 }
1584
1585
1586 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num)
1587 {
1588 struct ms_info *ms_card = &chip->ms_card;
1589 int retval;
1590 u8 val, data[6];
1591
1592 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1593 SystemParm, 6);
1594 if (retval != STATUS_SUCCESS) {
1595 rtsx_trace(chip);
1596 return STATUS_FAIL;
1597 }
1598
1599 if (CHK_MS4BIT(ms_card))
1600 data[0] = 0x88;
1601 else
1602 data[0] = 0x80;
1603
1604 data[1] = 0;
1605 data[2] = (u8)(block_addr >> 8);
1606 data[3] = (u8)block_addr;
1607 data[4] = 0x20;
1608 data[5] = page_num;
1609
1610 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1611 if (retval != STATUS_SUCCESS) {
1612 rtsx_trace(chip);
1613 return STATUS_FAIL;
1614 }
1615
1616 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1617 if (retval != STATUS_SUCCESS) {
1618 rtsx_trace(chip);
1619 return STATUS_FAIL;
1620 }
1621
1622 ms_set_err_code(chip, MS_NO_ERROR);
1623 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1624 if (retval != STATUS_SUCCESS) {
1625 rtsx_trace(chip);
1626 return STATUS_FAIL;
1627 }
1628
1629 if (val & INT_REG_CMDNK) {
1630 ms_set_err_code(chip, MS_CMD_NK);
1631 rtsx_trace(chip);
1632 return STATUS_FAIL;
1633 }
1634
1635 if (val & INT_REG_CED) {
1636 if (val & INT_REG_ERR) {
1637 if (!(val & INT_REG_BREQ)) {
1638 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1639 rtsx_trace(chip);
1640 return STATUS_FAIL;
1641 }
1642 retval = ms_read_status_reg(chip);
1643 if (retval != STATUS_SUCCESS)
1644 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1645
1646 } else {
1647 if (!(val & INT_REG_BREQ)) {
1648 ms_set_err_code(chip, MS_BREQ_ERROR);
1649 rtsx_trace(chip);
1650 return STATUS_FAIL;
1651 }
1652 }
1653 }
1654
1655 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA,
1656 0, NO_WAIT_INT);
1657 if (retval != STATUS_SUCCESS) {
1658 rtsx_trace(chip);
1659 return STATUS_FAIL;
1660 }
1661
1662 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
1663 rtsx_trace(chip);
1664 return STATUS_FAIL;
1665 }
1666
1667 return STATUS_SUCCESS;
1668 }
1669
1670
1671 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk)
1672 {
1673 struct ms_info *ms_card = &chip->ms_card;
1674 int retval;
1675 u8 val, data[8], extra[MS_EXTRA_SIZE];
1676
1677 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
1678 if (retval != STATUS_SUCCESS) {
1679 rtsx_trace(chip);
1680 return STATUS_FAIL;
1681 }
1682
1683 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1684 SystemParm, 7);
1685 if (retval != STATUS_SUCCESS) {
1686 rtsx_trace(chip);
1687 return STATUS_FAIL;
1688 }
1689
1690 ms_set_err_code(chip, MS_NO_ERROR);
1691
1692 if (CHK_MS4BIT(ms_card))
1693 data[0] = 0x88;
1694 else
1695 data[0] = 0x80;
1696
1697 data[1] = 0;
1698 data[2] = (u8)(phy_blk >> 8);
1699 data[3] = (u8)phy_blk;
1700 data[4] = 0x80;
1701 data[5] = 0;
1702 data[6] = extra[0] & 0x7F;
1703 data[7] = 0xFF;
1704
1705 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7);
1706 if (retval != STATUS_SUCCESS) {
1707 rtsx_trace(chip);
1708 return STATUS_FAIL;
1709 }
1710
1711 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1712 if (retval != STATUS_SUCCESS) {
1713 rtsx_trace(chip);
1714 return STATUS_FAIL;
1715 }
1716
1717 ms_set_err_code(chip, MS_NO_ERROR);
1718 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1719 if (retval != STATUS_SUCCESS) {
1720 rtsx_trace(chip);
1721 return STATUS_FAIL;
1722 }
1723
1724 if (val & INT_REG_CMDNK) {
1725 ms_set_err_code(chip, MS_CMD_NK);
1726 rtsx_trace(chip);
1727 return STATUS_FAIL;
1728 }
1729
1730 if (val & INT_REG_CED) {
1731 if (val & INT_REG_ERR) {
1732 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1733 rtsx_trace(chip);
1734 return STATUS_FAIL;
1735 }
1736 }
1737
1738 return STATUS_SUCCESS;
1739 }
1740
1741
1742 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk)
1743 {
1744 struct ms_info *ms_card = &chip->ms_card;
1745 int retval, i = 0;
1746 u8 val, data[6];
1747
1748 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1749 SystemParm, 6);
1750 if (retval != STATUS_SUCCESS) {
1751 rtsx_trace(chip);
1752 return STATUS_FAIL;
1753 }
1754
1755 ms_set_err_code(chip, MS_NO_ERROR);
1756
1757 if (CHK_MS4BIT(ms_card))
1758 data[0] = 0x88;
1759 else
1760 data[0] = 0x80;
1761
1762 data[1] = 0;
1763 data[2] = (u8)(phy_blk >> 8);
1764 data[3] = (u8)phy_blk;
1765 data[4] = 0;
1766 data[5] = 0;
1767
1768 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1769 if (retval != STATUS_SUCCESS) {
1770 rtsx_trace(chip);
1771 return STATUS_FAIL;
1772 }
1773
1774 ERASE_RTY:
1775 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT);
1776 if (retval != STATUS_SUCCESS) {
1777 rtsx_trace(chip);
1778 return STATUS_FAIL;
1779 }
1780
1781 ms_set_err_code(chip, MS_NO_ERROR);
1782 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1783 if (retval != STATUS_SUCCESS) {
1784 rtsx_trace(chip);
1785 return STATUS_FAIL;
1786 }
1787
1788 if (val & INT_REG_CMDNK) {
1789 if (i < 3) {
1790 i++;
1791 goto ERASE_RTY;
1792 }
1793
1794 ms_set_err_code(chip, MS_CMD_NK);
1795 ms_set_bad_block(chip, phy_blk);
1796 rtsx_trace(chip);
1797 return STATUS_FAIL;
1798 }
1799
1800 if (val & INT_REG_CED) {
1801 if (val & INT_REG_ERR) {
1802 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1803 rtsx_trace(chip);
1804 return STATUS_FAIL;
1805 }
1806 }
1807
1808 return STATUS_SUCCESS;
1809 }
1810
1811
1812 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
1813 {
1814 if (!extra || (extra_len < MS_EXTRA_SIZE))
1815 return;
1816
1817 memset(extra, 0xFF, MS_EXTRA_SIZE);
1818
1819 if (type == setPS_NG) {
1820 /* set page status as 1:NG,and block status keep 1:OK */
1821 extra[0] = 0xB8;
1822 } else {
1823 /* set page status as 0:Data Error,and block status keep 1:OK */
1824 extra[0] = 0x98;
1825 }
1826
1827 extra[2] = (u8)(log_blk >> 8);
1828 extra[3] = (u8)log_blk;
1829 }
1830
1831 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk,
1832 u8 start_page, u8 end_page)
1833 {
1834 int retval;
1835 u8 extra[MS_EXTRA_SIZE], i;
1836
1837 memset(extra, 0xff, MS_EXTRA_SIZE);
1838
1839 extra[0] = 0xf8; /* Block, page OK, data erased */
1840 extra[1] = 0xff;
1841 extra[2] = (u8)(log_blk >> 8);
1842 extra[3] = (u8)log_blk;
1843
1844 for (i = start_page; i < end_page; i++) {
1845 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1846 ms_set_err_code(chip, MS_NO_CARD);
1847 rtsx_trace(chip);
1848 return STATUS_FAIL;
1849 }
1850
1851 retval = ms_write_extra_data(chip, phy_blk, i,
1852 extra, MS_EXTRA_SIZE);
1853 if (retval != STATUS_SUCCESS) {
1854 rtsx_trace(chip);
1855 return STATUS_FAIL;
1856 }
1857 }
1858
1859 return STATUS_SUCCESS;
1860 }
1861
1862 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
1863 u16 log_blk, u8 start_page, u8 end_page)
1864 {
1865 struct ms_info *ms_card = &chip->ms_card;
1866 bool uncorrect_flag = false;
1867 int retval, rty_cnt;
1868 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
1869
1870 dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1871 old_blk, new_blk, log_blk);
1872 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n",
1873 start_page, end_page);
1874
1875 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1876 if (retval != STATUS_SUCCESS) {
1877 rtsx_trace(chip);
1878 return STATUS_FAIL;
1879 }
1880
1881 retval = ms_read_status_reg(chip);
1882 if (retval != STATUS_SUCCESS) {
1883 rtsx_trace(chip);
1884 return STATUS_FAIL;
1885 }
1886
1887 retval = rtsx_read_register(chip, PPBUF_BASE2, &val);
1888 if (retval) {
1889 rtsx_trace(chip);
1890 return retval;
1891 }
1892
1893 if (val & BUF_FULL) {
1894 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1895 if (retval != STATUS_SUCCESS) {
1896 rtsx_trace(chip);
1897 return STATUS_FAIL;
1898 }
1899
1900 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1901 if (retval != STATUS_SUCCESS) {
1902 rtsx_trace(chip);
1903 return STATUS_FAIL;
1904 }
1905
1906 if (!(val & INT_REG_CED)) {
1907 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1908 rtsx_trace(chip);
1909 return STATUS_FAIL;
1910 }
1911 }
1912
1913 for (i = start_page; i < end_page; i++) {
1914 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1915 ms_set_err_code(chip, MS_NO_CARD);
1916 rtsx_trace(chip);
1917 return STATUS_FAIL;
1918 }
1919
1920 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1921
1922 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1923 MS_EXTRA_SIZE, SystemParm, 6);
1924 if (retval != STATUS_SUCCESS) {
1925 rtsx_trace(chip);
1926 return STATUS_FAIL;
1927 }
1928
1929 ms_set_err_code(chip, MS_NO_ERROR);
1930
1931 if (CHK_MS4BIT(ms_card))
1932 data[0] = 0x88;
1933 else
1934 data[0] = 0x80;
1935
1936 data[1] = 0;
1937 data[2] = (u8)(old_blk >> 8);
1938 data[3] = (u8)old_blk;
1939 data[4] = 0x20;
1940 data[5] = i;
1941
1942 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1943 data, 6);
1944 if (retval != STATUS_SUCCESS) {
1945 rtsx_trace(chip);
1946 return STATUS_FAIL;
1947 }
1948
1949 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1950 if (retval != STATUS_SUCCESS) {
1951 rtsx_trace(chip);
1952 return STATUS_FAIL;
1953 }
1954
1955 ms_set_err_code(chip, MS_NO_ERROR);
1956 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1957 if (retval != STATUS_SUCCESS) {
1958 rtsx_trace(chip);
1959 return STATUS_FAIL;
1960 }
1961
1962 if (val & INT_REG_CMDNK) {
1963 ms_set_err_code(chip, MS_CMD_NK);
1964 rtsx_trace(chip);
1965 return STATUS_FAIL;
1966 }
1967
1968 if (val & INT_REG_CED) {
1969 if (val & INT_REG_ERR) {
1970 retval = ms_read_status_reg(chip);
1971 if (retval != STATUS_SUCCESS) {
1972 uncorrect_flag = true;
1973 dev_dbg(rtsx_dev(chip), "Uncorrectable error\n");
1974 } else {
1975 uncorrect_flag = false;
1976 }
1977
1978 retval = ms_transfer_tpc(chip,
1979 MS_TM_NORMAL_READ,
1980 READ_PAGE_DATA,
1981 0, NO_WAIT_INT);
1982 if (retval != STATUS_SUCCESS) {
1983 rtsx_trace(chip);
1984 return STATUS_FAIL;
1985 }
1986
1987 if (uncorrect_flag) {
1988 ms_set_page_status(log_blk, setPS_NG,
1989 extra, MS_EXTRA_SIZE);
1990 if (i == 0)
1991 extra[0] &= 0xEF;
1992
1993 ms_write_extra_data(chip, old_blk, i,
1994 extra, MS_EXTRA_SIZE);
1995 dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n",
1996 i, extra[0]);
1997 MS_SET_BAD_BLOCK_FLG(ms_card);
1998
1999 ms_set_page_status(log_blk, setPS_Error,
2000 extra, MS_EXTRA_SIZE);
2001 ms_write_extra_data(chip, new_blk, i,
2002 extra, MS_EXTRA_SIZE);
2003 continue;
2004 }
2005
2006 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT;
2007 rty_cnt++) {
2008 retval = ms_transfer_tpc(
2009 chip,
2010 MS_TM_NORMAL_WRITE,
2011 WRITE_PAGE_DATA,
2012 0, NO_WAIT_INT);
2013 if (retval == STATUS_SUCCESS)
2014 break;
2015 }
2016 if (rty_cnt == MS_MAX_RETRY_COUNT) {
2017 rtsx_trace(chip);
2018 return STATUS_FAIL;
2019 }
2020 }
2021
2022 if (!(val & INT_REG_BREQ)) {
2023 ms_set_err_code(chip, MS_BREQ_ERROR);
2024 rtsx_trace(chip);
2025 return STATUS_FAIL;
2026 }
2027 }
2028
2029 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
2030 MS_EXTRA_SIZE, SystemParm, (6 + MS_EXTRA_SIZE));
2031
2032 ms_set_err_code(chip, MS_NO_ERROR);
2033
2034 if (CHK_MS4BIT(ms_card))
2035 data[0] = 0x88;
2036 else
2037 data[0] = 0x80;
2038
2039 data[1] = 0;
2040 data[2] = (u8)(new_blk >> 8);
2041 data[3] = (u8)new_blk;
2042 data[4] = 0x20;
2043 data[5] = i;
2044
2045 if ((extra[0] & 0x60) != 0x60)
2046 data[6] = extra[0];
2047 else
2048 data[6] = 0xF8;
2049
2050 data[6 + 1] = 0xFF;
2051 data[6 + 2] = (u8)(log_blk >> 8);
2052 data[6 + 3] = (u8)log_blk;
2053
2054 for (j = 4; j <= MS_EXTRA_SIZE; j++)
2055 data[6 + j] = 0xFF;
2056
2057 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
2058 NO_WAIT_INT, data, 16);
2059 if (retval != STATUS_SUCCESS) {
2060 rtsx_trace(chip);
2061 return STATUS_FAIL;
2062 }
2063
2064 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
2065 if (retval != STATUS_SUCCESS) {
2066 rtsx_trace(chip);
2067 return STATUS_FAIL;
2068 }
2069
2070 ms_set_err_code(chip, MS_NO_ERROR);
2071 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
2072 if (retval != STATUS_SUCCESS) {
2073 rtsx_trace(chip);
2074 return STATUS_FAIL;
2075 }
2076
2077 if (val & INT_REG_CMDNK) {
2078 ms_set_err_code(chip, MS_CMD_NK);
2079 rtsx_trace(chip);
2080 return STATUS_FAIL;
2081 }
2082
2083 if (val & INT_REG_CED) {
2084 if (val & INT_REG_ERR) {
2085 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
2086 rtsx_trace(chip);
2087 return STATUS_FAIL;
2088 }
2089 }
2090
2091 if (i == 0) {
2092 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
2093 MS_EXTRA_SIZE, SystemParm, 7);
2094 if (retval != STATUS_SUCCESS) {
2095 rtsx_trace(chip);
2096 return STATUS_FAIL;
2097 }
2098
2099 ms_set_err_code(chip, MS_NO_ERROR);
2100
2101 if (CHK_MS4BIT(ms_card))
2102 data[0] = 0x88;
2103 else
2104 data[0] = 0x80;
2105
2106 data[1] = 0;
2107 data[2] = (u8)(old_blk >> 8);
2108 data[3] = (u8)old_blk;
2109 data[4] = 0x80;
2110 data[5] = 0;
2111 data[6] = 0xEF;
2112 data[7] = 0xFF;
2113
2114 retval = ms_write_bytes(chip, WRITE_REG, 7,
2115 NO_WAIT_INT, data, 8);
2116 if (retval != STATUS_SUCCESS) {
2117 rtsx_trace(chip);
2118 return STATUS_FAIL;
2119 }
2120
2121 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
2122 if (retval != STATUS_SUCCESS) {
2123 rtsx_trace(chip);
2124 return STATUS_FAIL;
2125 }
2126
2127 ms_set_err_code(chip, MS_NO_ERROR);
2128 retval = ms_read_bytes(chip, GET_INT, 1,
2129 NO_WAIT_INT, &val, 1);
2130 if (retval != STATUS_SUCCESS) {
2131 rtsx_trace(chip);
2132 return STATUS_FAIL;
2133 }
2134
2135 if (val & INT_REG_CMDNK) {
2136 ms_set_err_code(chip, MS_CMD_NK);
2137 rtsx_trace(chip);
2138 return STATUS_FAIL;
2139 }
2140
2141 if (val & INT_REG_CED) {
2142 if (val & INT_REG_ERR) {
2143 ms_set_err_code(chip,
2144 MS_FLASH_WRITE_ERROR);
2145 rtsx_trace(chip);
2146 return STATUS_FAIL;
2147 }
2148 }
2149 }
2150 }
2151
2152 return STATUS_SUCCESS;
2153 }
2154
2155
2156 static int reset_ms(struct rtsx_chip *chip)
2157 {
2158 struct ms_info *ms_card = &chip->ms_card;
2159 int retval;
2160 u16 i, reg_addr, block_size;
2161 u8 val, extra[MS_EXTRA_SIZE], j, *ptr;
2162 #ifndef SUPPORT_MAGIC_GATE
2163 u16 eblock_cnt;
2164 #endif
2165
2166 retval = ms_prepare_reset(chip);
2167 if (retval != STATUS_SUCCESS) {
2168 rtsx_trace(chip);
2169 return STATUS_FAIL;
2170 }
2171
2172 ms_card->ms_type |= TYPE_MS;
2173
2174 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
2175 if (retval != STATUS_SUCCESS) {
2176 rtsx_trace(chip);
2177 return STATUS_FAIL;
2178 }
2179
2180 retval = ms_read_status_reg(chip);
2181 if (retval != STATUS_SUCCESS) {
2182 rtsx_trace(chip);
2183 return STATUS_FAIL;
2184 }
2185
2186 retval = rtsx_read_register(chip, PPBUF_BASE2, &val);
2187 if (retval) {
2188 rtsx_trace(chip);
2189 return retval;
2190 }
2191 if (val & WRT_PRTCT)
2192 chip->card_wp |= MS_CARD;
2193 else
2194 chip->card_wp &= ~MS_CARD;
2195
2196 i = 0;
2197
2198 RE_SEARCH:
2199 /* Search Boot Block */
2200 while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
2201 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2202 ms_set_err_code(chip, MS_NO_CARD);
2203 rtsx_trace(chip);
2204 return STATUS_FAIL;
2205 }
2206
2207 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE);
2208 if (retval != STATUS_SUCCESS) {
2209 i++;
2210 continue;
2211 }
2212
2213 if (extra[0] & BLOCK_OK) {
2214 if (!(extra[1] & NOT_BOOT_BLOCK)) {
2215 ms_card->boot_block = i;
2216 break;
2217 }
2218 }
2219 i++;
2220 }
2221
2222 if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
2223 dev_dbg(rtsx_dev(chip), "No boot block found!");
2224 rtsx_trace(chip);
2225 return STATUS_FAIL;
2226 }
2227
2228 for (j = 0; j < 3; j++) {
2229 retval = ms_read_page(chip, ms_card->boot_block, j);
2230 if (retval != STATUS_SUCCESS) {
2231 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
2232 i = ms_card->boot_block + 1;
2233 ms_set_err_code(chip, MS_NO_ERROR);
2234 goto RE_SEARCH;
2235 }
2236 }
2237 }
2238
2239 retval = ms_read_page(chip, ms_card->boot_block, 0);
2240 if (retval != STATUS_SUCCESS) {
2241 rtsx_trace(chip);
2242 return STATUS_FAIL;
2243 }
2244
2245 /* Read MS system information as sys_info */
2246 rtsx_init_cmd(chip);
2247
2248 for (i = 0; i < 96; i++)
2249 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0);
2250
2251 retval = rtsx_send_cmd(chip, MS_CARD, 100);
2252 if (retval < 0) {
2253 rtsx_trace(chip);
2254 return STATUS_FAIL;
2255 }
2256
2257 ptr = rtsx_get_cmd_data(chip);
2258 memcpy(ms_card->raw_sys_info, ptr, 96);
2259
2260 /* Read useful block contents */
2261 rtsx_init_cmd(chip);
2262
2263 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
2264 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
2265
2266 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;
2267 reg_addr++)
2268 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2269
2270 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)
2271 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2272
2273 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
2274 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
2275
2276 retval = rtsx_send_cmd(chip, MS_CARD, 100);
2277 if (retval < 0) {
2278 rtsx_trace(chip);
2279 return STATUS_FAIL;
2280 }
2281
2282 ptr = rtsx_get_cmd_data(chip);
2283
2284 dev_dbg(rtsx_dev(chip), "Boot block data:\n");
2285 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr);
2286
2287 /* Block ID error
2288 * HEADER_ID0, HEADER_ID1
2289 */
2290 if (ptr[0] != 0x00 || ptr[1] != 0x01) {
2291 i = ms_card->boot_block + 1;
2292 goto RE_SEARCH;
2293 }
2294
2295 /* Page size error
2296 * PAGE_SIZE_0, PAGE_SIZE_1
2297 */
2298 if (ptr[12] != 0x02 || ptr[13] != 0x00) {
2299 i = ms_card->boot_block + 1;
2300 goto RE_SEARCH;
2301 }
2302
2303 if ((ptr[14] == 1) || (ptr[14] == 3))
2304 chip->card_wp |= MS_CARD;
2305
2306 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */
2307 block_size = ((u16)ptr[6] << 8) | ptr[7];
2308 if (block_size == 0x0010) {
2309 /* Block size 16KB */
2310 ms_card->block_shift = 5;
2311 ms_card->page_off = 0x1F;
2312 } else if (block_size == 0x0008) {
2313 /* Block size 8KB */
2314 ms_card->block_shift = 4;
2315 ms_card->page_off = 0x0F;
2316 }
2317
2318 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */
2319 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9];
2320
2321 #ifdef SUPPORT_MAGIC_GATE
2322 j = ptr[10];
2323
2324 if (ms_card->block_shift == 4) { /* 4MB or 8MB */
2325 if (j < 2) { /* Effective block for 4MB: 0x1F0 */
2326 ms_card->capacity = 0x1EE0;
2327 } else { /* Effective block for 8MB: 0x3E0 */
2328 ms_card->capacity = 0x3DE0;
2329 }
2330 } else { /* 16MB, 32MB, 64MB or 128MB */
2331 if (j < 5) { /* Effective block for 16MB: 0x3E0 */
2332 ms_card->capacity = 0x7BC0;
2333 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */
2334 ms_card->capacity = 0xF7C0;
2335 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */
2336 ms_card->capacity = 0x1EF80;
2337 } else { /* Effective block for 128MB: 0x1F00 */
2338 ms_card->capacity = 0x3DF00;
2339 }
2340 }
2341 #else
2342 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */
2343 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11];
2344
2345 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift;
2346 #endif
2347
2348 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
2349
2350 /* Switch I/F Mode */
2351 if (ptr[15]) {
2352 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
2353 if (retval != STATUS_SUCCESS) {
2354 rtsx_trace(chip);
2355 return STATUS_FAIL;
2356 }
2357
2358 retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88);
2359 if (retval) {
2360 rtsx_trace(chip);
2361 return retval;
2362 }
2363 retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0);
2364 if (retval) {
2365 rtsx_trace(chip);
2366 return retval;
2367 }
2368
2369 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1,
2370 NO_WAIT_INT);
2371 if (retval != STATUS_SUCCESS) {
2372 rtsx_trace(chip);
2373 return STATUS_FAIL;
2374 }
2375
2376 retval = rtsx_write_register(chip, MS_CFG,
2377 0x58 | MS_NO_CHECK_INT,
2378 MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT);
2379 if (retval) {
2380 rtsx_trace(chip);
2381 return retval;
2382 }
2383
2384 ms_card->ms_type |= MS_4BIT;
2385 }
2386
2387 if (CHK_MS4BIT(ms_card))
2388 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
2389 else
2390 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
2391
2392 return STATUS_SUCCESS;
2393 }
2394
2395 static int ms_init_l2p_tbl(struct rtsx_chip *chip)
2396 {
2397 struct ms_info *ms_card = &chip->ms_card;
2398 int size, i, seg_no, retval;
2399 u16 defect_block, reg_addr;
2400 u8 val1, val2;
2401
2402 ms_card->segment_cnt = ms_card->total_block >> 9;
2403 dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n",
2404 ms_card->segment_cnt);
2405
2406 size = ms_card->segment_cnt * sizeof(struct zone_entry);
2407 ms_card->segment = vzalloc(size);
2408 if (!ms_card->segment) {
2409 rtsx_trace(chip);
2410 return STATUS_FAIL;
2411 }
2412
2413 retval = ms_read_page(chip, ms_card->boot_block, 1);
2414 if (retval != STATUS_SUCCESS) {
2415 rtsx_trace(chip);
2416 goto INIT_FAIL;
2417 }
2418
2419 reg_addr = PPBUF_BASE2;
2420 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
2421 int block_no;
2422
2423 retval = rtsx_read_register(chip, reg_addr++, &val1);
2424 if (retval != STATUS_SUCCESS) {
2425 rtsx_trace(chip);
2426 goto INIT_FAIL;
2427 }
2428
2429 retval = rtsx_read_register(chip, reg_addr++, &val2);
2430 if (retval != STATUS_SUCCESS) {
2431 rtsx_trace(chip);
2432 goto INIT_FAIL;
2433 }
2434
2435 defect_block = ((u16)val1 << 8) | val2;
2436 if (defect_block == 0xFFFF)
2437 break;
2438
2439 seg_no = defect_block / 512;
2440
2441 block_no = ms_card->segment[seg_no].disable_count++;
2442 ms_card->segment[seg_no].defect_list[block_no] = defect_block;
2443 }
2444
2445 for (i = 0; i < ms_card->segment_cnt; i++) {
2446 ms_card->segment[i].build_flag = 0;
2447 ms_card->segment[i].l2p_table = NULL;
2448 ms_card->segment[i].free_table = NULL;
2449 ms_card->segment[i].get_index = 0;
2450 ms_card->segment[i].set_index = 0;
2451 ms_card->segment[i].unused_blk_cnt = 0;
2452
2453 dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n",
2454 i, ms_card->segment[i].disable_count);
2455 }
2456
2457 return STATUS_SUCCESS;
2458
2459 INIT_FAIL:
2460 vfree(ms_card->segment);
2461 ms_card->segment = NULL;
2462
2463 return STATUS_FAIL;
2464 }
2465
2466 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off)
2467 {
2468 struct ms_info *ms_card = &chip->ms_card;
2469 struct zone_entry *segment;
2470
2471 if (!ms_card->segment)
2472 return 0xFFFF;
2473
2474 segment = &(ms_card->segment[seg_no]);
2475
2476 if (segment->l2p_table)
2477 return segment->l2p_table[log_off];
2478
2479 return 0xFFFF;
2480 }
2481
2482 static void ms_set_l2p_tbl(struct rtsx_chip *chip,
2483 int seg_no, u16 log_off, u16 phy_blk)
2484 {
2485 struct ms_info *ms_card = &chip->ms_card;
2486 struct zone_entry *segment;
2487
2488 if (!ms_card->segment)
2489 return;
2490
2491 segment = &(ms_card->segment[seg_no]);
2492 if (segment->l2p_table)
2493 segment->l2p_table[log_off] = phy_blk;
2494 }
2495
2496 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk)
2497 {
2498 struct ms_info *ms_card = &chip->ms_card;
2499 struct zone_entry *segment;
2500 int seg_no;
2501
2502 seg_no = (int)phy_blk >> 9;
2503 segment = &(ms_card->segment[seg_no]);
2504
2505 segment->free_table[segment->set_index++] = phy_blk;
2506 if (segment->set_index >= MS_FREE_TABLE_CNT)
2507 segment->set_index = 0;
2508
2509 segment->unused_blk_cnt++;
2510 }
2511
2512 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no)
2513 {
2514 struct ms_info *ms_card = &chip->ms_card;
2515 struct zone_entry *segment;
2516 u16 phy_blk;
2517
2518 segment = &(ms_card->segment[seg_no]);
2519
2520 if (segment->unused_blk_cnt <= 0)
2521 return 0xFFFF;
2522
2523 phy_blk = segment->free_table[segment->get_index];
2524 segment->free_table[segment->get_index++] = 0xFFFF;
2525 if (segment->get_index >= MS_FREE_TABLE_CNT)
2526 segment->get_index = 0;
2527
2528 segment->unused_blk_cnt--;
2529
2530 return phy_blk;
2531 }
2532
2533 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478,
2534 2974, 3470, 3966, 4462, 4958,
2535 5454, 5950, 6446, 6942, 7438,
2536 7934};
2537
2538 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk,
2539 u16 log_off, u8 us1, u8 us2)
2540 {
2541 struct ms_info *ms_card = &chip->ms_card;
2542 struct zone_entry *segment;
2543 int seg_no;
2544 u16 tmp_blk;
2545
2546 seg_no = (int)phy_blk >> 9;
2547 segment = &(ms_card->segment[seg_no]);
2548 tmp_blk = segment->l2p_table[log_off];
2549
2550 if (us1 != us2) {
2551 if (us1 == 0) {
2552 if (!(chip->card_wp & MS_CARD))
2553 ms_erase_block(chip, tmp_blk);
2554
2555 ms_set_unused_block(chip, tmp_blk);
2556 segment->l2p_table[log_off] = phy_blk;
2557 } else {
2558 if (!(chip->card_wp & MS_CARD))
2559 ms_erase_block(chip, phy_blk);
2560
2561 ms_set_unused_block(chip, phy_blk);
2562 }
2563 } else {
2564 if (phy_blk < tmp_blk) {
2565 if (!(chip->card_wp & MS_CARD))
2566 ms_erase_block(chip, phy_blk);
2567
2568 ms_set_unused_block(chip, phy_blk);
2569 } else {
2570 if (!(chip->card_wp & MS_CARD))
2571 ms_erase_block(chip, tmp_blk);
2572
2573 ms_set_unused_block(chip, tmp_blk);
2574 segment->l2p_table[log_off] = phy_blk;
2575 }
2576 }
2577
2578 return STATUS_SUCCESS;
2579 }
2580
2581 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)
2582 {
2583 struct ms_info *ms_card = &chip->ms_card;
2584 struct zone_entry *segment;
2585 bool defect_flag;
2586 int retval, table_size, disable_cnt, i;
2587 u16 start, end, phy_blk, log_blk, tmp_blk, idx;
2588 u8 extra[MS_EXTRA_SIZE], us1, us2;
2589
2590 dev_dbg(rtsx_dev(chip), "ms_build_l2p_tbl: %d\n", seg_no);
2591
2592 if (!ms_card->segment) {
2593 retval = ms_init_l2p_tbl(chip);
2594 if (retval != STATUS_SUCCESS) {
2595 rtsx_trace(chip);
2596 return retval;
2597 }
2598 }
2599
2600 if (ms_card->segment[seg_no].build_flag) {
2601 dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n",
2602 seg_no);
2603 return STATUS_SUCCESS;
2604 }
2605
2606 if (seg_no == 0)
2607 table_size = 494;
2608 else
2609 table_size = 496;
2610
2611 segment = &(ms_card->segment[seg_no]);
2612
2613 if (!segment->l2p_table) {
2614 segment->l2p_table = vmalloc(table_size * 2);
2615 if (!segment->l2p_table) {
2616 rtsx_trace(chip);
2617 goto BUILD_FAIL;
2618 }
2619 }
2620 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2);
2621
2622 if (!segment->free_table) {
2623 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2);
2624 if (!segment->free_table) {
2625 rtsx_trace(chip);
2626 goto BUILD_FAIL;
2627 }
2628 }
2629 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
2630
2631 start = (u16)seg_no << 9;
2632 end = (u16)(seg_no + 1) << 9;
2633
2634 disable_cnt = segment->disable_count;
2635
2636 segment->get_index = segment->set_index = 0;
2637 segment->unused_blk_cnt = 0;
2638
2639 for (phy_blk = start; phy_blk < end; phy_blk++) {
2640 if (disable_cnt) {
2641 defect_flag = false;
2642 for (i = 0; i < segment->disable_count; i++) {
2643 if (phy_blk == segment->defect_list[i]) {
2644 defect_flag = true;
2645 break;
2646 }
2647 }
2648 if (defect_flag) {
2649 disable_cnt--;
2650 continue;
2651 }
2652 }
2653
2654 retval = ms_read_extra_data(chip, phy_blk, 0,
2655 extra, MS_EXTRA_SIZE);
2656 if (retval != STATUS_SUCCESS) {
2657 dev_dbg(rtsx_dev(chip), "read extra data fail\n");
2658 ms_set_bad_block(chip, phy_blk);
2659 continue;
2660 }
2661
2662 if (seg_no == ms_card->segment_cnt - 1) {
2663 if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
2664 if (!(chip->card_wp & MS_CARD)) {
2665 retval = ms_erase_block(chip, phy_blk);
2666 if (retval != STATUS_SUCCESS)
2667 continue;
2668 extra[2] = 0xff;
2669 extra[3] = 0xff;
2670 }
2671 }
2672 }
2673
2674 if (!(extra[0] & BLOCK_OK))
2675 continue;
2676 if (!(extra[1] & NOT_BOOT_BLOCK))
2677 continue;
2678 if ((extra[0] & PAGE_OK) != PAGE_OK)
2679 continue;
2680
2681 log_blk = ((u16)extra[2] << 8) | extra[3];
2682
2683 if (log_blk == 0xFFFF) {
2684 if (!(chip->card_wp & MS_CARD)) {
2685 retval = ms_erase_block(chip, phy_blk);
2686 if (retval != STATUS_SUCCESS)
2687 continue;
2688 }
2689 ms_set_unused_block(chip, phy_blk);
2690 continue;
2691 }
2692
2693 if ((log_blk < ms_start_idx[seg_no]) ||
2694 (log_blk >= ms_start_idx[seg_no+1])) {
2695 if (!(chip->card_wp & MS_CARD)) {
2696 retval = ms_erase_block(chip, phy_blk);
2697 if (retval != STATUS_SUCCESS)
2698 continue;
2699 }
2700 ms_set_unused_block(chip, phy_blk);
2701 continue;
2702 }
2703
2704 idx = log_blk - ms_start_idx[seg_no];
2705
2706 if (segment->l2p_table[idx] == 0xFFFF) {
2707 segment->l2p_table[idx] = phy_blk;
2708 continue;
2709 }
2710
2711 us1 = extra[0] & 0x10;
2712 tmp_blk = segment->l2p_table[idx];
2713 retval = ms_read_extra_data(chip, tmp_blk, 0,
2714 extra, MS_EXTRA_SIZE);
2715 if (retval != STATUS_SUCCESS)
2716 continue;
2717 us2 = extra[0] & 0x10;
2718
2719 (void)ms_arbitrate_l2p(chip, phy_blk,
2720 log_blk-ms_start_idx[seg_no], us1, us2);
2721 continue;
2722 }
2723
2724 segment->build_flag = 1;
2725
2726 dev_dbg(rtsx_dev(chip), "unused block count: %d\n",
2727 segment->unused_blk_cnt);
2728
2729 /* Logical Address Confirmation Process */
2730 if (seg_no == ms_card->segment_cnt - 1) {
2731 if (segment->unused_blk_cnt < 2)
2732 chip->card_wp |= MS_CARD;
2733 } else {
2734 if (segment->unused_blk_cnt < 1)
2735 chip->card_wp |= MS_CARD;
2736 }
2737
2738 if (chip->card_wp & MS_CARD)
2739 return STATUS_SUCCESS;
2740
2741 for (log_blk = ms_start_idx[seg_no];
2742 log_blk < ms_start_idx[seg_no + 1]; log_blk++) {
2743 idx = log_blk - ms_start_idx[seg_no];
2744 if (segment->l2p_table[idx] == 0xFFFF) {
2745 phy_blk = ms_get_unused_block(chip, seg_no);
2746 if (phy_blk == 0xFFFF) {
2747 chip->card_wp |= MS_CARD;
2748 return STATUS_SUCCESS;
2749 }
2750 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
2751 if (retval != STATUS_SUCCESS) {
2752 rtsx_trace(chip);
2753 goto BUILD_FAIL;
2754 }
2755
2756 segment->l2p_table[idx] = phy_blk;
2757 if (seg_no == ms_card->segment_cnt - 1) {
2758 if (segment->unused_blk_cnt < 2) {
2759 chip->card_wp |= MS_CARD;
2760 return STATUS_SUCCESS;
2761 }
2762 } else {
2763 if (segment->unused_blk_cnt < 1) {
2764 chip->card_wp |= MS_CARD;
2765 return STATUS_SUCCESS;
2766 }
2767 }
2768 }
2769 }
2770
2771 /* Make boot block be the first normal block */
2772 if (seg_no == 0) {
2773 for (log_blk = 0; log_blk < 494; log_blk++) {
2774 tmp_blk = segment->l2p_table[log_blk];
2775 if (tmp_blk < ms_card->boot_block) {
2776 dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n");
2777
2778 if (chip->card_wp & MS_CARD)
2779 break;
2780
2781 phy_blk = ms_get_unused_block(chip, 0);
2782 retval = ms_copy_page(chip, tmp_blk, phy_blk,
2783 log_blk, 0, ms_card->page_off + 1);
2784 if (retval != STATUS_SUCCESS) {
2785 rtsx_trace(chip);
2786 return STATUS_FAIL;
2787 }
2788
2789 segment->l2p_table[log_blk] = phy_blk;
2790
2791 retval = ms_set_bad_block(chip, tmp_blk);
2792 if (retval != STATUS_SUCCESS) {
2793 rtsx_trace(chip);
2794 return STATUS_FAIL;
2795 }
2796 }
2797 }
2798 }
2799
2800 return STATUS_SUCCESS;
2801
2802 BUILD_FAIL:
2803 segment->build_flag = 0;
2804 vfree(segment->l2p_table);
2805 segment->l2p_table = NULL;
2806 vfree(segment->free_table);
2807 segment->free_table = NULL;
2808
2809 return STATUS_FAIL;
2810 }
2811
2812
2813 int reset_ms_card(struct rtsx_chip *chip)
2814 {
2815 struct ms_info *ms_card = &chip->ms_card;
2816 int retval;
2817
2818 memset(ms_card, 0, sizeof(struct ms_info));
2819
2820 retval = enable_card_clock(chip, MS_CARD);
2821 if (retval != STATUS_SUCCESS) {
2822 rtsx_trace(chip);
2823 return STATUS_FAIL;
2824 }
2825
2826 retval = select_card(chip, MS_CARD);
2827 if (retval != STATUS_SUCCESS) {
2828 rtsx_trace(chip);
2829 return STATUS_FAIL;
2830 }
2831
2832 ms_card->ms_type = 0;
2833
2834 retval = reset_ms_pro(chip);
2835 if (retval != STATUS_SUCCESS) {
2836 if (ms_card->check_ms_flow) {
2837 retval = reset_ms(chip);
2838 if (retval != STATUS_SUCCESS) {
2839 rtsx_trace(chip);
2840 return STATUS_FAIL;
2841 }
2842 } else {
2843 rtsx_trace(chip);
2844 return STATUS_FAIL;
2845 }
2846 }
2847
2848 retval = ms_set_init_para(chip);
2849 if (retval != STATUS_SUCCESS) {
2850 rtsx_trace(chip);
2851 return STATUS_FAIL;
2852 }
2853
2854 if (!CHK_MSPRO(ms_card)) {
2855 /* Build table for the last segment,
2856 * to check if L2P table block exists, erasing it
2857 */
2858 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);
2859 if (retval != STATUS_SUCCESS) {
2860 rtsx_trace(chip);
2861 return STATUS_FAIL;
2862 }
2863 }
2864
2865 dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type);
2866
2867 return STATUS_SUCCESS;
2868 }
2869
2870 static int mspro_set_rw_cmd(struct rtsx_chip *chip,
2871 u32 start_sec, u16 sec_cnt, u8 cmd)
2872 {
2873 int retval, i;
2874 u8 data[8];
2875
2876 data[0] = cmd;
2877 data[1] = (u8)(sec_cnt >> 8);
2878 data[2] = (u8)sec_cnt;
2879 data[3] = (u8)(start_sec >> 24);
2880 data[4] = (u8)(start_sec >> 16);
2881 data[5] = (u8)(start_sec >> 8);
2882 data[6] = (u8)start_sec;
2883 data[7] = 0;
2884
2885 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2886 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7,
2887 WAIT_INT, data, 8);
2888 if (retval == STATUS_SUCCESS)
2889 break;
2890 }
2891 if (i == MS_MAX_RETRY_COUNT) {
2892 rtsx_trace(chip);
2893 return STATUS_FAIL;
2894 }
2895
2896 return STATUS_SUCCESS;
2897 }
2898
2899
2900 void mspro_stop_seq_mode(struct rtsx_chip *chip)
2901 {
2902 struct ms_info *ms_card = &chip->ms_card;
2903 int retval;
2904
2905 if (ms_card->seq_mode) {
2906 retval = ms_switch_clock(chip);
2907 if (retval != STATUS_SUCCESS)
2908 return;
2909
2910 ms_card->seq_mode = 0;
2911 ms_card->total_sec_cnt = 0;
2912 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2913
2914 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2915 }
2916 }
2917
2918 static inline int ms_auto_tune_clock(struct rtsx_chip *chip)
2919 {
2920 struct ms_info *ms_card = &chip->ms_card;
2921 int retval;
2922
2923 if (chip->asic_code) {
2924 if (ms_card->ms_clock > 30)
2925 ms_card->ms_clock -= 20;
2926 } else {
2927 if (ms_card->ms_clock == CLK_80)
2928 ms_card->ms_clock = CLK_60;
2929 else if (ms_card->ms_clock == CLK_60)
2930 ms_card->ms_clock = CLK_40;
2931 }
2932
2933 retval = ms_switch_clock(chip);
2934 if (retval != STATUS_SUCCESS) {
2935 rtsx_trace(chip);
2936 return STATUS_FAIL;
2937 }
2938
2939 return STATUS_SUCCESS;
2940 }
2941
2942 static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
2943 struct rtsx_chip *chip, u32 start_sector,
2944 u16 sector_cnt)
2945 {
2946 struct ms_info *ms_card = &chip->ms_card;
2947 bool mode_2k = false;
2948 int retval;
2949 u16 count;
2950 u8 val, trans_mode, rw_tpc, rw_cmd;
2951
2952 ms_set_err_code(chip, MS_NO_ERROR);
2953
2954 ms_card->cleanup_counter = 0;
2955
2956 if (CHK_MSHG(ms_card)) {
2957 if ((start_sector % 4) || (sector_cnt % 4)) {
2958 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2959 rw_tpc = PRO_READ_LONG_DATA;
2960 rw_cmd = PRO_READ_DATA;
2961 } else {
2962 rw_tpc = PRO_WRITE_LONG_DATA;
2963 rw_cmd = PRO_WRITE_DATA;
2964 }
2965 } else {
2966 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2967 rw_tpc = PRO_READ_QUAD_DATA;
2968 rw_cmd = PRO_READ_2K_DATA;
2969 } else {
2970 rw_tpc = PRO_WRITE_QUAD_DATA;
2971 rw_cmd = PRO_WRITE_2K_DATA;
2972 }
2973 mode_2k = true;
2974 }
2975 } else {
2976 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2977 rw_tpc = PRO_READ_LONG_DATA;
2978 rw_cmd = PRO_READ_DATA;
2979 } else {
2980 rw_tpc = PRO_WRITE_LONG_DATA;
2981 rw_cmd = PRO_WRITE_DATA;
2982 }
2983 }
2984
2985 retval = ms_switch_clock(chip);
2986 if (retval != STATUS_SUCCESS) {
2987 rtsx_trace(chip);
2988 return STATUS_FAIL;
2989 }
2990
2991 if (srb->sc_data_direction == DMA_FROM_DEVICE)
2992 trans_mode = MS_TM_AUTO_READ;
2993 else
2994 trans_mode = MS_TM_AUTO_WRITE;
2995
2996 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
2997 if (retval) {
2998 rtsx_trace(chip);
2999 return retval;
3000 }
3001
3002 if (ms_card->seq_mode) {
3003 if ((ms_card->pre_dir != srb->sc_data_direction)
3004 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector)
3005 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))
3006 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))
3007 || !(val & MS_INT_BREQ)
3008 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
3009 ms_card->seq_mode = 0;
3010 ms_card->total_sec_cnt = 0;
3011 if (val & MS_INT_BREQ) {
3012 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
3013 if (retval != STATUS_SUCCESS) {
3014 rtsx_trace(chip);
3015 return STATUS_FAIL;
3016 }
3017
3018 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3019 }
3020 }
3021 }
3022
3023 if (!ms_card->seq_mode) {
3024 ms_card->total_sec_cnt = 0;
3025 if (sector_cnt >= SEQ_START_CRITERIA) {
3026 if ((ms_card->capacity - start_sector) > 0xFE00)
3027 count = 0xFE00;
3028 else
3029 count = (u16)(ms_card->capacity - start_sector);
3030
3031 if (count > sector_cnt) {
3032 if (mode_2k)
3033 ms_card->seq_mode = MODE_2K_SEQ;
3034 else
3035 ms_card->seq_mode = MODE_512_SEQ;
3036 }
3037 } else {
3038 count = sector_cnt;
3039 }
3040 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
3041 if (retval != STATUS_SUCCESS) {
3042 ms_card->seq_mode = 0;
3043 rtsx_trace(chip);
3044 return STATUS_FAIL;
3045 }
3046 }
3047
3048 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt,
3049 WAIT_INT, mode_2k, scsi_sg_count(srb),
3050 scsi_sglist(srb), scsi_bufflen(srb));
3051 if (retval != STATUS_SUCCESS) {
3052 ms_card->seq_mode = 0;
3053 rtsx_read_register(chip, MS_TRANS_CFG, &val);
3054 rtsx_clear_ms_error(chip);
3055
3056 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3057 chip->rw_need_retry = 0;
3058 dev_dbg(rtsx_dev(chip), "No card exist, exit mspro_rw_multi_sector\n");
3059 rtsx_trace(chip);
3060 return STATUS_FAIL;
3061 }
3062
3063 if (val & MS_INT_BREQ)
3064 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
3065
3066 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3067 dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n");
3068 chip->rw_need_retry = 1;
3069 ms_auto_tune_clock(chip);
3070 }
3071
3072 rtsx_trace(chip);
3073 return retval;
3074 }
3075
3076 if (ms_card->seq_mode) {
3077 ms_card->pre_sec_addr = start_sector;
3078 ms_card->pre_sec_cnt = sector_cnt;
3079 ms_card->pre_dir = srb->sc_data_direction;
3080 ms_card->total_sec_cnt += sector_cnt;
3081 }
3082
3083 return STATUS_SUCCESS;
3084 }
3085
3086 static int mspro_read_format_progress(struct rtsx_chip *chip,
3087 const int short_data_len)
3088 {
3089 struct ms_info *ms_card = &chip->ms_card;
3090 int retval, i;
3091 u32 total_progress, cur_progress;
3092 u8 cnt, tmp;
3093 u8 data[8];
3094
3095 dev_dbg(rtsx_dev(chip), "mspro_read_format_progress, short_data_len = %d\n",
3096 short_data_len);
3097
3098 retval = ms_switch_clock(chip);
3099 if (retval != STATUS_SUCCESS) {
3100 ms_card->format_status = FORMAT_FAIL;
3101 rtsx_trace(chip);
3102 return STATUS_FAIL;
3103 }
3104
3105 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
3106 if (retval != STATUS_SUCCESS) {
3107 ms_card->format_status = FORMAT_FAIL;
3108 rtsx_trace(chip);
3109 return STATUS_FAIL;
3110 }
3111
3112 if (!(tmp & MS_INT_BREQ)) {
3113 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) {
3114 ms_card->format_status = FORMAT_SUCCESS;
3115 return STATUS_SUCCESS;
3116 }
3117 ms_card->format_status = FORMAT_FAIL;
3118 rtsx_trace(chip);
3119 return STATUS_FAIL;
3120 }
3121
3122 if (short_data_len >= 256)
3123 cnt = 0;
3124 else
3125 cnt = (u8)short_data_len;
3126
3127 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT,
3128 MS_NO_CHECK_INT);
3129 if (retval != STATUS_SUCCESS) {
3130 ms_card->format_status = FORMAT_FAIL;
3131 rtsx_trace(chip);
3132 return STATUS_FAIL;
3133 }
3134
3135 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT,
3136 data, 8);
3137 if (retval != STATUS_SUCCESS) {
3138 ms_card->format_status = FORMAT_FAIL;
3139 rtsx_trace(chip);
3140 return STATUS_FAIL;
3141 }
3142
3143 total_progress = (data[0] << 24) | (data[1] << 16) |
3144 (data[2] << 8) | data[3];
3145 cur_progress = (data[4] << 24) | (data[5] << 16) |
3146 (data[6] << 8) | data[7];
3147
3148 dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n",
3149 total_progress, cur_progress);
3150
3151 if (total_progress == 0) {
3152 ms_card->progress = 0;
3153 } else {
3154 u64 ulltmp = (u64)cur_progress * (u64)65535;
3155
3156 do_div(ulltmp, total_progress);
3157 ms_card->progress = (u16)ulltmp;
3158 }
3159 dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress);
3160
3161 for (i = 0; i < 5000; i++) {
3162 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
3163 if (retval != STATUS_SUCCESS) {
3164 ms_card->format_status = FORMAT_FAIL;
3165 rtsx_trace(chip);
3166 return STATUS_FAIL;
3167 }
3168 if (tmp & (MS_INT_CED | MS_INT_CMDNK |
3169 MS_INT_BREQ | MS_INT_ERR))
3170 break;
3171
3172 wait_timeout(1);
3173 }
3174
3175 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0);
3176 if (retval != STATUS_SUCCESS) {
3177 ms_card->format_status = FORMAT_FAIL;
3178 rtsx_trace(chip);
3179 return STATUS_FAIL;
3180 }
3181
3182 if (i == 5000) {
3183 ms_card->format_status = FORMAT_FAIL;
3184 rtsx_trace(chip);
3185 return STATUS_FAIL;
3186 }
3187
3188 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
3189 ms_card->format_status = FORMAT_FAIL;
3190 rtsx_trace(chip);
3191 return STATUS_FAIL;
3192 }
3193
3194 if (tmp & MS_INT_CED) {
3195 ms_card->format_status = FORMAT_SUCCESS;
3196 ms_card->pro_under_formatting = 0;
3197 } else if (tmp & MS_INT_BREQ) {
3198 ms_card->format_status = FORMAT_IN_PROGRESS;
3199 } else {
3200 ms_card->format_status = FORMAT_FAIL;
3201 ms_card->pro_under_formatting = 0;
3202 rtsx_trace(chip);
3203 return STATUS_FAIL;
3204 }
3205
3206 return STATUS_SUCCESS;
3207 }
3208
3209 void mspro_polling_format_status(struct rtsx_chip *chip)
3210 {
3211 struct ms_info *ms_card = &chip->ms_card;
3212 int i;
3213
3214 if (ms_card->pro_under_formatting &&
3215 (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
3216 rtsx_set_stat(chip, RTSX_STAT_RUN);
3217
3218 for (i = 0; i < 65535; i++) {
3219 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
3220 if (ms_card->format_status != FORMAT_IN_PROGRESS)
3221 break;
3222 }
3223 }
3224 }
3225
3226 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3227 int short_data_len, bool quick_format)
3228 {
3229 struct ms_info *ms_card = &chip->ms_card;
3230 int retval, i;
3231 u8 buf[8], tmp;
3232 u16 para;
3233
3234 retval = ms_switch_clock(chip);
3235 if (retval != STATUS_SUCCESS) {
3236 rtsx_trace(chip);
3237 return STATUS_FAIL;
3238 }
3239
3240 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
3241 if (retval != STATUS_SUCCESS) {
3242 rtsx_trace(chip);
3243 return STATUS_FAIL;
3244 }
3245
3246 memset(buf, 0, 2);
3247 switch (short_data_len) {
3248 case 32:
3249 buf[0] = 0;
3250 break;
3251 case 64:
3252 buf[0] = 1;
3253 break;
3254 case 128:
3255 buf[0] = 2;
3256 break;
3257 case 256:
3258 default:
3259 buf[0] = 3;
3260 break;
3261 }
3262
3263 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3264 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1,
3265 NO_WAIT_INT, buf, 2);
3266 if (retval == STATUS_SUCCESS)
3267 break;
3268 }
3269 if (i == MS_MAX_RETRY_COUNT) {
3270 rtsx_trace(chip);
3271 return STATUS_FAIL;
3272 }
3273
3274 if (quick_format)
3275 para = 0x0000;
3276 else
3277 para = 0x0001;
3278
3279 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
3280 if (retval != STATUS_SUCCESS) {
3281 rtsx_trace(chip);
3282 return STATUS_FAIL;
3283 }
3284
3285 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
3286 if (retval) {
3287 rtsx_trace(chip);
3288 return retval;
3289 }
3290
3291 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
3292 rtsx_trace(chip);
3293 return STATUS_FAIL;
3294 }
3295
3296 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
3297 ms_card->pro_under_formatting = 1;
3298 ms_card->progress = 0;
3299 ms_card->format_status = FORMAT_IN_PROGRESS;
3300 return STATUS_SUCCESS;
3301 }
3302
3303 if (tmp & MS_INT_CED) {
3304 ms_card->pro_under_formatting = 0;
3305 ms_card->progress = 0;
3306 ms_card->format_status = FORMAT_SUCCESS;
3307 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
3308 return STATUS_SUCCESS;
3309 }
3310
3311 rtsx_trace(chip);
3312 return STATUS_FAIL;
3313 }
3314
3315
3316 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk,
3317 u16 log_blk, u8 start_page, u8 end_page,
3318 u8 *buf, unsigned int *index,
3319 unsigned int *offset)
3320 {
3321 struct ms_info *ms_card = &chip->ms_card;
3322 int retval, i;
3323 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
3324 u8 *ptr;
3325
3326 retval = ms_read_extra_data(chip, phy_blk, start_page,
3327 extra, MS_EXTRA_SIZE);
3328 if (retval == STATUS_SUCCESS) {
3329 if ((extra[1] & 0x30) != 0x30) {
3330 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3331 rtsx_trace(chip);
3332 return STATUS_FAIL;
3333 }
3334 }
3335
3336 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3337 SystemParm, 6);
3338 if (retval != STATUS_SUCCESS) {
3339 rtsx_trace(chip);
3340 return STATUS_FAIL;
3341 }
3342
3343 if (CHK_MS4BIT(ms_card))
3344 data[0] = 0x88;
3345 else
3346 data[0] = 0x80;
3347
3348 data[1] = 0;
3349 data[2] = (u8)(phy_blk >> 8);
3350 data[3] = (u8)phy_blk;
3351 data[4] = 0;
3352 data[5] = start_page;
3353
3354 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3355 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
3356 data, 6);
3357 if (retval == STATUS_SUCCESS)
3358 break;
3359 }
3360 if (i == MS_MAX_RETRY_COUNT) {
3361 rtsx_trace(chip);
3362 return STATUS_FAIL;
3363 }
3364
3365 ms_set_err_code(chip, MS_NO_ERROR);
3366
3367 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
3368 if (retval != STATUS_SUCCESS) {
3369 rtsx_trace(chip);
3370 return STATUS_FAIL;
3371 }
3372
3373 ptr = buf;
3374
3375 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3376 ms_set_err_code(chip, MS_NO_ERROR);
3377
3378 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3379 ms_set_err_code(chip, MS_NO_CARD);
3380 rtsx_trace(chip);
3381 return STATUS_FAIL;
3382 }
3383
3384 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3385 if (retval != STATUS_SUCCESS) {
3386 rtsx_trace(chip);
3387 return STATUS_FAIL;
3388 }
3389
3390 if (val & INT_REG_CMDNK) {
3391 ms_set_err_code(chip, MS_CMD_NK);
3392 rtsx_trace(chip);
3393 return STATUS_FAIL;
3394 }
3395 if (val & INT_REG_ERR) {
3396 if (val & INT_REG_BREQ) {
3397 retval = ms_read_status_reg(chip);
3398 if (retval != STATUS_SUCCESS) {
3399 if (!(chip->card_wp & MS_CARD)) {
3400 reset_ms(chip);
3401 ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE);
3402 ms_write_extra_data(chip, phy_blk,
3403 page_addr, extra, MS_EXTRA_SIZE);
3404 }
3405 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3406 rtsx_trace(chip);
3407 return STATUS_FAIL;
3408 }
3409 } else {
3410 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3411 rtsx_trace(chip);
3412 return STATUS_FAIL;
3413 }
3414 } else {
3415 if (!(val & INT_REG_BREQ)) {
3416 ms_set_err_code(chip, MS_BREQ_ERROR);
3417 rtsx_trace(chip);
3418 return STATUS_FAIL;
3419 }
3420 }
3421
3422 if (page_addr == (end_page - 1)) {
3423 if (!(val & INT_REG_CED)) {
3424 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
3425 if (retval != STATUS_SUCCESS) {
3426 rtsx_trace(chip);
3427 return STATUS_FAIL;
3428 }
3429 }
3430
3431 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT,
3432 &val, 1);
3433 if (retval != STATUS_SUCCESS) {
3434 rtsx_trace(chip);
3435 return STATUS_FAIL;
3436 }
3437
3438 if (!(val & INT_REG_CED)) {
3439 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3440 rtsx_trace(chip);
3441 return STATUS_FAIL;
3442 }
3443
3444 trans_cfg = NO_WAIT_INT;
3445 } else {
3446 trans_cfg = WAIT_INT;
3447 }
3448
3449 rtsx_init_cmd(chip);
3450
3451 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
3452 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
3453 0xFF, trans_cfg);
3454 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3455 0x01, RING_BUFFER);
3456
3457 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
3458
3459 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3460 MS_TRANSFER_START | MS_TM_NORMAL_READ);
3461 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3462 MS_TRANSFER_END, MS_TRANSFER_END);
3463
3464 rtsx_send_cmd_no_wait(chip);
3465
3466 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr,
3467 512, scsi_sg_count(chip->srb),
3468 index, offset, DMA_FROM_DEVICE,
3469 chip->ms_timeout);
3470 if (retval < 0) {
3471 if (retval == -ETIMEDOUT) {
3472 ms_set_err_code(chip, MS_TO_ERROR);
3473 rtsx_clear_ms_error(chip);
3474 rtsx_trace(chip);
3475 return STATUS_TIMEDOUT;
3476 }
3477
3478 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3479 if (retval != STATUS_SUCCESS) {
3480 ms_set_err_code(chip, MS_TO_ERROR);
3481 rtsx_clear_ms_error(chip);
3482 rtsx_trace(chip);
3483 return STATUS_TIMEDOUT;
3484 }
3485 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3486 ms_set_err_code(chip, MS_CRC16_ERROR);
3487 rtsx_clear_ms_error(chip);
3488 rtsx_trace(chip);
3489 return STATUS_FAIL;
3490 }
3491 }
3492
3493 if (scsi_sg_count(chip->srb) == 0)
3494 ptr += 512;
3495 }
3496
3497 return STATUS_SUCCESS;
3498 }
3499
3500 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk,
3501 u16 new_blk, u16 log_blk, u8 start_page,
3502 u8 end_page, u8 *buf, unsigned int *index,
3503 unsigned int *offset)
3504 {
3505 struct ms_info *ms_card = &chip->ms_card;
3506 int retval, i;
3507 u8 page_addr, val, data[16];
3508 u8 *ptr;
3509
3510 if (!start_page) {
3511 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3512 SystemParm, 7);
3513 if (retval != STATUS_SUCCESS) {
3514 rtsx_trace(chip);
3515 return STATUS_FAIL;
3516 }
3517
3518 if (CHK_MS4BIT(ms_card))
3519 data[0] = 0x88;
3520 else
3521 data[0] = 0x80;
3522
3523 data[1] = 0;
3524 data[2] = (u8)(old_blk >> 8);
3525 data[3] = (u8)old_blk;
3526 data[4] = 0x80;
3527 data[5] = 0;
3528 data[6] = 0xEF;
3529 data[7] = 0xFF;
3530
3531 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT,
3532 data, 8);
3533 if (retval != STATUS_SUCCESS) {
3534 rtsx_trace(chip);
3535 return STATUS_FAIL;
3536 }
3537
3538 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3539 if (retval != STATUS_SUCCESS) {
3540 rtsx_trace(chip);
3541 return STATUS_FAIL;
3542 }
3543
3544 ms_set_err_code(chip, MS_NO_ERROR);
3545 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
3546 NO_WAIT_INT);
3547 if (retval != STATUS_SUCCESS) {
3548 rtsx_trace(chip);
3549 return STATUS_FAIL;
3550 }
3551 }
3552
3553 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3554 SystemParm, (6 + MS_EXTRA_SIZE));
3555 if (retval != STATUS_SUCCESS) {
3556 rtsx_trace(chip);
3557 return STATUS_FAIL;
3558 }
3559
3560 ms_set_err_code(chip, MS_NO_ERROR);
3561
3562 if (CHK_MS4BIT(ms_card))
3563 data[0] = 0x88;
3564 else
3565 data[0] = 0x80;
3566
3567 data[1] = 0;
3568 data[2] = (u8)(new_blk >> 8);
3569 data[3] = (u8)new_blk;
3570 if ((end_page - start_page) == 1)
3571 data[4] = 0x20;
3572 else
3573 data[4] = 0;
3574
3575 data[5] = start_page;
3576 data[6] = 0xF8;
3577 data[7] = 0xFF;
3578 data[8] = (u8)(log_blk >> 8);
3579 data[9] = (u8)log_blk;
3580
3581 for (i = 0x0A; i < 0x10; i++)
3582 data[i] = 0xFF;
3583
3584 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3585 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE,
3586 NO_WAIT_INT, data, 16);
3587 if (retval == STATUS_SUCCESS)
3588 break;
3589 }
3590 if (i == MS_MAX_RETRY_COUNT) {
3591 rtsx_trace(chip);
3592 return STATUS_FAIL;
3593 }
3594
3595 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3596 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3597 if (retval == STATUS_SUCCESS)
3598 break;
3599 }
3600 if (i == MS_MAX_RETRY_COUNT) {
3601 rtsx_trace(chip);
3602 return STATUS_FAIL;
3603 }
3604
3605 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3606 if (retval != STATUS_SUCCESS) {
3607 rtsx_trace(chip);
3608 return STATUS_FAIL;
3609 }
3610
3611 ptr = buf;
3612 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3613 ms_set_err_code(chip, MS_NO_ERROR);
3614
3615 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3616 ms_set_err_code(chip, MS_NO_CARD);
3617 rtsx_trace(chip);
3618 return STATUS_FAIL;
3619 }
3620
3621 if (val & INT_REG_CMDNK) {
3622 ms_set_err_code(chip, MS_CMD_NK);
3623 rtsx_trace(chip);
3624 return STATUS_FAIL;
3625 }
3626 if (val & INT_REG_ERR) {
3627 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3628 rtsx_trace(chip);
3629 return STATUS_FAIL;
3630 }
3631 if (!(val & INT_REG_BREQ)) {
3632 ms_set_err_code(chip, MS_BREQ_ERROR);
3633 rtsx_trace(chip);
3634 return STATUS_FAIL;
3635 }
3636
3637 udelay(30);
3638
3639 rtsx_init_cmd(chip);
3640
3641 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
3642 0xFF, WRITE_PAGE_DATA);
3643 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
3644 0xFF, WAIT_INT);
3645 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3646 0x01, RING_BUFFER);
3647
3648 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3649
3650 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3651 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3652 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3653 MS_TRANSFER_END, MS_TRANSFER_END);
3654
3655 rtsx_send_cmd_no_wait(chip);
3656
3657 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr,
3658 512, scsi_sg_count(chip->srb),
3659 index, offset, DMA_TO_DEVICE,
3660 chip->ms_timeout);
3661 if (retval < 0) {
3662 ms_set_err_code(chip, MS_TO_ERROR);
3663 rtsx_clear_ms_error(chip);
3664
3665 if (retval == -ETIMEDOUT) {
3666 rtsx_trace(chip);
3667 return STATUS_TIMEDOUT;
3668 }
3669 rtsx_trace(chip);
3670 return STATUS_FAIL;
3671 }
3672
3673 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3674 if (retval != STATUS_SUCCESS) {
3675 rtsx_trace(chip);
3676 return STATUS_FAIL;
3677 }
3678
3679 if ((end_page - start_page) == 1) {
3680 if (!(val & INT_REG_CED)) {
3681 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3682 rtsx_trace(chip);
3683 return STATUS_FAIL;
3684 }
3685 } else {
3686 if (page_addr == (end_page - 1)) {
3687 if (!(val & INT_REG_CED)) {
3688 retval = ms_send_cmd(chip, BLOCK_END,
3689 WAIT_INT);
3690 if (retval != STATUS_SUCCESS) {
3691 rtsx_trace(chip);
3692 return STATUS_FAIL;
3693 }
3694 }
3695
3696 retval = ms_read_bytes(chip, GET_INT, 1,
3697 NO_WAIT_INT, &val, 1);
3698 if (retval != STATUS_SUCCESS) {
3699 rtsx_trace(chip);
3700 return STATUS_FAIL;
3701 }
3702 }
3703
3704 if ((page_addr == (end_page - 1)) ||
3705 (page_addr == ms_card->page_off)) {
3706 if (!(val & INT_REG_CED)) {
3707 ms_set_err_code(chip,
3708 MS_FLASH_WRITE_ERROR);
3709 rtsx_trace(chip);
3710 return STATUS_FAIL;
3711 }
3712 }
3713 }
3714
3715 if (scsi_sg_count(chip->srb) == 0)
3716 ptr += 512;
3717 }
3718
3719 return STATUS_SUCCESS;
3720 }
3721
3722
3723 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3724 u16 log_blk, u8 page_off)
3725 {
3726 struct ms_info *ms_card = &chip->ms_card;
3727 int retval, seg_no;
3728
3729 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3730 page_off, ms_card->page_off + 1);
3731 if (retval != STATUS_SUCCESS) {
3732 rtsx_trace(chip);
3733 return STATUS_FAIL;
3734 }
3735
3736 seg_no = old_blk >> 9;
3737
3738 if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
3739 MS_CLR_BAD_BLOCK_FLG(ms_card);
3740 ms_set_bad_block(chip, old_blk);
3741 } else {
3742 retval = ms_erase_block(chip, old_blk);
3743 if (retval == STATUS_SUCCESS)
3744 ms_set_unused_block(chip, old_blk);
3745 }
3746
3747 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3748
3749 return STATUS_SUCCESS;
3750 }
3751
3752 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3753 u16 log_blk, u8 start_page)
3754 {
3755 int retval;
3756
3757 if (start_page) {
3758 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3759 0, start_page);
3760 if (retval != STATUS_SUCCESS) {
3761 rtsx_trace(chip);
3762 return STATUS_FAIL;
3763 }
3764 }
3765
3766 return STATUS_SUCCESS;
3767 }
3768
3769 #ifdef MS_DELAY_WRITE
3770 int ms_delay_write(struct rtsx_chip *chip)
3771 {
3772 struct ms_info *ms_card = &chip->ms_card;
3773 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3774 int retval;
3775
3776 if (delay_write->delay_write_flag) {
3777 retval = ms_set_init_para(chip);
3778 if (retval != STATUS_SUCCESS) {
3779 rtsx_trace(chip);
3780 return STATUS_FAIL;
3781 }
3782
3783 delay_write->delay_write_flag = 0;
3784 retval = ms_finish_write(chip,
3785 delay_write->old_phyblock,
3786 delay_write->new_phyblock,
3787 delay_write->logblock,
3788 delay_write->pageoff);
3789 if (retval != STATUS_SUCCESS) {
3790 rtsx_trace(chip);
3791 return STATUS_FAIL;
3792 }
3793 }
3794
3795 return STATUS_SUCCESS;
3796 }
3797 #endif
3798
3799 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3800 {
3801 if (srb->sc_data_direction == DMA_FROM_DEVICE)
3802 set_sense_type(chip, SCSI_LUN(srb),
3803 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3804 else
3805 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
3806 }
3807
3808 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3809 u32 start_sector, u16 sector_cnt)
3810 {
3811 struct ms_info *ms_card = &chip->ms_card;
3812 unsigned int lun = SCSI_LUN(srb);
3813 int retval, seg_no;
3814 unsigned int index = 0, offset = 0;
3815 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
3816 u8 start_page, end_page = 0, page_cnt;
3817 u8 *ptr;
3818 #ifdef MS_DELAY_WRITE
3819 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3820 #endif
3821
3822 ms_set_err_code(chip, MS_NO_ERROR);
3823
3824 ms_card->cleanup_counter = 0;
3825
3826 ptr = (u8 *)scsi_sglist(srb);
3827
3828 retval = ms_switch_clock(chip);
3829 if (retval != STATUS_SUCCESS) {
3830 ms_rw_fail(srb, chip);
3831 rtsx_trace(chip);
3832 return STATUS_FAIL;
3833 }
3834
3835 log_blk = (u16)(start_sector >> ms_card->block_shift);
3836 start_page = (u8)(start_sector & ms_card->page_off);
3837
3838 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {
3839 if (log_blk < ms_start_idx[seg_no+1])
3840 break;
3841 }
3842
3843 if (ms_card->segment[seg_no].build_flag == 0) {
3844 retval = ms_build_l2p_tbl(chip, seg_no);
3845 if (retval != STATUS_SUCCESS) {
3846 chip->card_fail |= MS_CARD;
3847 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3848 rtsx_trace(chip);
3849 return STATUS_FAIL;
3850 }
3851 }
3852
3853 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3854 #ifdef MS_DELAY_WRITE
3855 if (delay_write->delay_write_flag &&
3856 (delay_write->logblock == log_blk) &&
3857 (start_page > delay_write->pageoff)) {
3858 delay_write->delay_write_flag = 0;
3859 retval = ms_copy_page(chip,
3860 delay_write->old_phyblock,
3861 delay_write->new_phyblock, log_blk,
3862 delay_write->pageoff, start_page);
3863 if (retval != STATUS_SUCCESS) {
3864 set_sense_type(chip, lun,
3865 SENSE_TYPE_MEDIA_WRITE_ERR);
3866 rtsx_trace(chip);
3867 return STATUS_FAIL;
3868 }
3869 old_blk = delay_write->old_phyblock;
3870 new_blk = delay_write->new_phyblock;
3871 } else if (delay_write->delay_write_flag &&
3872 (delay_write->logblock == log_blk) &&
3873 (start_page == delay_write->pageoff)) {
3874 delay_write->delay_write_flag = 0;
3875 old_blk = delay_write->old_phyblock;
3876 new_blk = delay_write->new_phyblock;
3877 } else {
3878 retval = ms_delay_write(chip);
3879 if (retval != STATUS_SUCCESS) {
3880 set_sense_type(chip, lun,
3881 SENSE_TYPE_MEDIA_WRITE_ERR);
3882 rtsx_trace(chip);
3883 return STATUS_FAIL;
3884 }
3885 #endif
3886 old_blk = ms_get_l2p_tbl(chip, seg_no,
3887 log_blk - ms_start_idx[seg_no]);
3888 new_blk = ms_get_unused_block(chip, seg_no);
3889 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
3890 set_sense_type(chip, lun,
3891 SENSE_TYPE_MEDIA_WRITE_ERR);
3892 rtsx_trace(chip);
3893 return STATUS_FAIL;
3894 }
3895
3896 retval = ms_prepare_write(chip, old_blk, new_blk,
3897 log_blk, start_page);
3898 if (retval != STATUS_SUCCESS) {
3899 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3900 set_sense_type(chip, lun,
3901 SENSE_TYPE_MEDIA_NOT_PRESENT);
3902 rtsx_trace(chip);
3903 return STATUS_FAIL;
3904 }
3905 set_sense_type(chip, lun,
3906 SENSE_TYPE_MEDIA_WRITE_ERR);
3907 rtsx_trace(chip);
3908 return STATUS_FAIL;
3909 }
3910 #ifdef MS_DELAY_WRITE
3911 }
3912 #endif
3913 } else {
3914 #ifdef MS_DELAY_WRITE
3915 retval = ms_delay_write(chip);
3916 if (retval != STATUS_SUCCESS) {
3917 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3918 set_sense_type(chip, lun,
3919 SENSE_TYPE_MEDIA_NOT_PRESENT);
3920 rtsx_trace(chip);
3921 return STATUS_FAIL;
3922 }
3923 set_sense_type(chip, lun,
3924 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3925 rtsx_trace(chip);
3926 return STATUS_FAIL;
3927 }
3928 #endif
3929 old_blk = ms_get_l2p_tbl(chip, seg_no,
3930 log_blk - ms_start_idx[seg_no]);
3931 if (old_blk == 0xFFFF) {
3932 set_sense_type(chip, lun,
3933 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3934 rtsx_trace(chip);
3935 return STATUS_FAIL;
3936 }
3937 }
3938
3939 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
3940 seg_no, old_blk, new_blk);
3941
3942 while (total_sec_cnt) {
3943 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))
3944 end_page = ms_card->page_off + 1;
3945 else
3946 end_page = start_page + (u8)total_sec_cnt;
3947
3948 page_cnt = end_page - start_page;
3949
3950 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n",
3951 start_page, end_page, page_cnt);
3952
3953 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3954 retval = ms_read_multiple_pages(chip,
3955 old_blk, log_blk, start_page, end_page,
3956 ptr, &index, &offset);
3957 } else {
3958 retval = ms_write_multiple_pages(chip, old_blk,
3959 new_blk, log_blk, start_page, end_page,
3960 ptr, &index, &offset);
3961 }
3962
3963 if (retval != STATUS_SUCCESS) {
3964 toggle_gpio(chip, 1);
3965 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3966 set_sense_type(chip, lun,
3967 SENSE_TYPE_MEDIA_NOT_PRESENT);
3968 rtsx_trace(chip);
3969 return STATUS_FAIL;
3970 }
3971 ms_rw_fail(srb, chip);
3972 rtsx_trace(chip);
3973 return STATUS_FAIL;
3974 }
3975
3976 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3977 if (end_page == (ms_card->page_off + 1)) {
3978 retval = ms_erase_block(chip, old_blk);
3979 if (retval == STATUS_SUCCESS)
3980 ms_set_unused_block(chip, old_blk);
3981
3982 ms_set_l2p_tbl(chip, seg_no,
3983 log_blk - ms_start_idx[seg_no],
3984 new_blk);
3985 }
3986 }
3987
3988 total_sec_cnt -= page_cnt;
3989 if (scsi_sg_count(srb) == 0)
3990 ptr += page_cnt * 512;
3991
3992 if (total_sec_cnt == 0)
3993 break;
3994
3995 log_blk++;
3996
3997 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1;
3998 seg_no++) {
3999 if (log_blk < ms_start_idx[seg_no+1])
4000 break;
4001 }
4002
4003 if (ms_card->segment[seg_no].build_flag == 0) {
4004 retval = ms_build_l2p_tbl(chip, seg_no);
4005 if (retval != STATUS_SUCCESS) {
4006 chip->card_fail |= MS_CARD;
4007 set_sense_type(chip, lun,
4008 SENSE_TYPE_MEDIA_NOT_PRESENT);
4009 rtsx_trace(chip);
4010 return STATUS_FAIL;
4011 }
4012 }
4013
4014 old_blk = ms_get_l2p_tbl(chip, seg_no,
4015 log_blk - ms_start_idx[seg_no]);
4016 if (old_blk == 0xFFFF) {
4017 ms_rw_fail(srb, chip);
4018 rtsx_trace(chip);
4019 return STATUS_FAIL;
4020 }
4021
4022 if (srb->sc_data_direction == DMA_TO_DEVICE) {
4023 new_blk = ms_get_unused_block(chip, seg_no);
4024 if (new_blk == 0xFFFF) {
4025 ms_rw_fail(srb, chip);
4026 rtsx_trace(chip);
4027 return STATUS_FAIL;
4028 }
4029 }
4030
4031 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
4032 seg_no, old_blk, new_blk);
4033
4034 start_page = 0;
4035 }
4036
4037 if (srb->sc_data_direction == DMA_TO_DEVICE) {
4038 if (end_page < (ms_card->page_off + 1)) {
4039 #ifdef MS_DELAY_WRITE
4040 delay_write->delay_write_flag = 1;
4041 delay_write->old_phyblock = old_blk;
4042 delay_write->new_phyblock = new_blk;
4043 delay_write->logblock = log_blk;
4044 delay_write->pageoff = end_page;
4045 #else
4046 retval = ms_finish_write(chip, old_blk, new_blk,
4047 log_blk, end_page);
4048 if (retval != STATUS_SUCCESS) {
4049 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
4050 set_sense_type(chip, lun,
4051 SENSE_TYPE_MEDIA_NOT_PRESENT);
4052 rtsx_trace(chip);
4053 return STATUS_FAIL;
4054 }
4055
4056 ms_rw_fail(srb, chip);
4057 rtsx_trace(chip);
4058 return STATUS_FAIL;
4059 }
4060 #endif
4061 }
4062 }
4063
4064 scsi_set_resid(srb, 0);
4065
4066 return STATUS_SUCCESS;
4067 }
4068
4069 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
4070 u32 start_sector, u16 sector_cnt)
4071 {
4072 struct ms_info *ms_card = &chip->ms_card;
4073 int retval;
4074
4075 if (CHK_MSPRO(ms_card))
4076 retval = mspro_rw_multi_sector(srb, chip, start_sector,
4077 sector_cnt);
4078 else
4079 retval = ms_rw_multi_sector(srb, chip, start_sector,
4080 sector_cnt);
4081
4082 return retval;
4083 }
4084
4085
4086 void ms_free_l2p_tbl(struct rtsx_chip *chip)
4087 {
4088 struct ms_info *ms_card = &chip->ms_card;
4089 int i = 0;
4090
4091 if (ms_card->segment != NULL) {
4092 for (i = 0; i < ms_card->segment_cnt; i++) {
4093 vfree(ms_card->segment[i].l2p_table);
4094 ms_card->segment[i].l2p_table = NULL;
4095 vfree(ms_card->segment[i].free_table);
4096 ms_card->segment[i].free_table = NULL;
4097 }
4098 vfree(ms_card->segment);
4099 ms_card->segment = NULL;
4100 }
4101 }
4102
4103 #ifdef SUPPORT_MAGIC_GATE
4104
4105 #ifdef READ_BYTES_WAIT_INT
4106 static int ms_poll_int(struct rtsx_chip *chip)
4107 {
4108 int retval;
4109 u8 val;
4110
4111 rtsx_init_cmd(chip);
4112
4113 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED);
4114
4115 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
4116 if (retval != STATUS_SUCCESS) {
4117 rtsx_trace(chip);
4118 return STATUS_FAIL;
4119 }
4120
4121 val = *rtsx_get_cmd_data(chip);
4122 if (val & MS_INT_ERR) {
4123 rtsx_trace(chip);
4124 return STATUS_FAIL;
4125 }
4126
4127 return STATUS_SUCCESS;
4128 }
4129 #endif
4130
4131 #ifdef MS_SAMPLE_INT_ERR
4132 static int check_ms_err(struct rtsx_chip *chip)
4133 {
4134 int retval;
4135 u8 val;
4136
4137 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
4138 if (retval != STATUS_SUCCESS)
4139 return 1;
4140 if (val & MS_TRANSFER_ERR)
4141 return 1;
4142
4143 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
4144 if (retval != STATUS_SUCCESS)
4145 return 1;
4146
4147 if (val & (MS_INT_ERR | MS_INT_CMDNK))
4148 return 1;
4149
4150 return 0;
4151 }
4152 #else
4153 static int check_ms_err(struct rtsx_chip *chip)
4154 {
4155 int retval;
4156 u8 val;
4157
4158 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
4159 if (retval != STATUS_SUCCESS)
4160 return 1;
4161 if (val & MS_TRANSFER_ERR)
4162 return 1;
4163
4164 return 0;
4165 }
4166 #endif
4167
4168 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num)
4169 {
4170 int retval, i;
4171 u8 data[8];
4172
4173 data[0] = cmd;
4174 data[1] = 0;
4175 data[2] = 0;
4176 data[3] = 0;
4177 data[4] = 0;
4178 data[5] = 0;
4179 data[6] = entry_num;
4180 data[7] = 0;
4181
4182 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
4183 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT,
4184 data, 8);
4185 if (retval == STATUS_SUCCESS)
4186 break;
4187 }
4188 if (i == MS_MAX_RETRY_COUNT) {
4189 rtsx_trace(chip);
4190 return STATUS_FAIL;
4191 }
4192
4193 if (check_ms_err(chip)) {
4194 rtsx_clear_ms_error(chip);
4195 rtsx_trace(chip);
4196 return STATUS_FAIL;
4197 }
4198
4199 return STATUS_SUCCESS;
4200 }
4201
4202 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type,
4203 u8 mg_entry_num)
4204 {
4205 int retval;
4206 u8 buf[6];
4207
4208 if (type == 0)
4209 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1);
4210 else
4211 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
4212
4213 if (retval != STATUS_SUCCESS) {
4214 rtsx_trace(chip);
4215 return STATUS_FAIL;
4216 }
4217
4218 buf[0] = 0;
4219 buf[1] = 0;
4220 if (type == 1) {
4221 buf[2] = 0;
4222 buf[3] = 0;
4223 buf[4] = 0;
4224 buf[5] = mg_entry_num;
4225 }
4226 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6,
4227 NO_WAIT_INT, buf, 6);
4228 if (retval != STATUS_SUCCESS) {
4229 rtsx_trace(chip);
4230 return STATUS_FAIL;
4231 }
4232
4233 return STATUS_SUCCESS;
4234 }
4235
4236 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4237 {
4238 int retval;
4239 int i;
4240 unsigned int lun = SCSI_LUN(srb);
4241 u8 buf1[32], buf2[12];
4242
4243 if (scsi_bufflen(srb) < 12) {
4244 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4245 rtsx_trace(chip);
4246 return STATUS_FAIL;
4247 }
4248
4249 ms_cleanup_work(chip);
4250
4251 retval = ms_switch_clock(chip);
4252 if (retval != STATUS_SUCCESS) {
4253 rtsx_trace(chip);
4254 return STATUS_FAIL;
4255 }
4256
4257 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0);
4258 if (retval != STATUS_SUCCESS) {
4259 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4260 rtsx_trace(chip);
4261 return STATUS_FAIL;
4262 }
4263
4264 memset(buf1, 0, 32);
4265 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb);
4266 for (i = 0; i < 8; i++)
4267 buf1[8+i] = buf2[4+i];
4268
4269 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
4270 buf1, 32);
4271 if (retval != STATUS_SUCCESS) {
4272 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4273 rtsx_trace(chip);
4274 return STATUS_FAIL;
4275 }
4276 if (check_ms_err(chip)) {
4277 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4278 rtsx_clear_ms_error(chip);
4279 rtsx_trace(chip);
4280 return STATUS_FAIL;
4281 }
4282
4283 return STATUS_SUCCESS;
4284 }
4285
4286 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4287 {
4288 int retval = STATUS_FAIL;
4289 int bufflen;
4290 unsigned int lun = SCSI_LUN(srb);
4291 u8 *buf = NULL;
4292
4293 ms_cleanup_work(chip);
4294
4295 retval = ms_switch_clock(chip);
4296 if (retval != STATUS_SUCCESS) {
4297 rtsx_trace(chip);
4298 return STATUS_FAIL;
4299 }
4300
4301 buf = kmalloc(1540, GFP_KERNEL);
4302 if (!buf) {
4303 rtsx_trace(chip);
4304 return STATUS_ERROR;
4305 }
4306
4307 buf[0] = 0x04;
4308 buf[1] = 0x1A;
4309 buf[2] = 0x00;
4310 buf[3] = 0x00;
4311
4312 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0);
4313 if (retval != STATUS_SUCCESS) {
4314 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4315 rtsx_trace(chip);
4316 goto GetEKBFinish;
4317 }
4318
4319 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
4320 3, WAIT_INT, 0, 0, buf + 4, 1536);
4321 if (retval != STATUS_SUCCESS) {
4322 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4323 rtsx_clear_ms_error(chip);
4324 rtsx_trace(chip);
4325 goto GetEKBFinish;
4326 }
4327 if (check_ms_err(chip)) {
4328 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4329 rtsx_clear_ms_error(chip);
4330 rtsx_trace(chip);
4331 return STATUS_FAIL;
4332 }
4333
4334 bufflen = min_t(int, 1052, scsi_bufflen(srb));
4335 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
4336
4337 GetEKBFinish:
4338 kfree(buf);
4339 return retval;
4340 }
4341
4342 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4343 {
4344 struct ms_info *ms_card = &chip->ms_card;
4345 int retval;
4346 int bufflen;
4347 int i;
4348 unsigned int lun = SCSI_LUN(srb);
4349 u8 buf[32];
4350
4351 ms_cleanup_work(chip);
4352
4353 retval = ms_switch_clock(chip);
4354 if (retval != STATUS_SUCCESS) {
4355 rtsx_trace(chip);
4356 return STATUS_FAIL;
4357 }
4358
4359 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0);
4360 if (retval != STATUS_SUCCESS) {
4361 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4362 rtsx_trace(chip);
4363 return STATUS_FAIL;
4364 }
4365
4366 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
4367 buf, 32);
4368 if (retval != STATUS_SUCCESS) {
4369 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4370 rtsx_trace(chip);
4371 return STATUS_FAIL;
4372 }
4373 if (check_ms_err(chip)) {
4374 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4375 rtsx_clear_ms_error(chip);
4376 rtsx_trace(chip);
4377 return STATUS_FAIL;
4378 }
4379
4380 memcpy(ms_card->magic_gate_id, buf, 16);
4381
4382 #ifdef READ_BYTES_WAIT_INT
4383 retval = ms_poll_int(chip);
4384 if (retval != STATUS_SUCCESS) {
4385 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4386 rtsx_trace(chip);
4387 return STATUS_FAIL;
4388 }
4389 #endif
4390
4391 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0);
4392 if (retval != STATUS_SUCCESS) {
4393 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4394 rtsx_trace(chip);
4395 return STATUS_FAIL;
4396 }
4397
4398 bufflen = min_t(int, 12, scsi_bufflen(srb));
4399 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4400
4401 for (i = 0; i < 8; i++)
4402 buf[i] = buf[4+i];
4403
4404 for (i = 0; i < 24; i++)
4405 buf[8+i] = 0;
4406
4407 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA,
4408 32, WAIT_INT, buf, 32);
4409 if (retval != STATUS_SUCCESS) {
4410 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4411 rtsx_trace(chip);
4412 return STATUS_FAIL;
4413 }
4414 if (check_ms_err(chip)) {
4415 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
4416 rtsx_clear_ms_error(chip);
4417 rtsx_trace(chip);
4418 return STATUS_FAIL;
4419 }
4420
4421 ms_card->mg_auth = 0;
4422
4423 return STATUS_SUCCESS;
4424 }
4425
4426 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4427 {
4428 struct ms_info *ms_card = &chip->ms_card;
4429 int retval;
4430 int bufflen;
4431 unsigned int lun = SCSI_LUN(srb);
4432 u8 buf1[32], buf2[36];
4433
4434 ms_cleanup_work(chip);
4435
4436 retval = ms_switch_clock(chip);
4437 if (retval != STATUS_SUCCESS) {
4438 rtsx_trace(chip);
4439 return STATUS_FAIL;
4440 }
4441
4442 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0);
4443 if (retval != STATUS_SUCCESS) {
4444 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4445 rtsx_trace(chip);
4446 return STATUS_FAIL;
4447 }
4448
4449 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
4450 buf1, 32);
4451 if (retval != STATUS_SUCCESS) {
4452 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4453 rtsx_trace(chip);
4454 return STATUS_FAIL;
4455 }
4456 if (check_ms_err(chip)) {
4457 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4458 rtsx_clear_ms_error(chip);
4459 rtsx_trace(chip);
4460 return STATUS_FAIL;
4461 }
4462
4463 buf2[0] = 0x00;
4464 buf2[1] = 0x22;
4465 buf2[2] = 0x00;
4466 buf2[3] = 0x00;
4467
4468 memcpy(buf2 + 4, ms_card->magic_gate_id, 16);
4469 memcpy(buf2 + 20, buf1, 16);
4470
4471 bufflen = min_t(int, 36, scsi_bufflen(srb));
4472 rtsx_stor_set_xfer_buf(buf2, bufflen, srb);
4473
4474 #ifdef READ_BYTES_WAIT_INT
4475 retval = ms_poll_int(chip);
4476 if (retval != STATUS_SUCCESS) {
4477 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4478 rtsx_trace(chip);
4479 return STATUS_FAIL;
4480 }
4481 #endif
4482
4483 return STATUS_SUCCESS;
4484 }
4485
4486 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4487 {
4488 struct ms_info *ms_card = &chip->ms_card;
4489 int retval;
4490 int i;
4491 int bufflen;
4492 unsigned int lun = SCSI_LUN(srb);
4493 u8 buf[32];
4494
4495 ms_cleanup_work(chip);
4496
4497 retval = ms_switch_clock(chip);
4498 if (retval != STATUS_SUCCESS) {
4499 rtsx_trace(chip);
4500 return STATUS_FAIL;
4501 }
4502
4503 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0);
4504 if (retval != STATUS_SUCCESS) {
4505 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4506 rtsx_trace(chip);
4507 return STATUS_FAIL;
4508 }
4509
4510 bufflen = min_t(int, 12, scsi_bufflen(srb));
4511 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4512
4513 for (i = 0; i < 8; i++)
4514 buf[i] = buf[4+i];
4515
4516 for (i = 0; i < 24; i++)
4517 buf[8+i] = 0;
4518
4519 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
4520 buf, 32);
4521 if (retval != STATUS_SUCCESS) {
4522 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4523 rtsx_trace(chip);
4524 return STATUS_FAIL;
4525 }
4526 if (check_ms_err(chip)) {
4527 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
4528 rtsx_clear_ms_error(chip);
4529 rtsx_trace(chip);
4530 return STATUS_FAIL;
4531 }
4532
4533 ms_card->mg_auth = 1;
4534
4535 return STATUS_SUCCESS;
4536 }
4537
4538 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4539 {
4540 struct ms_info *ms_card = &chip->ms_card;
4541 int retval;
4542 int bufflen;
4543 unsigned int lun = SCSI_LUN(srb);
4544 u8 *buf = NULL;
4545
4546 ms_cleanup_work(chip);
4547
4548 retval = ms_switch_clock(chip);
4549 if (retval != STATUS_SUCCESS) {
4550 rtsx_trace(chip);
4551 return STATUS_FAIL;
4552 }
4553
4554 buf = kmalloc(1028, GFP_KERNEL);
4555 if (!buf) {
4556 rtsx_trace(chip);
4557 return STATUS_ERROR;
4558 }
4559
4560 buf[0] = 0x04;
4561 buf[1] = 0x02;
4562 buf[2] = 0x00;
4563 buf[3] = 0x00;
4564
4565 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num);
4566 if (retval != STATUS_SUCCESS) {
4567 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4568 rtsx_trace(chip);
4569 goto GetICVFinish;
4570 }
4571
4572 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
4573 2, WAIT_INT, 0, 0, buf + 4, 1024);
4574 if (retval != STATUS_SUCCESS) {
4575 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4576 rtsx_clear_ms_error(chip);
4577 rtsx_trace(chip);
4578 goto GetICVFinish;
4579 }
4580 if (check_ms_err(chip)) {
4581 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4582 rtsx_clear_ms_error(chip);
4583 rtsx_trace(chip);
4584 return STATUS_FAIL;
4585 }
4586
4587 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4588 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
4589
4590 GetICVFinish:
4591 kfree(buf);
4592 return retval;
4593 }
4594
4595 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4596 {
4597 struct ms_info *ms_card = &chip->ms_card;
4598 int retval;
4599 int bufflen;
4600 #ifdef MG_SET_ICV_SLOW
4601 int i;
4602 #endif
4603 unsigned int lun = SCSI_LUN(srb);
4604 u8 *buf = NULL;
4605
4606 ms_cleanup_work(chip);
4607
4608 retval = ms_switch_clock(chip);
4609 if (retval != STATUS_SUCCESS) {
4610 rtsx_trace(chip);
4611 return STATUS_FAIL;
4612 }
4613
4614 buf = kmalloc(1028, GFP_KERNEL);
4615 if (!buf) {
4616 rtsx_trace(chip);
4617 return STATUS_ERROR;
4618 }
4619
4620 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4621 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4622
4623 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num);
4624 if (retval != STATUS_SUCCESS) {
4625 if (ms_card->mg_auth == 0) {
4626 if ((buf[5] & 0xC0) != 0)
4627 set_sense_type(chip, lun,
4628 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4629 else
4630 set_sense_type(chip, lun,
4631 SENSE_TYPE_MG_WRITE_ERR);
4632 } else {
4633 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4634 }
4635 rtsx_trace(chip);
4636 goto SetICVFinish;
4637 }
4638
4639 #ifdef MG_SET_ICV_SLOW
4640 for (i = 0; i < 2; i++) {
4641 udelay(50);
4642
4643 rtsx_init_cmd(chip);
4644
4645 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
4646 0xFF, PRO_WRITE_LONG_DATA);
4647 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
4648 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
4649 0x01, RING_BUFFER);
4650
4651 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
4652
4653 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
4654 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
4655 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
4656 MS_TRANSFER_END, MS_TRANSFER_END);
4657
4658 rtsx_send_cmd_no_wait(chip);
4659
4660 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i*512,
4661 512, 0, DMA_TO_DEVICE, 3000);
4662 if ((retval < 0) || check_ms_err(chip)) {
4663 rtsx_clear_ms_error(chip);
4664 if (ms_card->mg_auth == 0) {
4665 if ((buf[5] & 0xC0) != 0)
4666 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4667 else
4668 set_sense_type(chip, lun,
4669 SENSE_TYPE_MG_WRITE_ERR);
4670 } else {
4671 set_sense_type(chip, lun,
4672 SENSE_TYPE_MG_WRITE_ERR);
4673 }
4674 retval = STATUS_FAIL;
4675 rtsx_trace(chip);
4676 goto SetICVFinish;
4677 }
4678 }
4679 #else
4680 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA,
4681 2, WAIT_INT, 0, 0, buf + 4, 1024);
4682 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) {
4683 rtsx_clear_ms_error(chip);
4684 if (ms_card->mg_auth == 0) {
4685 if ((buf[5] & 0xC0) != 0)
4686 set_sense_type(chip, lun,
4687 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4688 else
4689 set_sense_type(chip, lun,
4690 SENSE_TYPE_MG_WRITE_ERR);
4691 } else {
4692 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4693 }
4694 rtsx_trace(chip);
4695 goto SetICVFinish;
4696 }
4697 #endif
4698
4699 SetICVFinish:
4700 kfree(buf);
4701 return retval;
4702 }
4703
4704 #endif /* SUPPORT_MAGIC_GATE */
4705
4706 void ms_cleanup_work(struct rtsx_chip *chip)
4707 {
4708 struct ms_info *ms_card = &(chip->ms_card);
4709
4710 if (CHK_MSPRO(ms_card)) {
4711 if (ms_card->seq_mode) {
4712 dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n");
4713 mspro_stop_seq_mode(chip);
4714 ms_card->cleanup_counter = 0;
4715 }
4716 if (CHK_MSHG(ms_card)) {
4717 rtsx_write_register(chip, MS_CFG,
4718 MS_2K_SECTOR_MODE, 0x00);
4719 }
4720 }
4721 #ifdef MS_DELAY_WRITE
4722 else if ((!CHK_MSPRO(ms_card)) && ms_card->delay_write.delay_write_flag) {
4723 dev_dbg(rtsx_dev(chip), "MS: delay write\n");
4724 ms_delay_write(chip);
4725 ms_card->cleanup_counter = 0;
4726 }
4727 #endif
4728 }
4729
4730 int ms_power_off_card3v3(struct rtsx_chip *chip)
4731 {
4732 int retval;
4733
4734 retval = disable_card_clock(chip, MS_CARD);
4735 if (retval != STATUS_SUCCESS) {
4736 rtsx_trace(chip);
4737 return STATUS_FAIL;
4738 }
4739
4740 if (chip->asic_code) {
4741 retval = ms_pull_ctl_disable(chip);
4742 if (retval != STATUS_SUCCESS) {
4743 rtsx_trace(chip);
4744 return STATUS_FAIL;
4745 }
4746 } else {
4747 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
4748 FPGA_MS_PULL_CTL_BIT | 0x20,
4749 FPGA_MS_PULL_CTL_BIT);
4750 if (retval) {
4751 rtsx_trace(chip);
4752 return retval;
4753 }
4754 }
4755 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
4756 if (retval) {
4757 rtsx_trace(chip);
4758 return retval;
4759 }
4760 if (!chip->ft2_fast_mode) {
4761 retval = card_power_off(chip, MS_CARD);
4762 if (retval != STATUS_SUCCESS) {
4763 rtsx_trace(chip);
4764 return STATUS_FAIL;
4765 }
4766 }
4767
4768 return STATUS_SUCCESS;
4769 }
4770
4771 int release_ms_card(struct rtsx_chip *chip)
4772 {
4773 struct ms_info *ms_card = &(chip->ms_card);
4774 int retval;
4775
4776 #ifdef MS_DELAY_WRITE
4777 ms_card->delay_write.delay_write_flag = 0;
4778 #endif
4779 ms_card->pro_under_formatting = 0;
4780
4781 chip->card_ready &= ~MS_CARD;
4782 chip->card_fail &= ~MS_CARD;
4783 chip->card_wp &= ~MS_CARD;
4784
4785 ms_free_l2p_tbl(chip);
4786
4787 memset(ms_card->raw_sys_info, 0, 96);
4788 #ifdef SUPPORT_PCGL_1P18
4789 memset(ms_card->raw_model_name, 0, 48);
4790 #endif
4791
4792 retval = ms_power_off_card3v3(chip);
4793 if (retval != STATUS_SUCCESS) {
4794 rtsx_trace(chip);
4795 return STATUS_FAIL;
4796 }
4797
4798 return STATUS_SUCCESS;
4799 }
Linux kernel - Deliverables
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