1 #include "ddk750_reg.h"
2 #include "ddk750_help.h"
3 #include "ddk750_display.h"
4 #include "ddk750_power.h"
5 #include "ddk750_dvi.h"
7 #define primaryWaitVerticalSync(delay) waitNextVerticalSync(0, delay)
9 static void setDisplayControl(int ctrl
, int disp_state
)
11 /* state != 0 means turn on both timing & plane en_bit */
12 unsigned long reg
, val
, reserved
;
16 reg
= PANEL_DISPLAY_CTRL
;
17 reserved
= PANEL_DISPLAY_CTRL_RESERVED_MASK
;
19 reg
= CRT_DISPLAY_CTRL
;
20 reserved
= CRT_DISPLAY_CTRL_RESERVED_MASK
;
26 * Timing should be enabled first before enabling the
27 * plane because changing at the same time does not
28 * guarantee that the plane will also enabled or
31 val
|= DISPLAY_CTRL_TIMING
;
34 val
|= DISPLAY_CTRL_PLANE
;
37 * Somehow the register value on the plane is not set
38 * until a few delay. Need to write and read it a
44 } while ((PEEK32(reg
) & ~reserved
) != (val
& ~reserved
));
45 pr_debug("Set Plane enbit:after tried %d times\n", cnt
);
48 * When turning off, there is no rule on the
49 * programming sequence since whenever the clock is
50 * off, then it does not matter whether the plane is
51 * enabled or disabled. Note: Modifying the plane bit
52 * will take effect on the next vertical sync. Need to
53 * find out if it is necessary to wait for 1 vsync
54 * before modifying the timing enable bit.
56 val
&= ~DISPLAY_CTRL_PLANE
;
59 val
&= ~DISPLAY_CTRL_TIMING
;
64 static void waitNextVerticalSync(int ctrl
, int delay
)
69 /* primary controller */
71 /* Do not wait when the Primary PLL is off or display control is already off.
72 This will prevent the software to wait forever. */
73 if (!(PEEK32(PANEL_PLL_CTRL
) & PLL_CTRL_POWER
) ||
74 !(PEEK32(PANEL_DISPLAY_CTRL
) & DISPLAY_CTRL_TIMING
)) {
79 /* Wait for end of vsync. */
81 status
= PEEK32(SYSTEM_CTRL
);
82 } while (status
& SYSTEM_CTRL_PANEL_VSYNC_ACTIVE
);
84 /* Wait for start of vsync. */
86 status
= PEEK32(SYSTEM_CTRL
);
87 } while (!(status
& SYSTEM_CTRL_PANEL_VSYNC_ACTIVE
));
92 /* Do not wait when the Primary PLL is off or display control is already off.
93 This will prevent the software to wait forever. */
94 if (!(PEEK32(CRT_PLL_CTRL
) & PLL_CTRL_POWER
) ||
95 !(PEEK32(CRT_DISPLAY_CTRL
) & DISPLAY_CTRL_TIMING
)) {
100 /* Wait for end of vsync. */
102 status
= PEEK32(SYSTEM_CTRL
);
103 } while (status
& SYSTEM_CTRL_PANEL_VSYNC_ACTIVE
);
105 /* Wait for start of vsync. */
107 status
= PEEK32(SYSTEM_CTRL
);
108 } while (!(status
& SYSTEM_CTRL_PANEL_VSYNC_ACTIVE
));
113 static void swPanelPowerSequence(int disp
, int delay
)
117 /* disp should be 1 to open sequence */
118 reg
= PEEK32(PANEL_DISPLAY_CTRL
);
119 reg
|= (disp
? PANEL_DISPLAY_CTRL_FPEN
: 0);
120 POKE32(PANEL_DISPLAY_CTRL
, reg
);
121 primaryWaitVerticalSync(delay
);
123 reg
= PEEK32(PANEL_DISPLAY_CTRL
);
124 reg
|= (disp
? PANEL_DISPLAY_CTRL_DATA
: 0);
125 POKE32(PANEL_DISPLAY_CTRL
, reg
);
126 primaryWaitVerticalSync(delay
);
128 reg
= PEEK32(PANEL_DISPLAY_CTRL
);
129 reg
|= (disp
? PANEL_DISPLAY_CTRL_VBIASEN
: 0);
130 POKE32(PANEL_DISPLAY_CTRL
, reg
);
131 primaryWaitVerticalSync(delay
);
133 reg
= PEEK32(PANEL_DISPLAY_CTRL
);
134 reg
|= (disp
? PANEL_DISPLAY_CTRL_FPEN
: 0);
135 POKE32(PANEL_DISPLAY_CTRL
, reg
);
136 primaryWaitVerticalSync(delay
);
140 void ddk750_setLogicalDispOut(disp_output_t output
)
144 if (output
& PNL_2_USAGE
) {
145 /* set panel path controller select */
146 reg
= PEEK32(PANEL_DISPLAY_CTRL
);
147 reg
&= ~PANEL_DISPLAY_CTRL_SELECT_MASK
;
148 reg
|= (((output
& PNL_2_MASK
) >> PNL_2_OFFSET
) <<
149 PANEL_DISPLAY_CTRL_SELECT_SHIFT
);
150 POKE32(PANEL_DISPLAY_CTRL
, reg
);
153 if (output
& CRT_2_USAGE
) {
154 /* set crt path controller select */
155 reg
= PEEK32(CRT_DISPLAY_CTRL
);
156 reg
&= ~CRT_DISPLAY_CTRL_SELECT_MASK
;
157 reg
|= (((output
& CRT_2_MASK
) >> CRT_2_OFFSET
) <<
158 CRT_DISPLAY_CTRL_SELECT_SHIFT
);
160 reg
&= ~CRT_DISPLAY_CTRL_BLANK
;
161 POKE32(CRT_DISPLAY_CTRL
, reg
);
165 if (output
& PRI_TP_USAGE
) {
166 /* set primary timing and plane en_bit */
167 setDisplayControl(0, (output
& PRI_TP_MASK
) >> PRI_TP_OFFSET
);
170 if (output
& SEC_TP_USAGE
) {
171 /* set secondary timing and plane en_bit*/
172 setDisplayControl(1, (output
& SEC_TP_MASK
) >> SEC_TP_OFFSET
);
175 if (output
& PNL_SEQ_USAGE
) {
176 /* set panel sequence */
177 swPanelPowerSequence((output
& PNL_SEQ_MASK
) >> PNL_SEQ_OFFSET
, 4);
180 if (output
& DAC_USAGE
)
181 setDAC((output
& DAC_MASK
) >> DAC_OFFSET
);
183 if (output
& DPMS_USAGE
)
184 ddk750_setDPMS((output
& DPMS_MASK
) >> DPMS_OFFSET
);