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Merge git://git.kvack.org/~bcrl/aio-next
[deliverable/linux.git] / drivers / staging / winbond / reg.c
1 #include "wbhal.h"
2 #include "wb35reg_f.h"
3 #include "core.h"
4
5 /*
6 * ====================================================
7 * Original Phy.h
8 * ====================================================
9 */
10
11 /*
12 * ====================================================
13 * For MAXIM2825/6/7 Ver. 331 or more
14 *
15 * 0x00 0x000a2
16 * 0x01 0x21cc0
17 * 0x02 0x13802
18 * 0x02 0x1383a
19 *
20 * channe1 01 ; 0x03 0x30142 ; 0x04 0x0b333;
21 * channe1 02 ; 0x03 0x32141 ; 0x04 0x08444;
22 * channe1 03 ; 0x03 0x32143 ; 0x04 0x0aeee;
23 * channe1 04 ; 0x03 0x32142 ; 0x04 0x0b333;
24 * channe1 05 ; 0x03 0x31141 ; 0x04 0x08444;
25 * channe1 06 ; 0x03 0x31143 ; 0x04 0x0aeee;
26 * channe1 07 ; 0x03 0x31142 ; 0x04 0x0b333;
27 * channe1 08 ; 0x03 0x33141 ; 0x04 0x08444;
28 * channe1 09 ; 0x03 0x33143 ; 0x04 0x0aeee;
29 * channe1 10 ; 0x03 0x33142 ; 0x04 0x0b333;
30 * channe1 11 ; 0x03 0x30941 ; 0x04 0x08444;
31 * channe1 12 ; 0x03 0x30943 ; 0x04 0x0aeee;
32 * channe1 13 ; 0x03 0x30942 ; 0x04 0x0b333;
33 *
34 * 0x05 0x28986
35 * 0x06 0x18008
36 * 0x07 0x38400
37 * 0x08 0x05100; 100 Hz DC
38 * 0x08 0x05900; 30 KHz DC
39 * 0x09 0x24f08
40 * 0x0a 0x17e00, 0x17ea0
41 * 0x0b 0x37d80
42 * 0x0c 0x0c900 -- 0x0ca00 (lager power 9db than 0x0c000), 0x0c000
43 */
44
45 /* MAX2825 (pure b/g) */
46 static u32 max2825_rf_data[] = {
47 (0x00<<18) | 0x000a2,
48 (0x01<<18) | 0x21cc0,
49 (0x02<<18) | 0x13806,
50 (0x03<<18) | 0x30142,
51 (0x04<<18) | 0x0b333,
52 (0x05<<18) | 0x289A6,
53 (0x06<<18) | 0x18008,
54 (0x07<<18) | 0x38000,
55 (0x08<<18) | 0x05100,
56 (0x09<<18) | 0x24f08,
57 (0x0A<<18) | 0x14000,
58 (0x0B<<18) | 0x37d80,
59 (0x0C<<18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */
60 };
61
62 static u32 max2825_channel_data_24[][3] = {
63 {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 01 */
64 {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 02 */
65 {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 03 */
66 {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 04 */
67 {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 05 */
68 {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 06 */
69 {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 07 */
70 {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 08 */
71 {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 09 */
72 {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 10 */
73 {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channel 11 */
74 {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channel 12 */
75 {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 13 */
76 {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */
77 };
78
79 static u32 max2825_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
80
81 /* ========================================== */
82 /* MAX2827 (a/b/g) */
83 static u32 max2827_rf_data[] = {
84 (0x00 << 18) | 0x000a2,
85 (0x01 << 18) | 0x21cc0,
86 (0x02 << 18) | 0x13806,
87 (0x03 << 18) | 0x30142,
88 (0x04 << 18) | 0x0b333,
89 (0x05 << 18) | 0x289A6,
90 (0x06 << 18) | 0x18008,
91 (0x07 << 18) | 0x38000,
92 (0x08 << 18) | 0x05100,
93 (0x09 << 18) | 0x24f08,
94 (0x0A << 18) | 0x14000,
95 (0x0B << 18) | 0x37d80,
96 (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */
97 };
98
99 static u32 max2827_channel_data_24[][3] = {
100 {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */
101 {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */
102 {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */
103 {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */
104 {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */
105 {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */
106 {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */
107 {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */
108 {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */
109 {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */
110 {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */
111 {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */
112 {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */
113 {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */
114 };
115
116 static u32 max2827_channel_data_50[][3] = {
117 {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 36 */
118 {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 40 */
119 {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6}, /* channel 44 */
120 {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x2A9A6}, /* channel 48 */
121 {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x2A9A6}, /* channel 52 */
122 {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x2A9A6}, /* channel 56 */
123 {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x2A9A6}, /* channel 60 */
124 {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x2A9A6} /* channel 64 */
125 };
126
127 static u32 max2827_power_data_24[] = {(0x0C << 18) | 0x0C000, (0x0C << 18) | 0x0D600, (0x0C << 18) | 0x0C100};
128 static u32 max2827_power_data_50[] = {(0x0C << 18) | 0x0C400, (0x0C << 18) | 0x0D500, (0x0C << 18) | 0x0C300};
129
130 /* ======================================================= */
131 /* MAX2828 (a/b/g) */
132 static u32 max2828_rf_data[] = {
133 (0x00 << 18) | 0x000a2,
134 (0x01 << 18) | 0x21cc0,
135 (0x02 << 18) | 0x13806,
136 (0x03 << 18) | 0x30142,
137 (0x04 << 18) | 0x0b333,
138 (0x05 << 18) | 0x289A6,
139 (0x06 << 18) | 0x18008,
140 (0x07 << 18) | 0x38000,
141 (0x08 << 18) | 0x05100,
142 (0x09 << 18) | 0x24f08,
143 (0x0A << 18) | 0x14000,
144 (0x0B << 18) | 0x37d80,
145 (0x0C << 18) | 0x0c100 /* 11a: 0x0c300, 11g: 0x0c100 */
146 };
147
148 static u32 max2828_channel_data_24[][3] = {
149 {(0x03 << 18) | 0x30142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 01 */
150 {(0x03 << 18) | 0x32141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 02 */
151 {(0x03 << 18) | 0x32143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 03 */
152 {(0x03 << 18) | 0x32142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 04 */
153 {(0x03 << 18) | 0x31141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 05 */
154 {(0x03 << 18) | 0x31143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 06 */
155 {(0x03 << 18) | 0x31142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 07 */
156 {(0x03 << 18) | 0x33141, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 08 */
157 {(0x03 << 18) | 0x33143, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 09 */
158 {(0x03 << 18) | 0x33142, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 10 */
159 {(0x03 << 18) | 0x30941, (0x04 << 18) | 0x08444, (0x05 << 18) | 0x289A6}, /* channe1 11 */
160 {(0x03 << 18) | 0x30943, (0x04 << 18) | 0x0aeee, (0x05 << 18) | 0x289A6}, /* channe1 12 */
161 {(0x03 << 18) | 0x30942, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channe1 13 */
162 {(0x03 << 18) | 0x32941, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6} /* channel 14 (2484MHz) */
163 };
164
165 static u32 max2828_channel_data_50[][3] = {
166 {(0x03 << 18) | 0x33cc3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 36 */
167 {(0x03 << 18) | 0x302c0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 40 */
168 {(0x03 << 18) | 0x302c2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6}, /* channel 44 */
169 {(0x03 << 18) | 0x322c1, (0x04 << 18) | 0x09999, (0x05 << 18) | 0x289A6}, /* channel 48 */
170 {(0x03 << 18) | 0x312c1, (0x04 << 18) | 0x0a666, (0x05 << 18) | 0x289A6}, /* channel 52 */
171 {(0x03 << 18) | 0x332c3, (0x04 << 18) | 0x08ccc, (0x05 << 18) | 0x289A6}, /* channel 56 */
172 {(0x03 << 18) | 0x30ac0, (0x04 << 18) | 0x08000, (0x05 << 18) | 0x289A6}, /* channel 60 */
173 {(0x03 << 18) | 0x30ac2, (0x04 << 18) | 0x0b333, (0x05 << 18) | 0x289A6} /* channel 64 */
174 };
175
176 static u32 max2828_power_data_24[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
177 static u32 max2828_power_data_50[] = {(0x0C << 18) | 0x0c000, (0x0C << 18) | 0x0c100};
178
179 /* ========================================================== */
180 /* MAX2829 (a/b/g) */
181 static u32 max2829_rf_data[] = {
182 (0x00 << 18) | 0x000a2,
183 (0x01 << 18) | 0x23520,
184 (0x02 << 18) | 0x13802,
185 (0x03 << 18) | 0x30142,
186 (0x04 << 18) | 0x0b333,
187 (0x05 << 18) | 0x28906,
188 (0x06 << 18) | 0x18008,
189 (0x07 << 18) | 0x3B500,
190 (0x08 << 18) | 0x05100,
191 (0x09 << 18) | 0x24f08,
192 (0x0A << 18) | 0x14000,
193 (0x0B << 18) | 0x37d80,
194 (0x0C << 18) | 0x0F300 /* TXVGA=51, (MAX-6 dB) */
195 };
196
197 static u32 max2829_channel_data_24[][3] = {
198 {(3 << 18) | 0x30142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 01 (2412MHz) */
199 {(3 << 18) | 0x32141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 02 (2417MHz) */
200 {(3 << 18) | 0x32143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 03 (2422MHz) */
201 {(3 << 18) | 0x32142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 04 (2427MHz) */
202 {(3 << 18) | 0x31141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 05 (2432MHz) */
203 {(3 << 18) | 0x31143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 06 (2437MHz) */
204 {(3 << 18) | 0x31142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 07 (2442MHz) */
205 {(3 << 18) | 0x33141, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 08 (2447MHz) */
206 {(3 << 18) | 0x33143, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 09 (2452MHz) */
207 {(3 << 18) | 0x33142, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 10 (2457MHz) */
208 {(3 << 18) | 0x30941, (4 << 18) | 0x08444, (5 << 18) | 0x289C6}, /* 11 (2462MHz) */
209 {(3 << 18) | 0x30943, (4 << 18) | 0x0aeee, (5 << 18) | 0x289C6}, /* 12 (2467MHz) */
210 {(3 << 18) | 0x30942, (4 << 18) | 0x0b333, (5 << 18) | 0x289C6}, /* 13 (2472MHz) */
211 {(3 << 18) | 0x32941, (4 << 18) | 0x09999, (5 << 18) | 0x289C6}, /* 14 (2484MHz) */
212 };
213
214 static u32 max2829_channel_data_50[][4] = {
215 {36, (3 << 18) | 0x33cc3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 36 (5.180GHz) */
216 {40, (3 << 18) | 0x302c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 40 (5.200GHz) */
217 {44, (3 << 18) | 0x302c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 44 (5.220GHz) */
218 {48, (3 << 18) | 0x322c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 48 (5.240GHz) */
219 {52, (3 << 18) | 0x312c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 52 (5.260GHz) */
220 {56, (3 << 18) | 0x332c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 56 (5.280GHz) */
221 {60, (3 << 18) | 0x30ac0, (4 << 18) | 0x08000, (5 << 18) | 0x2A946}, /* 60 (5.300GHz) */
222 {64, (3 << 18) | 0x30ac2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 64 (5.320GHz) */
223
224 {100, (3 << 18) | 0x30ec0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 100 (5.500GHz) */
225 {104, (3 << 18) | 0x30ec2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 104 (5.520GHz) */
226 {108, (3 << 18) | 0x32ec1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 108 (5.540GHz) */
227 {112, (3 << 18) | 0x31ec1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 112 (5.560GHz) */
228 {116, (3 << 18) | 0x33ec3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 116 (5.580GHz) */
229 {120, (3 << 18) | 0x301c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 120 (5.600GHz) */
230 {124, (3 << 18) | 0x301c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 124 (5.620GHz) */
231 {128, (3 << 18) | 0x321c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 128 (5.640GHz) */
232 {132, (3 << 18) | 0x311c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 132 (5.660GHz) */
233 {136, (3 << 18) | 0x331c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 136 (5.680GHz) */
234 {140, (3 << 18) | 0x309c0, (4 << 18) | 0x08000, (5 << 18) | 0x2A9C6}, /* 140 (5.700GHz) */
235
236 {149, (3 << 18) | 0x329c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A9C6}, /* 149 (5.745GHz) */
237 {153, (3 << 18) | 0x319c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A9C6}, /* 153 (5.765GHz) */
238 {157, (3 << 18) | 0x339c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A9C6}, /* 157 (5.785GHz) */
239 {161, (3 << 18) | 0x305c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A9C6}, /* 161 (5.805GHz) */
240
241 /* Japan */
242 { 184, (3 << 18) | 0x308c2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 184 (4.920GHz) */
243 { 188, (3 << 18) | 0x328c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 188 (4.940GHz) */
244 { 192, (3 << 18) | 0x318c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 192 (4.960GHz) */
245 { 196, (3 << 18) | 0x338c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 196 (4.980GHz) */
246 { 8, (3 << 18) | 0x324c1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 8 (5.040GHz) */
247 { 12, (3 << 18) | 0x314c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 12 (5.060GHz) */
248 { 16, (3 << 18) | 0x334c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 16 (5.080GHz) */
249 { 34, (3 << 18) | 0x31cc2, (4 << 18) | 0x0b333, (5 << 18) | 0x2A946}, /* 34 (5.170GHz) */
250 { 38, (3 << 18) | 0x33cc1, (4 << 18) | 0x09999, (5 << 18) | 0x2A946}, /* 38 (5.190GHz) */
251 { 42, (3 << 18) | 0x302c1, (4 << 18) | 0x0a666, (5 << 18) | 0x2A946}, /* 42 (5.210GHz) */
252 { 46, (3 << 18) | 0x322c3, (4 << 18) | 0x08ccc, (5 << 18) | 0x2A946}, /* 46 (5.230GHz) */
253 };
254
255 /*
256 * ====================================================================
257 * For MAXIM2825/6/7 Ver. 317 or less
258 *
259 * 0x00 0x00080
260 * 0x01 0x214c0
261 * 0x02 0x13802
262 *
263 * 2.4GHz Channels
264 * channe1 01 (2.412GHz); 0x03 0x30143 ;0x04 0x0accc
265 * channe1 02 (2.417GHz); 0x03 0x32140 ;0x04 0x09111
266 * channe1 03 (2.422GHz); 0x03 0x32142 ;0x04 0x0bbbb
267 * channe1 04 (2.427GHz); 0x03 0x32143 ;0x04 0x0accc
268 * channe1 05 (2.432GHz); 0x03 0x31140 ;0x04 0x09111
269 * channe1 06 (2.437GHz); 0x03 0x31142 ;0x04 0x0bbbb
270 * channe1 07 (2.442GHz); 0x03 0x31143 ;0x04 0x0accc
271 * channe1 08 (2.447GHz); 0x03 0x33140 ;0x04 0x09111
272 * channe1 09 (2.452GHz); 0x03 0x33142 ;0x04 0x0bbbb
273 * channe1 10 (2.457GHz); 0x03 0x33143 ;0x04 0x0accc
274 * channe1 11 (2.462GHz); 0x03 0x30940 ;0x04 0x09111
275 * channe1 12 (2.467GHz); 0x03 0x30942 ;0x04 0x0bbbb
276 * channe1 13 (2.472GHz); 0x03 0x30943 ;0x04 0x0accc
277 *
278 * 5.0Ghz Channels
279 * channel 36 (5.180GHz); 0x03 0x33cc0 ;0x04 0x0b333
280 * channel 40 (5.200GHz); 0x03 0x302c0 ;0x04 0x08000
281 * channel 44 (5.220GHz); 0x03 0x302c2 ;0x04 0x0b333
282 * channel 48 (5.240GHz); 0x03 0x322c1 ;0x04 0x09999
283 * channel 52 (5.260GHz); 0x03 0x312c1 ;0x04 0x0a666
284 * channel 56 (5.280GHz); 0x03 0x332c3 ;0x04 0x08ccc
285 * channel 60 (5.300GHz); 0x03 0x30ac0 ;0x04 0x08000
286 * channel 64 (5.320GHz); 0x03 0x30ac2 ;0x04 0x08333
287 *
288 * 2.4GHz band ; 0x05 0x28986;
289 * 5.0GHz band ; 0x05 0x2a986
290 * 0x06 0x18008
291 * 0x07 0x38400
292 * 0x08 0x05108
293 * 0x09 0x27ff8
294 * 0x0a 0x14000
295 * 0x0b 0x37f99
296 * 0x0c 0x0c000
297 * ====================================================================
298 */
299
300 /*
301 * ===================================================================
302 * AL2230 MP (Mass Production Version)
303 * RF Registers Setting for Airoha AL2230 silicon after June 1st, 2004
304 * 20-bit length and LSB first
305 *
306 * Ch01 (2412MHz) ;0x00 0x09EFC ;0x01 0x8CCCC;
307 * Ch02 (2417MHz) ;0x00 0x09EFC ;0x01 0x8CCCD;
308 * Ch03 (2422MHz) ;0x00 0x09E7C ;0x01 0x8CCCC;
309 * Ch04 (2427MHz) ;0x00 0x09E7C ;0x01 0x8CCCD;
310 * Ch05 (2432MHz) ;0x00 0x05EFC ;0x01 0x8CCCC;
311 * Ch06 (2437MHz) ;0x00 0x05EFC ;0x01 0x8CCCD;
312 * Ch07 (2442MHz) ;0x00 0x05E7C ;0x01 0x8CCCC;
313 * Ch08 (2447MHz) ;0x00 0x05E7C ;0x01 0x8CCCD;
314 * Ch09 (2452MHz) ;0x00 0x0DEFC ;0x01 0x8CCCC;
315 * Ch10 (2457MHz) ;0x00 0x0DEFC ;0x01 0x8CCCD;
316 * Ch11 (2462MHz) ;0x00 0x0DE7C ;0x01 0x8CCCC;
317 * Ch12 (2467MHz) ;0x00 0x0DE7C ;0x01 0x8CCCD;
318 * Ch13 (2472MHz) ;0x00 0x03EFC ;0x01 0x8CCCC;
319 * Ch14 (2484Mhz) ;0x00 0x03E7C ;0x01 0x86666;
320 *
321 * 0x02 0x401D8; RXDCOC BW 100Hz for RXHP low
322 * 0x02 0x481DC; RXDCOC BW 30Khz for RXHP low
323 *
324 * 0x03 0xCFFF0
325 * 0x04 0x23800
326 * 0x05 0xA3B72
327 * 0x06 0x6DA01
328 * 0x07 0xE1688
329 * 0x08 0x11600
330 * 0x09 0x99E02
331 * 0x0A 0x5DDB0
332 * 0x0B 0xD9900
333 * 0x0C 0x3FFBD
334 * 0x0D 0xB0000
335 * 0x0F 0xF00A0
336 *
337 * RF Calibration for Airoha AL2230
338 *
339 * 0x0f 0xf00a0 ; Initial Setting
340 * 0x0f 0xf00b0 ; Activate TX DCC
341 * 0x0f 0xf02a0 ; Activate Phase Calibration
342 * 0x0f 0xf00e0 ; Activate Filter RC Calibration
343 * 0x0f 0xf00a0 ; Restore Initial Setting
344 * ==================================================================
345 */
346 static u32 al2230_rf_data[] = {
347 (0x00 << 20) | 0x09EFC,
348 (0x01 << 20) | 0x8CCCC,
349 (0x02 << 20) | 0x40058,
350 (0x03 << 20) | 0xCFFF0,
351 (0x04 << 20) | 0x24100,
352 (0x05 << 20) | 0xA3B2F,
353 (0x06 << 20) | 0x6DA01,
354 (0x07 << 20) | 0xE3628,
355 (0x08 << 20) | 0x11600,
356 (0x09 << 20) | 0x9DC02,
357 (0x0A << 20) | 0x5ddb0,
358 (0x0B << 20) | 0xD9900,
359 (0x0C << 20) | 0x3FFBD,
360 (0x0D << 20) | 0xB0000,
361 (0x0F << 20) | 0xF01A0
362 };
363
364 static u32 al2230s_rf_data[] = {
365 (0x00 << 20) | 0x09EFC,
366 (0x01 << 20) | 0x8CCCC,
367 (0x02 << 20) | 0x40058,
368 (0x03 << 20) | 0xCFFF0,
369 (0x04 << 20) | 0x24100,
370 (0x05 << 20) | 0xA3B2F,
371 (0x06 << 20) | 0x6DA01,
372 (0x07 << 20) | 0xE3628,
373 (0x08 << 20) | 0x11600,
374 (0x09 << 20) | 0x9DC02,
375 (0x0A << 20) | 0x5DDB0,
376 (0x0B << 20) | 0xD9900,
377 (0x0C << 20) | 0x3FFBD,
378 (0x0D << 20) | 0xB0000,
379 (0x0F << 20) | 0xF01A0
380 };
381
382 static u32 al2230_channel_data_24[][2] = {
383 {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 01 */
384 {(0x00 << 20) | 0x09EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 02 */
385 {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 03 */
386 {(0x00 << 20) | 0x09E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 04 */
387 {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 05 */
388 {(0x00 << 20) | 0x05EFC, (0x01 << 20) | 0x8CCCD}, /* channe1 06 */
389 {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCC}, /* channe1 07 */
390 {(0x00 << 20) | 0x05E7C, (0x01 << 20) | 0x8CCCD}, /* channe1 08 */
391 {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCC}, /* channe1 09 */
392 {(0x00 << 20) | 0x0DEFC, (0x01 << 20) | 0x8CCCD}, /* channe1 10 */
393 {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCC}, /* channe1 11 */
394 {(0x00 << 20) | 0x0DE7C, (0x01 << 20) | 0x8CCCD}, /* channe1 12 */
395 {(0x00 << 20) | 0x03EFC, (0x01 << 20) | 0x8CCCC}, /* channe1 13 */
396 {(0x00 << 20) | 0x03E7C, (0x01 << 20) | 0x86666} /* channe1 14 */
397 };
398
399 /* Current setting. u32 airoha_power_data_24[] = {(0x09 << 20) | 0x90202, (0x09 << 20) | 0x96602, (0x09 << 20) | 0x97602}; */
400 #define AIROHA_TXVGA_LOW_INDEX 31 /* Index for 0x90202 */
401 #define AIROHA_TXVGA_MIDDLE_INDEX 12 /* Index for 0x96602 */
402 #define AIROHA_TXVGA_HIGH_INDEX 8 /* Index for 0x97602 1.0.24.0 1.0.28.0 */
403
404 static u32 al2230_txvga_data[][2] = {
405 /* value , index */
406 {0x090202, 0},
407 {0x094202, 2},
408 {0x092202, 4},
409 {0x096202, 6},
410 {0x091202, 8},
411 {0x095202, 10},
412 {0x093202, 12},
413 {0x097202, 14},
414 {0x090A02, 16},
415 {0x094A02, 18},
416 {0x092A02, 20},
417 {0x096A02, 22},
418 {0x091A02, 24},
419 {0x095A02, 26},
420 {0x093A02, 28},
421 {0x097A02, 30},
422 {0x090602, 32},
423 {0x094602, 34},
424 {0x092602, 36},
425 {0x096602, 38},
426 {0x091602, 40},
427 {0x095602, 42},
428 {0x093602, 44},
429 {0x097602, 46},
430 {0x090E02, 48},
431 {0x098E02, 49},
432 {0x094E02, 50},
433 {0x09CE02, 51},
434 {0x092E02, 52},
435 {0x09AE02, 53},
436 {0x096E02, 54},
437 {0x09EE02, 55},
438 {0x091E02, 56},
439 {0x099E02, 57},
440 {0x095E02, 58},
441 {0x09DE02, 59},
442 {0x093E02, 60},
443 {0x09BE02, 61},
444 {0x097E02, 62},
445 {0x09FE02, 63}
446 };
447
448 /*
449 * ==========================================
450 * For Airoha AL7230, 2.4Ghz band
451 * 24bit, MSB first
452 */
453
454 /* channel independent registers: */
455 static u32 al7230_rf_data_24[] = {
456 (0x00 << 24) | 0x003790,
457 (0x01 << 24) | 0x133331,
458 (0x02 << 24) | 0x841FF2,
459 (0x03 << 24) | 0x3FDFA3,
460 (0x04 << 24) | 0x7FD784,
461 (0x05 << 24) | 0x802B55,
462 (0x06 << 24) | 0x56AF36,
463 (0x07 << 24) | 0xCE0207,
464 (0x08 << 24) | 0x6EBC08,
465 (0x09 << 24) | 0x221BB9,
466 (0x0A << 24) | 0xE0000A,
467 (0x0B << 24) | 0x08071B,
468 (0x0C << 24) | 0x000A3C,
469 (0x0D << 24) | 0xFFFFFD,
470 (0x0E << 24) | 0x00000E,
471 (0x0F << 24) | 0x1ABA8F
472 };
473
474 static u32 al7230_channel_data_24[][2] = {
475 {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x133331}, /* channe1 01 */
476 {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x1B3331}, /* channe1 02 */
477 {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x033331}, /* channe1 03 */
478 {(0x00 << 24) | 0x003790, (0x01 << 24) | 0x0B3331}, /* channe1 04 */
479 {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x133331}, /* channe1 05 */
480 {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x1B3331}, /* channe1 06 */
481 {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x033331}, /* channe1 07 */
482 {(0x00 << 24) | 0x0037A0, (0x01 << 24) | 0x0B3331}, /* channe1 08 */
483 {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x133331}, /* channe1 09 */
484 {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x1B3331}, /* channe1 10 */
485 {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x033331}, /* channe1 11 */
486 {(0x00 << 24) | 0x0037B0, (0x01 << 24) | 0x0B3331}, /* channe1 12 */
487 {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x133331}, /* channe1 13 */
488 {(0x00 << 24) | 0x0037C0, (0x01 << 24) | 0x066661} /* channel 14 */
489 };
490
491 /* channel independent registers: */
492 static u32 al7230_rf_data_50[] = {
493 (0x00 << 24) | 0x0FF520,
494 (0x01 << 24) | 0x000001,
495 (0x02 << 24) | 0x451FE2,
496 (0x03 << 24) | 0x5FDFA3,
497 (0x04 << 24) | 0x6FD784,
498 (0x05 << 24) | 0x853F55,
499 (0x06 << 24) | 0x56AF36,
500 (0x07 << 24) | 0xCE0207,
501 (0x08 << 24) | 0x6EBC08,
502 (0x09 << 24) | 0x221BB9,
503 (0x0A << 24) | 0xE0600A,
504 (0x0B << 24) | 0x08044B,
505 (0x0C << 24) | 0x00143C,
506 (0x0D << 24) | 0xFFFFFD,
507 (0x0E << 24) | 0x00000E,
508 (0x0F << 24) | 0x12BACF /* 5Ghz default state */
509 };
510
511 static u32 al7230_channel_data_5[][4] = {
512 /* channel dependent registers: 0x00, 0x01 and 0x04 */
513 /* 11J =========== */
514 {184, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 184 */
515 {188, (0x00 << 24) | 0x0FF520, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 188 */
516 {192, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 192 */
517 {196, (0x00 << 24) | 0x0FF530, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 196 */
518 {8, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 008 */
519 {12, (0x00 << 24) | 0x0FF540, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 012 */
520 {16, (0x00 << 24) | 0x0FF550, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 016 */
521 {34, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 034 */
522 {38, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x100001, (0x04 << 24) | 0x77F784}, /* channel 038 */
523 {42, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x1AAAA1, (0x04 << 24) | 0x77F784}, /* channel 042 */
524 {46, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x055551, (0x04 << 24) | 0x77F784}, /* channel 046 */
525 /* 11 A/H ========= */
526 {36, (0x00 << 24) | 0x0FF560, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 036 */
527 {40, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 040 */
528 {44, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 044 */
529 {48, (0x00 << 24) | 0x0FF570, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 048 */
530 {52, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 052 */
531 {56, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 056 */
532 {60, (0x00 << 24) | 0x0FF580, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 060 */
533 {64, (0x00 << 24) | 0x0FF590, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 064 */
534 {100, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 100 */
535 {104, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 104 */
536 {108, (0x00 << 24) | 0x0FF5C0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 108 */
537 {112, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 112 */
538 {116, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 116 */
539 {120, (0x00 << 24) | 0x0FF5D0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 120 */
540 {124, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 124 */
541 {128, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 128 */
542 {132, (0x00 << 24) | 0x0FF5E0, (0x01 << 24) | 0x0AAAA1, (0x04 << 24) | 0x77F784}, /* channel 132 */
543 {136, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x155551, (0x04 << 24) | 0x77F784}, /* channel 136 */
544 {140, (0x00 << 24) | 0x0FF5F0, (0x01 << 24) | 0x000001, (0x04 << 24) | 0x67F784}, /* channel 140 */
545 {149, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 149 */
546 {153, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784}, /* channel 153 */
547 {157, (0x00 << 24) | 0x0FF600, (0x01 << 24) | 0x0D5551, (0x04 << 24) | 0x77F784}, /* channel 157 */
548 {161, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x180001, (0x04 << 24) | 0x77F784}, /* channel 161 */
549 {165, (0x00 << 24) | 0x0FF610, (0x01 << 24) | 0x02AAA1, (0x04 << 24) | 0x77F784} /* channel 165 */
550 };
551
552 /*
553 * RF Calibration <=== Register 0x0F
554 * 0x0F 0x1ABA8F; start from 2.4Ghz default state
555 * 0x0F 0x9ABA8F; TXDC compensation
556 * 0x0F 0x3ABA8F; RXFIL adjustment
557 * 0x0F 0x1ABA8F; restore 2.4Ghz default state
558 */
559
560 /* TXVGA Mapping Table <=== Register 0x0B */
561 static u32 al7230_txvga_data[][2] = {
562 {0x08040B, 0}, /* TXVGA = 0; */
563 {0x08041B, 1}, /* TXVGA = 1; */
564 {0x08042B, 2}, /* TXVGA = 2; */
565 {0x08043B, 3}, /* TXVGA = 3; */
566 {0x08044B, 4}, /* TXVGA = 4; */
567 {0x08045B, 5}, /* TXVGA = 5; */
568 {0x08046B, 6}, /* TXVGA = 6; */
569 {0x08047B, 7}, /* TXVGA = 7; */
570 {0x08048B, 8}, /* TXVGA = 8; */
571 {0x08049B, 9}, /* TXVGA = 9; */
572 {0x0804AB, 10}, /* TXVGA = 10; */
573 {0x0804BB, 11}, /* TXVGA = 11; */
574 {0x0804CB, 12}, /* TXVGA = 12; */
575 {0x0804DB, 13}, /* TXVGA = 13; */
576 {0x0804EB, 14}, /* TXVGA = 14; */
577 {0x0804FB, 15}, /* TXVGA = 15; */
578 {0x08050B, 16}, /* TXVGA = 16; */
579 {0x08051B, 17}, /* TXVGA = 17; */
580 {0x08052B, 18}, /* TXVGA = 18; */
581 {0x08053B, 19}, /* TXVGA = 19; */
582 {0x08054B, 20}, /* TXVGA = 20; */
583 {0x08055B, 21}, /* TXVGA = 21; */
584 {0x08056B, 22}, /* TXVGA = 22; */
585 {0x08057B, 23}, /* TXVGA = 23; */
586 {0x08058B, 24}, /* TXVGA = 24; */
587 {0x08059B, 25}, /* TXVGA = 25; */
588 {0x0805AB, 26}, /* TXVGA = 26; */
589 {0x0805BB, 27}, /* TXVGA = 27; */
590 {0x0805CB, 28}, /* TXVGA = 28; */
591 {0x0805DB, 29}, /* TXVGA = 29; */
592 {0x0805EB, 30}, /* TXVGA = 30; */
593 {0x0805FB, 31}, /* TXVGA = 31; */
594 {0x08060B, 32}, /* TXVGA = 32; */
595 {0x08061B, 33}, /* TXVGA = 33; */
596 {0x08062B, 34}, /* TXVGA = 34; */
597 {0x08063B, 35}, /* TXVGA = 35; */
598 {0x08064B, 36}, /* TXVGA = 36; */
599 {0x08065B, 37}, /* TXVGA = 37; */
600 {0x08066B, 38}, /* TXVGA = 38; */
601 {0x08067B, 39}, /* TXVGA = 39; */
602 {0x08068B, 40}, /* TXVGA = 40; */
603 {0x08069B, 41}, /* TXVGA = 41; */
604 {0x0806AB, 42}, /* TXVGA = 42; */
605 {0x0806BB, 43}, /* TXVGA = 43; */
606 {0x0806CB, 44}, /* TXVGA = 44; */
607 {0x0806DB, 45}, /* TXVGA = 45; */
608 {0x0806EB, 46}, /* TXVGA = 46; */
609 {0x0806FB, 47}, /* TXVGA = 47; */
610 {0x08070B, 48}, /* TXVGA = 48; */
611 {0x08071B, 49}, /* TXVGA = 49; */
612 {0x08072B, 50}, /* TXVGA = 50; */
613 {0x08073B, 51}, /* TXVGA = 51; */
614 {0x08074B, 52}, /* TXVGA = 52; */
615 {0x08075B, 53}, /* TXVGA = 53; */
616 {0x08076B, 54}, /* TXVGA = 54; */
617 {0x08077B, 55}, /* TXVGA = 55; */
618 {0x08078B, 56}, /* TXVGA = 56; */
619 {0x08079B, 57}, /* TXVGA = 57; */
620 {0x0807AB, 58}, /* TXVGA = 58; */
621 {0x0807BB, 59}, /* TXVGA = 59; */
622 {0x0807CB, 60}, /* TXVGA = 60; */
623 {0x0807DB, 61}, /* TXVGA = 61; */
624 {0x0807EB, 62}, /* TXVGA = 62; */
625 {0x0807FB, 63}, /* TXVGA = 63; */
626 };
627 /* ============================================= */
628
629 /*
630 * W89RF242 RFIC SPI programming initial data
631 * Winbond WLAN 11g RFIC BB-SPI register -- version FA5976A rev 1.3b
632 */
633 static u32 w89rf242_rf_data[] = {
634 (0x00 << 24) | 0xF86100, /* 3E184; MODA (0x00) -- Normal mode ; calibration off */
635 (0x01 << 24) | 0xEFFFC2, /* 3BFFF; MODB (0x01) -- turn off RSSI, and other circuits are turned on */
636 (0x02 << 24) | 0x102504, /* 04094; FSET (0x02) -- default 20MHz crystal ; Icmp=1.5mA */
637 (0x03 << 24) | 0x026286, /* 0098A; FCHN (0x03) -- default CH7, 2442MHz */
638 (0x04 << 24) | 0x000208, /* 02008; FCAL (0x04) -- XTAL Freq Trim=001000 (socket board#1); FA5976AYG_v1.3C */
639 (0x05 << 24) | 0x24C60A, /* 09316; GANA (0x05) -- TX VGA default (TXVGA=0x18(12)) & TXGPK=110 ; FA5976A_1.3D */
640 (0x06 << 24) | 0x3432CC, /* 0D0CB; GANB (0x06) -- RXDC(DC offset) on; LNA=11; RXVGA=001011(11) ; RXFLSW=11(010001); RXGPK=00; RXGCF=00; -50dBm input */
641 (0x07 << 24) | 0x0C68CE, /* 031A3; FILT (0x07) -- TX/RX filter with auto-tuning; TFLBW=011; RFLBW=100 */
642 (0x08 << 24) | 0x100010, /* 04000; TCAL (0x08) -- for LO */
643 (0x09 << 24) | 0x004012, /* 1B900; RCALA (0x09) -- FASTS=11; HPDE=01 (100nsec); SEHP=1 (select B0 pin=RXHP); RXHP=1 (Turn on RXHP function)(FA5976A_1.3C) */
644 (0x0A << 24) | 0x704014, /* 1C100; RCALB (0x0A) */
645 (0x0B << 24) | 0x18BDD6, /* 062F7; IQCAL (0x0B) -- Turn on LO phase tuner=0111 & RX-LO phase = 0111; FA5976A_1.3B */
646 (0x0C << 24) | 0x575558, /* 15D55 ; IBSA (0x0C) -- IFPre =11 ; TC5376A_v1.3A for corner */
647 (0x0D << 24) | 0x55545A, /* 15555 ; IBSB (0x0D) */
648 (0x0E << 24) | 0x5557DC, /* 1555F ; IBSC (0x0E) -- IRLNA & IRLNB (PTAT & Const current)=01/01; FA5976B_1.3F */
649 (0x10 << 24) | 0x000C20, /* 00030 ; TMODA (0x10) -- LNA_gain_step=0011 ; LNA=15/16dB */
650 (0x11 << 24) | 0x0C0022, /* 03000 ; TMODB (0x11) -- Turn ON RX-Q path Test Switch; To improve IQ path group delay (FA5976A_1.3C) */
651 (0x12 << 24) | 0x000024 /* TMODC (0x12) -- Turn OFF Temperature sensor */
652 };
653
654 static u32 w89rf242_channel_data_24[][2] = {
655 {(0x03 << 24) | 0x025B06, (0x04 << 24) | 0x080408}, /* channe1 01 */
656 {(0x03 << 24) | 0x025C46, (0x04 << 24) | 0x080408}, /* channe1 02 */
657 {(0x03 << 24) | 0x025D86, (0x04 << 24) | 0x080408}, /* channe1 03 */
658 {(0x03 << 24) | 0x025EC6, (0x04 << 24) | 0x080408}, /* channe1 04 */
659 {(0x03 << 24) | 0x026006, (0x04 << 24) | 0x080408}, /* channe1 05 */
660 {(0x03 << 24) | 0x026146, (0x04 << 24) | 0x080408}, /* channe1 06 */
661 {(0x03 << 24) | 0x026286, (0x04 << 24) | 0x080408}, /* channe1 07 */
662 {(0x03 << 24) | 0x0263C6, (0x04 << 24) | 0x080408}, /* channe1 08 */
663 {(0x03 << 24) | 0x026506, (0x04 << 24) | 0x080408}, /* channe1 09 */
664 {(0x03 << 24) | 0x026646, (0x04 << 24) | 0x080408}, /* channe1 10 */
665 {(0x03 << 24) | 0x026786, (0x04 << 24) | 0x080408}, /* channe1 11 */
666 {(0x03 << 24) | 0x0268C6, (0x04 << 24) | 0x080408}, /* channe1 12 */
667 {(0x03 << 24) | 0x026A06, (0x04 << 24) | 0x080408}, /* channe1 13 */
668 {(0x03 << 24) | 0x026D06, (0x04 << 24) | 0x080408} /* channe1 14 */
669 };
670
671 static u32 w89rf242_txvga_old_mapping[][2] = {
672 {0, 0} , /* New <-> Old */
673 {1, 1} ,
674 {2, 2} ,
675 {3, 3} ,
676 {4, 4} ,
677 {6, 5} ,
678 {8, 6},
679 {10, 7},
680 {12, 8},
681 {14, 9},
682 {16, 10},
683 {18, 11},
684 {20, 12},
685 {22, 13},
686 {24, 14},
687 {26, 15},
688 {28, 16},
689 {30, 17},
690 {32, 18},
691 {34, 19},
692 };
693
694 static u32 w89rf242_txvga_data[][5] = {
695 /* low gain mode */
696 {(0x05 << 24) | 0x24C00A, 0, 0x00292315, 0x0800FEFF, 0x52523131}, /* min gain */
697 {(0x05 << 24) | 0x24C80A, 1, 0x00292315, 0x0800FEFF, 0x52523131},
698 {(0x05 << 24) | 0x24C04A, 2, 0x00292315, 0x0800FEFF, 0x52523131}, /* (default) +14dBm (ANT) */
699 {(0x05 << 24) | 0x24C84A, 3, 0x00292315, 0x0800FEFF, 0x52523131},
700
701 /* TXVGA=0x10 */
702 {(0x05 << 24) | 0x24C40A, 4, 0x00292315, 0x0800FEFF, 0x60603838},
703 {(0x05 << 24) | 0x24C40A, 5, 0x00262114, 0x0700FEFF, 0x65653B3B},
704
705 /* TXVGA=0x11 */
706 { (0x05 << 24) | 0x24C44A, 6, 0x00241F13, 0x0700FFFF, 0x58583333},
707 { (0x05 << 24) | 0x24C44A, 7, 0x00292315, 0x0800FEFF, 0x5E5E3737},
708
709 /* TXVGA=0x12 */
710 {(0x05 << 24) | 0x24C48A, 8, 0x00262114, 0x0700FEFF, 0x53533030},
711 {(0x05 << 24) | 0x24C48A, 9, 0x00241F13, 0x0700FFFF, 0x59593434},
712
713 /* TXVGA=0x13 */
714 {(0x05 << 24) | 0x24C4CA, 10, 0x00292315, 0x0800FEFF, 0x52523030},
715 {(0x05 << 24) | 0x24C4CA, 11, 0x00262114, 0x0700FEFF, 0x56563232},
716
717 /* TXVGA=0x14 */
718 {(0x05 << 24) | 0x24C50A, 12, 0x00292315, 0x0800FEFF, 0x54543131},
719 {(0x05 << 24) | 0x24C50A, 13, 0x00262114, 0x0700FEFF, 0x58583434},
720
721 /* TXVGA=0x15 */
722 {(0x05 << 24) | 0x24C54A, 14, 0x00292315, 0x0800FEFF, 0x54543131},
723 {(0x05 << 24) | 0x24C54A, 15, 0x00262114, 0x0700FEFF, 0x59593434},
724
725 /* TXVGA=0x16 */
726 {(0x05 << 24) | 0x24C58A, 16, 0x00292315, 0x0800FEFF, 0x55553131},
727 {(0x05 << 24) | 0x24C58A, 17, 0x00292315, 0x0800FEFF, 0x5B5B3535},
728
729 /* TXVGA=0x17 */
730 {(0x05 << 24) | 0x24C5CA, 18, 0x00262114, 0x0700FEFF, 0x51512F2F},
731 {(0x05 << 24) | 0x24C5CA, 19, 0x00241F13, 0x0700FFFF, 0x55553131},
732
733 /* TXVGA=0x18 */
734 {(0x05 << 24) | 0x24C60A, 20, 0x00292315, 0x0800FEFF, 0x4F4F2E2E},
735 {(0x05 << 24) | 0x24C60A, 21, 0x00262114, 0x0700FEFF, 0x53533030},
736
737 /* TXVGA=0x19 */
738 {(0x05 << 24) | 0x24C64A, 22, 0x00292315, 0x0800FEFF, 0x4E4E2D2D},
739 {(0x05 << 24) | 0x24C64A, 23, 0x00262114, 0x0700FEFF, 0x53533030},
740
741 /* TXVGA=0x1A */
742 {(0x05 << 24) | 0x24C68A, 24, 0x00292315, 0x0800FEFF, 0x50502E2E},
743 {(0x05 << 24) | 0x24C68A, 25, 0x00262114, 0x0700FEFF, 0x55553131},
744
745 /* TXVGA=0x1B */
746 {(0x05 << 24) | 0x24C6CA, 26, 0x00262114, 0x0700FEFF, 0x53533030},
747 {(0x05 << 24) | 0x24C6CA, 27, 0x00292315, 0x0800FEFF, 0x5A5A3434},
748
749 /* TXVGA=0x1C */
750 {(0x05 << 24) | 0x24C70A, 28, 0x00292315, 0x0800FEFF, 0x55553131},
751 {(0x05 << 24) | 0x24C70A, 29, 0x00292315, 0x0800FEFF, 0x5D5D3636},
752
753 /* TXVGA=0x1D */
754 {(0x05 << 24) | 0x24C74A, 30, 0x00292315, 0x0800FEFF, 0x5F5F3737},
755 {(0x05 << 24) | 0x24C74A, 31, 0x00262114, 0x0700FEFF, 0x65653B3B},
756
757 /* TXVGA=0x1E */
758 {(0x05 << 24) | 0x24C78A, 32, 0x00292315, 0x0800FEFF, 0x66663B3B},
759 {(0x05 << 24) | 0x24C78A, 33, 0x00262114, 0x0700FEFF, 0x70704141},
760
761 /* TXVGA=0x1F */
762 {(0x05 << 24) | 0x24C7CA, 34, 0x00292315, 0x0800FEFF, 0x72724242}
763 };
764
765 /* ================================================================================================== */
766
767
768
769 /*
770 * =============================================================================================================
771 * Uxx_ReadEthernetAddress --
772 *
773 * Routine Description:
774 * Reads in the Ethernet address from the IC.
775 *
776 * Arguments:
777 * pHwData - The pHwData structure
778 *
779 * Return Value:
780 *
781 * The address is stored in EthernetIDAddr.
782 * =============================================================================================================
783 */
784 void Uxx_ReadEthernetAddress(struct hw_data *pHwData)
785 {
786 u32 ltmp;
787
788 /*
789 * Reading Ethernet address from EEPROM and set into hardware due to MAC address maybe change.
790 * Only unplug and plug again can make hardware read EEPROM again.
791 */
792 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08000000); /* Start EEPROM access + Read + address(0x0d) */
793 Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp);
794 *(u16 *)pHwData->PermanentMacAddress = cpu_to_le16((u16) ltmp);
795 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08010000); /* Start EEPROM access + Read + address(0x0d) */
796 Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp);
797 *(u16 *)(pHwData->PermanentMacAddress + 2) = cpu_to_le16((u16) ltmp);
798 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08020000); /* Start EEPROM access + Read + address(0x0d) */
799 Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp);
800 *(u16 *)(pHwData->PermanentMacAddress + 4) = cpu_to_le16((u16) ltmp);
801 *(u16 *)(pHwData->PermanentMacAddress + 6) = 0;
802 Wb35Reg_WriteSync(pHwData, 0x03e8, cpu_to_le32(*(u32 *)pHwData->PermanentMacAddress));
803 Wb35Reg_WriteSync(pHwData, 0x03ec, cpu_to_le32(*(u32 *)(pHwData->PermanentMacAddress + 4)));
804 }
805
806
807 /*
808 * ===============================================================================================================
809 * CardGetMulticastBit --
810 * Description:
811 * For a given multicast address, returns the byte and bit in the card multicast registers that it hashes to.
812 * Calls CardComputeCrc() to determine the CRC value.
813 * Arguments:
814 * Address - the address
815 * Byte - the byte that it hashes to
816 * Value - will have a 1 in the relevant bit
817 * Return Value:
818 * None.
819 * ==============================================================================================================
820 */
821 void CardGetMulticastBit(u8 Address[ETH_ALEN], u8 *Byte, u8 *Value)
822 {
823 u32 Crc;
824 u32 BitNumber;
825
826 /* First compute the CRC. */
827 Crc = CardComputeCrc(Address, ETH_ALEN);
828
829 /* The computed CRC is bit0~31 from left to right */
830 /* At first we should do right shift 25bits, and read 7bits by using '&', 2^7=128 */
831 BitNumber = (u32) ((Crc >> 26) & 0x3f);
832
833 *Byte = (u8) (BitNumber >> 3); /* 900514 original (BitNumber / 8) */
834 *Value = (u8) ((u8) 1 << (BitNumber % 8));
835 }
836
837 void Uxx_power_on_procedure(struct hw_data *pHwData)
838 {
839 u32 ltmp, loop;
840
841 if (pHwData->phy_type <= RF_MAXIM_V1)
842 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xffffff38);
843 else {
844 Wb35Reg_WriteSync(pHwData, 0x03f4, 0xFF5807FF);
845 Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */
846 msleep(10);
847 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xb8); /* REG_ON RF_RSTN on, and */
848 msleep(10);
849 ltmp = 0x4968;
850 if ((pHwData->phy_type == RF_WB_242) ||
851 (RF_WB_242_1 == pHwData->phy_type))
852 ltmp = 0x4468;
853
854 Wb35Reg_WriteSync(pHwData, 0x03d0, ltmp);
855 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */
856
857 msleep(20);
858 Wb35Reg_ReadSync(pHwData, 0x03d0, &ltmp);
859 loop = 500; /* Wait for 5 second */
860 while (!(ltmp & 0x20) && loop--) {
861 msleep(10);
862 if (!Wb35Reg_ReadSync(pHwData, 0x03d0, &ltmp))
863 break;
864 }
865
866 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */
867 }
868
869 Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */
870 msleep(10);
871
872 /* Set burst write delay */
873 Wb35Reg_WriteSync(pHwData, 0x03f8, 0x7ff);
874 }
875
876 static void Set_ChanIndep_RfData_al7230_24(struct hw_data *pHwData, u32 *pltmp,
877 char number)
878 {
879 u8 i;
880 for (i = 0; i < number; i++) {
881 pHwData->phy_para[i] = al7230_rf_data_24[i];
882 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_24[i] & 0xffffff);
883 }
884 }
885
886 static void Set_ChanIndep_RfData_al7230_50(struct hw_data *pHwData, u32 *pltmp,
887 char number)
888 {
889 u8 i;
890 for (i = 0; i < number; i++) {
891 pHwData->phy_para[i] = al7230_rf_data_50[i];
892 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_rf_data_50[i] & 0xffffff);
893 }
894 }
895
896
897 /*
898 * =============================================================================================================
899 * RFSynthesizer_initial --
900 * =============================================================================================================
901 */
902 void RFSynthesizer_initial(struct hw_data *pHwData)
903 {
904 u32 altmp[32];
905 u32 *pltmp = altmp;
906 u32 ltmp;
907 u8 number = 0x00; /* The number of register vale */
908 u8 i;
909
910 /*
911 * bit[31] SPI Enable.
912 * 1=perform synthesizer program operation. This bit will
913 * cleared automatically after the operation is completed.
914 * bit[30] SPI R/W Control
915 * 0=write, 1=read
916 * bit[29:24] SPI Data Format Length
917 * bit[17:4 ] RF Data bits.
918 * bit[3 :0 ] RF address.
919 */
920 switch (pHwData->phy_type) {
921 case RF_MAXIM_2825:
922 case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
923 number = ARRAY_SIZE(max2825_rf_data);
924 for (i = 0; i < number; i++) {
925 pHwData->phy_para[i] = max2825_rf_data[i]; /* Backup Rf parameter */
926 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_rf_data[i], 18);
927 }
928 break;
929 case RF_MAXIM_2827:
930 number = ARRAY_SIZE(max2827_rf_data);
931 for (i = 0; i < number; i++) {
932 pHwData->phy_para[i] = max2827_rf_data[i];
933 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_rf_data[i], 18);
934 }
935 break;
936 case RF_MAXIM_2828:
937 number = ARRAY_SIZE(max2828_rf_data);
938 for (i = 0; i < number; i++) {
939 pHwData->phy_para[i] = max2828_rf_data[i];
940 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_rf_data[i], 18);
941 }
942 break;
943 case RF_MAXIM_2829:
944 number = ARRAY_SIZE(max2829_rf_data);
945 for (i = 0; i < number; i++) {
946 pHwData->phy_para[i] = max2829_rf_data[i];
947 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_rf_data[i], 18);
948 }
949 break;
950 case RF_AIROHA_2230:
951 number = ARRAY_SIZE(al2230_rf_data);
952 for (i = 0; i < number; i++) {
953 pHwData->phy_para[i] = al2230_rf_data[i];
954 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data[i], 20);
955 }
956 break;
957 case RF_AIROHA_2230S:
958 number = ARRAY_SIZE(al2230s_rf_data);
959 for (i = 0; i < number; i++) {
960 pHwData->phy_para[i] = al2230s_rf_data[i];
961 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230s_rf_data[i], 20);
962 }
963 break;
964 case RF_AIROHA_7230:
965 /* Start to fill RF parameters, PLL_ON should be pulled low. */
966 Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000);
967 pr_debug("* PLL_ON low\n");
968 number = ARRAY_SIZE(al7230_rf_data_24);
969 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
970 break;
971 case RF_WB_242:
972 case RF_WB_242_1:
973 number = ARRAY_SIZE(w89rf242_rf_data);
974 for (i = 0; i < number; i++) {
975 ltmp = w89rf242_rf_data[i];
976 if (i == 4) { /* Update the VCO trim from EEPROM */
977 ltmp &= ~0xff0; /* Mask bit4 ~bit11 */
978 ltmp |= pHwData->VCO_trim << 4;
979 }
980
981 pHwData->phy_para[i] = ltmp;
982 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(ltmp, 24);
983 }
984 break;
985 }
986
987 pHwData->phy_number = number;
988
989 /* The 16 is the maximum capability of hardware. Here use 12 */
990 if (number > 12) {
991 for (i = 0; i < 12; i++) /* For Al2230 */
992 Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]);
993
994 pltmp += 12;
995 number -= 12;
996 }
997
998 /* Write to register. number must less and equal than 16 */
999 for (i = 0; i < number; i++)
1000 Wb35Reg_WriteSync(pHwData, 0x864, pltmp[i]);
1001
1002 /* Calibration only 1 time */
1003 if (pHwData->CalOneTime)
1004 return;
1005 pHwData->CalOneTime = 1;
1006
1007 switch (pHwData->phy_type) {
1008 case RF_AIROHA_2230:
1009 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x07 << 20) | 0xE168E, 20);
1010 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1011 msleep(10);
1012 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_rf_data[7], 20);
1013 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1014 msleep(10);
1015 case RF_AIROHA_2230S:
1016 Wb35Reg_WriteSync(pHwData, 0x03d4, 0x80); /* regulator on only */
1017 msleep(10);
1018 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xa0); /* PLL_PD REF_PD set to 0 */
1019 msleep(10);
1020 Wb35Reg_WriteSync(pHwData, 0x03d4, 0xe0); /* MLK_EN */
1021 Wb35Reg_WriteSync(pHwData, 0x03b0, 1); /* Reset hardware first */
1022 msleep(10);
1023 /* ========================================================= */
1024
1025 /* The follow code doesn't use the burst-write mode */
1026 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F<<20) | 0xF01A0, 20);
1027 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1028
1029 ltmp = pHwData->reg.BB5C & 0xfffff000;
1030 Wb35Reg_WriteSync(pHwData, 0x105c, ltmp);
1031 pHwData->reg.BB50 |= 0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START) */
1032 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1033 msleep(5);
1034
1035 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01B0, 20);
1036 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1037 msleep(5);
1038
1039 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01E0, 20);
1040 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1041 msleep(5);
1042
1043 ltmp = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse((0x0F << 20) | 0xF01A0, 20);
1044 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1045
1046 Wb35Reg_WriteSync(pHwData, 0x105c, pHwData->reg.BB5C);
1047 pHwData->reg.BB50 &= ~0x13; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
1048 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1049 break;
1050 case RF_AIROHA_7230:
1051 /* RF parameters have filled completely, PLL_ON should be pulled high */
1052 Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080);
1053 pr_debug("* PLL_ON high\n");
1054
1055 /* 2.4GHz */
1056 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1057 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1058 msleep(5);
1059 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1060 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1061 msleep(5);
1062 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x1ABA8F;
1063 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1064 msleep(5);
1065
1066 /* 5GHz */
1067 Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000000);
1068 pr_debug("* PLL_ON low\n");
1069
1070 number = ARRAY_SIZE(al7230_rf_data_50);
1071 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
1072 /* Write to register. number must less and equal than 16 */
1073 for (i = 0; i < number; i++)
1074 Wb35Reg_WriteSync(pHwData, 0x0864, pltmp[i]);
1075 msleep(5);
1076
1077 Wb35Reg_WriteSync(pHwData, 0x03dc, 0x00000080);
1078 pr_debug("* PLL_ON high\n");
1079
1080 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x9ABA8F;
1081 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1082 msleep(5);
1083 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x3ABA8F;
1084 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1085 msleep(5);
1086 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x12BACF;
1087 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1088 msleep(5);
1089 break;
1090 case RF_WB_242:
1091 case RF_WB_242_1:
1092 /* for FA5976A */
1093 ltmp = pHwData->reg.BB5C & 0xfffff000;
1094 Wb35Reg_WriteSync(pHwData, 0x105c, ltmp);
1095 Wb35Reg_WriteSync(pHwData, 0x1058, 0);
1096 pHwData->reg.BB50 |= 0x3; /* (MASK_IQCAL_MODE|MASK_CALIB_START); */
1097 Wb35Reg_WriteSync(pHwData, 0x1050, pHwData->reg.BB50);
1098
1099 /* ----- Calibration (1). VCO frequency calibration */
1100 /* Calibration (1a.0). Synthesizer reset */
1101 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00101E, 24);
1102 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1103 msleep(5);
1104 /* Calibration (1a). VCO frequency calibration mode ; waiting 2msec VCO calibration time */
1105 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFE69c0, 24);
1106 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1107 msleep(2);
1108
1109 /* ----- Calibration (2). TX baseband Gm-C filter auto-tuning */
1110 /* Calibration (2a). turn off ENCAL signal */
1111 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24);
1112 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1113 /* Calibration (2b.0). TX filter auto-tuning BW: TFLBW=101 (TC5376A default) */
1114 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24);
1115 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1116 /* Calibration (2b). send TX reset signal */
1117 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00201E, 24);
1118 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1119 /* Calibration (2c). turn-on TX Gm-C filter auto-tuning */
1120 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFCEBC0, 24);
1121 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1122 udelay(150); /* Sleep 150 us */
1123 /* turn off ENCAL signal */
1124 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF8EBC0, 24);
1125 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1126
1127 /* ----- Calibration (3). RX baseband Gm-C filter auto-tuning */
1128 /* Calibration (3a). turn off ENCAL signal */
1129 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1130 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1131 /* Calibration (3b.0). RX filter auto-tuning BW: RFLBW=100 (TC5376A+corner default;) */
1132 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x07<<24) | 0x0C68CE, 24);
1133 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1134 /* Calibration (3b). send RX reset signal */
1135 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x0F<<24) | 0x00401E, 24);
1136 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1137 /* Calibration (3c). turn-on RX Gm-C filter auto-tuning */
1138 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFEEDC0, 24);
1139 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1140 udelay(150); /* Sleep 150 us */
1141 /* Calibration (3e). turn off ENCAL signal */
1142 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1143 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1144
1145 /* ----- Calibration (4). TX LO leakage calibration */
1146 /* Calibration (4a). TX LO leakage calibration */
1147 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFD6BC0, 24);
1148 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1149 udelay(150); /* Sleep 150 us */
1150
1151 /* ----- Calibration (5). RX DC offset calibration */
1152 /* Calibration (5a). turn off ENCAL signal and set to RX SW DC calibration mode */
1153 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1154 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1155 /* Calibration (5b). turn off AGC servo-loop & RSSI */
1156 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEBFFC2, 24);
1157 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1158
1159 /* for LNA=11 -------- */
1160 /* Calibration (5c-h). RX DC offset current bias ON; & LNA=11; RXVGA=111111 */
1161 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x343FCC, 24);
1162 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1163 /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1164 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1165 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1166 msleep(2);
1167 /* Calibration (5f). turn off ENCAL signal */
1168 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1169 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1170
1171 /* for LNA=10 -------- */
1172 /* Calibration (5c-m). RX DC offset current bias ON; & LNA=10; RXVGA=111111 */
1173 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x342FCC, 24);
1174 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1175 /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1176 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1177 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1178 msleep(2);
1179 /* Calibration (5f). turn off ENCAL signal */
1180 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1181 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1182
1183 /* for LNA=01 -------- */
1184 /* Calibration (5c-m). RX DC offset current bias ON; & LNA=01; RXVGA=111111 */
1185 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x341FCC, 24);
1186 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1187 /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1188 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1189 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1190 msleep(2);
1191 /* Calibration (5f). turn off ENCAL signal */
1192 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1193 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1194
1195 /* for LNA=00 -------- */
1196 /* Calibration (5c-l). RX DC offset current bias ON; & LNA=00; RXVGA=111111 */
1197 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x06<<24) | 0x340FCC, 24);
1198 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1199 /* Calibration (5d). turn on RX DC offset cal function; and waiting 2 msec cal time */
1200 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFF6DC0, 24);
1201 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1202 msleep(2);
1203 /* Calibration (5f). turn off ENCAL signal */
1204 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xFAEDC0, 24);
1205 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1206 /* Calibration (5g). turn on AGC servo-loop */
1207 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x01<<24) | 0xEFFFC2, 24);
1208 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1209
1210 /* ----- Calibration (7). Switch RF chip to normal mode */
1211 /* 0x00 0xF86100 ; 3E184 ; Switch RF chip to normal mode */
1212 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse((0x00<<24) | 0xF86100, 24);
1213 Wb35Reg_WriteSync(pHwData, 0x0864, ltmp);
1214 msleep(5);
1215 break;
1216 }
1217 }
1218
1219 static void BBProcessor_AL7230_2400(struct hw_data *pHwData)
1220 {
1221 struct wb35_reg *reg = &pHwData->reg;
1222 u32 pltmp[12];
1223
1224 pltmp[0] = 0x16A8337A; /* 0x1000 AGC_Ctrl1 */
1225 pltmp[1] = 0x9AFF9AA6; /* 0x1004 AGC_Ctrl2 */
1226 pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1227 pltmp[3] = 0xFFF72031; /* 0x100c AGC_Ctrl4 */
1228 reg->BB0C = 0xFFF72031;
1229 pltmp[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */
1230 pltmp[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */
1231 pltmp[6] = 0xF2211111; /* 0x1018 AGC_Ctrl7 */
1232 pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1233 pltmp[8] = 0x06443440; /* 0x1020 AGC_Ctrl9 */
1234 pltmp[9] = 0xA8002A79; /* 0x1024 AGC_Ctrl10 */
1235 pltmp[10] = 0x40000528;
1236 pltmp[11] = 0x232D7F30; /* 0x102c A_ACQ_Ctrl */
1237 reg->BB2C = 0x232D7F30;
1238 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1239
1240 pltmp[0] = 0x00002c54; /* 0x1030 B_ACQ_Ctrl */
1241 reg->BB30 = 0x00002c54;
1242 pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1243 pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1244 pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1245 reg->BB3C = 0x00000000;
1246 pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1247 pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1248 pltmp[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */
1249 pltmp[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */
1250 pltmp[8] = 0x2B106208; /* 0x1050 MODE_Ctrl */
1251 reg->BB50 = 0x2B106208;
1252 pltmp[9] = 0; /* 0x1054 */
1253 reg->BB54 = 0x00000000;
1254 pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */
1255 reg->BB58 = 0x52524242;
1256 pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1257 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1258 }
1259
1260 static void BBProcessor_AL7230_5000(struct hw_data *pHwData)
1261 {
1262 struct wb35_reg *reg = &pHwData->reg;
1263 u32 pltmp[12];
1264
1265 pltmp[0] = 0x16AA6678; /* 0x1000 AGC_Ctrl1 */
1266 pltmp[1] = 0x9AFFA0B2; /* 0x1004 AGC_Ctrl2 */
1267 pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1268 pltmp[3] = 0xEFFF233E; /* 0x100c AGC_Ctrl4 */
1269 reg->BB0C = 0xEFFF233E;
1270 pltmp[4] = 0x0FacDCC5; /* 0x1010 AGC_Ctrl5 */
1271 pltmp[5] = 0x00CAA333; /* 0x1014 AGC_Ctrl6 */
1272 pltmp[6] = 0xF2432111; /* 0x1018 AGC_Ctrl7 */
1273 pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1274 pltmp[8] = 0x05C43440; /* 0x1020 AGC_Ctrl9 */
1275 pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1276 pltmp[10] = 0x40000528;
1277 pltmp[11] = 0x232FDF30;/* 0x102c A_ACQ_Ctrl */
1278 reg->BB2C = 0x232FDF30;
1279 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1280
1281 pltmp[0] = 0x80002C7C; /* 0x1030 B_ACQ_Ctrl */
1282 pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1283 pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1284 pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1285 reg->BB3C = 0x00000000;
1286 pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1287 pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1288 pltmp[6] = 0x00332C1B; /* 0x1048 11b TX RC filter */
1289 pltmp[7] = 0x0A00FEFF; /* 0x104c 11b TX RC filter */
1290 pltmp[8] = 0x2B107208; /* 0x1050 MODE_Ctrl */
1291 reg->BB50 = 0x2B107208;
1292 pltmp[9] = 0; /* 0x1054 */
1293 reg->BB54 = 0x00000000;
1294 pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */
1295 reg->BB58 = 0x52524242;
1296 pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1297 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1298 }
1299
1300 /*
1301 * ===========================================================================
1302 * BBProcessorPowerupInit --
1303 *
1304 * Description:
1305 * Initialize the Baseband processor.
1306 *
1307 * Arguments:
1308 * pHwData - Handle of the USB Device.
1309 *
1310 * Return values:
1311 * None.
1312 *============================================================================
1313 */
1314 void BBProcessor_initial(struct hw_data *pHwData)
1315 {
1316 struct wb35_reg *reg = &pHwData->reg;
1317 u32 i, pltmp[12];
1318
1319 switch (pHwData->phy_type) {
1320 case RF_MAXIM_V1: /* Initializng the Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
1321 pltmp[0] = 0x16F47E77; /* 0x1000 AGC_Ctrl1 */
1322 pltmp[1] = 0x9AFFAEA4; /* 0x1004 AGC_Ctrl2 */
1323 pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1324 pltmp[3] = 0xEFFF1A34; /* 0x100c AGC_Ctrl4 */
1325 reg->BB0C = 0xEFFF1A34;
1326 pltmp[4] = 0x0FABE0B7; /* 0x1010 AGC_Ctrl5 */
1327 pltmp[5] = 0x00CAA332; /* 0x1014 AGC_Ctrl6 */
1328 pltmp[6] = 0xF6632111; /* 0x1018 AGC_Ctrl7 */
1329 pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1330 pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */
1331 pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1332 pltmp[10] = (pHwData->phy_type == 3) ? 0x40000a28 : 0x40000228; /* 0x1028 MAXIM_331(b31=0) + WBRF_V1(b11=1) : MAXIM_331(b31=0) + WBRF_V2(b11=0) */
1333 pltmp[11] = 0x232FDF30; /* 0x102c A_ACQ_Ctrl */
1334 reg->BB2C = 0x232FDF30; /* Modify for 33's 1.0.95.xxx version, antenna 1 */
1335 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1336
1337 pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1338 reg->BB30 = 0x00002C54;
1339 pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1340 pltmp[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */
1341 pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1342 reg->BB3C = 0x00000000;
1343 pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1344 pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1345 pltmp[6] = 0x00453B24; /* 0x1048 11b TX RC filter */
1346 pltmp[7] = 0x0E00FEFF; /* 0x104c 11b TX RC filter */
1347 pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1348 reg->BB50 = 0x27106208;
1349 pltmp[9] = 0; /* 0x1054 */
1350 reg->BB54 = 0x00000000;
1351 pltmp[10] = 0x64646464; /* 0x1058 IQ_Alpha */
1352 reg->BB58 = 0x64646464;
1353 pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1354 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1355
1356 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1357 break;
1358
1359 case RF_MAXIM_2825:
1360 case RF_MAXIM_2827:
1361 case RF_MAXIM_2828:
1362 pltmp[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */
1363 pltmp[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */
1364 pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1365 pltmp[3] = 0xefff1a34; /* 0x100c AGC_Ctrl4 */
1366 reg->BB0C = 0xefff1a34;
1367 pltmp[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */
1368 pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1369 pltmp[6] = 0xf6632111; /* 0x1018 AGC_Ctrl7 */
1370 pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1371 pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */
1372 pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1373 pltmp[10] = 0x40000528;
1374 pltmp[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */
1375 reg->BB2C = 0x232fdf30; /* antenna 1 */
1376 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1377
1378 pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1379 reg->BB30 = 0x00002C54;
1380 pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1381 pltmp[2] = 0x5B6C8769; /* 0x1038 B_TXRX_Ctrl */
1382 pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1383 reg->BB3C = 0x00000000;
1384 pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1385 pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1386 pltmp[6] = 0x00453B24; /* 0x1048 11b TX RC filter */
1387 pltmp[7] = 0x0D00FDFF; /* 0x104c 11b TX RC filter */
1388 pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1389 reg->BB50 = 0x27106208;
1390 pltmp[9] = 0; /* 0x1054 */
1391 reg->BB54 = 0x00000000;
1392 pltmp[10] = 0x64646464; /* 0x1058 IQ_Alpha */
1393 reg->BB58 = 0x64646464;
1394 pltmp[11] = 0xAA28C000; /* 0x105c DC_Cancel */
1395 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1396
1397 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1398 break;
1399
1400 case RF_MAXIM_2829:
1401 pltmp[0] = 0x16b47e77; /* 0x1000 AGC_Ctrl1 */
1402 pltmp[1] = 0x9affaea4; /* 0x1004 AGC_Ctrl2 */
1403 pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1404 pltmp[3] = 0xf4ff1632; /* 0x100c AGC_Ctrl4 */
1405 reg->BB0C = 0xf4ff1632;
1406 pltmp[4] = 0x0fabe0b7; /* 0x1010 AGC_Ctrl5 */
1407 pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1408 pltmp[6] = 0xf8632112; /* 0x1018 AGC_Ctrl7 */
1409 pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1410 pltmp[8] = 0x04CC3640; /* 0x1020 AGC_Ctrl9 */
1411 pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1412 pltmp[10] = 0x40000528;
1413 pltmp[11] = 0x232fdf30; /* 0x102c A_ACQ_Ctrl */
1414 reg->BB2C = 0x232fdf30; /* antenna 1 */
1415 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1416
1417 pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1418 reg->BB30 = 0x00002C54;
1419 pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1420 pltmp[2] = 0x5b2c8769; /* 0x1038 B_TXRX_Ctrl */
1421 pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1422 reg->BB3C = 0x00000000;
1423 pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1424 pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1425 pltmp[6] = 0x002c2617; /* 0x1048 11b TX RC filter */
1426 pltmp[7] = 0x0800feff; /* 0x104c 11b TX RC filter */
1427 pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1428 reg->BB50 = 0x27106208;
1429 pltmp[9] = 0; /* 0x1054 */
1430 reg->BB54 = 0x00000000;
1431 pltmp[10] = 0x64644a4a; /* 0x1058 IQ_Alpha */
1432 reg->BB58 = 0x64646464;
1433 pltmp[11] = 0xAA28C000; /* 0x105c DC_Cancel */
1434 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1435 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1436 break;
1437 case RF_AIROHA_2230:
1438 pltmp[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */
1439 pltmp[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */
1440 pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1441 pltmp[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */
1442 reg->BB0C = 0xFFFd203c;
1443 pltmp[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */
1444 pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1445 pltmp[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */
1446 pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1447 pltmp[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */
1448 pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1449 pltmp[10] = 0X40000528;
1450 pltmp[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */
1451 reg->BB2C = 0x232dfF30; /* antenna 1 */
1452 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1453
1454 pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1455 reg->BB30 = 0x00002C54;
1456 pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1457 pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1458 pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1459 reg->BB3C = 0x00000000;
1460 pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1461 pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1462 pltmp[6] = BB48_DEFAULT_AL2230_11G; /* 0x1048 11b TX RC filter */
1463 reg->BB48 = BB48_DEFAULT_AL2230_11G; /* 20051221 ch14 */
1464 pltmp[7] = BB4C_DEFAULT_AL2230_11G; /* 0x104c 11b TX RC filter */
1465 reg->BB4C = BB4C_DEFAULT_AL2230_11G;
1466 pltmp[8] = 0x27106200; /* 0x1050 MODE_Ctrl */
1467 reg->BB50 = 0x27106200;
1468 pltmp[9] = 0; /* 0x1054 */
1469 reg->BB54 = 0x00000000;
1470 pltmp[10] = 0x52524242; /* 0x1058 IQ_Alpha */
1471 reg->BB58 = 0x52524242;
1472 pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1473 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1474
1475 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1476 break;
1477 case RF_AIROHA_2230S:
1478 pltmp[0] = 0X16764A77; /* 0x1000 AGC_Ctrl1 */
1479 pltmp[1] = 0x9affafb2; /* 0x1004 AGC_Ctrl2 */
1480 pltmp[2] = 0x55d00a04; /* 0x1008 AGC_Ctrl3 */
1481 pltmp[3] = 0xFFFd203c; /* 0x100c AGC_Ctrl4 */
1482 reg->BB0C = 0xFFFd203c;
1483 pltmp[4] = 0X0FBFDCc5; /* 0x1010 AGC_Ctrl5 */
1484 pltmp[5] = 0x00caa332; /* 0x1014 AGC_Ctrl6 */
1485 pltmp[6] = 0XF6632111; /* 0x1018 AGC_Ctrl7 */
1486 pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1487 pltmp[8] = 0x04C43640; /* 0x1020 AGC_Ctrl9 */
1488 pltmp[9] = 0x00002A79; /* 0x1024 AGC_Ctrl10 */
1489 pltmp[10] = 0X40000528;
1490 pltmp[11] = 0x232dfF30; /* 0x102c A_ACQ_Ctrl */
1491 reg->BB2C = 0x232dfF30; /* antenna 1 */
1492 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1493
1494 pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1495 reg->BB30 = 0x00002C54;
1496 pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1497 pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1498 pltmp[3] = 0x00000000; /* 0x103c 11a TX LS filter */
1499 reg->BB3C = 0x00000000;
1500 pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1501 pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1502 pltmp[6] = BB48_DEFAULT_AL2230_11G; /* 0x1048 11b TX RC filter */
1503 reg->BB48 = BB48_DEFAULT_AL2230_11G; /* ch14 */
1504 pltmp[7] = BB4C_DEFAULT_AL2230_11G; /* 0x104c 11b TX RC filter */
1505 reg->BB4C = BB4C_DEFAULT_AL2230_11G;
1506 pltmp[8] = 0x27106200; /* 0x1050 MODE_Ctrl */
1507 reg->BB50 = 0x27106200;
1508 pltmp[9] = 0; /* 0x1054 */
1509 reg->BB54 = 0x00000000;
1510 pltmp[10] = 0x52523232; /* 0x1058 IQ_Alpha */
1511 reg->BB58 = 0x52523232;
1512 pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1513 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1514
1515 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1516 break;
1517 case RF_AIROHA_7230:
1518 BBProcessor_AL7230_2400(pHwData);
1519
1520 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1521 break;
1522 case RF_WB_242:
1523 case RF_WB_242_1:
1524 pltmp[0] = 0x16A8525D; /* 0x1000 AGC_Ctrl1 */
1525 pltmp[1] = 0x9AFF9ABA; /* 0x1004 AGC_Ctrl2 */
1526 pltmp[2] = 0x55D00A04; /* 0x1008 AGC_Ctrl3 */
1527 pltmp[3] = 0xEEE91C32; /* 0x100c AGC_Ctrl4 */
1528 reg->BB0C = 0xEEE91C32;
1529 pltmp[4] = 0x0FACDCC5; /* 0x1010 AGC_Ctrl5 */
1530 pltmp[5] = 0x000AA344; /* 0x1014 AGC_Ctrl6 */
1531 pltmp[6] = 0x22222221; /* 0x1018 AGC_Ctrl7 */
1532 pltmp[7] = 0x0FA3F0ED; /* 0x101c AGC_Ctrl8 */
1533 pltmp[8] = 0x04CC3440; /* 0x1020 AGC_Ctrl9 */
1534 pltmp[9] = 0xA9002A79; /* 0x1024 AGC_Ctrl10 */
1535 pltmp[10] = 0x40000528; /* 0x1028 */
1536 pltmp[11] = 0x23457F30; /* 0x102c A_ACQ_Ctrl */
1537 reg->BB2C = 0x23457F30;
1538 Wb35Reg_BurstWrite(pHwData, 0x1000, pltmp, 12, AUTO_INCREMENT);
1539
1540 pltmp[0] = 0x00002C54; /* 0x1030 B_ACQ_Ctrl */
1541 reg->BB30 = 0x00002C54;
1542 pltmp[1] = 0x00C0D6C5; /* 0x1034 A_TXRX_Ctrl */
1543 pltmp[2] = 0x5B2C8769; /* 0x1038 B_TXRX_Ctrl */
1544 pltmp[3] = pHwData->BB3c_cal; /* 0x103c 11a TX LS filter */
1545 reg->BB3C = pHwData->BB3c_cal;
1546 pltmp[4] = 0x00003F29; /* 0x1040 11a TX LS filter */
1547 pltmp[5] = 0x0EFEFBFE; /* 0x1044 11a TX LS filter */
1548 pltmp[6] = BB48_DEFAULT_WB242_11G; /* 0x1048 11b TX RC filter */
1549 reg->BB48 = BB48_DEFAULT_WB242_11G;
1550 pltmp[7] = BB4C_DEFAULT_WB242_11G; /* 0x104c 11b TX RC filter */
1551 reg->BB4C = BB4C_DEFAULT_WB242_11G;
1552 pltmp[8] = 0x27106208; /* 0x1050 MODE_Ctrl */
1553 reg->BB50 = 0x27106208;
1554 pltmp[9] = pHwData->BB54_cal; /* 0x1054 */
1555 reg->BB54 = pHwData->BB54_cal;
1556 pltmp[10] = 0x52523131; /* 0x1058 IQ_Alpha */
1557 reg->BB58 = 0x52523131;
1558 pltmp[11] = 0xAA0AC000; /* 0x105c DC_Cancel */
1559 Wb35Reg_BurstWrite(pHwData, 0x1030, pltmp, 12, AUTO_INCREMENT);
1560
1561 Wb35Reg_Write(pHwData, 0x1070, 0x00000045);
1562 break;
1563 }
1564
1565 /* Fill the LNA table */
1566 reg->LNAValue[0] = (u8) (reg->BB0C & 0xff);
1567 reg->LNAValue[1] = 0;
1568 reg->LNAValue[2] = (u8) ((reg->BB0C & 0xff00) >> 8);
1569 reg->LNAValue[3] = 0;
1570
1571 /* Fill SQ3 table */
1572 for (i = 0; i < MAX_SQ3_FILTER_SIZE; i++)
1573 reg->SQ3_filter[i] = 0x2f; /* half of Bit 0 ~ 6 */
1574 }
1575
1576 static inline void set_tx_power_per_channel_max2829(struct hw_data *pHwData,
1577 struct chan_info Channel)
1578 {
1579 RFSynthesizer_SetPowerIndex(pHwData, 100);
1580 }
1581
1582 static void set_tx_power_per_channel_al2230(struct hw_data *pHwData,
1583 struct chan_info Channel)
1584 {
1585 u8 index = 100;
1586 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1587 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1588
1589 RFSynthesizer_SetPowerIndex(pHwData, index);
1590 }
1591
1592 static void set_tx_power_per_channel_al7230(struct hw_data *pHwData,
1593 struct chan_info Channel)
1594 {
1595 u8 i, index = 100;
1596
1597 switch (Channel.band) {
1598 case BAND_TYPE_DSSS:
1599 case BAND_TYPE_OFDM_24:
1600 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1601 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1602 break;
1603 case BAND_TYPE_OFDM_5:
1604 for (i = 0; i < 35; i++) {
1605 if (Channel.ChanNo == pHwData->TxVgaFor50[i].ChanNo) {
1606 if (pHwData->TxVgaFor50[i].TxVgaValue != 0xff)
1607 index = pHwData->TxVgaFor50[i].TxVgaValue;
1608 break;
1609 }
1610 }
1611 break;
1612 }
1613 RFSynthesizer_SetPowerIndex(pHwData, index);
1614 }
1615
1616 static void set_tx_power_per_channel_wb242(struct hw_data *pHwData,
1617 struct chan_info Channel)
1618 {
1619 u8 index = 100;
1620
1621 switch (Channel.band) {
1622 case BAND_TYPE_DSSS:
1623 case BAND_TYPE_OFDM_24:
1624 if (pHwData->TxVgaFor24[Channel.ChanNo - 1] != 0xff)
1625 index = pHwData->TxVgaFor24[Channel.ChanNo - 1];
1626 break;
1627 case BAND_TYPE_OFDM_5:
1628 break;
1629 }
1630 RFSynthesizer_SetPowerIndex(pHwData, index);
1631 }
1632
1633 /*
1634 * ==========================================================================
1635 * RFSynthesizer_SwitchingChannel --
1636 *
1637 * Description:
1638 * Swithch the RF channel.
1639 *
1640 * Arguments:
1641 * pHwData - Handle of the USB Device.
1642 * Channel - The channel no.
1643 *
1644 * Return values:
1645 * None.
1646 * ===========================================================================
1647 */
1648 void RFSynthesizer_SwitchingChannel(struct hw_data *pHwData, struct chan_info Channel)
1649 {
1650 struct wb35_reg *reg = &pHwData->reg;
1651 u32 pltmp[16]; /* The 16 is the maximum capability of hardware */
1652 u32 count, ltmp;
1653 u8 i, j, number;
1654 u8 ChnlTmp;
1655
1656 switch (pHwData->phy_type) {
1657 case RF_MAXIM_2825:
1658 case RF_MAXIM_V1: /* 11g Winbond 2nd BB(with Phy board (v1) + Maxim 331) */
1659
1660 if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */
1661 for (i = 0; i < 3; i++)
1662 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_channel_data_24[Channel.ChanNo-1][i], 18);
1663 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1664 }
1665 RFSynthesizer_SetPowerIndex(pHwData, 100);
1666 break;
1667 case RF_MAXIM_2827:
1668 if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */
1669 for (i = 0; i < 3; i++)
1670 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_24[Channel.ChanNo-1][i], 18);
1671 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1672 } else if (Channel.band == BAND_TYPE_OFDM_5) { /* channel 36 ~ 64 */
1673 ChnlTmp = (Channel.ChanNo - 36) / 4;
1674 for (i = 0; i < 3; i++)
1675 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_channel_data_50[ChnlTmp][i], 18);
1676 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1677 }
1678 RFSynthesizer_SetPowerIndex(pHwData, 100);
1679 break;
1680 case RF_MAXIM_2828:
1681 if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 13 */
1682 for (i = 0; i < 3; i++)
1683 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_24[Channel.ChanNo-1][i], 18);
1684 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1685 } else if (Channel.band == BAND_TYPE_OFDM_5) { /* channel 36 ~ 64 */
1686 ChnlTmp = (Channel.ChanNo - 36) / 4;
1687 for (i = 0; i < 3; i++)
1688 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_channel_data_50[ChnlTmp][i], 18);
1689 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1690 }
1691 RFSynthesizer_SetPowerIndex(pHwData, 100);
1692 break;
1693 case RF_MAXIM_2829:
1694 if (Channel.band <= BAND_TYPE_OFDM_24) {
1695 for (i = 0; i < 3; i++)
1696 pltmp[i] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_24[Channel.ChanNo-1][i], 18);
1697 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1698 } else if (Channel.band == BAND_TYPE_OFDM_5) {
1699 count = ARRAY_SIZE(max2829_channel_data_50);
1700
1701 for (i = 0; i < count; i++) {
1702 if (max2829_channel_data_50[i][0] == Channel.ChanNo) {
1703 for (j = 0; j < 3; j++)
1704 pltmp[j] = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2829_channel_data_50[i][j+1], 18);
1705 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1706
1707 if ((max2829_channel_data_50[i][3] & 0x3FFFF) == 0x2A946) {
1708 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A906, 18);
1709 Wb35Reg_Write(pHwData, 0x0864, ltmp);
1710 } else { /* 0x2A9C6 */
1711 ltmp = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse((5 << 18) | 0x2A986, 18);
1712 Wb35Reg_Write(pHwData, 0x0864, ltmp);
1713 }
1714 }
1715 }
1716 }
1717 set_tx_power_per_channel_max2829(pHwData, Channel);
1718 break;
1719 case RF_AIROHA_2230:
1720 case RF_AIROHA_2230S:
1721 if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */
1722 for (i = 0; i < 2; i++)
1723 pltmp[i] = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_channel_data_24[Channel.ChanNo-1][i], 20);
1724 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT);
1725 }
1726 set_tx_power_per_channel_al2230(pHwData, Channel);
1727 break;
1728 case RF_AIROHA_7230:
1729 /* Channel independent registers */
1730 if (Channel.band != pHwData->band) {
1731 if (Channel.band <= BAND_TYPE_OFDM_24) {
1732 /* Update BB register */
1733 BBProcessor_AL7230_2400(pHwData);
1734
1735 number = ARRAY_SIZE(al7230_rf_data_24);
1736 Set_ChanIndep_RfData_al7230_24(pHwData, pltmp, number);
1737 } else {
1738 /* Update BB register */
1739 BBProcessor_AL7230_5000(pHwData);
1740
1741 number = ARRAY_SIZE(al7230_rf_data_50);
1742 Set_ChanIndep_RfData_al7230_50(pHwData, pltmp, number);
1743 }
1744
1745 /* Write to register. number must less and equal than 16 */
1746 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, number, NO_INCREMENT);
1747 pr_debug("Band changed\n");
1748 }
1749
1750 if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */
1751 for (i = 0; i < 2; i++)
1752 pltmp[i] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_24[Channel.ChanNo-1][i]&0xffffff);
1753 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 2, NO_INCREMENT);
1754 } else if (Channel.band == BAND_TYPE_OFDM_5) {
1755 /* Update Reg12 */
1756 if ((Channel.ChanNo > 64) && (Channel.ChanNo <= 165)) {
1757 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00143c;
1758 Wb35Reg_Write(pHwData, 0x0864, ltmp);
1759 } else { /* reg12 = 0x00147c at Channel 4920 ~ 5320 */
1760 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | 0x00147c;
1761 Wb35Reg_Write(pHwData, 0x0864, ltmp);
1762 }
1763
1764 count = ARRAY_SIZE(al7230_channel_data_5);
1765
1766 for (i = 0; i < count; i++) {
1767 if (al7230_channel_data_5[i][0] == Channel.ChanNo) {
1768 for (j = 0; j < 3; j++)
1769 pltmp[j] = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_channel_data_5[i][j+1] & 0xffffff);
1770 Wb35Reg_BurstWrite(pHwData, 0x0864, pltmp, 3, NO_INCREMENT);
1771 }
1772 }
1773 }
1774 set_tx_power_per_channel_al7230(pHwData, Channel);
1775 break;
1776 case RF_WB_242:
1777 case RF_WB_242_1:
1778
1779 if (Channel.band <= BAND_TYPE_OFDM_24) { /* channel 1 ~ 14 */
1780 ltmp = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_channel_data_24[Channel.ChanNo-1][0], 24);
1781 Wb35Reg_Write(pHwData, 0x864, ltmp);
1782 }
1783 set_tx_power_per_channel_wb242(pHwData, Channel);
1784 break;
1785 }
1786
1787 if (Channel.band <= BAND_TYPE_OFDM_24) {
1788 /* BB: select 2.4 GHz, bit[12-11]=00 */
1789 reg->BB50 &= ~(BIT(11) | BIT(12));
1790 Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */
1791 /* MAC: select 2.4 GHz, bit[5]=0 */
1792 reg->M78_ERPInformation &= ~BIT(5);
1793 Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation);
1794 /* enable 11b Baseband */
1795 reg->BB30 &= ~BIT(31);
1796 Wb35Reg_Write(pHwData, 0x1030, reg->BB30);
1797 } else if (Channel.band == BAND_TYPE_OFDM_5) {
1798 /* BB: select 5 GHz */
1799 reg->BB50 &= ~(BIT(11) | BIT(12));
1800 if (Channel.ChanNo <= 64)
1801 reg->BB50 |= BIT(12); /* 10-5.25GHz */
1802 else if ((Channel.ChanNo >= 100) && (Channel.ChanNo <= 124))
1803 reg->BB50 |= BIT(11); /* 01-5.48GHz */
1804 else if ((Channel.ChanNo >= 128) && (Channel.ChanNo <= 161))
1805 reg->BB50 |= (BIT(12) | BIT(11)); /* 11-5.775GHz */
1806 else /* Chan 184 ~ 196 will use bit[12-11] = 10 in version sh-src-1.2.25 */
1807 reg->BB50 |= BIT(12);
1808 Wb35Reg_Write(pHwData, 0x1050, reg->BB50); /* MODE_Ctrl */
1809
1810 /* (1) M78 should alway use 2.4G setting when using RF_AIROHA_7230 */
1811 /* (2) BB30 has been updated previously. */
1812 if (pHwData->phy_type != RF_AIROHA_7230) {
1813 /* MAC: select 5 GHz, bit[5]=1 */
1814 reg->M78_ERPInformation |= BIT(5);
1815 Wb35Reg_Write(pHwData, 0x0878, reg->M78_ERPInformation);
1816
1817 /* disable 11b Baseband */
1818 reg->BB30 |= BIT(31);
1819 Wb35Reg_Write(pHwData, 0x1030, reg->BB30);
1820 }
1821 }
1822 }
1823
1824 /*
1825 * Set the tx power directly from DUT GUI, not from the EEPROM.
1826 * Return the current setting
1827 */
1828 u8 RFSynthesizer_SetPowerIndex(struct hw_data *pHwData, u8 PowerIndex)
1829 {
1830 u32 Band = pHwData->band;
1831 u8 index = 0;
1832
1833 if (pHwData->power_index == PowerIndex)
1834 return PowerIndex;
1835
1836 if (RF_MAXIM_2825 == pHwData->phy_type) {
1837 /* Channel 1 - 13 */
1838 index = RFSynthesizer_SetMaxim2825Power(pHwData, PowerIndex);
1839 } else if (RF_MAXIM_2827 == pHwData->phy_type) {
1840 if (Band <= BAND_TYPE_OFDM_24) /* Channel 1 - 13 */
1841 index = RFSynthesizer_SetMaxim2827_24Power(pHwData, PowerIndex);
1842 else /* Channel 36 - 64 */
1843 index = RFSynthesizer_SetMaxim2827_50Power(pHwData, PowerIndex);
1844 } else if (RF_MAXIM_2828 == pHwData->phy_type) {
1845 if (Band <= BAND_TYPE_OFDM_24) /* Channel 1 - 13 */
1846 index = RFSynthesizer_SetMaxim2828_24Power(pHwData, PowerIndex);
1847 else /* Channel 36 - 64 */
1848 index = RFSynthesizer_SetMaxim2828_50Power(pHwData, PowerIndex);
1849 } else if (RF_AIROHA_2230 == pHwData->phy_type) {
1850 /* Power index: 0 ~ 63 --- Channel 1 - 14 */
1851 index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex);
1852 index = (u8) al2230_txvga_data[index][1];
1853 } else if (RF_AIROHA_2230S == pHwData->phy_type) {
1854 /* Power index: 0 ~ 63 --- Channel 1 - 14 */
1855 index = RFSynthesizer_SetAiroha2230Power(pHwData, PowerIndex);
1856 index = (u8) al2230_txvga_data[index][1];
1857 } else if (RF_AIROHA_7230 == pHwData->phy_type) {
1858 /* Power index: 0 ~ 63 */
1859 index = RFSynthesizer_SetAiroha7230Power(pHwData, PowerIndex);
1860 index = (u8)al7230_txvga_data[index][1];
1861 } else if ((RF_WB_242 == pHwData->phy_type) ||
1862 (RF_WB_242_1 == pHwData->phy_type)) {
1863 /* Power index: 0 ~ 19 for original. New range is 0 ~ 33 */
1864 index = RFSynthesizer_SetWinbond242Power(pHwData, PowerIndex);
1865 index = (u8)w89rf242_txvga_data[index][1];
1866 }
1867
1868 pHwData->power_index = index; /* Backup current */
1869 return index;
1870 }
1871
1872 /* -- Sub function */
1873 u8 RFSynthesizer_SetMaxim2828_24Power(struct hw_data *pHwData, u8 index)
1874 {
1875 u32 PowerData;
1876 if (index > 1)
1877 index = 1;
1878 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_24[index], 18);
1879 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1880 return index;
1881 }
1882
1883 u8 RFSynthesizer_SetMaxim2828_50Power(struct hw_data *pHwData, u8 index)
1884 {
1885 u32 PowerData;
1886 if (index > 1)
1887 index = 1;
1888 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2828_power_data_50[index], 18);
1889 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1890 return index;
1891 }
1892
1893 u8 RFSynthesizer_SetMaxim2827_24Power(struct hw_data *pHwData, u8 index)
1894 {
1895 u32 PowerData;
1896 if (index > 1)
1897 index = 1;
1898 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_24[index], 18);
1899 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1900 return index;
1901 }
1902
1903 u8 RFSynthesizer_SetMaxim2827_50Power(struct hw_data *pHwData, u8 index)
1904 {
1905 u32 PowerData;
1906 if (index > 1)
1907 index = 1;
1908 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2827_power_data_50[index], 18);
1909 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1910 return index;
1911 }
1912
1913 u8 RFSynthesizer_SetMaxim2825Power(struct hw_data *pHwData, u8 index)
1914 {
1915 u32 PowerData;
1916 if (index > 1)
1917 index = 1;
1918 PowerData = (1 << 31) | (0 << 30) | (18 << 24) | BitReverse(max2825_power_data_24[index], 18);
1919 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1920 return index;
1921 }
1922
1923 u8 RFSynthesizer_SetAiroha2230Power(struct hw_data *pHwData, u8 index)
1924 {
1925 u32 PowerData;
1926 u8 i, count;
1927
1928 count = ARRAY_SIZE(al2230_txvga_data);
1929 for (i = 0; i < count; i++) {
1930 if (al2230_txvga_data[i][1] >= index)
1931 break;
1932 }
1933 if (i == count)
1934 i--;
1935
1936 PowerData = (1 << 31) | (0 << 30) | (20 << 24) | BitReverse(al2230_txvga_data[i][0], 20);
1937 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1938 return i;
1939 }
1940
1941 u8 RFSynthesizer_SetAiroha7230Power(struct hw_data *pHwData, u8 index)
1942 {
1943 u32 PowerData;
1944 u8 i, count;
1945
1946 count = ARRAY_SIZE(al7230_txvga_data);
1947 for (i = 0; i < count; i++) {
1948 if (al7230_txvga_data[i][1] >= index)
1949 break;
1950 }
1951 if (i == count)
1952 i--;
1953 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | (al7230_txvga_data[i][0] & 0xffffff);
1954 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1955 return i;
1956 }
1957
1958 u8 RFSynthesizer_SetWinbond242Power(struct hw_data *pHwData, u8 index)
1959 {
1960 u32 PowerData;
1961 u8 i, count;
1962
1963 count = ARRAY_SIZE(w89rf242_txvga_data);
1964 for (i = 0; i < count; i++) {
1965 if (w89rf242_txvga_data[i][1] >= index)
1966 break;
1967 }
1968 if (i == count)
1969 i--;
1970
1971 /* Set TxVga into RF */
1972 PowerData = (1 << 31) | (0 << 30) | (24 << 24) | BitReverse(w89rf242_txvga_data[i][0], 24);
1973 Wb35Reg_Write(pHwData, 0x0864, PowerData);
1974
1975 /* Update BB48 BB4C BB58 for high precision txvga */
1976 Wb35Reg_Write(pHwData, 0x1048, w89rf242_txvga_data[i][2]);
1977 Wb35Reg_Write(pHwData, 0x104c, w89rf242_txvga_data[i][3]);
1978 Wb35Reg_Write(pHwData, 0x1058, w89rf242_txvga_data[i][4]);
1979
1980 return i;
1981 }
1982
1983 /*
1984 * ===========================================================================
1985 * Dxx_initial --
1986 * Mxx_initial --
1987 *
1988 * Routine Description:
1989 * Initial the hardware setting and module variable
1990 * ===========================================================================
1991 */
1992 void Dxx_initial(struct hw_data *pHwData)
1993 {
1994 struct wb35_reg *reg = &pHwData->reg;
1995
1996 /*
1997 * Old IC: Single mode only.
1998 * New IC: operation decide by Software set bit[4]. 1:multiple 0: single
1999 */
2000 reg->D00_DmaControl = 0xc0000004; /* Txon, Rxon, multiple Rx for new 4k DMA */
2001 /* Txon, Rxon, single Rx for old 8k ASIC */
2002 if (!HAL_USB_MODE_BURST(pHwData))
2003 reg->D00_DmaControl = 0xc0000000; /* Txon, Rxon, single Rx for new 4k DMA */
2004
2005 Wb35Reg_WriteSync(pHwData, 0x0400, reg->D00_DmaControl);
2006 }
2007
2008 void Mxx_initial(struct hw_data *pHwData)
2009 {
2010 struct wb35_reg *reg = &pHwData->reg;
2011 u32 tmp;
2012 u32 pltmp[11];
2013 u16 i;
2014
2015
2016 /*
2017 * ======================================================
2018 * Initial Mxx register
2019 * ======================================================
2020 */
2021
2022 /* M00 bit set */
2023 reg->M00_MacControl = 0x80000000; /* Solve beacon sequence number stop by hardware */
2024
2025 /* M24 disable enter power save, BB RxOn and enable NAV attack */
2026 reg->M24_MacControl = 0x08040042;
2027 pltmp[0] = reg->M24_MacControl;
2028
2029 pltmp[1] = 0; /* Skip M28, because no initialize value is required. */
2030
2031 /* M2C CWmin and CWmax setting */
2032 pHwData->cwmin = DEFAULT_CWMIN;
2033 pHwData->cwmax = DEFAULT_CWMAX;
2034 reg->M2C_MacControl = DEFAULT_CWMIN << 10;
2035 reg->M2C_MacControl |= DEFAULT_CWMAX;
2036 pltmp[2] = reg->M2C_MacControl;
2037
2038 /* M30 BSSID */
2039 pltmp[3] = *(u32 *)pHwData->bssid;
2040
2041 /* M34 */
2042 pHwData->AID = DEFAULT_AID;
2043 tmp = *(u16 *) (pHwData->bssid + 4);
2044 tmp |= DEFAULT_AID << 16;
2045 pltmp[4] = tmp;
2046
2047 /* M38 */
2048 reg->M38_MacControl = (DEFAULT_RATE_RETRY_LIMIT << 8) | (DEFAULT_LONG_RETRY_LIMIT << 4) | DEFAULT_SHORT_RETRY_LIMIT;
2049 pltmp[5] = reg->M38_MacControl;
2050
2051 /* M3C */
2052 tmp = (DEFAULT_PIFST << 26) | (DEFAULT_EIFST << 16) | (DEFAULT_DIFST << 8) | (DEFAULT_SIFST << 4) | DEFAULT_OSIFST;
2053 reg->M3C_MacControl = tmp;
2054 pltmp[6] = tmp;
2055
2056 /* M40 */
2057 pHwData->slot_time_select = DEFAULT_SLOT_TIME;
2058 tmp = (DEFAULT_ATIMWD << 16) | DEFAULT_SLOT_TIME;
2059 reg->M40_MacControl = tmp;
2060 pltmp[7] = tmp;
2061
2062 /* M44 */
2063 tmp = DEFAULT_MAX_TX_MSDU_LIFE_TIME << 10; /* *1024 */
2064 reg->M44_MacControl = tmp;
2065 pltmp[8] = tmp;
2066
2067 /* M48 */
2068 pHwData->BeaconPeriod = DEFAULT_BEACON_INTERVAL;
2069 pHwData->ProbeDelay = DEFAULT_PROBE_DELAY_TIME;
2070 tmp = (DEFAULT_BEACON_INTERVAL << 16) | DEFAULT_PROBE_DELAY_TIME;
2071 reg->M48_MacControl = tmp;
2072 pltmp[9] = tmp;
2073
2074 /* M4C */
2075 reg->M4C_MacStatus = (DEFAULT_PROTOCOL_VERSION << 30) | (DEFAULT_MAC_POWER_STATE << 28) | (DEFAULT_DTIM_ALERT_TIME << 24);
2076 pltmp[10] = reg->M4C_MacStatus;
2077
2078 for (i = 0; i < 11; i++)
2079 Wb35Reg_WriteSync(pHwData, 0x0824 + i * 4, pltmp[i]);
2080
2081 /* M60 */
2082 Wb35Reg_WriteSync(pHwData, 0x0860, 0x12481248);
2083 reg->M60_MacControl = 0x12481248;
2084
2085 /* M68 */
2086 Wb35Reg_WriteSync(pHwData, 0x0868, 0x00050900);
2087 reg->M68_MacControl = 0x00050900;
2088
2089 /* M98 */
2090 Wb35Reg_WriteSync(pHwData, 0x0898, 0xffff8888);
2091 reg->M98_MacControl = 0xffff8888;
2092 }
2093
2094
2095 void Uxx_power_off_procedure(struct hw_data *pHwData)
2096 {
2097 /* SW, PMU reset and turn off clock */
2098 Wb35Reg_WriteSync(pHwData, 0x03b0, 3);
2099 Wb35Reg_WriteSync(pHwData, 0x03f0, 0xf9);
2100 }
2101
2102 /*Decide the TxVga of every channel */
2103 void GetTxVgaFromEEPROM(struct hw_data *pHwData)
2104 {
2105 u32 i, j, ltmp;
2106 u16 Value[MAX_TXVGA_EEPROM];
2107 u8 *pctmp;
2108 u8 ctmp = 0;
2109
2110 /* Get the entire TxVga setting in EEPROM */
2111 for (i = 0; i < MAX_TXVGA_EEPROM; i++) {
2112 Wb35Reg_WriteSync(pHwData, 0x03b4, 0x08100000 + 0x00010000 * i);
2113 Wb35Reg_ReadSync(pHwData, 0x03b4, &ltmp);
2114 Value[i] = (u16) (ltmp & 0xffff); /* Get 16 bit available */
2115 Value[i] = cpu_to_le16(Value[i]); /* [7:0]2412 [7:0]2417 .... */
2116 }
2117
2118 /* Adjust the filed which fills with reserved value. */
2119 pctmp = (u8 *) Value;
2120 for (i = 0; i < (MAX_TXVGA_EEPROM * 2); i++) {
2121 if (pctmp[i] != 0xff)
2122 ctmp = pctmp[i];
2123 else
2124 pctmp[i] = ctmp;
2125 }
2126
2127 /* Adjust WB_242 to WB_242_1 TxVga scale */
2128 if (pHwData->phy_type == RF_WB_242) {
2129 for (i = 0; i < 4; i++) { /* Only 2412 2437 2462 2484 case must be modified */
2130 for (j = 0; j < ARRAY_SIZE(w89rf242_txvga_old_mapping); j++) {
2131 if (pctmp[i] < (u8) w89rf242_txvga_old_mapping[j][1]) {
2132 pctmp[i] = (u8) w89rf242_txvga_old_mapping[j][0];
2133 break;
2134 }
2135 }
2136
2137 if (j == ARRAY_SIZE(w89rf242_txvga_old_mapping))
2138 pctmp[i] = (u8)w89rf242_txvga_old_mapping[j-1][0];
2139 }
2140 }
2141
2142 memcpy(pHwData->TxVgaSettingInEEPROM, pctmp, MAX_TXVGA_EEPROM * 2); /* MAX_TXVGA_EEPROM is u16 count */
2143 EEPROMTxVgaAdjust(pHwData);
2144 }
2145
2146 /*
2147 * This function will affect the TxVga parameter in HAL. If hal_set_current_channel
2148 * or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect.
2149 * TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35
2150 * This function will use default TxVgaSettingInEEPROM data to calculate new TxVga.
2151 */
2152 void EEPROMTxVgaAdjust(struct hw_data *pHwData)
2153 {
2154 u8 *pTxVga = pHwData->TxVgaSettingInEEPROM;
2155 s16 i, stmp;
2156
2157 /* -- 2.4G -- */
2158 /* channel 1 ~ 5 */
2159 stmp = pTxVga[1] - pTxVga[0];
2160 for (i = 0; i < 5; i++)
2161 pHwData->TxVgaFor24[i] = pTxVga[0] + stmp * i / 4;
2162 /* channel 6 ~ 10 */
2163 stmp = pTxVga[2] - pTxVga[1];
2164 for (i = 5; i < 10; i++)
2165 pHwData->TxVgaFor24[i] = pTxVga[1] + stmp * (i - 5) / 4;
2166 /* channel 11 ~ 13 */
2167 stmp = pTxVga[3] - pTxVga[2];
2168 for (i = 10; i < 13; i++)
2169 pHwData->TxVgaFor24[i] = pTxVga[2] + stmp * (i - 10) / 2;
2170 /* channel 14 */
2171 pHwData->TxVgaFor24[13] = pTxVga[3];
2172
2173 /* -- 5G -- */
2174 if (pHwData->phy_type == RF_AIROHA_7230) {
2175 /* channel 184 */
2176 pHwData->TxVgaFor50[0].ChanNo = 184;
2177 pHwData->TxVgaFor50[0].TxVgaValue = pTxVga[4];
2178 /* channel 196 */
2179 pHwData->TxVgaFor50[3].ChanNo = 196;
2180 pHwData->TxVgaFor50[3].TxVgaValue = pTxVga[5];
2181 /* interpolate */
2182 pHwData->TxVgaFor50[1].ChanNo = 188;
2183 pHwData->TxVgaFor50[2].ChanNo = 192;
2184 stmp = pTxVga[5] - pTxVga[4];
2185 pHwData->TxVgaFor50[2].TxVgaValue = pTxVga[5] - stmp / 3;
2186 pHwData->TxVgaFor50[1].TxVgaValue = pTxVga[5] - stmp * 2 / 3;
2187
2188 /* channel 16 */
2189 pHwData->TxVgaFor50[6].ChanNo = 16;
2190 pHwData->TxVgaFor50[6].TxVgaValue = pTxVga[6];
2191 pHwData->TxVgaFor50[4].ChanNo = 8;
2192 pHwData->TxVgaFor50[4].TxVgaValue = pTxVga[6];
2193 pHwData->TxVgaFor50[5].ChanNo = 12;
2194 pHwData->TxVgaFor50[5].TxVgaValue = pTxVga[6];
2195
2196 /* channel 36 */
2197 pHwData->TxVgaFor50[8].ChanNo = 36;
2198 pHwData->TxVgaFor50[8].TxVgaValue = pTxVga[7];
2199 pHwData->TxVgaFor50[7].ChanNo = 34;
2200 pHwData->TxVgaFor50[7].TxVgaValue = pTxVga[7];
2201 pHwData->TxVgaFor50[9].ChanNo = 38;
2202 pHwData->TxVgaFor50[9].TxVgaValue = pTxVga[7];
2203
2204 /* channel 40 */
2205 pHwData->TxVgaFor50[10].ChanNo = 40;
2206 pHwData->TxVgaFor50[10].TxVgaValue = pTxVga[8];
2207 /* channel 48 */
2208 pHwData->TxVgaFor50[14].ChanNo = 48;
2209 pHwData->TxVgaFor50[14].TxVgaValue = pTxVga[9];
2210 /* interpolate */
2211 pHwData->TxVgaFor50[11].ChanNo = 42;
2212 pHwData->TxVgaFor50[12].ChanNo = 44;
2213 pHwData->TxVgaFor50[13].ChanNo = 46;
2214 stmp = pTxVga[9] - pTxVga[8];
2215 pHwData->TxVgaFor50[13].TxVgaValue = pTxVga[9] - stmp / 4;
2216 pHwData->TxVgaFor50[12].TxVgaValue = pTxVga[9] - stmp * 2 / 4;
2217 pHwData->TxVgaFor50[11].TxVgaValue = pTxVga[9] - stmp * 3 / 4;
2218
2219 /* channel 52 */
2220 pHwData->TxVgaFor50[15].ChanNo = 52;
2221 pHwData->TxVgaFor50[15].TxVgaValue = pTxVga[10];
2222 /* channel 64 */
2223 pHwData->TxVgaFor50[18].ChanNo = 64;
2224 pHwData->TxVgaFor50[18].TxVgaValue = pTxVga[11];
2225 /* interpolate */
2226 pHwData->TxVgaFor50[16].ChanNo = 56;
2227 pHwData->TxVgaFor50[17].ChanNo = 60;
2228 stmp = pTxVga[11] - pTxVga[10];
2229 pHwData->TxVgaFor50[17].TxVgaValue = pTxVga[11] - stmp / 3;
2230 pHwData->TxVgaFor50[16].TxVgaValue = pTxVga[11] - stmp * 2 / 3;
2231
2232 /* channel 100 */
2233 pHwData->TxVgaFor50[19].ChanNo = 100;
2234 pHwData->TxVgaFor50[19].TxVgaValue = pTxVga[12];
2235 /* channel 112 */
2236 pHwData->TxVgaFor50[22].ChanNo = 112;
2237 pHwData->TxVgaFor50[22].TxVgaValue = pTxVga[13];
2238 /* interpolate */
2239 pHwData->TxVgaFor50[20].ChanNo = 104;
2240 pHwData->TxVgaFor50[21].ChanNo = 108;
2241 stmp = pTxVga[13] - pTxVga[12];
2242 pHwData->TxVgaFor50[21].TxVgaValue = pTxVga[13] - stmp / 3;
2243 pHwData->TxVgaFor50[20].TxVgaValue = pTxVga[13] - stmp * 2 / 3;
2244
2245 /* channel 128 */
2246 pHwData->TxVgaFor50[26].ChanNo = 128;
2247 pHwData->TxVgaFor50[26].TxVgaValue = pTxVga[14];
2248 /* interpolate */
2249 pHwData->TxVgaFor50[23].ChanNo = 116;
2250 pHwData->TxVgaFor50[24].ChanNo = 120;
2251 pHwData->TxVgaFor50[25].ChanNo = 124;
2252 stmp = pTxVga[14] - pTxVga[13];
2253 pHwData->TxVgaFor50[25].TxVgaValue = pTxVga[14] - stmp / 4;
2254 pHwData->TxVgaFor50[24].TxVgaValue = pTxVga[14] - stmp * 2 / 4;
2255 pHwData->TxVgaFor50[23].TxVgaValue = pTxVga[14] - stmp * 3 / 4;
2256
2257 /* channel 140 */
2258 pHwData->TxVgaFor50[29].ChanNo = 140;
2259 pHwData->TxVgaFor50[29].TxVgaValue = pTxVga[15];
2260 /* interpolate */
2261 pHwData->TxVgaFor50[27].ChanNo = 132;
2262 pHwData->TxVgaFor50[28].ChanNo = 136;
2263 stmp = pTxVga[15] - pTxVga[14];
2264 pHwData->TxVgaFor50[28].TxVgaValue = pTxVga[15] - stmp / 3;
2265 pHwData->TxVgaFor50[27].TxVgaValue = pTxVga[15] - stmp * 2 / 3;
2266
2267 /* channel 149 */
2268 pHwData->TxVgaFor50[30].ChanNo = 149;
2269 pHwData->TxVgaFor50[30].TxVgaValue = pTxVga[16];
2270 /* channel 165 */
2271 pHwData->TxVgaFor50[34].ChanNo = 165;
2272 pHwData->TxVgaFor50[34].TxVgaValue = pTxVga[17];
2273 /* interpolate */
2274 pHwData->TxVgaFor50[31].ChanNo = 153;
2275 pHwData->TxVgaFor50[32].ChanNo = 157;
2276 pHwData->TxVgaFor50[33].ChanNo = 161;
2277 stmp = pTxVga[17] - pTxVga[16];
2278 pHwData->TxVgaFor50[33].TxVgaValue = pTxVga[17] - stmp / 4;
2279 pHwData->TxVgaFor50[32].TxVgaValue = pTxVga[17] - stmp * 2 / 4;
2280 pHwData->TxVgaFor50[31].TxVgaValue = pTxVga[17] - stmp * 3 / 4;
2281 }
2282 }
2283
2284 void BBProcessor_RateChanging(struct hw_data *pHwData, u8 rate)
2285 {
2286 struct wb35_reg *reg = &pHwData->reg;
2287 unsigned char Is11bRate;
2288
2289 Is11bRate = (rate % 6) ? 1 : 0;
2290 switch (pHwData->phy_type) {
2291 case RF_AIROHA_2230:
2292 case RF_AIROHA_2230S:
2293 if (Is11bRate) {
2294 if ((reg->BB48 != BB48_DEFAULT_AL2230_11B) &&
2295 (reg->BB4C != BB4C_DEFAULT_AL2230_11B)) {
2296 Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11B);
2297 Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11B);
2298 }
2299 } else {
2300 if ((reg->BB48 != BB48_DEFAULT_AL2230_11G) &&
2301 (reg->BB4C != BB4C_DEFAULT_AL2230_11G)) {
2302 Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_AL2230_11G);
2303 Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_AL2230_11G);
2304 }
2305 }
2306 break;
2307 case RF_WB_242:
2308 if (Is11bRate) {
2309 if ((reg->BB48 != BB48_DEFAULT_WB242_11B) &&
2310 (reg->BB4C != BB4C_DEFAULT_WB242_11B)) {
2311 reg->BB48 = BB48_DEFAULT_WB242_11B;
2312 reg->BB4C = BB4C_DEFAULT_WB242_11B;
2313 Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11B);
2314 Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11B);
2315 }
2316 } else {
2317 if ((reg->BB48 != BB48_DEFAULT_WB242_11G) &&
2318 (reg->BB4C != BB4C_DEFAULT_WB242_11G)) {
2319 reg->BB48 = BB48_DEFAULT_WB242_11G;
2320 reg->BB4C = BB4C_DEFAULT_WB242_11G;
2321 Wb35Reg_Write(pHwData, 0x1048, BB48_DEFAULT_WB242_11G);
2322 Wb35Reg_Write(pHwData, 0x104c, BB4C_DEFAULT_WB242_11G);
2323 }
2324 }
2325 break;
2326 }
2327 }
2328
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