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staging: xgifb: vb_init: make internal functions static
[deliverable/linux.git] / drivers / staging / xgifb / vb_init.c
1 #include "vgatypes.h"
2
3 #include <linux/version.h>
4 #include <linux/types.h>
5 #include <linux/delay.h> /* udelay */
6 #include "XGIfb.h"
7
8 #include "vb_def.h"
9 #include "vb_struct.h"
10 #include "vb_util.h"
11 #include "vb_setmode.h"
12 #include "vb_init.h"
13 #include "vb_ext.h"
14
15
16 #include <asm/io.h>
17
18 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
19
20 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
21 { 2, 13, 9, 64, 0x45},
22 { 2, 12, 9, 32, 0x35},
23 { 2, 12, 8, 16, 0x31},
24 { 2, 11, 8, 8, 0x21} };
25
26 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
27 { 2, 14, 11, 128, 0x5D},
28 { 2, 14, 10, 64, 0x59},
29 { 2, 13, 11, 64, 0x4D},
30 { 2, 14, 9, 32, 0x55},
31 { 2, 13, 10, 32, 0x49},
32 { 2, 12, 11, 32, 0x3D},
33 { 2, 14, 8, 16, 0x51},
34 { 2, 13, 9, 16, 0x45},
35 { 2, 12, 10, 16, 0x39},
36 { 2, 13, 8, 8, 0x41},
37 { 2, 12, 9, 8, 0x35},
38 { 2, 12, 8, 4, 0x31} };
39
40 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *, struct vb_device_info *);
41 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
42 static void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension,
43 unsigned long, struct vb_device_info *);
44 static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
45 struct vb_device_info *pVBInfo);
46
47 static int XGINew_DDRSizing340(struct xgi_hw_device_info *, struct vb_device_info *);
48 static int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
49 static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo);
50 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo);
51 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
52 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
53 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo);
54 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
55 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo);
56 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
57
58 static void DelayUS(unsigned long MicroSeconds)
59 {
60 udelay(MicroSeconds);
61 }
62
63 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
64 {
65 struct vb_device_info VBINF;
66 struct vb_device_info *pVBInfo = &VBINF;
67 unsigned char i, temp = 0, temp1;
68 /* VBIOSVersion[5]; */
69 volatile unsigned char *pVideoMemory;
70
71 /* unsigned long j, k; */
72
73 unsigned long Temp;
74
75 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
76
77 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
78
79 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
80
81 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
82
83 /* Newdebugcode(0x99); */
84
85
86 /* if (pVBInfo->ROMAddr == 0) */
87 /* return(0); */
88
89 if (pVBInfo->FBAddr == NULL) {
90 printk("\n pVBInfo->FBAddr == 0 ");
91 return 0;
92 }
93 printk("1");
94 if (pVBInfo->BaseAddr == 0) {
95 printk("\npVBInfo->BaseAddr == 0 ");
96 return 0;
97 }
98 printk("2");
99
100 XGINew_SetReg3((pVBInfo->BaseAddr + 0x12), 0x67); /* 3c2 <- 67 ,ynlai */
101
102 pVBInfo->ISXPDOS = 0;
103 printk("3");
104
105 printk("4");
106
107 /* VBIOSVersion[4] = 0x0; */
108
109 /* 09/07/99 modify by domao */
110
111 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
112 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
113 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
114 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
115 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
116 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
117 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
118 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
119 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
120 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
121 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
122 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
123 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
124 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
125 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
126 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
127 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
128 printk("5");
129
130 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
131 XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
132
133 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
134
135 /* ReadVBIOSData */
136 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
137
138 /* 1.Openkey */
139 XGINew_SetReg1(pVBInfo->P3c4, 0x05, 0x86);
140 printk("6");
141
142 /* GetXG21Sense (GPIO) */
143 if (HwDeviceExtension->jChipType == XG21)
144 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
145
146 if (HwDeviceExtension->jChipType == XG27)
147 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
148
149 printk("7");
150
151 /* 2.Reset Extended register */
152
153 for (i = 0x06; i < 0x20; i++)
154 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
155
156 for (i = 0x21; i <= 0x27; i++)
157 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
158
159 /* for(i = 0x06; i <= 0x27; i++) */
160 /* XGINew_SetReg1(pVBInfo->P3c4, i, 0); */
161
162 printk("8");
163
164 if ((HwDeviceExtension->jChipType >= XG20) || (HwDeviceExtension->jChipType >= XG40)) {
165 for (i = 0x31; i <= 0x3B; i++)
166 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
167 } else {
168 for (i = 0x31; i <= 0x3D; i++)
169 XGINew_SetReg1(pVBInfo->P3c4, i, 0);
170 }
171 printk("9");
172
173 if (HwDeviceExtension->jChipType == XG42) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
174 XGINew_SetReg1(pVBInfo->P3c4, 0x3B, 0xC0);
175
176 /* for (i = 0x30; i <= 0x3F; i++) */
177 /* XGINew_SetReg1(pVBInfo->P3d4, i, 0); */
178
179 for (i = 0x79; i <= 0x7C; i++)
180 XGINew_SetReg1(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
181
182 printk("10");
183
184 if (HwDeviceExtension->jChipType >= XG20)
185 XGINew_SetReg1(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
186
187 /* 3.SetMemoryClock
188
189 if (HwDeviceExtension->jChipType >= XG40)
190 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
191
192 if (HwDeviceExtension->jChipType < XG40)
193 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo); */
194
195 printk("11");
196
197 /* 4.SetDefExt1Regs begin */
198 XGINew_SetReg1(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
199 if (HwDeviceExtension->jChipType == XG27) {
200 XGINew_SetReg1(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
201 XGINew_SetReg1(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
202 }
203 XGINew_SetReg1(pVBInfo->P3c4, 0x11, 0x0F);
204 XGINew_SetReg1(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
205 /* XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0x20); */
206 XGINew_SetReg1(pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */
207 XGINew_SetReg1(pVBInfo->P3c4, 0x36, 0x70); /* Hsuan, 2006/01/01 H/W request for slow corner chip */
208 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
209 XGINew_SetReg1(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
210
211 /* SR11 = 0x0F; */
212 /* XGINew_SetReg1(pVBInfo->P3c4, 0x11, SR11); */
213
214 printk("12");
215
216 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
217 /* Set AGP Rate */
218 /*
219 temp1 = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
220 temp1 &= 0x02;
221 if (temp1 == 0x02) {
222 XGINew_SetReg4(0xcf8, 0x80000000);
223 ChipsetID = XGINew_GetReg3(0x0cfc);
224 XGINew_SetReg4(0xcf8, 0x8000002C);
225 VendorID = XGINew_GetReg3(0x0cfc);
226 VendorID &= 0x0000FFFF;
227 XGINew_SetReg4(0xcf8, 0x8001002C);
228 GraphicVendorID = XGINew_GetReg3(0x0cfc);
229 GraphicVendorID &= 0x0000FFFF;
230
231 if (ChipsetID == 0x7301039)
232 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x09);
233
234 ChipsetID &= 0x0000FFFF;
235
236 if ((ChipsetID == 0x700E) || (ChipsetID == 0x1022) || (ChipsetID == 0x1106) || (ChipsetID == 0x10DE)) {
237 if (ChipsetID == 0x1106) {
238 if ((VendorID == 0x1019) && (GraphicVendorID == 0x1019))
239 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0D);
240 else
241 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
242 } else {
243 XGINew_SetReg1(pVBInfo->P3d4, 0x5F, 0x0B);
244 }
245 }
246 }
247 */
248
249 printk("13");
250
251 if (HwDeviceExtension->jChipType >= XG40) {
252 /* Set AGP customize registers (in SetDefAGPRegs) Start */
253 for (i = 0x47; i <= 0x4C; i++)
254 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[i - 0x47]);
255
256 for (i = 0x70; i <= 0x71; i++)
257 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[6 + i - 0x70]);
258
259 for (i = 0x74; i <= 0x77; i++)
260 XGINew_SetReg1(pVBInfo->P3d4, i, pVBInfo->AGPReg[8 + i - 0x74]);
261 /* Set AGP customize registers (in SetDefAGPRegs) End */
262 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
263 /* XGINew_SetReg4(0xcf8 , 0x80000000); */
264 /* ChipsetID = XGINew_GetReg3(0x0cfc); */
265 /* if (ChipsetID == 0x25308086) */
266 /* XGINew_SetReg1(pVBInfo->P3d4, 0x77, 0xF0); */
267
268 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x50, 0, &Temp); /* Get */
269 Temp >>= 20;
270 Temp &= 0xF;
271
272 if (Temp == 1)
273 XGINew_SetReg1(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
274 }
275 printk("14");
276
277 if (HwDeviceExtension->jChipType < XG40)
278 XGINew_SetReg1(pVBInfo->P3d4, 0x49, pVBInfo->CR49[0]);
279 } /* != XG20 */
280
281 /* Set PCI */
282 XGINew_SetReg1(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
283 XGINew_SetReg1(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
284 XGINew_SetReg1(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
285 printk("15");
286
287 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
288 /* Set VB */
289 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
290 XGINew_SetRegANDOR(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); /* alan, disable VideoCapture */
291 XGINew_SetReg1(pVBInfo->Part1Port, 0x00, 0x00);
292 temp1 = (unsigned char) XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
293 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
294
295 XGINew_SetReg1(pVBInfo->Part1Port, 0x02, (*pVBInfo->pCRT2Data_1_2));
296
297 printk("16");
298
299 XGINew_SetReg1(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
300 } /* != XG20 */
301
302 XGINew_SetReg1(pVBInfo->P3c4, 0x27, 0x1F);
303
304 if ((HwDeviceExtension->jChipType == XG42)
305 && XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { /* Not DDR */
306 XGINew_SetReg1(pVBInfo->P3c4, 0x31, (*pVBInfo->pSR31 & 0x3F) | 0x40);
307 XGINew_SetReg1(pVBInfo->P3c4, 0x32, (*pVBInfo->pSR32 & 0xFC) | 0x01);
308 } else {
309 XGINew_SetReg1(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
310 XGINew_SetReg1(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
311 }
312 XGINew_SetReg1(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
313 printk("17");
314
315 /*
316 if (HwDeviceExtension->jChipType >= XG40)
317 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
318
319 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
320 if (XGI_BridgeIsOn(pVBInfo) == 1) {
321 if (pVBInfo->IF_DEF_LVDS == 0) {
322 XGINew_SetReg1(pVBInfo->Part2Port, 0x00, 0x1C);
323 XGINew_SetReg1(pVBInfo->Part4Port, 0x0D, *pVBInfo->pCRT2Data_4_D);
324 XGINew_SetReg1(pVBInfo->Part4Port, 0x0E, *pVBInfo->pCRT2Data_4_E);
325 XGINew_SetReg1(pVBInfo->Part4Port, 0x10, *pVBInfo->pCRT2Data_4_10);
326 XGINew_SetReg1(pVBInfo->Part4Port, 0x0F, 0x3F);
327 }
328
329 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
330 }
331 } /* != XG20 */
332 printk("18");
333
334 if (HwDeviceExtension->jChipType < XG40)
335 XGINew_SetReg1(pVBInfo->P3d4, 0x83, 0x00);
336 printk("181");
337
338 printk("182");
339
340 XGI_SenseCRT1(pVBInfo);
341
342 printk("183");
343 /* XGINew_DetectMonitor(HwDeviceExtension); */
344 pVBInfo->IF_DEF_CH7007 = 0;
345 if ((HwDeviceExtension->jChipType == XG21) && (pVBInfo->IF_DEF_CH7007)) {
346 printk("184");
347 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo); /* sense CRT2 */
348 printk("185");
349
350 }
351 if (HwDeviceExtension->jChipType == XG21) {
352 printk("186");
353
354 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
355 temp = GetXG21FPBits(pVBInfo);
356 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x01, temp);
357 printk("187");
358
359 }
360 if (HwDeviceExtension->jChipType == XG27) {
361 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
362 temp = GetXG27FPBits(pVBInfo);
363 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x37, ~0x03, temp);
364 }
365 printk("19");
366
367 if (HwDeviceExtension->jChipType >= XG40) {
368 if (HwDeviceExtension->jChipType >= XG40)
369 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
370
371 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, pVBInfo->P3d4, pVBInfo);
372
373 printk("20");
374 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
375 printk("21");
376 } /* XG40 */
377
378 printk("22");
379
380 /* SetDefExt2Regs begin */
381 /*
382 AGP = 1;
383 temp = (unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x3A);
384 temp &= 0x30;
385 if (temp == 0x30)
386 AGP = 0;
387
388 if (AGP == 0)
389 *pVBInfo->pSR21 &= 0xEF;
390
391 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
392 if (AGP == 1)
393 *pVBInfo->pSR22 &= 0x20;
394 XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
395 */
396 /* base = 0x80000000; */
397 /* OutPortLong(0xcf8, base); */
398 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
399 /* if (Temp == 0x1039) { */
400 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
401 /* } else { */
402 /* XGINew_SetReg1(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
403 /* } */
404
405 XGINew_SetReg1(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
406
407 printk("23");
408
409 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
410 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
411
412 printk("24");
413
414 XGINew_SetReg1(pVBInfo->P3d4, 0x8c, 0x87);
415 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31);
416 printk("25");
417
418 return 1;
419 } /* end of init */
420
421 /* ============== alan ====================== */
422
423 static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
424 struct vb_device_info *pVBInfo)
425 {
426 unsigned char data, temp;
427
428 if (HwDeviceExtension->jChipType < XG20) {
429 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
430 data = *pVBInfo->pSoftSetting & 0x07;
431 return data;
432 } else {
433 data = XGINew_GetReg1(pVBInfo->P3c4, 0x39) & 0x02;
434
435 if (data == 0)
436 data = (XGINew_GetReg1(pVBInfo->P3c4, 0x3A) & 0x02) >> 1;
437
438 return data;
439 }
440 } else if (HwDeviceExtension->jChipType == XG27) {
441 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
442 data = *pVBInfo->pSoftSetting & 0x07;
443 return data;
444 }
445 temp = XGINew_GetReg1(pVBInfo->P3c4, 0x3B);
446
447 if ((temp & 0x88) == 0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
448 data = 0; /* DDR */
449 else
450 data = 1; /* DDRII */
451 return data;
452 } else if (HwDeviceExtension->jChipType == XG21) {
453 XGINew_SetRegAND(pVBInfo->P3d4, 0xB4, ~0x02); /* Independent GPIO control */
454 DelayUS(800);
455 XGINew_SetRegOR(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
456 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48); /* GPIOF 0:DVI 1:DVO */
457 /* HOTPLUG_SUPPORT */
458 /* for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily */
459 if (temp & 0x01) /* DVI read GPIOH */
460 data = 1; /* DDRII */
461 else
462 data = 0; /* DDR */
463 /* ~HOTPLUG_SUPPORT */
464 XGINew_SetRegOR(pVBInfo->P3d4, 0xB4, 0x02);
465 return data;
466 } else {
467 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97) & 0x01;
468
469 if (data == 1)
470 data++;
471
472 return data;
473 }
474 }
475
476 static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
477 {
478 XGINew_SetReg1(P3c4, 0x18, 0x01);
479 XGINew_SetReg1(P3c4, 0x19, 0x20);
480 XGINew_SetReg1(P3c4, 0x16, 0x00);
481 XGINew_SetReg1(P3c4, 0x16, 0x80);
482
483 if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
484 DelayUS(3000); /* Delay 67 x 3 Delay15us */
485 XGINew_SetReg1(P3c4, 0x18, 0x00);
486 XGINew_SetReg1(P3c4, 0x19, 0x20);
487 XGINew_SetReg1(P3c4, 0x16, 0x00);
488 XGINew_SetReg1(P3c4, 0x16, 0x80);
489 }
490
491 DelayUS(60);
492 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
493 XGINew_SetReg1(P3c4, 0x19, 0x01);
494 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[0]);
495 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[1]);
496 DelayUS(1000);
497 XGINew_SetReg1(P3c4, 0x1B, 0x03);
498 DelayUS(500);
499 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
500 XGINew_SetReg1(P3c4, 0x19, 0x00);
501 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[2]);
502 XGINew_SetReg1(P3c4, 0x16, pVBInfo->SR16[3]);
503 XGINew_SetReg1(P3c4, 0x1B, 0x00);
504 }
505
506 static void XGINew_DDRII_Bootup_XG27(
507 struct xgi_hw_device_info *HwDeviceExtension,
508 unsigned long P3c4, struct vb_device_info *pVBInfo)
509 {
510 unsigned long P3d4 = P3c4 + 0x10;
511 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
512 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
513
514 /* Set Double Frequency */
515 /* XGINew_SetReg1(P3d4, 0x97, 0x11); *//* CR97 */
516 XGINew_SetReg1(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
517
518 DelayUS(200);
519
520 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
521 XGINew_SetReg1(P3c4, 0x19, 0x80); /* Set SR19 */
522 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
523 DelayUS(15);
524 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
525 DelayUS(15);
526
527 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
528 XGINew_SetReg1(P3c4, 0x19, 0xC0); /* Set SR19 */
529 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
530 DelayUS(15);
531 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
532 DelayUS(15);
533
534 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
535 XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
536 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
537 DelayUS(30);
538 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
539 DelayUS(15);
540
541 XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
542 XGINew_SetReg1(P3c4, 0x19, 0x0A); /* Set SR19 */
543 XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
544 DelayUS(30);
545 XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
546 XGINew_SetReg1(P3c4, 0x16, 0x80); /* Set SR16 */
547 /* DelayUS(15); */
548
549 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B */
550 DelayUS(60);
551 XGINew_SetReg1(P3c4, 0x1B, 0x00); /* Set SR1B */
552
553 XGINew_SetReg1(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
554 XGINew_SetReg1(P3c4, 0x19, 0x08); /* Set SR19 */
555 XGINew_SetReg1(P3c4, 0x16, 0x00); /* Set SR16 */
556
557 DelayUS(30);
558 XGINew_SetReg1(P3c4, 0x16, 0x83); /* Set SR16 */
559 DelayUS(15);
560
561 XGINew_SetReg1(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
562 XGINew_SetReg1(P3c4, 0x19, 0x46); /* Set SR19 */
563 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
564 DelayUS(30);
565 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
566 DelayUS(15);
567
568 XGINew_SetReg1(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
569 XGINew_SetReg1(P3c4, 0x19, 0x40); /* Set SR19 */
570 XGINew_SetReg1(P3c4, 0x16, 0x20); /* Set SR16 */
571 DelayUS(30);
572 XGINew_SetReg1(P3c4, 0x16, 0xA0); /* Set SR16 */
573 DelayUS(15);
574
575 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* Set SR1B refresh control 000:close; 010:open */
576 DelayUS(200);
577
578 }
579
580 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
581 unsigned long P3c4, struct vb_device_info *pVBInfo)
582 {
583 unsigned long P3d4 = P3c4 + 0x10;
584
585 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
586 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
587
588 XGINew_SetReg1(P3d4, 0x97, 0x11); /* CR97 */
589
590 DelayUS(200);
591 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS2 */
592 XGINew_SetReg1(P3c4, 0x19, 0x80);
593 XGINew_SetReg1(P3c4, 0x16, 0x05);
594 XGINew_SetReg1(P3c4, 0x16, 0x85);
595
596 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS3 */
597 XGINew_SetReg1(P3c4, 0x19, 0xC0);
598 XGINew_SetReg1(P3c4, 0x16, 0x05);
599 XGINew_SetReg1(P3c4, 0x16, 0x85);
600
601 XGINew_SetReg1(P3c4, 0x18, 0x00); /* EMRS1 */
602 XGINew_SetReg1(P3c4, 0x19, 0x40);
603 XGINew_SetReg1(P3c4, 0x16, 0x05);
604 XGINew_SetReg1(P3c4, 0x16, 0x85);
605
606 /* XGINew_SetReg1(P3c4, 0x18, 0x52); */ /* MRS1 */
607 XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
608 XGINew_SetReg1(P3c4, 0x19, 0x02);
609 XGINew_SetReg1(P3c4, 0x16, 0x05);
610 XGINew_SetReg1(P3c4, 0x16, 0x85);
611
612 DelayUS(15);
613 XGINew_SetReg1(P3c4, 0x1B, 0x04); /* SR1B */
614 DelayUS(30);
615 XGINew_SetReg1(P3c4, 0x1B, 0x00); /* SR1B */
616 DelayUS(100);
617
618 /* XGINew_SetReg1(P3c4 ,0x18, 0x52); */ /* MRS2 */
619 XGINew_SetReg1(P3c4, 0x18, 0x42); /* MRS1 */
620 XGINew_SetReg1(P3c4, 0x19, 0x00);
621 XGINew_SetReg1(P3c4, 0x16, 0x05);
622 XGINew_SetReg1(P3c4, 0x16, 0x85);
623
624 DelayUS(200);
625 }
626
627 static void XGINew_DDR1x_DefaultRegister(
628 struct xgi_hw_device_info *HwDeviceExtension,
629 unsigned long Port, struct vb_device_info *pVBInfo)
630 {
631 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
632
633 if (HwDeviceExtension->jChipType >= XG20) {
634 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
635 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
636 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
637 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
638
639 XGINew_SetReg1(P3d4, 0x98, 0x01);
640 XGINew_SetReg1(P3d4, 0x9A, 0x02);
641
642 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
643 } else {
644 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
645
646 switch (HwDeviceExtension->jChipType) {
647 case XG41:
648 case XG42:
649 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
650 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
651 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
652 break;
653 default:
654 XGINew_SetReg1(P3d4, 0x82, 0x88);
655 XGINew_SetReg1(P3d4, 0x86, 0x00);
656 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
657 XGINew_SetReg1(P3d4, 0x86, 0x88);
658 XGINew_GetReg1(P3d4, 0x86);
659 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
660 XGINew_SetReg1(P3d4, 0x82, 0x77);
661 XGINew_SetReg1(P3d4, 0x85, 0x00);
662 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
663 XGINew_SetReg1(P3d4, 0x85, 0x88);
664 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
665 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
666 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
667 break;
668 }
669
670 XGINew_SetReg1(P3d4, 0x97, 0x00);
671 XGINew_SetReg1(P3d4, 0x98, 0x01);
672 XGINew_SetReg1(P3d4, 0x9A, 0x02);
673 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
674 }
675 }
676
677 static void XGINew_DDR2_DefaultRegister(
678 struct xgi_hw_device_info *HwDeviceExtension,
679 unsigned long Port, struct vb_device_info *pVBInfo)
680 {
681 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
682
683 /* keep following setting sequence, each setting in the same reg insert idle */
684 XGINew_SetReg1(P3d4, 0x82, 0x77);
685 XGINew_SetReg1(P3d4, 0x86, 0x00);
686 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
687 XGINew_SetReg1(P3d4, 0x86, 0x88);
688 XGINew_GetReg1(P3d4, 0x86); /* Insert read command for delay */
689 XGINew_SetReg1(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
690 XGINew_SetReg1(P3d4, 0x82, 0x77);
691 XGINew_SetReg1(P3d4, 0x85, 0x00);
692 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
693 XGINew_SetReg1(P3d4, 0x85, 0x88);
694 XGINew_GetReg1(P3d4, 0x85); /* Insert read command for delay */
695 XGINew_SetReg1(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
696 if (HwDeviceExtension->jChipType == XG27)
697 XGINew_SetReg1(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
698 else
699 XGINew_SetReg1(P3d4, 0x82, 0xA8); /* CR82 */
700
701 XGINew_SetReg1(P3d4, 0x98, 0x01);
702 XGINew_SetReg1(P3d4, 0x9A, 0x02);
703 if (HwDeviceExtension->jChipType == XG27)
704 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
705 else
706 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
707 }
708
709 static void XGINew_SetDRAMDefaultRegister340(
710 struct xgi_hw_device_info *HwDeviceExtension,
711 unsigned long Port, struct vb_device_info *pVBInfo)
712 {
713 unsigned char temp, temp1, temp2, temp3, i, j, k;
714
715 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
716
717 XGINew_SetReg1(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
718 XGINew_SetReg1(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
719 XGINew_SetReg1(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
720 XGINew_SetReg1(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
721
722 temp2 = 0;
723 for (i = 0; i < 4; i++) {
724 temp = pVBInfo->CR6B[XGINew_RAMType][i]; /* CR6B DQS fine tune delay */
725 for (j = 0; j < 4; j++) {
726 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
727 temp2 |= temp1;
728 XGINew_SetReg1(P3d4, 0x6B, temp2);
729 XGINew_GetReg1(P3d4, 0x6B); /* Insert read command for delay */
730 temp2 &= 0xF0;
731 temp2 += 0x10;
732 }
733 }
734
735 temp2 = 0;
736 for (i = 0; i < 4; i++) {
737 temp = pVBInfo->CR6E[XGINew_RAMType][i]; /* CR6E DQM fine tune delay */
738 for (j = 0; j < 4; j++) {
739 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
740 temp2 |= temp1;
741 XGINew_SetReg1(P3d4, 0x6E, temp2);
742 XGINew_GetReg1(P3d4, 0x6E); /* Insert read command for delay */
743 temp2 &= 0xF0;
744 temp2 += 0x10;
745 }
746 }
747
748 temp3 = 0;
749 for (k = 0; k < 4; k++) {
750 XGINew_SetRegANDOR(P3d4, 0x6E, 0xFC, temp3); /* CR6E_D[1:0] select channel */
751 temp2 = 0;
752 for (i = 0; i < 8; i++) {
753 temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i]; /* CR6F DQ fine tune delay */
754 for (j = 0; j < 4; j++) {
755 temp1 = (temp >> (2 * j)) & 0x03;
756 temp2 |= temp1;
757 XGINew_SetReg1(P3d4, 0x6F, temp2);
758 XGINew_GetReg1(P3d4, 0x6F); /* Insert read command for delay */
759 temp2 &= 0xF8;
760 temp2 += 0x08;
761 }
762 }
763 temp3 += 0x01;
764 }
765
766 XGINew_SetReg1(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
767 XGINew_SetReg1(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
768
769 temp2 = 0x80;
770 temp = pVBInfo->CR89[XGINew_RAMType][0]; /* CR89 terminator type select */
771 for (j = 0; j < 4; j++) {
772 temp1 = (temp >> (2 * j)) & 0x03;
773 temp2 |= temp1;
774 XGINew_SetReg1(P3d4, 0x89, temp2);
775 XGINew_GetReg1(P3d4, 0x89); /* Insert read command for delay */
776 temp2 &= 0xF0;
777 temp2 += 0x10;
778 }
779
780 temp = pVBInfo->CR89[XGINew_RAMType][1];
781 temp1 = temp & 0x03;
782 temp2 |= temp1;
783 XGINew_SetReg1(P3d4, 0x89, temp2);
784
785 temp = pVBInfo->CR40[3][XGINew_RAMType];
786 temp1 = temp & 0x0F;
787 temp2 = (temp >> 4) & 0x07;
788 temp3 = temp & 0x80;
789 XGINew_SetReg1(P3d4, 0x45, temp1); /* CR45 */
790 XGINew_SetReg1(P3d4, 0x99, temp2); /* CR99 */
791 XGINew_SetRegOR(P3d4, 0x40, temp3); /* CR40_D[7] */
792 XGINew_SetReg1(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
793
794 if (HwDeviceExtension->jChipType == XG27)
795 XGINew_SetReg1(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
796
797 for (j = 0; j <= 6; j++)
798 XGINew_SetReg1(P3d4, (0x90 + j),
799 pVBInfo->CR40[14 + j][XGINew_RAMType]); /* CR90 - CR96 */
800
801 for (j = 0; j <= 2; j++)
802 XGINew_SetReg1(P3d4, (0xC3 + j),
803 pVBInfo->CR40[21 + j][XGINew_RAMType]); /* CRC3 - CRC5 */
804
805 for (j = 0; j < 2; j++)
806 XGINew_SetReg1(P3d4, (0x8A + j),
807 pVBInfo->CR40[1 + j][XGINew_RAMType]); /* CR8A - CR8B */
808
809 if ((HwDeviceExtension->jChipType == XG41) || (HwDeviceExtension->jChipType == XG42))
810 XGINew_SetReg1(P3d4, 0x8C, 0x87);
811
812 XGINew_SetReg1(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
813
814 XGINew_SetReg1(P3d4, 0x83, 0x09); /* CR83 */
815 XGINew_SetReg1(P3d4, 0x87, 0x00); /* CR87 */
816 XGINew_SetReg1(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
817 if (XGINew_RAMType) {
818 /* XGINew_SetReg1(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
819 XGINew_SetReg1(P3c4, 0x17, 0x80); /* SR17 DDRII */
820 if (HwDeviceExtension->jChipType == XG27)
821 XGINew_SetReg1(P3c4, 0x17, 0x02); /* SR17 DDRII */
822
823 } else {
824 XGINew_SetReg1(P3c4, 0x17, 0x00); /* SR17 DDR */
825 }
826 XGINew_SetReg1(P3c4, 0x1A, 0x87); /* SR1A */
827
828 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
829 if (temp == 0) {
830 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
831 } else {
832 XGINew_SetReg1(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
833 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
834 }
835 XGINew_SetReg1(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
836 }
837
838 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
839 struct vb_device_info *pVBInfo)
840 {
841 unsigned short data;
842
843 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
844 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
845
846 XGISetModeNew(HwDeviceExtension, 0x2e);
847
848 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
849 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
850 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
851
852 /* data = XGINew_GetReg1(pVBInfo->P3c4, 0x1); */
853 /* data |= 0x20 ; */
854 /* XGINew_SetReg1(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
855 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
856 data = XGINew_GetReg1(pVBInfo->P3c4, 0x21);
857 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
858 }
859
860 static void XGINew_SetDRAMSizingType(int index,
861 unsigned short DRAMTYPE_TABLE[][5],
862 struct vb_device_info *pVBInfo)
863 {
864 unsigned short data;
865
866 data = DRAMTYPE_TABLE[index][4];
867 XGINew_SetRegANDOR(pVBInfo->P3c4, 0x13, 0x80, data);
868 DelayUS(15);
869 /* should delay 50 ns */
870 }
871
872 static unsigned short XGINew_SetDRAMSizeReg(int index,
873 unsigned short DRAMTYPE_TABLE[][5],
874 struct vb_device_info *pVBInfo)
875 {
876 unsigned short data = 0, memsize = 0;
877 int RankSize;
878 unsigned char ChannelNo;
879
880 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
881 data = XGINew_GetReg1(pVBInfo->P3c4, 0x13);
882 data &= 0x80;
883
884 if (data == 0x80)
885 RankSize *= 2;
886
887 data = 0;
888
889 if (XGINew_ChannelAB == 3)
890 ChannelNo = 4;
891 else
892 ChannelNo = XGINew_ChannelAB;
893
894 if (ChannelNo * RankSize <= 256) {
895 while ((RankSize >>= 1) > 0)
896 data += 0x10;
897
898 memsize = data >> 4;
899
900 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
901 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (XGINew_GetReg1(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
902
903 /* data |= XGINew_ChannelAB << 2; */
904 /* data |= (XGINew_DataBusWidth / 64) << 1; */
905 /* XGINew_SetReg1(pVBInfo->P3c4, 0x14, data); */
906
907 /* should delay */
908 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
909 }
910 return memsize;
911 }
912
913 static unsigned short XGINew_SetDRAMSize20Reg(int index,
914 unsigned short DRAMTYPE_TABLE[][5],
915 struct vb_device_info *pVBInfo)
916 {
917 unsigned short data = 0, memsize = 0;
918 int RankSize;
919 unsigned char ChannelNo;
920
921 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
922 data = XGINew_GetReg1(pVBInfo->P3c4, 0x13);
923 data &= 0x80;
924
925 if (data == 0x80)
926 RankSize *= 2;
927
928 data = 0;
929
930 if (XGINew_ChannelAB == 3)
931 ChannelNo = 4;
932 else
933 ChannelNo = XGINew_ChannelAB;
934
935 if (ChannelNo * RankSize <= 256) {
936 while ((RankSize >>= 1) > 0)
937 data += 0x10;
938
939 memsize = data >> 4;
940
941 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
942 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (XGINew_GetReg1(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
943 DelayUS(15);
944
945 /* data |= XGINew_ChannelAB << 2; */
946 /* data |= (XGINew_DataBusWidth / 64) << 1; */
947 /* XGINew_SetReg1(pVBInfo->P3c4, 0x14, data); */
948
949 /* should delay */
950 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
951 }
952 return memsize;
953 }
954
955 static int XGINew_ReadWriteRest(unsigned short StopAddr,
956 unsigned short StartAddr, struct vb_device_info *pVBInfo)
957 {
958 int i;
959 unsigned long Position = 0;
960
961 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
962
963 for (i = StartAddr; i <= StopAddr; i++) {
964 Position = 1 << i;
965 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
966 }
967
968 DelayUS(500); /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
969
970 Position = 0;
971
972 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
973 return 0;
974
975 for (i = StartAddr; i <= StopAddr; i++) {
976 Position = 1 << i;
977 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
978 return 0;
979 }
980 return 1;
981 }
982
983 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
984 {
985 unsigned char data;
986
987 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97);
988
989 if ((data & 0x10) == 0) {
990 data = XGINew_GetReg1(pVBInfo->P3c4, 0x39);
991 data = (data & 0x02) >> 1;
992 return data;
993 } else {
994 return data & 0x01;
995 }
996 }
997
998 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
999 struct vb_device_info *pVBInfo)
1000 {
1001 unsigned char data;
1002
1003 switch (HwDeviceExtension->jChipType) {
1004 case XG20:
1005 case XG21:
1006 data = XGINew_GetReg1(pVBInfo->P3d4, 0x97);
1007 data = data & 0x01;
1008 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
1009
1010 if (data == 0) { /* Single_32_16 */
1011
1012 if ((HwDeviceExtension->ulVideoMemorySize - 1)
1013 > 0x1000000) {
1014
1015 XGINew_DataBusWidth = 32; /* 32 bits */
1016 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 32bit */
1017 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
1018 DelayUS(15);
1019
1020 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1021 return;
1022
1023 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
1024 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* 22bit + 1 rank + 32bit */
1025 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
1026 DelayUS(15);
1027
1028 if (XGINew_ReadWriteRest(23, 23, pVBInfo) == 1)
1029 return;
1030 }
1031 }
1032
1033 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
1034 XGINew_DataBusWidth = 16; /* 16 bits */
1035 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 16bit */
1036 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41);
1037 DelayUS(15);
1038
1039 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
1040 return;
1041 else
1042 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31);
1043 DelayUS(15);
1044 }
1045
1046 } else { /* Dual_16_8 */
1047 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
1048
1049 XGINew_DataBusWidth = 16; /* 16 bits */
1050 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
1051 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x41); /* 0x41:16Mx16 bit*/
1052 DelayUS(15);
1053
1054 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
1055 return;
1056
1057 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
1058 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
1059 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x31); /* 0x31:8Mx16 bit*/
1060 DelayUS(15);
1061
1062 if (XGINew_ReadWriteRest(22, 22, pVBInfo) == 1)
1063 return;
1064 }
1065 }
1066
1067 if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
1068 XGINew_DataBusWidth = 8; /* 8 bits */
1069 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
1070 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x30); /* 0x30:8Mx8 bit*/
1071 DelayUS(15);
1072
1073 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
1074 return;
1075 else
1076 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
1077 DelayUS(15);
1078 }
1079 }
1080 break;
1081
1082 case XG27:
1083 XGINew_DataBusWidth = 16; /* 16 bits */
1084 XGINew_ChannelAB = 1; /* Single channel */
1085 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
1086 break;
1087 case XG41:
1088 if (XGINew_CheckFrequence(pVBInfo) == 1) {
1089 XGINew_DataBusWidth = 32; /* 32 bits */
1090 XGINew_ChannelAB = 3; /* Quad Channel */
1091 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1092 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4C);
1093
1094 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
1095 return;
1096
1097 XGINew_ChannelAB = 2; /* Dual channels */
1098 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x48);
1099
1100 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1101 return;
1102
1103 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x49);
1104
1105 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1106 return;
1107
1108 XGINew_ChannelAB = 3;
1109 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1110 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x3C);
1111
1112 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1113 return;
1114
1115 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x38);
1116
1117 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
1118 return;
1119 else
1120 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x39);
1121 } else { /* DDR */
1122 XGINew_DataBusWidth = 64; /* 64 bits */
1123 XGINew_ChannelAB = 2; /* Dual channels */
1124 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1125 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x5A);
1126
1127 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
1128 return;
1129
1130 XGINew_ChannelAB = 1; /* Single channels */
1131 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
1132
1133 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1134 return;
1135
1136 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x53);
1137
1138 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1139 return;
1140
1141 XGINew_ChannelAB = 2; /* Dual channels */
1142 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1143 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4A);
1144
1145 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1146 return;
1147
1148 XGINew_ChannelAB = 1; /* Single channels */
1149 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
1150
1151 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
1152 return;
1153 else
1154 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x43);
1155 }
1156
1157 break;
1158
1159 case XG42:
1160 /*
1161 XG42 SR14 D[3] Reserve
1162 D[2] = 1, Dual Channel
1163 = 0, Single Channel
1164
1165 It's Different from Other XG40 Series.
1166 */
1167 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
1168 XGINew_DataBusWidth = 32; /* 32 bits */
1169 XGINew_ChannelAB = 2; /* 2 Channel */
1170 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1171 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x44);
1172
1173 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1174 return;
1175
1176 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1177 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x34);
1178 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
1179 return;
1180
1181 XGINew_ChannelAB = 1; /* Single Channel */
1182 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1183 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x40);
1184
1185 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
1186 return;
1187 else {
1188 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1189 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x30);
1190 }
1191 } else { /* DDR */
1192 XGINew_DataBusWidth = 64; /* 64 bits */
1193 XGINew_ChannelAB = 1; /* 1 channels */
1194 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1195 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x52);
1196
1197 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1198 return;
1199 else {
1200 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1201 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x42);
1202 }
1203 }
1204
1205 break;
1206
1207 default: /* XG40 */
1208
1209 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
1210 XGINew_DataBusWidth = 32; /* 32 bits */
1211 XGINew_ChannelAB = 3;
1212 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1213 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4C);
1214
1215 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
1216 return;
1217
1218 XGINew_ChannelAB = 2; /* 2 channels */
1219 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x48);
1220
1221 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
1222 return;
1223
1224 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1225 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x3C);
1226
1227 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
1228 XGINew_ChannelAB = 3; /* 4 channels */
1229 } else {
1230 XGINew_ChannelAB = 2; /* 2 channels */
1231 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x38);
1232 }
1233 } else { /* DDR */
1234 XGINew_DataBusWidth = 64; /* 64 bits */
1235 XGINew_ChannelAB = 2; /* 2 channels */
1236 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0xA1);
1237 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x5A);
1238
1239 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
1240 return;
1241 } else {
1242 XGINew_SetReg1(pVBInfo->P3c4, 0x13, 0x21);
1243 XGINew_SetReg1(pVBInfo->P3c4, 0x14, 0x4A);
1244 }
1245 }
1246 break;
1247 }
1248 }
1249
1250 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1251 struct vb_device_info *pVBInfo)
1252 {
1253 int i;
1254 unsigned short memsize, addr;
1255
1256 XGINew_SetReg1(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
1257 XGINew_SetReg1(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
1258 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
1259
1260 if (HwDeviceExtension->jChipType >= XG20) {
1261 for (i = 0; i < 12; i++) {
1262 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
1263 memsize = XGINew_SetDRAMSize20Reg(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
1264 if (memsize == 0)
1265 continue;
1266
1267 addr = memsize + (XGINew_ChannelAB - 2) + 20;
1268 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
1269 continue;
1270
1271 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
1272 return 1;
1273 }
1274 } else {
1275 for (i = 0; i < 4; i++) {
1276 XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
1277 memsize = XGINew_SetDRAMSizeReg(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
1278
1279 if (memsize == 0)
1280 continue;
1281
1282 addr = memsize + (XGINew_ChannelAB - 2) + 20;
1283 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
1284 continue;
1285
1286 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
1287 return 1;
1288 }
1289 }
1290 return 0;
1291 }
1292
1293 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
1294 struct vb_device_info *pVBInfo)
1295 {
1296
1297 XGINew_SetReg1(pVBInfo->P3c4, 0x28, pVBInfo->MCLKData[XGINew_RAMType].SR28);
1298 XGINew_SetReg1(pVBInfo->P3c4, 0x29, pVBInfo->MCLKData[XGINew_RAMType].SR29);
1299 XGINew_SetReg1(pVBInfo->P3c4, 0x2A, pVBInfo->MCLKData[XGINew_RAMType].SR2A);
1300
1301 XGINew_SetReg1(pVBInfo->P3c4, 0x2E, pVBInfo->ECLKData[XGINew_RAMType].SR2E);
1302 XGINew_SetReg1(pVBInfo->P3c4, 0x2F, pVBInfo->ECLKData[XGINew_RAMType].SR2F);
1303 XGINew_SetReg1(pVBInfo->P3c4, 0x30, pVBInfo->ECLKData[XGINew_RAMType].SR30);
1304
1305 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
1306 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
1307 if (HwDeviceExtension->jChipType == XG42) {
1308 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C)
1309 && (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01)
1310 && (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C)
1311 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))
1312 || ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22)
1313 && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
1314 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char) XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
1315 }
1316 }
1317
1318 static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
1319 {
1320 volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1321 unsigned long i;
1322 unsigned char j, k;
1323 /* Volari customize data area end */
1324
1325 if (ChipType == XG21) {
1326 pVBInfo->IF_DEF_LVDS = 0;
1327 if (pVideoMemory[0x65] & 0x1) {
1328 pVBInfo->IF_DEF_LVDS = 1;
1329 i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
1330 j = pVideoMemory[i - 1];
1331 if (j != 0xff) {
1332 k = 0;
1333 do {
1334 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability
1335 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
1336 pVBInfo->XG21_LVDSCapList[k].LVDSHT
1337 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
1338 pVBInfo->XG21_LVDSCapList[k].LVDSVT
1339 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
1340 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
1341 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
1342 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
1343 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
1344 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
1345 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
1346 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
1347 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
1348 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
1349 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
1350 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1351 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
1352 pVBInfo->XG21_LVDSCapList[k].VCLKData1
1353 = pVideoMemory[i + 18];
1354 pVBInfo->XG21_LVDSCapList[k].VCLKData2
1355 = pVideoMemory[i + 19];
1356 pVBInfo->XG21_LVDSCapList[k].PSC_S1
1357 = pVideoMemory[i + 20];
1358 pVBInfo->XG21_LVDSCapList[k].PSC_S2
1359 = pVideoMemory[i + 21];
1360 pVBInfo->XG21_LVDSCapList[k].PSC_S3
1361 = pVideoMemory[i + 22];
1362 pVBInfo->XG21_LVDSCapList[k].PSC_S4
1363 = pVideoMemory[i + 23];
1364 pVBInfo->XG21_LVDSCapList[k].PSC_S5
1365 = pVideoMemory[i + 24];
1366 i += 25;
1367 j--;
1368 k++;
1369 } while ((j > 0) && (k < (sizeof(XGI21_LCDCapList) / sizeof(struct XGI21_LVDSCapStruct))));
1370 } else {
1371 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1372 = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
1373 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1374 = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
1375 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1376 = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
1377 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1378 = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
1379 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1380 = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
1381 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1382 = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
1383 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1384 = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
1385 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1386 = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
1387 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1388 = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
1389 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1390 = pVideoMemory[i + 18];
1391 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1392 = pVideoMemory[i + 19];
1393 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1394 = pVideoMemory[i + 20];
1395 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1396 = pVideoMemory[i + 21];
1397 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1398 = pVideoMemory[i + 22];
1399 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1400 = pVideoMemory[i + 23];
1401 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1402 = pVideoMemory[i + 24];
1403 }
1404 }
1405 }
1406 }
1407
1408 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
1409 {
1410
1411 XGINew_SetReg1(P3c4, 0x18, 0x01);
1412 XGINew_SetReg1(P3c4, 0x19, 0x40);
1413 XGINew_SetReg1(P3c4, 0x16, 0x00);
1414 XGINew_SetReg1(P3c4, 0x16, 0x80);
1415 DelayUS(60);
1416
1417 XGINew_SetReg1(P3c4, 0x18, 0x00);
1418 XGINew_SetReg1(P3c4, 0x19, 0x40);
1419 XGINew_SetReg1(P3c4, 0x16, 0x00);
1420 XGINew_SetReg1(P3c4, 0x16, 0x80);
1421 DelayUS(60);
1422 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
1423 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
1424 XGINew_SetReg1(P3c4, 0x19, 0x01);
1425 XGINew_SetReg1(P3c4, 0x16, 0x03);
1426 XGINew_SetReg1(P3c4, 0x16, 0x83);
1427 DelayUS(1000);
1428 XGINew_SetReg1(P3c4, 0x1B, 0x03);
1429 DelayUS(500);
1430 /* XGINew_SetReg1(P3c4, 0x18, 0x31); */
1431 XGINew_SetReg1(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
1432 XGINew_SetReg1(P3c4, 0x19, 0x00);
1433 XGINew_SetReg1(P3c4, 0x16, 0x03);
1434 XGINew_SetReg1(P3c4, 0x16, 0x83);
1435 XGINew_SetReg1(P3c4, 0x1B, 0x00);
1436 }
1437
1438 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1439 struct vb_device_info *pVBInfo)
1440 {
1441 unsigned short tempbx = 0, temp, tempcx, CR3CData;
1442
1443 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x32);
1444
1445 if (temp & Monitor1Sense)
1446 tempbx |= ActiveCRT1;
1447 if (temp & LCDSense)
1448 tempbx |= ActiveLCD;
1449 if (temp & Monitor2Sense)
1450 tempbx |= ActiveCRT2;
1451 if (temp & TVSense) {
1452 tempbx |= ActiveTV;
1453 if (temp & AVIDEOSense)
1454 tempbx |= (ActiveAVideo << 8);
1455 if (temp & SVIDEOSense)
1456 tempbx |= (ActiveSVideo << 8);
1457 if (temp & SCARTSense)
1458 tempbx |= (ActiveSCART << 8);
1459 if (temp & HiTVSense)
1460 tempbx |= (ActiveHiTV << 8);
1461 if (temp & YPbPrSense)
1462 tempbx |= (ActiveYPbPr << 8);
1463 }
1464
1465 tempcx = XGINew_GetReg1(pVBInfo->P3d4, 0x3d);
1466 tempcx |= (XGINew_GetReg1(pVBInfo->P3d4, 0x3e) << 8);
1467
1468 if (tempbx & tempcx) {
1469 CR3CData = XGINew_GetReg1(pVBInfo->P3d4, 0x3c);
1470 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1471 tempcx = 0x1FF0;
1472 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1473 tempbx = 0x1FF0;
1474 }
1475 } else {
1476 tempcx = 0x1FF0;
1477 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1478 tempbx = 0x1FF0;
1479 }
1480
1481 tempbx &= tempcx;
1482 XGINew_SetReg1(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1483 XGINew_SetReg1(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1484 }
1485
1486 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1487 struct vb_device_info *pVBInfo)
1488 {
1489 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1490
1491 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x3d);
1492 temp |= XGINew_GetReg1(pVBInfo->P3d4, 0x3e) << 8;
1493 temp |= (XGINew_GetReg1(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1494
1495 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1496 if (temp & ActiveCRT2)
1497 tempcl = SetCRT2ToRAMDAC;
1498 }
1499
1500 if (temp & ActiveLCD) {
1501 tempcl |= SetCRT2ToLCD;
1502 if (temp & DriverMode) {
1503 if (temp & ActiveTV) {
1504 tempch = SetToLCDA | EnableDualEdge;
1505 temp ^= SetCRT2ToLCD;
1506
1507 if ((temp >> 8) & ActiveAVideo)
1508 tempcl |= SetCRT2ToAVIDEO;
1509 if ((temp >> 8) & ActiveSVideo)
1510 tempcl |= SetCRT2ToSVIDEO;
1511 if ((temp >> 8) & ActiveSCART)
1512 tempcl |= SetCRT2ToSCART;
1513
1514 if (pVBInfo->IF_DEF_HiVision == 1) {
1515 if ((temp >> 8) & ActiveHiTV)
1516 tempcl |= SetCRT2ToHiVisionTV;
1517 }
1518
1519 if (pVBInfo->IF_DEF_YPbPr == 1) {
1520 if ((temp >> 8) & ActiveYPbPr)
1521 tempch |= SetYPbPr;
1522 }
1523 }
1524 }
1525 } else {
1526 if ((temp >> 8) & ActiveAVideo)
1527 tempcl |= SetCRT2ToAVIDEO;
1528 if ((temp >> 8) & ActiveSVideo)
1529 tempcl |= SetCRT2ToSVIDEO;
1530 if ((temp >> 8) & ActiveSCART)
1531 tempcl |= SetCRT2ToSCART;
1532
1533 if (pVBInfo->IF_DEF_HiVision == 1) {
1534 if ((temp >> 8) & ActiveHiTV)
1535 tempcl |= SetCRT2ToHiVisionTV;
1536 }
1537
1538 if (pVBInfo->IF_DEF_YPbPr == 1) {
1539 if ((temp >> 8) & ActiveYPbPr)
1540 tempch |= SetYPbPr;
1541 }
1542 }
1543
1544 tempcl |= SetSimuScanMode;
1545 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1546 || (temp & ActiveCRT2)))
1547 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1548 if ((temp & ActiveLCD) && (temp & ActiveTV))
1549 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1550 XGINew_SetReg1(pVBInfo->P3d4, 0x30, tempcl);
1551
1552 CR31Data = XGINew_GetReg1(pVBInfo->P3d4, 0x31);
1553 CR31Data &= ~(SetNotSimuMode >> 8);
1554 if (!(temp & ActiveCRT1))
1555 CR31Data |= (SetNotSimuMode >> 8);
1556 CR31Data &= ~(DisableCRT2Display >> 8);
1557 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1558 CR31Data |= (DisableCRT2Display >> 8);
1559 XGINew_SetReg1(pVBInfo->P3d4, 0x31, CR31Data);
1560
1561 CR38Data = XGINew_GetReg1(pVBInfo->P3d4, 0x38);
1562 CR38Data &= ~SetYPbPr;
1563 CR38Data |= tempch;
1564 XGINew_SetReg1(pVBInfo->P3d4, 0x38, CR38Data);
1565
1566 }
1567
1568 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1569 struct vb_device_info *pVBInfo)
1570 {
1571 unsigned char Temp;
1572 volatile unsigned char *pVideoMemory =
1573 (unsigned char *) pVBInfo->ROMAddr;
1574
1575 pVBInfo->IF_DEF_LVDS = 0;
1576
1577 #if 1
1578 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1579 pVBInfo->IF_DEF_LVDS = 1;
1580 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
1581 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS on chip */
1582 } else {
1583 #endif
1584 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* Enable GPIOA/B read */
1585 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0xC0;
1586 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1587 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1588 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
1589 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x20, 0x20); /* Enable read GPIOF */
1590 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0x04;
1591 if (!Temp)
1592 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0x80); /* TMDS on chip */
1593 else
1594 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* Only DVO on chip */
1595 XGINew_SetRegAND(pVBInfo->P3d4, 0x4A, ~0x20); /* Disable read GPIOF */
1596 }
1597 #if 1
1598 }
1599 #endif
1600 }
1601
1602 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1603 struct vb_device_info *pVBInfo)
1604 {
1605 unsigned char Temp, bCR4A;
1606
1607 pVBInfo->IF_DEF_LVDS = 0;
1608 bCR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
1609 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x07, 0x07); /* Enable GPIOA/B/C read */
1610 Temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48) & 0x07;
1611 XGINew_SetReg1(pVBInfo->P3d4, 0x4A, bCR4A);
1612
1613 if (Temp <= 0x02) {
1614 pVBInfo->IF_DEF_LVDS = 1;
1615 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS setting */
1616 XGINew_SetReg1(pVBInfo->P3d4, 0x30, 0x21);
1617 } else {
1618 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* TMDS/DVO setting */
1619 }
1620 XGINew_SetRegOR(pVBInfo->P3d4, 0x32, LCDSense);
1621
1622 }
1623
1624 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1625 {
1626 unsigned char CR38, CR4A, temp;
1627
1628 CR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
1629 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x10, 0x10); /* enable GPIOE read */
1630 CR38 = XGINew_GetReg1(pVBInfo->P3d4, 0x38);
1631 temp = 0;
1632 if ((CR38 & 0xE0) > 0x80) {
1633 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48);
1634 temp &= 0x08;
1635 temp >>= 3;
1636 }
1637
1638 XGINew_SetReg1(pVBInfo->P3d4, 0x4A, CR4A);
1639
1640 return temp;
1641 }
1642
1643 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1644 {
1645 unsigned char CR4A, temp;
1646
1647 CR4A = XGINew_GetReg1(pVBInfo->P3d4, 0x4A);
1648 XGINew_SetRegANDOR(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* enable GPIOA/B/C read */
1649 temp = XGINew_GetReg1(pVBInfo->P3d4, 0x48);
1650 if (temp <= 2)
1651 temp &= 0x03;
1652 else
1653 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1654
1655 XGINew_SetReg1(pVBInfo->P3d4, 0x4A, CR4A);
1656
1657 return temp;
1658 }
1659
Linux kernel - Deliverables
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