drivers/thermal/samsung/exynos_tmu.h

   1 /*
   2  * exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
   3  *
   4  *  Copyright (C) 2011 Samsung Electronics
   5  *  Donggeun Kim <dg77.kim@samsung.com>
   6  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #ifndef _EXYNOS_TMU_H
  24 #define _EXYNOS_TMU_H
  25 #include <linux/cpu_cooling.h>
  26
  27 #include "exynos_thermal_common.h"
  28
  29 enum calibration_type {
  30         TYPE_ONE_POINT_TRIMMING,
  31         TYPE_ONE_POINT_TRIMMING_25,
  32         TYPE_ONE_POINT_TRIMMING_85,
  33         TYPE_TWO_POINT_TRIMMING,
  34         TYPE_NONE,
  35 };
  36
  37 enum calibration_mode {
  38         SW_MODE,
  39         HW_MODE,
  40 };
  41
  42 enum soc_type {
  43         SOC_ARCH_EXYNOS4210 = 1,
  44         SOC_ARCH_EXYNOS4412,
  45         SOC_ARCH_EXYNOS5250,
  46         SOC_ARCH_EXYNOS5260,
  47         SOC_ARCH_EXYNOS5420_TRIMINFO,
  48         SOC_ARCH_EXYNOS5440,
  49 };
  50
  51 /**
  52  * EXYNOS TMU supported features.
  53  * TMU_SUPPORT_EMULATION - This features is used to set user defined
  54  *                      temperature to the TMU controller.
  55  * TMU_SUPPORT_MULTI_INST - This features denotes that the soc
  56  *                      has many instances of TMU.
  57  * TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
  58  *                      be reloaded.
  59  * TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
  60  *                      be registered for falling trips also.
  61  * TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current
  62  *                      state(active/idle) can be checked.
  63  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  64  *                      sample time.
  65  * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  66  *                      sensors shares some common registers.
  67  * TMU_SUPPORT - macro to compare the above features with the supplied.
  68  */
  69 #define TMU_SUPPORT_EMULATION                   BIT(0)
  70 #define TMU_SUPPORT_MULTI_INST                  BIT(1)
  71 #define TMU_SUPPORT_TRIM_RELOAD                 BIT(2)
  72 #define TMU_SUPPORT_FALLING_TRIP                BIT(3)
  73 #define TMU_SUPPORT_READY_STATUS                BIT(4)
  74 #define TMU_SUPPORT_EMUL_TIME                   BIT(5)
  75 #define TMU_SUPPORT_ADDRESS_MULTIPLE            BIT(6)
  76
  77 #define TMU_SUPPORTS(a, b)      (a->features & TMU_SUPPORT_ ## b)
  78
  79 /**
  80  * struct exynos_tmu_register - register descriptors to access registers and
  81  * bitfields. The register validity, offsets and bitfield values may vary
  82  * slightly across different exynos SOC's.
  83  * @triminfo_data: register containing 2 pont trimming data
  84  * @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
  85  * @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
  86  * @triminfo_ctrl: trim info controller register.
  87  * @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl
  88         reg.
  89  * @tmu_ctrl: TMU main controller register.
  90  * @test_mux_addr_shift: shift bits of test mux address.
  91  * @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
  92  * @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
  93  * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
  94  * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
  95  * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
  96  * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
  97         register.
  98  * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
  99  * @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl
 100         register.
 101  * @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl
 102         register.
 103  * @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in
 104         tmu_ctrl register.
 105  * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
 106  * @tmu_status: register drescribing the TMU status.
 107  * @tmu_cur_temp: register containing the current temperature of the TMU.
 108  * @tmu_cur_temp_shift: shift bits of current temp value in tmu_cur_temp
 109         register.
 110  * @threshold_temp: register containing the base threshold level.
 111  * @threshold_th0: Register containing first set of rising levels.
 112  * @threshold_th0_l0_shift: shift bits of level0 threshold temperature.
 113  * @threshold_th0_l1_shift: shift bits of level1 threshold temperature.
 114  * @threshold_th0_l2_shift: shift bits of level2 threshold temperature.
 115  * @threshold_th0_l3_shift: shift bits of level3 threshold temperature.
 116  * @threshold_th1: Register containing second set of rising levels.
 117  * @threshold_th1_l0_shift: shift bits of level0 threshold temperature.
 118  * @threshold_th1_l1_shift: shift bits of level1 threshold temperature.
 119  * @threshold_th1_l2_shift: shift bits of level2 threshold temperature.
 120  * @threshold_th1_l3_shift: shift bits of level3 threshold temperature.
 121  * @threshold_th2: Register containing third set of rising levels.
 122  * @threshold_th2_l0_shift: shift bits of level0 threshold temperature.
 123  * @threshold_th3: Register containing fourth set of rising levels.
 124  * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
 125  * @tmu_inten: register containing the different threshold interrupt
 126         enable bits.
 127  * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
 128  * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
 129  * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
 130  * @inten_rise3_shift: shift bits of rising 3 interrupt bits.
 131  * @inten_fall0_shift: shift bits of falling 0 interrupt bits.
 132  * @inten_fall1_shift: shift bits of falling 1 interrupt bits.
 133  * @inten_fall2_shift: shift bits of falling 2 interrupt bits.
 134  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
 135  * @tmu_intstat: Register containing the interrupt status values.
 136  * @tmu_intclear: Register for clearing the raised interrupt status.
 137  * @intclr_fall_shift: shift bits for interrupt clear fall 0
 138  * @intclr_rise_shift: shift bits of all rising interrupt bits.
 139  * @intclr_rise_mask: mask bits of all rising interrupt bits.
 140  * @intclr_fall_mask: mask bits of all rising interrupt bits.
 141  * @emul_con: TMU emulation controller register.
 142  * @emul_temp_shift: shift bits of emulation temperature.
 143  * @emul_time_shift: shift bits of emulation time.
 144  * @emul_time_mask: mask bits of emulation time.
 145  * @tmu_irqstatus: register to find which TMU generated interrupts.
 146  * @tmu_pmin: register to get/set the Pmin value.
 147  */
 148 struct exynos_tmu_registers {
 149         u32     triminfo_data;
 150         u32     triminfo_25_shift;
 151         u32     triminfo_85_shift;
 152
 153         u32     triminfo_ctrl;
 154         u32     triminfo_ctrl1;
 155         u32     triminfo_reload_shift;
 156
 157         u32     tmu_ctrl;
 158         u32     test_mux_addr_shift;
 159         u32     buf_vref_sel_shift;
 160         u32     buf_vref_sel_mask;
 161         u32     therm_trip_mode_shift;
 162         u32     therm_trip_mode_mask;
 163         u32     therm_trip_en_shift;
 164         u32     buf_slope_sel_shift;
 165         u32     buf_slope_sel_mask;
 166         u32     calib_mode_shift;
 167         u32     calib_mode_mask;
 168         u32     therm_trip_tq_en_shift;
 169         u32     core_en_shift;
 170
 171         u32     tmu_status;
 172
 173         u32     tmu_cur_temp;
 174         u32     tmu_cur_temp_shift;
 175
 176         u32     threshold_temp;
 177
 178         u32     threshold_th0;
 179         u32     threshold_th0_l0_shift;
 180         u32     threshold_th0_l1_shift;
 181         u32     threshold_th0_l2_shift;
 182         u32     threshold_th0_l3_shift;
 183
 184         u32     threshold_th1;
 185         u32     threshold_th1_l0_shift;
 186         u32     threshold_th1_l1_shift;
 187         u32     threshold_th1_l2_shift;
 188         u32     threshold_th1_l3_shift;
 189
 190         u32     threshold_th2;
 191         u32     threshold_th2_l0_shift;
 192
 193         u32     threshold_th3;
 194         u32     threshold_th3_l0_shift;
 195
 196         u32     tmu_inten;
 197         u32     inten_rise0_shift;
 198         u32     inten_rise1_shift;
 199         u32     inten_rise2_shift;
 200         u32     inten_rise3_shift;
 201         u32     inten_fall0_shift;
 202         u32     inten_fall1_shift;
 203         u32     inten_fall2_shift;
 204         u32     inten_fall3_shift;
 205
 206         u32     tmu_intstat;
 207
 208         u32     tmu_intclear;
 209         u32     intclr_fall_shift;
 210         u32     intclr_rise_shift;
 211         u32     intclr_fall_mask;
 212         u32     intclr_rise_mask;
 213
 214         u32     emul_con;
 215         u32     emul_temp_shift;
 216         u32     emul_time_shift;
 217         u32     emul_time_mask;
 218
 219         u32     tmu_irqstatus;
 220         u32     tmu_pmin;
 221 };
 222
 223 /**
 224  * struct exynos_tmu_platform_data
 225  * @threshold: basic temperature for generating interrupt
 226  *             25 <= threshold <= 125 [unit: degree Celsius]
 227  * @threshold_falling: differntial value for setting threshold
 228  *                     of temperature falling interrupt.
 229  * @trigger_levels: array for each interrupt levels
 230  *      [unit: degree Celsius]
 231  *      0: temperature for trigger_level0 interrupt
 232  *         condition for trigger_level0 interrupt:
 233  *              current temperature > threshold + trigger_levels[0]
 234  *      1: temperature for trigger_level1 interrupt
 235  *         condition for trigger_level1 interrupt:
 236  *              current temperature > threshold + trigger_levels[1]
 237  *      2: temperature for trigger_level2 interrupt
 238  *         condition for trigger_level2 interrupt:
 239  *              current temperature > threshold + trigger_levels[2]
 240  *      3: temperature for trigger_level3 interrupt
 241  *         condition for trigger_level3 interrupt:
 242  *              current temperature > threshold + trigger_levels[3]
 243  * @trigger_type: defines the type of trigger. Possible values are,
 244  *      THROTTLE_ACTIVE trigger type
 245  *      THROTTLE_PASSIVE trigger type
 246  *      SW_TRIP trigger type
 247  *      HW_TRIP
 248  * @trigger_enable[]: array to denote which trigger levels are enabled.
 249  *      1 = enable trigger_level[] interrupt,
 250  *      0 = disable trigger_level[] interrupt
 251  * @max_trigger_level: max trigger level supported by the TMU
 252  * @gain: gain of amplifier in the positive-TC generator block
 253  *      0 <= gain <= 15
 254  * @reference_voltage: reference voltage of amplifier
 255  *      in the positive-TC generator block
 256  *      0 <= reference_voltage <= 31
 257  * @noise_cancel_mode: noise cancellation mode
 258  *      000, 100, 101, 110 and 111 can be different modes
 259  * @type: determines the type of SOC
 260  * @efuse_value: platform defined fuse value
 261  * @min_efuse_value: minimum valid trimming data
 262  * @max_efuse_value: maximum valid trimming data
 263  * @first_point_trim: temp value of the first point trimming
 264  * @second_point_trim: temp value of the second point trimming
 265  * @default_temp_offset: default temperature offset in case of no trimming
 266  * @test_mux; information if SoC supports test MUX
 267  * @cal_type: calibration type for temperature
 268  * @cal_mode: calibration mode for temperature
 269  * @freq_clip_table: Table representing frequency reduction percentage.
 270  * @freq_tab_count: Count of the above table as frequency reduction may
 271  *      applicable to only some of the trigger levels.
 272  * @registers: Pointer to structure containing all the TMU controller registers
 273  *      and bitfields shifts and masks.
 274  * @features: a bitfield value indicating the features supported in SOC like
 275  *      emulation, multi instance etc
 276  *
 277  * This structure is required for configuration of exynos_tmu driver.
 278  */
 279 struct exynos_tmu_platform_data {
 280         u8 threshold;
 281         u8 threshold_falling;
 282         u8 trigger_levels[MAX_TRIP_COUNT];
 283         enum trigger_type trigger_type[MAX_TRIP_COUNT];
 284         bool trigger_enable[MAX_TRIP_COUNT];
 285         u8 max_trigger_level;
 286         u8 gain;
 287         u8 reference_voltage;
 288         u8 noise_cancel_mode;
 289
 290         u32 efuse_value;
 291         u32 min_efuse_value;
 292         u32 max_efuse_value;
 293         u8 first_point_trim;
 294         u8 second_point_trim;
 295         u8 default_temp_offset;
 296         u8 test_mux;
 297
 298         enum calibration_type cal_type;
 299         enum calibration_mode cal_mode;
 300         enum soc_type type;
 301         struct freq_clip_table freq_tab[4];
 302         unsigned int freq_tab_count;
 303         const struct exynos_tmu_registers *registers;
 304         unsigned int features;
 305 };
 306
 307 /**
 308  * struct exynos_tmu_init_data
 309  * @tmu_count: number of TMU instances.
 310  * @tmu_data: platform data of all TMU instances.
 311  * This structure is required to store data for multi-instance exynos tmu
 312  * driver.
 313  */
 314 struct exynos_tmu_init_data {
 315         int tmu_count;
 316         struct exynos_tmu_platform_data tmu_data[];
 317 };
 318
 319 #endif /* _EXYNOS_TMU_H */