drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
  29         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  30         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  31 };
  32
  33 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
  34         .tmu_data = {
  35                 {
  36                 .threshold = 80,
  37                 .trigger_levels[0] = 5,
  38                 .trigger_levels[1] = 20,
  39                 .trigger_levels[2] = 30,
  40                 .trigger_enable[0] = true,
  41                 .trigger_enable[1] = true,
  42                 .trigger_enable[2] = true,
  43                 .trigger_enable[3] = false,
  44                 .trigger_type[0] = THROTTLE_ACTIVE,
  45                 .trigger_type[1] = THROTTLE_ACTIVE,
  46                 .trigger_type[2] = SW_TRIP,
  47                 .max_trigger_level = 4,
  48                 .non_hw_trigger_levels = 3,
  49                 .gain = 15,
  50                 .reference_voltage = 7,
  51                 .cal_type = TYPE_ONE_POINT_TRIMMING,
  52                 .min_efuse_value = 40,
  53                 .max_efuse_value = 100,
  54                 .first_point_trim = 25,
  55                 .second_point_trim = 85,
  56                 .default_temp_offset = 50,
  57                 .freq_tab[0] = {
  58                         .freq_clip_max = 800 * 1000,
  59                         .temp_level = 85,
  60                         },
  61                 .freq_tab[1] = {
  62                         .freq_clip_max = 200 * 1000,
  63                         .temp_level = 100,
  64                 },
  65                 .freq_tab_count = 2,
  66                 .type = SOC_ARCH_EXYNOS4210,
  67                 .registers = &exynos4210_tmu_registers,
  68                 },
  69         },
  70         .tmu_count = 1,
  71 };
  72 #endif
  73
  74 #if defined(CONFIG_SOC_EXYNOS3250)
  75 static const struct exynos_tmu_registers exynos3250_tmu_registers = {
  76         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  77         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  78         .emul_con = EXYNOS_EMUL_CON,
  79 };
  80
  81 #define EXYNOS3250_TMU_DATA \
  82         .threshold_falling = 10, \
  83         .trigger_levels[0] = 70, \
  84         .trigger_levels[1] = 95, \
  85         .trigger_levels[2] = 110, \
  86         .trigger_levels[3] = 120, \
  87         .trigger_enable[0] = true, \
  88         .trigger_enable[1] = true, \
  89         .trigger_enable[2] = true, \
  90         .trigger_enable[3] = false, \
  91         .trigger_type[0] = THROTTLE_ACTIVE, \
  92         .trigger_type[1] = THROTTLE_ACTIVE, \
  93         .trigger_type[2] = SW_TRIP, \
  94         .trigger_type[3] = HW_TRIP, \
  95         .max_trigger_level = 4, \
  96         .non_hw_trigger_levels = 3, \
  97         .gain = 8, \
  98         .reference_voltage = 16, \
  99         .noise_cancel_mode = 4, \
 100         .cal_type = TYPE_TWO_POINT_TRIMMING, \
 101         .efuse_value = 55, \
 102         .min_efuse_value = 40, \
 103         .max_efuse_value = 100, \
 104         .first_point_trim = 25, \
 105         .second_point_trim = 85, \
 106         .default_temp_offset = 50, \
 107         .freq_tab[0] = { \
 108                 .freq_clip_max = 800 * 1000, \
 109                 .temp_level = 70, \
 110         }, \
 111         .freq_tab[1] = { \
 112                 .freq_clip_max = 400 * 1000, \
 113                 .temp_level = 95, \
 114         }, \
 115         .freq_tab_count = 2, \
 116         .registers = &exynos3250_tmu_registers, \
 117         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 118                         TMU_SUPPORT_EMUL_TIME)
 119 #endif
 120
 121 #if defined(CONFIG_SOC_EXYNOS3250)
 122 struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
 123         .tmu_data = {
 124                 {
 125                         EXYNOS3250_TMU_DATA,
 126                         .type = SOC_ARCH_EXYNOS3250,
 127                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 128                 },
 129         },
 130         .tmu_count = 1,
 131 };
 132 #endif
 133
 134 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
 135 static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 136         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 137         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 138         .emul_con = EXYNOS_EMUL_CON,
 139 };
 140
 141 #define EXYNOS4412_TMU_DATA \
 142         .threshold_falling = 10, \
 143         .trigger_levels[0] = 70, \
 144         .trigger_levels[1] = 95, \
 145         .trigger_levels[2] = 110, \
 146         .trigger_levels[3] = 120, \
 147         .trigger_enable[0] = true, \
 148         .trigger_enable[1] = true, \
 149         .trigger_enable[2] = true, \
 150         .trigger_enable[3] = false, \
 151         .trigger_type[0] = THROTTLE_ACTIVE, \
 152         .trigger_type[1] = THROTTLE_ACTIVE, \
 153         .trigger_type[2] = SW_TRIP, \
 154         .trigger_type[3] = HW_TRIP, \
 155         .max_trigger_level = 4, \
 156         .non_hw_trigger_levels = 3, \
 157         .gain = 8, \
 158         .reference_voltage = 16, \
 159         .noise_cancel_mode = 4, \
 160         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 161         .efuse_value = 55, \
 162         .min_efuse_value = 40, \
 163         .max_efuse_value = 100, \
 164         .first_point_trim = 25, \
 165         .second_point_trim = 85, \
 166         .default_temp_offset = 50, \
 167         .freq_tab[0] = { \
 168                 .freq_clip_max = 1400 * 1000, \
 169                 .temp_level = 70, \
 170         }, \
 171         .freq_tab[1] = { \
 172                 .freq_clip_max = 400 * 1000, \
 173                 .temp_level = 95, \
 174         }, \
 175         .freq_tab_count = 2, \
 176         .registers = &exynos4412_tmu_registers, \
 177         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 178                         TMU_SUPPORT_EMUL_TIME)
 179 #endif
 180
 181 #if defined(CONFIG_SOC_EXYNOS4412)
 182 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
 183         .tmu_data = {
 184                 {
 185                         EXYNOS4412_TMU_DATA,
 186                         .type = SOC_ARCH_EXYNOS4412,
 187                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 188                 },
 189         },
 190         .tmu_count = 1,
 191 };
 192 #endif
 193
 194 #if defined(CONFIG_SOC_EXYNOS5250)
 195 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 196         .tmu_data = {
 197                 {
 198                         EXYNOS4412_TMU_DATA,
 199                         .type = SOC_ARCH_EXYNOS5250,
 200                 },
 201         },
 202         .tmu_count = 1,
 203 };
 204 #endif
 205
 206 #if defined(CONFIG_SOC_EXYNOS5260)
 207 static const struct exynos_tmu_registers exynos5260_tmu_registers = {
 208         .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
 209         .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
 210         .emul_con = EXYNOS5260_EMUL_CON,
 211 };
 212
 213 #define __EXYNOS5260_TMU_DATA   \
 214         .threshold_falling = 10, \
 215         .trigger_levels[0] = 85, \
 216         .trigger_levels[1] = 103, \
 217         .trigger_levels[2] = 110, \
 218         .trigger_levels[3] = 120, \
 219         .trigger_enable[0] = true, \
 220         .trigger_enable[1] = true, \
 221         .trigger_enable[2] = true, \
 222         .trigger_enable[3] = false, \
 223         .trigger_type[0] = THROTTLE_ACTIVE, \
 224         .trigger_type[1] = THROTTLE_ACTIVE, \
 225         .trigger_type[2] = SW_TRIP, \
 226         .trigger_type[3] = HW_TRIP, \
 227         .max_trigger_level = 4, \
 228         .non_hw_trigger_levels = 3, \
 229         .gain = 8, \
 230         .reference_voltage = 16, \
 231         .noise_cancel_mode = 4, \
 232         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 233         .efuse_value = 55, \
 234         .min_efuse_value = 40, \
 235         .max_efuse_value = 100, \
 236         .first_point_trim = 25, \
 237         .second_point_trim = 85, \
 238         .default_temp_offset = 50, \
 239         .freq_tab[0] = { \
 240                 .freq_clip_max = 800 * 1000, \
 241                 .temp_level = 85, \
 242         }, \
 243         .freq_tab[1] = { \
 244                 .freq_clip_max = 200 * 1000, \
 245                 .temp_level = 103, \
 246         }, \
 247         .freq_tab_count = 2, \
 248         .registers = &exynos5260_tmu_registers, \
 249
 250 #define EXYNOS5260_TMU_DATA \
 251         __EXYNOS5260_TMU_DATA \
 252         .type = SOC_ARCH_EXYNOS5260, \
 253         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 254                         TMU_SUPPORT_EMUL_TIME)
 255
 256 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
 257         .tmu_data = {
 258                 { EXYNOS5260_TMU_DATA },
 259                 { EXYNOS5260_TMU_DATA },
 260                 { EXYNOS5260_TMU_DATA },
 261                 { EXYNOS5260_TMU_DATA },
 262                 { EXYNOS5260_TMU_DATA },
 263         },
 264         .tmu_count = 5,
 265 };
 266 #endif
 267
 268 #if defined(CONFIG_SOC_EXYNOS5420)
 269 static const struct exynos_tmu_registers exynos5420_tmu_registers = {
 270         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 271         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 272         .emul_con = EXYNOS_EMUL_CON,
 273 };
 274
 275 #define __EXYNOS5420_TMU_DATA   \
 276         .threshold_falling = 10, \
 277         .trigger_levels[0] = 85, \
 278         .trigger_levels[1] = 103, \
 279         .trigger_levels[2] = 110, \
 280         .trigger_levels[3] = 120, \
 281         .trigger_enable[0] = true, \
 282         .trigger_enable[1] = true, \
 283         .trigger_enable[2] = true, \
 284         .trigger_enable[3] = false, \
 285         .trigger_type[0] = THROTTLE_ACTIVE, \
 286         .trigger_type[1] = THROTTLE_ACTIVE, \
 287         .trigger_type[2] = SW_TRIP, \
 288         .trigger_type[3] = HW_TRIP, \
 289         .max_trigger_level = 4, \
 290         .non_hw_trigger_levels = 3, \
 291         .gain = 8, \
 292         .reference_voltage = 16, \
 293         .noise_cancel_mode = 4, \
 294         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 295         .efuse_value = 55, \
 296         .min_efuse_value = 40, \
 297         .max_efuse_value = 100, \
 298         .first_point_trim = 25, \
 299         .second_point_trim = 85, \
 300         .default_temp_offset = 50, \
 301         .freq_tab[0] = { \
 302                 .freq_clip_max = 800 * 1000, \
 303                 .temp_level = 85, \
 304         }, \
 305         .freq_tab[1] = { \
 306                 .freq_clip_max = 200 * 1000, \
 307                 .temp_level = 103, \
 308         }, \
 309         .freq_tab_count = 2, \
 310         .registers = &exynos5420_tmu_registers, \
 311
 312 #define EXYNOS5420_TMU_DATA \
 313         __EXYNOS5420_TMU_DATA \
 314         .type = SOC_ARCH_EXYNOS5420, \
 315         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 316                         TMU_SUPPORT_EMUL_TIME)
 317
 318 #define EXYNOS5420_TMU_DATA_SHARED \
 319         __EXYNOS5420_TMU_DATA \
 320         .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
 321         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 322                         TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
 323
 324 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
 325         .tmu_data = {
 326                 { EXYNOS5420_TMU_DATA },
 327                 { EXYNOS5420_TMU_DATA },
 328                 { EXYNOS5420_TMU_DATA_SHARED },
 329                 { EXYNOS5420_TMU_DATA_SHARED },
 330                 { EXYNOS5420_TMU_DATA_SHARED },
 331         },
 332         .tmu_count = 5,
 333 };
 334 #endif
 335
 336 #if defined(CONFIG_SOC_EXYNOS5440)
 337 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 338         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 339         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
 340         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 341 };
 342
 343 #define EXYNOS5440_TMU_DATA \
 344         .trigger_levels[0] = 100, \
 345         .trigger_levels[4] = 105, \
 346         .trigger_enable[0] = 1, \
 347         .trigger_type[0] = SW_TRIP, \
 348         .trigger_type[4] = HW_TRIP, \
 349         .max_trigger_level = 5, \
 350         .non_hw_trigger_levels = 1, \
 351         .gain = 5, \
 352         .reference_voltage = 16, \
 353         .noise_cancel_mode = 4, \
 354         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 355         .efuse_value = 0x5b2d, \
 356         .min_efuse_value = 16, \
 357         .max_efuse_value = 76, \
 358         .first_point_trim = 25, \
 359         .second_point_trim = 70, \
 360         .default_temp_offset = 25, \
 361         .type = SOC_ARCH_EXYNOS5440, \
 362         .registers = &exynos5440_tmu_registers, \
 363         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 364                         TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 365
 366 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 367         .tmu_data = {
 368                 { EXYNOS5440_TMU_DATA } ,
 369                 { EXYNOS5440_TMU_DATA } ,
 370                 { EXYNOS5440_TMU_DATA } ,
 371         },
 372         .tmu_count = 3,
 373 };
 374 #endif