2 * exynos_tmu_data.c - Samsung EXYNOS tmu data file
4 * Copyright (C) 2013 Samsung Electronics
5 * Amit Daniel Kachhap <amit.daniel@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include "exynos_thermal_common.h"
24 #include "exynos_tmu.h"
26 struct exynos_tmu_init_data
const exynos4210_default_tmu_data
= {
30 .trigger_levels
[0] = 5,
31 .trigger_levels
[1] = 20,
32 .trigger_levels
[2] = 30,
33 .trigger_enable
[0] = true,
34 .trigger_enable
[1] = true,
35 .trigger_enable
[2] = true,
36 .trigger_enable
[3] = false,
37 .trigger_type
[0] = THROTTLE_ACTIVE
,
38 .trigger_type
[1] = THROTTLE_ACTIVE
,
39 .trigger_type
[2] = SW_TRIP
,
40 .max_trigger_level
= 4,
41 .non_hw_trigger_levels
= 3,
43 .reference_voltage
= 7,
44 .cal_type
= TYPE_ONE_POINT_TRIMMING
,
45 .min_efuse_value
= 40,
46 .max_efuse_value
= 100,
47 .first_point_trim
= 25,
48 .second_point_trim
= 85,
49 .default_temp_offset
= 50,
51 .freq_clip_max
= 800 * 1000,
55 .freq_clip_max
= 200 * 1000,
59 .type
= SOC_ARCH_EXYNOS4210
,
65 #define EXYNOS3250_TMU_DATA \
66 .threshold_falling = 10, \
67 .trigger_levels[0] = 70, \
68 .trigger_levels[1] = 95, \
69 .trigger_levels[2] = 110, \
70 .trigger_levels[3] = 120, \
71 .trigger_enable[0] = true, \
72 .trigger_enable[1] = true, \
73 .trigger_enable[2] = true, \
74 .trigger_enable[3] = false, \
75 .trigger_type[0] = THROTTLE_ACTIVE, \
76 .trigger_type[1] = THROTTLE_ACTIVE, \
77 .trigger_type[2] = SW_TRIP, \
78 .trigger_type[3] = HW_TRIP, \
79 .max_trigger_level = 4, \
80 .non_hw_trigger_levels = 3, \
82 .reference_voltage = 16, \
83 .noise_cancel_mode = 4, \
84 .cal_type = TYPE_TWO_POINT_TRIMMING, \
86 .min_efuse_value = 40, \
87 .max_efuse_value = 100, \
88 .first_point_trim = 25, \
89 .second_point_trim = 85, \
90 .default_temp_offset = 50, \
92 .freq_clip_max = 800 * 1000, \
96 .freq_clip_max = 400 * 1000, \
101 struct exynos_tmu_init_data
const exynos3250_default_tmu_data
= {
105 .type
= SOC_ARCH_EXYNOS3250
,
111 #define EXYNOS4412_TMU_DATA \
112 .threshold_falling = 10, \
113 .trigger_levels[0] = 70, \
114 .trigger_levels[1] = 95, \
115 .trigger_levels[2] = 110, \
116 .trigger_levels[3] = 120, \
117 .trigger_enable[0] = true, \
118 .trigger_enable[1] = true, \
119 .trigger_enable[2] = true, \
120 .trigger_enable[3] = false, \
121 .trigger_type[0] = THROTTLE_ACTIVE, \
122 .trigger_type[1] = THROTTLE_ACTIVE, \
123 .trigger_type[2] = SW_TRIP, \
124 .trigger_type[3] = HW_TRIP, \
125 .max_trigger_level = 4, \
126 .non_hw_trigger_levels = 3, \
128 .reference_voltage = 16, \
129 .noise_cancel_mode = 4, \
130 .cal_type = TYPE_ONE_POINT_TRIMMING, \
132 .min_efuse_value = 40, \
133 .max_efuse_value = 100, \
134 .first_point_trim = 25, \
135 .second_point_trim = 85, \
136 .default_temp_offset = 50, \
138 .freq_clip_max = 1400 * 1000, \
142 .freq_clip_max = 400 * 1000, \
147 struct exynos_tmu_init_data
const exynos4412_default_tmu_data
= {
151 .type
= SOC_ARCH_EXYNOS4412
,
157 struct exynos_tmu_init_data
const exynos5250_default_tmu_data
= {
161 .type
= SOC_ARCH_EXYNOS5250
,
167 #define __EXYNOS5260_TMU_DATA \
168 .threshold_falling = 10, \
169 .trigger_levels[0] = 85, \
170 .trigger_levels[1] = 103, \
171 .trigger_levels[2] = 110, \
172 .trigger_levels[3] = 120, \
173 .trigger_enable[0] = true, \
174 .trigger_enable[1] = true, \
175 .trigger_enable[2] = true, \
176 .trigger_enable[3] = false, \
177 .trigger_type[0] = THROTTLE_ACTIVE, \
178 .trigger_type[1] = THROTTLE_ACTIVE, \
179 .trigger_type[2] = SW_TRIP, \
180 .trigger_type[3] = HW_TRIP, \
181 .max_trigger_level = 4, \
182 .non_hw_trigger_levels = 3, \
184 .reference_voltage = 16, \
185 .noise_cancel_mode = 4, \
186 .cal_type = TYPE_ONE_POINT_TRIMMING, \
188 .min_efuse_value = 40, \
189 .max_efuse_value = 100, \
190 .first_point_trim = 25, \
191 .second_point_trim = 85, \
192 .default_temp_offset = 50, \
194 .freq_clip_max = 800 * 1000, \
198 .freq_clip_max = 200 * 1000, \
201 .freq_tab_count = 2, \
203 #define EXYNOS5260_TMU_DATA \
204 __EXYNOS5260_TMU_DATA \
205 .type = SOC_ARCH_EXYNOS5260
207 struct exynos_tmu_init_data
const exynos5260_default_tmu_data
= {
209 { EXYNOS5260_TMU_DATA
},
210 { EXYNOS5260_TMU_DATA
},
211 { EXYNOS5260_TMU_DATA
},
212 { EXYNOS5260_TMU_DATA
},
213 { EXYNOS5260_TMU_DATA
},
218 #define EXYNOS5420_TMU_DATA \
219 __EXYNOS5260_TMU_DATA \
220 .type = SOC_ARCH_EXYNOS5420
222 #define EXYNOS5420_TMU_DATA_SHARED \
223 __EXYNOS5260_TMU_DATA \
224 .type = SOC_ARCH_EXYNOS5420_TRIMINFO
226 struct exynos_tmu_init_data
const exynos5420_default_tmu_data
= {
228 { EXYNOS5420_TMU_DATA
},
229 { EXYNOS5420_TMU_DATA
},
230 { EXYNOS5420_TMU_DATA_SHARED
},
231 { EXYNOS5420_TMU_DATA_SHARED
},
232 { EXYNOS5420_TMU_DATA_SHARED
},
237 #define EXYNOS5440_TMU_DATA \
238 .trigger_levels[0] = 100, \
239 .trigger_levels[4] = 105, \
240 .trigger_enable[0] = 1, \
241 .trigger_type[0] = SW_TRIP, \
242 .trigger_type[4] = HW_TRIP, \
243 .max_trigger_level = 5, \
244 .non_hw_trigger_levels = 1, \
246 .reference_voltage = 16, \
247 .noise_cancel_mode = 4, \
248 .cal_type = TYPE_ONE_POINT_TRIMMING, \
249 .efuse_value = 0x5b2d, \
250 .min_efuse_value = 16, \
251 .max_efuse_value = 76, \
252 .first_point_trim = 25, \
253 .second_point_trim = 70, \
254 .default_temp_offset = 25, \
255 .type = SOC_ARCH_EXYNOS5440
257 struct exynos_tmu_init_data
const exynos5440_default_tmu_data
= {
259 { EXYNOS5440_TMU_DATA
} ,
260 { EXYNOS5440_TMU_DATA
} ,
261 { EXYNOS5440_TMU_DATA
} ,