Merge branch 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
[deliverable/linux.git] / drivers / thermal / samsung / exynos_tmu_data.c
1 /*
2 * exynos_tmu_data.c - Samsung EXYNOS tmu data file
3 *
4 * Copyright (C) 2013 Samsung Electronics
5 * Amit Daniel Kachhap <amit.daniel@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23 #include "exynos_thermal_common.h"
24 #include "exynos_tmu.h"
25
26 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
27 .tmu_data = {
28 {
29 .threshold = 80,
30 .trigger_levels[0] = 5,
31 .trigger_levels[1] = 20,
32 .trigger_levels[2] = 30,
33 .trigger_enable[0] = true,
34 .trigger_enable[1] = true,
35 .trigger_enable[2] = true,
36 .trigger_enable[3] = false,
37 .trigger_type[0] = THROTTLE_ACTIVE,
38 .trigger_type[1] = THROTTLE_ACTIVE,
39 .trigger_type[2] = SW_TRIP,
40 .max_trigger_level = 4,
41 .non_hw_trigger_levels = 3,
42 .gain = 15,
43 .reference_voltage = 7,
44 .cal_type = TYPE_ONE_POINT_TRIMMING,
45 .min_efuse_value = 40,
46 .max_efuse_value = 100,
47 .first_point_trim = 25,
48 .second_point_trim = 85,
49 .default_temp_offset = 50,
50 .freq_tab[0] = {
51 .freq_clip_max = 800 * 1000,
52 .temp_level = 85,
53 },
54 .freq_tab[1] = {
55 .freq_clip_max = 200 * 1000,
56 .temp_level = 100,
57 },
58 .freq_tab_count = 2,
59 .type = SOC_ARCH_EXYNOS4210,
60 },
61 },
62 .tmu_count = 1,
63 };
64
65 #define EXYNOS3250_TMU_DATA \
66 .threshold_falling = 10, \
67 .trigger_levels[0] = 70, \
68 .trigger_levels[1] = 95, \
69 .trigger_levels[2] = 110, \
70 .trigger_levels[3] = 120, \
71 .trigger_enable[0] = true, \
72 .trigger_enable[1] = true, \
73 .trigger_enable[2] = true, \
74 .trigger_enable[3] = false, \
75 .trigger_type[0] = THROTTLE_ACTIVE, \
76 .trigger_type[1] = THROTTLE_ACTIVE, \
77 .trigger_type[2] = SW_TRIP, \
78 .trigger_type[3] = HW_TRIP, \
79 .max_trigger_level = 4, \
80 .non_hw_trigger_levels = 3, \
81 .gain = 8, \
82 .reference_voltage = 16, \
83 .noise_cancel_mode = 4, \
84 .cal_type = TYPE_TWO_POINT_TRIMMING, \
85 .efuse_value = 55, \
86 .min_efuse_value = 40, \
87 .max_efuse_value = 100, \
88 .first_point_trim = 25, \
89 .second_point_trim = 85, \
90 .default_temp_offset = 50, \
91 .freq_tab[0] = { \
92 .freq_clip_max = 800 * 1000, \
93 .temp_level = 70, \
94 }, \
95 .freq_tab[1] = { \
96 .freq_clip_max = 400 * 1000, \
97 .temp_level = 95, \
98 }, \
99 .freq_tab_count = 2
100
101 struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
102 .tmu_data = {
103 {
104 EXYNOS3250_TMU_DATA,
105 .type = SOC_ARCH_EXYNOS3250,
106 },
107 },
108 .tmu_count = 1,
109 };
110
111 #define EXYNOS4412_TMU_DATA \
112 .threshold_falling = 10, \
113 .trigger_levels[0] = 70, \
114 .trigger_levels[1] = 95, \
115 .trigger_levels[2] = 110, \
116 .trigger_levels[3] = 120, \
117 .trigger_enable[0] = true, \
118 .trigger_enable[1] = true, \
119 .trigger_enable[2] = true, \
120 .trigger_enable[3] = false, \
121 .trigger_type[0] = THROTTLE_ACTIVE, \
122 .trigger_type[1] = THROTTLE_ACTIVE, \
123 .trigger_type[2] = SW_TRIP, \
124 .trigger_type[3] = HW_TRIP, \
125 .max_trigger_level = 4, \
126 .non_hw_trigger_levels = 3, \
127 .gain = 8, \
128 .reference_voltage = 16, \
129 .noise_cancel_mode = 4, \
130 .cal_type = TYPE_ONE_POINT_TRIMMING, \
131 .efuse_value = 55, \
132 .min_efuse_value = 40, \
133 .max_efuse_value = 100, \
134 .first_point_trim = 25, \
135 .second_point_trim = 85, \
136 .default_temp_offset = 50, \
137 .freq_tab[0] = { \
138 .freq_clip_max = 1400 * 1000, \
139 .temp_level = 70, \
140 }, \
141 .freq_tab[1] = { \
142 .freq_clip_max = 400 * 1000, \
143 .temp_level = 95, \
144 }, \
145 .freq_tab_count = 2
146
147 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
148 .tmu_data = {
149 {
150 EXYNOS4412_TMU_DATA,
151 .type = SOC_ARCH_EXYNOS4412,
152 },
153 },
154 .tmu_count = 1,
155 };
156
157 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
158 .tmu_data = {
159 {
160 EXYNOS4412_TMU_DATA,
161 .type = SOC_ARCH_EXYNOS5250,
162 },
163 },
164 .tmu_count = 1,
165 };
166
167 #define __EXYNOS5260_TMU_DATA \
168 .threshold_falling = 10, \
169 .trigger_levels[0] = 85, \
170 .trigger_levels[1] = 103, \
171 .trigger_levels[2] = 110, \
172 .trigger_levels[3] = 120, \
173 .trigger_enable[0] = true, \
174 .trigger_enable[1] = true, \
175 .trigger_enable[2] = true, \
176 .trigger_enable[3] = false, \
177 .trigger_type[0] = THROTTLE_ACTIVE, \
178 .trigger_type[1] = THROTTLE_ACTIVE, \
179 .trigger_type[2] = SW_TRIP, \
180 .trigger_type[3] = HW_TRIP, \
181 .max_trigger_level = 4, \
182 .non_hw_trigger_levels = 3, \
183 .gain = 8, \
184 .reference_voltage = 16, \
185 .noise_cancel_mode = 4, \
186 .cal_type = TYPE_ONE_POINT_TRIMMING, \
187 .efuse_value = 55, \
188 .min_efuse_value = 40, \
189 .max_efuse_value = 100, \
190 .first_point_trim = 25, \
191 .second_point_trim = 85, \
192 .default_temp_offset = 50, \
193 .freq_tab[0] = { \
194 .freq_clip_max = 800 * 1000, \
195 .temp_level = 85, \
196 }, \
197 .freq_tab[1] = { \
198 .freq_clip_max = 200 * 1000, \
199 .temp_level = 103, \
200 }, \
201 .freq_tab_count = 2, \
202
203 #define EXYNOS5260_TMU_DATA \
204 __EXYNOS5260_TMU_DATA \
205 .type = SOC_ARCH_EXYNOS5260
206
207 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
208 .tmu_data = {
209 { EXYNOS5260_TMU_DATA },
210 { EXYNOS5260_TMU_DATA },
211 { EXYNOS5260_TMU_DATA },
212 { EXYNOS5260_TMU_DATA },
213 { EXYNOS5260_TMU_DATA },
214 },
215 .tmu_count = 5,
216 };
217
218 #define EXYNOS5420_TMU_DATA \
219 __EXYNOS5260_TMU_DATA \
220 .type = SOC_ARCH_EXYNOS5420
221
222 #define EXYNOS5420_TMU_DATA_SHARED \
223 __EXYNOS5260_TMU_DATA \
224 .type = SOC_ARCH_EXYNOS5420_TRIMINFO
225
226 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
227 .tmu_data = {
228 { EXYNOS5420_TMU_DATA },
229 { EXYNOS5420_TMU_DATA },
230 { EXYNOS5420_TMU_DATA_SHARED },
231 { EXYNOS5420_TMU_DATA_SHARED },
232 { EXYNOS5420_TMU_DATA_SHARED },
233 },
234 .tmu_count = 5,
235 };
236
237 #define EXYNOS5440_TMU_DATA \
238 .trigger_levels[0] = 100, \
239 .trigger_levels[4] = 105, \
240 .trigger_enable[0] = 1, \
241 .trigger_type[0] = SW_TRIP, \
242 .trigger_type[4] = HW_TRIP, \
243 .max_trigger_level = 5, \
244 .non_hw_trigger_levels = 1, \
245 .gain = 5, \
246 .reference_voltage = 16, \
247 .noise_cancel_mode = 4, \
248 .cal_type = TYPE_ONE_POINT_TRIMMING, \
249 .efuse_value = 0x5b2d, \
250 .min_efuse_value = 16, \
251 .max_efuse_value = 76, \
252 .first_point_trim = 25, \
253 .second_point_trim = 70, \
254 .default_temp_offset = 25, \
255 .type = SOC_ARCH_EXYNOS5440
256
257 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
258 .tmu_data = {
259 { EXYNOS5440_TMU_DATA } ,
260 { EXYNOS5440_TMU_DATA } ,
261 { EXYNOS5440_TMU_DATA } ,
262 },
263 .tmu_count = 3,
264 };
This page took 0.035747 seconds and 6 git commands to generate.