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tty: move drivers/serial/ to drivers/tty/serial/
[deliverable/linux.git] / drivers / tty / serial / cpm_uart / cpm_uart_core.c
1 /*
2 * linux/drivers/serial/cpm_uart.c
3 *
4 * Driver for CPM (SCC/SMC) serial ports; core driver
5 *
6 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek
7 * Based on ppc8xx.c by Thomas Gleixner
8 * Based on drivers/serial/amba.c by Russell King
9 *
10 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
11 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
12 *
13 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc.
14 * (C) 2004 Intracom, S.A.
15 * (C) 2005-2006 MontaVista Software, Inc.
16 * Vitaly Bordug <vbordug@ru.mvista.com>
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 */
33
34 #include <linux/module.h>
35 #include <linux/tty.h>
36 #include <linux/ioport.h>
37 #include <linux/init.h>
38 #include <linux/serial.h>
39 #include <linux/console.h>
40 #include <linux/sysrq.h>
41 #include <linux/device.h>
42 #include <linux/bootmem.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/fs_uart_pd.h>
45 #include <linux/of_platform.h>
46 #include <linux/gpio.h>
47 #include <linux/of_gpio.h>
48 #include <linux/clk.h>
49
50 #include <asm/io.h>
51 #include <asm/irq.h>
52 #include <asm/delay.h>
53 #include <asm/fs_pd.h>
54 #include <asm/udbg.h>
55
56 #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
57 #define SUPPORT_SYSRQ
58 #endif
59
60 #include <linux/serial_core.h>
61 #include <linux/kernel.h>
62
63 #include "cpm_uart.h"
64
65
66 /**************************************************************/
67
68 static int cpm_uart_tx_pump(struct uart_port *port);
69 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo);
70 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo);
71 static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
72
73 /**************************************************************/
74
75 #define HW_BUF_SPD_THRESHOLD 9600
76
77 /*
78 * Check, if transmit buffers are processed
79 */
80 static unsigned int cpm_uart_tx_empty(struct uart_port *port)
81 {
82 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
83 cbd_t __iomem *bdp = pinfo->tx_bd_base;
84 int ret = 0;
85
86 while (1) {
87 if (in_be16(&bdp->cbd_sc) & BD_SC_READY)
88 break;
89
90 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) {
91 ret = TIOCSER_TEMT;
92 break;
93 }
94 bdp++;
95 }
96
97 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret);
98
99 return ret;
100 }
101
102 static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
103 {
104 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
105
106 if (pinfo->gpios[GPIO_RTS] >= 0)
107 gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS));
108
109 if (pinfo->gpios[GPIO_DTR] >= 0)
110 gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR));
111 }
112
113 static unsigned int cpm_uart_get_mctrl(struct uart_port *port)
114 {
115 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
116 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
117
118 if (pinfo->gpios[GPIO_CTS] >= 0) {
119 if (gpio_get_value(pinfo->gpios[GPIO_CTS]))
120 mctrl &= ~TIOCM_CTS;
121 }
122
123 if (pinfo->gpios[GPIO_DSR] >= 0) {
124 if (gpio_get_value(pinfo->gpios[GPIO_DSR]))
125 mctrl &= ~TIOCM_DSR;
126 }
127
128 if (pinfo->gpios[GPIO_DCD] >= 0) {
129 if (gpio_get_value(pinfo->gpios[GPIO_DCD]))
130 mctrl &= ~TIOCM_CAR;
131 }
132
133 if (pinfo->gpios[GPIO_RI] >= 0) {
134 if (!gpio_get_value(pinfo->gpios[GPIO_RI]))
135 mctrl |= TIOCM_RNG;
136 }
137
138 return mctrl;
139 }
140
141 /*
142 * Stop transmitter
143 */
144 static void cpm_uart_stop_tx(struct uart_port *port)
145 {
146 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
147 smc_t __iomem *smcp = pinfo->smcp;
148 scc_t __iomem *sccp = pinfo->sccp;
149
150 pr_debug("CPM uart[%d]:stop tx\n", port->line);
151
152 if (IS_SMC(pinfo))
153 clrbits8(&smcp->smc_smcm, SMCM_TX);
154 else
155 clrbits16(&sccp->scc_sccm, UART_SCCM_TX);
156 }
157
158 /*
159 * Start transmitter
160 */
161 static void cpm_uart_start_tx(struct uart_port *port)
162 {
163 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
164 smc_t __iomem *smcp = pinfo->smcp;
165 scc_t __iomem *sccp = pinfo->sccp;
166
167 pr_debug("CPM uart[%d]:start tx\n", port->line);
168
169 if (IS_SMC(pinfo)) {
170 if (in_8(&smcp->smc_smcm) & SMCM_TX)
171 return;
172 } else {
173 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX)
174 return;
175 }
176
177 if (cpm_uart_tx_pump(port) != 0) {
178 if (IS_SMC(pinfo)) {
179 setbits8(&smcp->smc_smcm, SMCM_TX);
180 } else {
181 setbits16(&sccp->scc_sccm, UART_SCCM_TX);
182 }
183 }
184 }
185
186 /*
187 * Stop receiver
188 */
189 static void cpm_uart_stop_rx(struct uart_port *port)
190 {
191 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
192 smc_t __iomem *smcp = pinfo->smcp;
193 scc_t __iomem *sccp = pinfo->sccp;
194
195 pr_debug("CPM uart[%d]:stop rx\n", port->line);
196
197 if (IS_SMC(pinfo))
198 clrbits8(&smcp->smc_smcm, SMCM_RX);
199 else
200 clrbits16(&sccp->scc_sccm, UART_SCCM_RX);
201 }
202
203 /*
204 * Enable Modem status interrupts
205 */
206 static void cpm_uart_enable_ms(struct uart_port *port)
207 {
208 pr_debug("CPM uart[%d]:enable ms\n", port->line);
209 }
210
211 /*
212 * Generate a break.
213 */
214 static void cpm_uart_break_ctl(struct uart_port *port, int break_state)
215 {
216 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
217
218 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line,
219 break_state);
220
221 if (break_state)
222 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
223 else
224 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
225 }
226
227 /*
228 * Transmit characters, refill buffer descriptor, if possible
229 */
230 static void cpm_uart_int_tx(struct uart_port *port)
231 {
232 pr_debug("CPM uart[%d]:TX INT\n", port->line);
233
234 cpm_uart_tx_pump(port);
235 }
236
237 #ifdef CONFIG_CONSOLE_POLL
238 static int serial_polled;
239 #endif
240
241 /*
242 * Receive characters
243 */
244 static void cpm_uart_int_rx(struct uart_port *port)
245 {
246 int i;
247 unsigned char ch;
248 u8 *cp;
249 struct tty_struct *tty = port->state->port.tty;
250 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
251 cbd_t __iomem *bdp;
252 u16 status;
253 unsigned int flg;
254
255 pr_debug("CPM uart[%d]:RX INT\n", port->line);
256
257 /* Just loop through the closed BDs and copy the characters into
258 * the buffer.
259 */
260 bdp = pinfo->rx_cur;
261 for (;;) {
262 #ifdef CONFIG_CONSOLE_POLL
263 if (unlikely(serial_polled)) {
264 serial_polled = 0;
265 return;
266 }
267 #endif
268 /* get status */
269 status = in_be16(&bdp->cbd_sc);
270 /* If this one is empty, return happy */
271 if (status & BD_SC_EMPTY)
272 break;
273
274 /* get number of characters, and check spce in flip-buffer */
275 i = in_be16(&bdp->cbd_datlen);
276
277 /* If we have not enough room in tty flip buffer, then we try
278 * later, which will be the next rx-interrupt or a timeout
279 */
280 if(tty_buffer_request_room(tty, i) < i) {
281 printk(KERN_WARNING "No room in flip buffer\n");
282 return;
283 }
284
285 /* get pointer */
286 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
287
288 /* loop through the buffer */
289 while (i-- > 0) {
290 ch = *cp++;
291 port->icount.rx++;
292 flg = TTY_NORMAL;
293
294 if (status &
295 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
296 goto handle_error;
297 if (uart_handle_sysrq_char(port, ch))
298 continue;
299 #ifdef CONFIG_CONSOLE_POLL
300 if (unlikely(serial_polled)) {
301 serial_polled = 0;
302 return;
303 }
304 #endif
305 error_return:
306 tty_insert_flip_char(tty, ch, flg);
307
308 } /* End while (i--) */
309
310 /* This BD is ready to be used again. Clear status. get next */
311 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR |
312 BD_SC_OV | BD_SC_ID);
313 setbits16(&bdp->cbd_sc, BD_SC_EMPTY);
314
315 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
316 bdp = pinfo->rx_bd_base;
317 else
318 bdp++;
319
320 } /* End for (;;) */
321
322 /* Write back buffer pointer */
323 pinfo->rx_cur = bdp;
324
325 /* activate BH processing */
326 tty_flip_buffer_push(tty);
327
328 return;
329
330 /* Error processing */
331
332 handle_error:
333 /* Statistics */
334 if (status & BD_SC_BR)
335 port->icount.brk++;
336 if (status & BD_SC_PR)
337 port->icount.parity++;
338 if (status & BD_SC_FR)
339 port->icount.frame++;
340 if (status & BD_SC_OV)
341 port->icount.overrun++;
342
343 /* Mask out ignored conditions */
344 status &= port->read_status_mask;
345
346 /* Handle the remaining ones */
347 if (status & BD_SC_BR)
348 flg = TTY_BREAK;
349 else if (status & BD_SC_PR)
350 flg = TTY_PARITY;
351 else if (status & BD_SC_FR)
352 flg = TTY_FRAME;
353
354 /* overrun does not affect the current character ! */
355 if (status & BD_SC_OV) {
356 ch = 0;
357 flg = TTY_OVERRUN;
358 /* We skip this buffer */
359 /* CHECK: Is really nothing senseful there */
360 /* ASSUMPTION: it contains nothing valid */
361 i = 0;
362 }
363 #ifdef SUPPORT_SYSRQ
364 port->sysrq = 0;
365 #endif
366 goto error_return;
367 }
368
369 /*
370 * Asynchron mode interrupt handler
371 */
372 static irqreturn_t cpm_uart_int(int irq, void *data)
373 {
374 u8 events;
375 struct uart_port *port = data;
376 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
377 smc_t __iomem *smcp = pinfo->smcp;
378 scc_t __iomem *sccp = pinfo->sccp;
379
380 pr_debug("CPM uart[%d]:IRQ\n", port->line);
381
382 if (IS_SMC(pinfo)) {
383 events = in_8(&smcp->smc_smce);
384 out_8(&smcp->smc_smce, events);
385 if (events & SMCM_BRKE)
386 uart_handle_break(port);
387 if (events & SMCM_RX)
388 cpm_uart_int_rx(port);
389 if (events & SMCM_TX)
390 cpm_uart_int_tx(port);
391 } else {
392 events = in_be16(&sccp->scc_scce);
393 out_be16(&sccp->scc_scce, events);
394 if (events & UART_SCCM_BRKE)
395 uart_handle_break(port);
396 if (events & UART_SCCM_RX)
397 cpm_uart_int_rx(port);
398 if (events & UART_SCCM_TX)
399 cpm_uart_int_tx(port);
400 }
401 return (events) ? IRQ_HANDLED : IRQ_NONE;
402 }
403
404 static int cpm_uart_startup(struct uart_port *port)
405 {
406 int retval;
407 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
408
409 pr_debug("CPM uart[%d]:startup\n", port->line);
410
411 /* If the port is not the console, make sure rx is disabled. */
412 if (!(pinfo->flags & FLAG_CONSOLE)) {
413 /* Disable UART rx */
414 if (IS_SMC(pinfo)) {
415 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN);
416 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
417 } else {
418 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR);
419 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
420 }
421 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
422 }
423 /* Install interrupt handler. */
424 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port);
425 if (retval)
426 return retval;
427
428 /* Startup rx-int */
429 if (IS_SMC(pinfo)) {
430 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX);
431 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN));
432 } else {
433 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX);
434 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT));
435 }
436
437 return 0;
438 }
439
440 inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo)
441 {
442 set_current_state(TASK_UNINTERRUPTIBLE);
443 schedule_timeout(pinfo->wait_closing);
444 }
445
446 /*
447 * Shutdown the uart
448 */
449 static void cpm_uart_shutdown(struct uart_port *port)
450 {
451 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
452
453 pr_debug("CPM uart[%d]:shutdown\n", port->line);
454
455 /* free interrupt handler */
456 free_irq(port->irq, port);
457
458 /* If the port is not the console, disable Rx and Tx. */
459 if (!(pinfo->flags & FLAG_CONSOLE)) {
460 /* Wait for all the BDs marked sent */
461 while(!cpm_uart_tx_empty(port)) {
462 set_current_state(TASK_UNINTERRUPTIBLE);
463 schedule_timeout(2);
464 }
465
466 if (pinfo->wait_closing)
467 cpm_uart_wait_until_send(pinfo);
468
469 /* Stop uarts */
470 if (IS_SMC(pinfo)) {
471 smc_t __iomem *smcp = pinfo->smcp;
472 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
473 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX);
474 } else {
475 scc_t __iomem *sccp = pinfo->sccp;
476 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
477 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
478 }
479
480 /* Shut them really down and reinit buffer descriptors */
481 if (IS_SMC(pinfo)) {
482 out_be16(&pinfo->smcup->smc_brkcr, 0);
483 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
484 } else {
485 out_be16(&pinfo->sccup->scc_brkcr, 0);
486 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
487 }
488
489 cpm_uart_initbd(pinfo);
490 }
491 }
492
493 static void cpm_uart_set_termios(struct uart_port *port,
494 struct ktermios *termios,
495 struct ktermios *old)
496 {
497 int baud;
498 unsigned long flags;
499 u16 cval, scval, prev_mode;
500 int bits, sbits;
501 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
502 smc_t __iomem *smcp = pinfo->smcp;
503 scc_t __iomem *sccp = pinfo->sccp;
504
505 pr_debug("CPM uart[%d]:set_termios\n", port->line);
506
507 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
508 if (baud <= HW_BUF_SPD_THRESHOLD ||
509 (pinfo->port.state && pinfo->port.state->port.tty->low_latency))
510 pinfo->rx_fifosize = 1;
511 else
512 pinfo->rx_fifosize = RX_BUF_SIZE;
513
514 /* Character length programmed into the mode register is the
515 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
516 * 1 or 2 stop bits, minus 1.
517 * The value 'bits' counts this for us.
518 */
519 cval = 0;
520 scval = 0;
521
522 /* byte size */
523 switch (termios->c_cflag & CSIZE) {
524 case CS5:
525 bits = 5;
526 break;
527 case CS6:
528 bits = 6;
529 break;
530 case CS7:
531 bits = 7;
532 break;
533 case CS8:
534 bits = 8;
535 break;
536 /* Never happens, but GCC is too dumb to figure it out */
537 default:
538 bits = 8;
539 break;
540 }
541 sbits = bits - 5;
542
543 if (termios->c_cflag & CSTOPB) {
544 cval |= SMCMR_SL; /* Two stops */
545 scval |= SCU_PSMR_SL;
546 bits++;
547 }
548
549 if (termios->c_cflag & PARENB) {
550 cval |= SMCMR_PEN;
551 scval |= SCU_PSMR_PEN;
552 bits++;
553 if (!(termios->c_cflag & PARODD)) {
554 cval |= SMCMR_PM_EVEN;
555 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP);
556 }
557 }
558
559 /*
560 * Update the timeout
561 */
562 uart_update_timeout(port, termios->c_cflag, baud);
563
564 /*
565 * Set up parity check flag
566 */
567 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
568
569 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
570 if (termios->c_iflag & INPCK)
571 port->read_status_mask |= BD_SC_FR | BD_SC_PR;
572 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK))
573 port->read_status_mask |= BD_SC_BR;
574
575 /*
576 * Characters to ignore
577 */
578 port->ignore_status_mask = 0;
579 if (termios->c_iflag & IGNPAR)
580 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
581 if (termios->c_iflag & IGNBRK) {
582 port->ignore_status_mask |= BD_SC_BR;
583 /*
584 * If we're ignore parity and break indicators, ignore
585 * overruns too. (For real raw support).
586 */
587 if (termios->c_iflag & IGNPAR)
588 port->ignore_status_mask |= BD_SC_OV;
589 }
590 /*
591 * !!! ignore all characters if CREAD is not set
592 */
593 if ((termios->c_cflag & CREAD) == 0)
594 port->read_status_mask &= ~BD_SC_EMPTY;
595
596 spin_lock_irqsave(&port->lock, flags);
597
598 /* Start bit has not been added (so don't, because we would just
599 * subtract it later), and we need to add one for the number of
600 * stops bits (there is always at least one).
601 */
602 bits++;
603 if (IS_SMC(pinfo)) {
604 /*
605 * MRBLR can be changed while an SMC/SCC is operating only
606 * if it is done in a single bus cycle with one 16-bit move
607 * (not two 8-bit bus cycles back-to-back). This occurs when
608 * the cp shifts control to the next RxBD, so the change does
609 * not take effect immediately. To guarantee the exact RxBD
610 * on which the change occurs, change MRBLR only while the
611 * SMC/SCC receiver is disabled.
612 */
613 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize);
614
615 /* Set the mode register. We want to keep a copy of the
616 * enables, because we want to put them back if they were
617 * present.
618 */
619 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN);
620 /* Output in *one* operation, so we don't interrupt RX/TX if they
621 * were already enabled. */
622 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval |
623 SMCMR_SM_UART | prev_mode);
624 } else {
625 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
626 out_be16(&sccp->scc_psmr, (sbits << 12) | scval);
627 }
628
629 if (pinfo->clk)
630 clk_set_rate(pinfo->clk, baud);
631 else
632 cpm_set_brg(pinfo->brg - 1, baud);
633 spin_unlock_irqrestore(&port->lock, flags);
634 }
635
636 static const char *cpm_uart_type(struct uart_port *port)
637 {
638 pr_debug("CPM uart[%d]:uart_type\n", port->line);
639
640 return port->type == PORT_CPM ? "CPM UART" : NULL;
641 }
642
643 /*
644 * verify the new serial_struct (for TIOCSSERIAL).
645 */
646 static int cpm_uart_verify_port(struct uart_port *port,
647 struct serial_struct *ser)
648 {
649 int ret = 0;
650
651 pr_debug("CPM uart[%d]:verify_port\n", port->line);
652
653 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
654 ret = -EINVAL;
655 if (ser->irq < 0 || ser->irq >= nr_irqs)
656 ret = -EINVAL;
657 if (ser->baud_base < 9600)
658 ret = -EINVAL;
659 return ret;
660 }
661
662 /*
663 * Transmit characters, refill buffer descriptor, if possible
664 */
665 static int cpm_uart_tx_pump(struct uart_port *port)
666 {
667 cbd_t __iomem *bdp;
668 u8 *p;
669 int count;
670 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
671 struct circ_buf *xmit = &port->state->xmit;
672
673 /* Handle xon/xoff */
674 if (port->x_char) {
675 /* Pick next descriptor and fill from buffer */
676 bdp = pinfo->tx_cur;
677
678 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
679
680 *p++ = port->x_char;
681
682 out_be16(&bdp->cbd_datlen, 1);
683 setbits16(&bdp->cbd_sc, BD_SC_READY);
684 /* Get next BD. */
685 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
686 bdp = pinfo->tx_bd_base;
687 else
688 bdp++;
689 pinfo->tx_cur = bdp;
690
691 port->icount.tx++;
692 port->x_char = 0;
693 return 1;
694 }
695
696 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
697 cpm_uart_stop_tx(port);
698 return 0;
699 }
700
701 /* Pick next descriptor and fill from buffer */
702 bdp = pinfo->tx_cur;
703
704 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) &&
705 xmit->tail != xmit->head) {
706 count = 0;
707 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo);
708 while (count < pinfo->tx_fifosize) {
709 *p++ = xmit->buf[xmit->tail];
710 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
711 port->icount.tx++;
712 count++;
713 if (xmit->head == xmit->tail)
714 break;
715 }
716 out_be16(&bdp->cbd_datlen, count);
717 setbits16(&bdp->cbd_sc, BD_SC_READY);
718 /* Get next BD. */
719 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
720 bdp = pinfo->tx_bd_base;
721 else
722 bdp++;
723 }
724 pinfo->tx_cur = bdp;
725
726 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
727 uart_write_wakeup(port);
728
729 if (uart_circ_empty(xmit)) {
730 cpm_uart_stop_tx(port);
731 return 0;
732 }
733
734 return 1;
735 }
736
737 /*
738 * init buffer descriptors
739 */
740 static void cpm_uart_initbd(struct uart_cpm_port *pinfo)
741 {
742 int i;
743 u8 *mem_addr;
744 cbd_t __iomem *bdp;
745
746 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line);
747
748 /* Set the physical address of the host memory
749 * buffers in the buffer descriptors, and the
750 * virtual address for us to work with.
751 */
752 mem_addr = pinfo->mem_addr;
753 bdp = pinfo->rx_cur = pinfo->rx_bd_base;
754 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) {
755 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
756 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT);
757 mem_addr += pinfo->rx_fifosize;
758 }
759
760 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
761 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
762
763 /* Set the physical address of the host memory
764 * buffers in the buffer descriptors, and the
765 * virtual address for us to work with.
766 */
767 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize);
768 bdp = pinfo->tx_cur = pinfo->tx_bd_base;
769 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) {
770 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
771 out_be16(&bdp->cbd_sc, BD_SC_INTRPT);
772 mem_addr += pinfo->tx_fifosize;
773 }
774
775 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo));
776 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT);
777 }
778
779 static void cpm_uart_init_scc(struct uart_cpm_port *pinfo)
780 {
781 scc_t __iomem *scp;
782 scc_uart_t __iomem *sup;
783
784 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line);
785
786 scp = pinfo->sccp;
787 sup = pinfo->sccup;
788
789 /* Store address */
790 out_be16(&pinfo->sccup->scc_genscc.scc_rbase,
791 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
792 out_be16(&pinfo->sccup->scc_genscc.scc_tbase,
793 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
794
795 /* Set up the uart parameters in the
796 * parameter ram.
797 */
798
799 cpm_set_scc_fcr(sup);
800
801 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize);
802 out_be16(&sup->scc_maxidl, pinfo->rx_fifosize);
803 out_be16(&sup->scc_brkcr, 1);
804 out_be16(&sup->scc_parec, 0);
805 out_be16(&sup->scc_frmec, 0);
806 out_be16(&sup->scc_nosec, 0);
807 out_be16(&sup->scc_brkec, 0);
808 out_be16(&sup->scc_uaddr1, 0);
809 out_be16(&sup->scc_uaddr2, 0);
810 out_be16(&sup->scc_toseq, 0);
811 out_be16(&sup->scc_char1, 0x8000);
812 out_be16(&sup->scc_char2, 0x8000);
813 out_be16(&sup->scc_char3, 0x8000);
814 out_be16(&sup->scc_char4, 0x8000);
815 out_be16(&sup->scc_char5, 0x8000);
816 out_be16(&sup->scc_char6, 0x8000);
817 out_be16(&sup->scc_char7, 0x8000);
818 out_be16(&sup->scc_char8, 0x8000);
819 out_be16(&sup->scc_rccm, 0xc0ff);
820
821 /* Send the CPM an initialize command.
822 */
823 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
824
825 /* Set UART mode, 8 bit, no parity, one stop.
826 * Enable receive and transmit.
827 */
828 out_be32(&scp->scc_gsmrh, 0);
829 out_be32(&scp->scc_gsmrl,
830 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
831
832 /* Enable rx interrupts and clear all pending events. */
833 out_be16(&scp->scc_sccm, 0);
834 out_be16(&scp->scc_scce, 0xffff);
835 out_be16(&scp->scc_dsr, 0x7e7e);
836 out_be16(&scp->scc_psmr, 0x3000);
837
838 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
839 }
840
841 static void cpm_uart_init_smc(struct uart_cpm_port *pinfo)
842 {
843 smc_t __iomem *sp;
844 smc_uart_t __iomem *up;
845
846 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line);
847
848 sp = pinfo->smcp;
849 up = pinfo->smcup;
850
851 /* Store address */
852 out_be16(&pinfo->smcup->smc_rbase,
853 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE);
854 out_be16(&pinfo->smcup->smc_tbase,
855 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE);
856
857 /*
858 * In case SMC1 is being relocated...
859 */
860 #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
861 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase));
862 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase));
863 out_be32(&up->smc_rstate, 0);
864 out_be32(&up->smc_tstate, 0);
865 out_be16(&up->smc_brkcr, 1); /* number of break chars */
866 out_be16(&up->smc_brkec, 0);
867 #endif
868
869 /* Set up the uart parameters in the
870 * parameter ram.
871 */
872 cpm_set_smc_fcr(up);
873
874 /* Using idle character time requires some additional tuning. */
875 out_be16(&up->smc_mrblr, pinfo->rx_fifosize);
876 out_be16(&up->smc_maxidl, pinfo->rx_fifosize);
877 out_be16(&up->smc_brklen, 0);
878 out_be16(&up->smc_brkec, 0);
879 out_be16(&up->smc_brkcr, 1);
880
881 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX);
882
883 /* Set UART mode, 8 bit, no parity, one stop.
884 * Enable receive and transmit.
885 */
886 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART);
887
888 /* Enable only rx interrupts clear all pending events. */
889 out_8(&sp->smc_smcm, 0);
890 out_8(&sp->smc_smce, 0xff);
891
892 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
893 }
894
895 /*
896 * Initialize port. This is called from early_console stuff
897 * so we have to be careful here !
898 */
899 static int cpm_uart_request_port(struct uart_port *port)
900 {
901 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
902 int ret;
903
904 pr_debug("CPM uart[%d]:request port\n", port->line);
905
906 if (pinfo->flags & FLAG_CONSOLE)
907 return 0;
908
909 if (IS_SMC(pinfo)) {
910 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
911 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
912 } else {
913 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
914 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
915 }
916
917 ret = cpm_uart_allocbuf(pinfo, 0);
918
919 if (ret)
920 return ret;
921
922 cpm_uart_initbd(pinfo);
923 if (IS_SMC(pinfo))
924 cpm_uart_init_smc(pinfo);
925 else
926 cpm_uart_init_scc(pinfo);
927
928 return 0;
929 }
930
931 static void cpm_uart_release_port(struct uart_port *port)
932 {
933 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
934
935 if (!(pinfo->flags & FLAG_CONSOLE))
936 cpm_uart_freebuf(pinfo);
937 }
938
939 /*
940 * Configure/autoconfigure the port.
941 */
942 static void cpm_uart_config_port(struct uart_port *port, int flags)
943 {
944 pr_debug("CPM uart[%d]:config_port\n", port->line);
945
946 if (flags & UART_CONFIG_TYPE) {
947 port->type = PORT_CPM;
948 cpm_uart_request_port(port);
949 }
950 }
951
952 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE)
953 /*
954 * Write a string to the serial port
955 * Note that this is called with interrupts already disabled
956 */
957 static void cpm_uart_early_write(struct uart_cpm_port *pinfo,
958 const char *string, u_int count)
959 {
960 unsigned int i;
961 cbd_t __iomem *bdp, *bdbase;
962 unsigned char *cpm_outp_addr;
963
964 /* Get the address of the host memory buffer.
965 */
966 bdp = pinfo->tx_cur;
967 bdbase = pinfo->tx_bd_base;
968
969 /*
970 * Now, do each character. This is not as bad as it looks
971 * since this is a holding FIFO and not a transmitting FIFO.
972 * We could add the complexity of filling the entire transmit
973 * buffer, but we would just wait longer between accesses......
974 */
975 for (i = 0; i < count; i++, string++) {
976 /* Wait for transmitter fifo to empty.
977 * Ready indicates output is ready, and xmt is doing
978 * that, not that it is ready for us to send.
979 */
980 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
981 ;
982
983 /* Send the character out.
984 * If the buffer address is in the CPM DPRAM, don't
985 * convert it.
986 */
987 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
988 pinfo);
989 *cpm_outp_addr = *string;
990
991 out_be16(&bdp->cbd_datlen, 1);
992 setbits16(&bdp->cbd_sc, BD_SC_READY);
993
994 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
995 bdp = bdbase;
996 else
997 bdp++;
998
999 /* if a LF, also do CR... */
1000 if (*string == 10) {
1001 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1002 ;
1003
1004 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr),
1005 pinfo);
1006 *cpm_outp_addr = 13;
1007
1008 out_be16(&bdp->cbd_datlen, 1);
1009 setbits16(&bdp->cbd_sc, BD_SC_READY);
1010
1011 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP)
1012 bdp = bdbase;
1013 else
1014 bdp++;
1015 }
1016 }
1017
1018 /*
1019 * Finally, Wait for transmitter & holding register to empty
1020 * and restore the IER
1021 */
1022 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0)
1023 ;
1024
1025 pinfo->tx_cur = bdp;
1026 }
1027 #endif
1028
1029 #ifdef CONFIG_CONSOLE_POLL
1030 /* Serial polling routines for writing and reading from the uart while
1031 * in an interrupt or debug context.
1032 */
1033
1034 #define GDB_BUF_SIZE 512 /* power of 2, please */
1035
1036 static char poll_buf[GDB_BUF_SIZE];
1037 static char *pollp;
1038 static int poll_chars;
1039
1040 static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo)
1041 {
1042 u_char c, *cp;
1043 volatile cbd_t *bdp;
1044 int i;
1045
1046 /* Get the address of the host memory buffer.
1047 */
1048 bdp = pinfo->rx_cur;
1049 while (bdp->cbd_sc & BD_SC_EMPTY)
1050 ;
1051
1052 /* If the buffer address is in the CPM DPRAM, don't
1053 * convert it.
1054 */
1055 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo);
1056
1057 if (obuf) {
1058 i = c = bdp->cbd_datlen;
1059 while (i-- > 0)
1060 *obuf++ = *cp++;
1061 } else
1062 c = *cp;
1063 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID);
1064 bdp->cbd_sc |= BD_SC_EMPTY;
1065
1066 if (bdp->cbd_sc & BD_SC_WRAP)
1067 bdp = pinfo->rx_bd_base;
1068 else
1069 bdp++;
1070 pinfo->rx_cur = (cbd_t *)bdp;
1071
1072 return (int)c;
1073 }
1074
1075 static int cpm_get_poll_char(struct uart_port *port)
1076 {
1077 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1078
1079 if (!serial_polled) {
1080 serial_polled = 1;
1081 poll_chars = 0;
1082 }
1083 if (poll_chars <= 0) {
1084 poll_chars = poll_wait_key(poll_buf, pinfo);
1085 pollp = poll_buf;
1086 }
1087 poll_chars--;
1088 return *pollp++;
1089 }
1090
1091 static void cpm_put_poll_char(struct uart_port *port,
1092 unsigned char c)
1093 {
1094 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port;
1095 static char ch[2];
1096
1097 ch[0] = (char)c;
1098 cpm_uart_early_write(pinfo, ch, 1);
1099 }
1100 #endif /* CONFIG_CONSOLE_POLL */
1101
1102 static struct uart_ops cpm_uart_pops = {
1103 .tx_empty = cpm_uart_tx_empty,
1104 .set_mctrl = cpm_uart_set_mctrl,
1105 .get_mctrl = cpm_uart_get_mctrl,
1106 .stop_tx = cpm_uart_stop_tx,
1107 .start_tx = cpm_uart_start_tx,
1108 .stop_rx = cpm_uart_stop_rx,
1109 .enable_ms = cpm_uart_enable_ms,
1110 .break_ctl = cpm_uart_break_ctl,
1111 .startup = cpm_uart_startup,
1112 .shutdown = cpm_uart_shutdown,
1113 .set_termios = cpm_uart_set_termios,
1114 .type = cpm_uart_type,
1115 .release_port = cpm_uart_release_port,
1116 .request_port = cpm_uart_request_port,
1117 .config_port = cpm_uart_config_port,
1118 .verify_port = cpm_uart_verify_port,
1119 #ifdef CONFIG_CONSOLE_POLL
1120 .poll_get_char = cpm_get_poll_char,
1121 .poll_put_char = cpm_put_poll_char,
1122 #endif
1123 };
1124
1125 struct uart_cpm_port cpm_uart_ports[UART_NR];
1126
1127 static int cpm_uart_init_port(struct device_node *np,
1128 struct uart_cpm_port *pinfo)
1129 {
1130 const u32 *data;
1131 void __iomem *mem, *pram;
1132 int len;
1133 int ret;
1134 int i;
1135
1136 data = of_get_property(np, "clock", NULL);
1137 if (data) {
1138 struct clk *clk = clk_get(NULL, (const char*)data);
1139 if (!IS_ERR(clk))
1140 pinfo->clk = clk;
1141 }
1142 if (!pinfo->clk) {
1143 data = of_get_property(np, "fsl,cpm-brg", &len);
1144 if (!data || len != 4) {
1145 printk(KERN_ERR "CPM UART %s has no/invalid "
1146 "fsl,cpm-brg property.\n", np->name);
1147 return -EINVAL;
1148 }
1149 pinfo->brg = *data;
1150 }
1151
1152 data = of_get_property(np, "fsl,cpm-command", &len);
1153 if (!data || len != 4) {
1154 printk(KERN_ERR "CPM UART %s has no/invalid "
1155 "fsl,cpm-command property.\n", np->name);
1156 return -EINVAL;
1157 }
1158 pinfo->command = *data;
1159
1160 mem = of_iomap(np, 0);
1161 if (!mem)
1162 return -ENOMEM;
1163
1164 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
1165 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
1166 pinfo->sccp = mem;
1167 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
1168 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
1169 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
1170 pinfo->flags |= FLAG_SMC;
1171 pinfo->smcp = mem;
1172 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
1173 } else {
1174 ret = -ENODEV;
1175 goto out_mem;
1176 }
1177
1178 if (!pram) {
1179 ret = -ENOMEM;
1180 goto out_mem;
1181 }
1182
1183 pinfo->tx_nrfifos = TX_NUM_FIFO;
1184 pinfo->tx_fifosize = TX_BUF_SIZE;
1185 pinfo->rx_nrfifos = RX_NUM_FIFO;
1186 pinfo->rx_fifosize = RX_BUF_SIZE;
1187
1188 pinfo->port.uartclk = ppc_proc_freq;
1189 pinfo->port.mapbase = (unsigned long)mem;
1190 pinfo->port.type = PORT_CPM;
1191 pinfo->port.ops = &cpm_uart_pops,
1192 pinfo->port.iotype = UPIO_MEM;
1193 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize;
1194 spin_lock_init(&pinfo->port.lock);
1195
1196 pinfo->port.irq = of_irq_to_resource(np, 0, NULL);
1197 if (pinfo->port.irq == NO_IRQ) {
1198 ret = -EINVAL;
1199 goto out_pram;
1200 }
1201
1202 for (i = 0; i < NUM_GPIOS; i++)
1203 pinfo->gpios[i] = of_get_gpio(np, i);
1204
1205 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1206 udbg_putc = NULL;
1207 #endif
1208
1209 return cpm_uart_request_port(&pinfo->port);
1210
1211 out_pram:
1212 cpm_uart_unmap_pram(pinfo, pram);
1213 out_mem:
1214 iounmap(mem);
1215 return ret;
1216 }
1217
1218 #ifdef CONFIG_SERIAL_CPM_CONSOLE
1219 /*
1220 * Print a string to the serial port trying not to disturb
1221 * any possible real use of the port...
1222 *
1223 * Note that this is called with interrupts already disabled
1224 */
1225 static void cpm_uart_console_write(struct console *co, const char *s,
1226 u_int count)
1227 {
1228 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index];
1229 unsigned long flags;
1230 int nolock = oops_in_progress;
1231
1232 if (unlikely(nolock)) {
1233 local_irq_save(flags);
1234 } else {
1235 spin_lock_irqsave(&pinfo->port.lock, flags);
1236 }
1237
1238 cpm_uart_early_write(pinfo, s, count);
1239
1240 if (unlikely(nolock)) {
1241 local_irq_restore(flags);
1242 } else {
1243 spin_unlock_irqrestore(&pinfo->port.lock, flags);
1244 }
1245 }
1246
1247
1248 static int __init cpm_uart_console_setup(struct console *co, char *options)
1249 {
1250 int baud = 38400;
1251 int bits = 8;
1252 int parity = 'n';
1253 int flow = 'n';
1254 int ret;
1255 struct uart_cpm_port *pinfo;
1256 struct uart_port *port;
1257
1258 struct device_node *np = NULL;
1259 int i = 0;
1260
1261 if (co->index >= UART_NR) {
1262 printk(KERN_ERR "cpm_uart: console index %d too high\n",
1263 co->index);
1264 return -ENODEV;
1265 }
1266
1267 do {
1268 np = of_find_node_by_type(np, "serial");
1269 if (!np)
1270 return -ENODEV;
1271
1272 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") &&
1273 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") &&
1274 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") &&
1275 !of_device_is_compatible(np, "fsl,cpm2-scc-uart"))
1276 i--;
1277 } while (i++ != co->index);
1278
1279 pinfo = &cpm_uart_ports[co->index];
1280
1281 pinfo->flags |= FLAG_CONSOLE;
1282 port = &pinfo->port;
1283
1284 ret = cpm_uart_init_port(np, pinfo);
1285 of_node_put(np);
1286 if (ret)
1287 return ret;
1288
1289 if (options) {
1290 uart_parse_options(options, &baud, &parity, &bits, &flow);
1291 } else {
1292 if ((baud = uart_baudrate()) == -1)
1293 baud = 9600;
1294 }
1295
1296 if (IS_SMC(pinfo)) {
1297 out_be16(&pinfo->smcup->smc_brkcr, 0);
1298 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX);
1299 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX);
1300 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN);
1301 } else {
1302 out_be16(&pinfo->sccup->scc_brkcr, 0);
1303 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX);
1304 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX);
1305 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
1306 }
1307
1308 ret = cpm_uart_allocbuf(pinfo, 1);
1309
1310 if (ret)
1311 return ret;
1312
1313 cpm_uart_initbd(pinfo);
1314
1315 if (IS_SMC(pinfo))
1316 cpm_uart_init_smc(pinfo);
1317 else
1318 cpm_uart_init_scc(pinfo);
1319
1320 uart_set_options(port, co, baud, parity, bits, flow);
1321 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX);
1322
1323 return 0;
1324 }
1325
1326 static struct uart_driver cpm_reg;
1327 static struct console cpm_scc_uart_console = {
1328 .name = "ttyCPM",
1329 .write = cpm_uart_console_write,
1330 .device = uart_console_device,
1331 .setup = cpm_uart_console_setup,
1332 .flags = CON_PRINTBUFFER,
1333 .index = -1,
1334 .data = &cpm_reg,
1335 };
1336
1337 static int __init cpm_uart_console_init(void)
1338 {
1339 register_console(&cpm_scc_uart_console);
1340 return 0;
1341 }
1342
1343 console_initcall(cpm_uart_console_init);
1344
1345 #define CPM_UART_CONSOLE &cpm_scc_uart_console
1346 #else
1347 #define CPM_UART_CONSOLE NULL
1348 #endif
1349
1350 static struct uart_driver cpm_reg = {
1351 .owner = THIS_MODULE,
1352 .driver_name = "ttyCPM",
1353 .dev_name = "ttyCPM",
1354 .major = SERIAL_CPM_MAJOR,
1355 .minor = SERIAL_CPM_MINOR,
1356 .cons = CPM_UART_CONSOLE,
1357 .nr = UART_NR,
1358 };
1359
1360 static int probe_index;
1361
1362 static int __devinit cpm_uart_probe(struct platform_device *ofdev,
1363 const struct of_device_id *match)
1364 {
1365 int index = probe_index++;
1366 struct uart_cpm_port *pinfo = &cpm_uart_ports[index];
1367 int ret;
1368
1369 pinfo->port.line = index;
1370
1371 if (index >= UART_NR)
1372 return -ENODEV;
1373
1374 dev_set_drvdata(&ofdev->dev, pinfo);
1375
1376 /* initialize the device pointer for the port */
1377 pinfo->port.dev = &ofdev->dev;
1378
1379 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo);
1380 if (ret)
1381 return ret;
1382
1383 return uart_add_one_port(&cpm_reg, &pinfo->port);
1384 }
1385
1386 static int __devexit cpm_uart_remove(struct platform_device *ofdev)
1387 {
1388 struct uart_cpm_port *pinfo = dev_get_drvdata(&ofdev->dev);
1389 return uart_remove_one_port(&cpm_reg, &pinfo->port);
1390 }
1391
1392 static struct of_device_id cpm_uart_match[] = {
1393 {
1394 .compatible = "fsl,cpm1-smc-uart",
1395 },
1396 {
1397 .compatible = "fsl,cpm1-scc-uart",
1398 },
1399 {
1400 .compatible = "fsl,cpm2-smc-uart",
1401 },
1402 {
1403 .compatible = "fsl,cpm2-scc-uart",
1404 },
1405 {}
1406 };
1407
1408 static struct of_platform_driver cpm_uart_driver = {
1409 .driver = {
1410 .name = "cpm_uart",
1411 .owner = THIS_MODULE,
1412 .of_match_table = cpm_uart_match,
1413 },
1414 .probe = cpm_uart_probe,
1415 .remove = cpm_uart_remove,
1416 };
1417
1418 static int __init cpm_uart_init(void)
1419 {
1420 int ret = uart_register_driver(&cpm_reg);
1421 if (ret)
1422 return ret;
1423
1424 ret = of_register_platform_driver(&cpm_uart_driver);
1425 if (ret)
1426 uart_unregister_driver(&cpm_reg);
1427
1428 return ret;
1429 }
1430
1431 static void __exit cpm_uart_exit(void)
1432 {
1433 of_unregister_platform_driver(&cpm_uart_driver);
1434 uart_unregister_driver(&cpm_reg);
1435 }
1436
1437 module_init(cpm_uart_init);
1438 module_exit(cpm_uart_exit);
1439
1440 MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis");
1441 MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $");
1442 MODULE_LICENSE("GPL");
1443 MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR);
Linux kernel - Deliverables
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