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serial i.MX: do not depend on grouped clocks
[deliverable/linux.git] / drivers / tty / serial / imx.c
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50
51 #include <asm/io.h>
52 #include <asm/irq.h>
53 #include <mach/imx-uart.h>
54
55 /* Register definitions */
56 #define URXD0 0x0 /* Receiver Register */
57 #define URTX0 0x40 /* Transmitter Register */
58 #define UCR1 0x80 /* Control Register 1 */
59 #define UCR2 0x84 /* Control Register 2 */
60 #define UCR3 0x88 /* Control Register 3 */
61 #define UCR4 0x8c /* Control Register 4 */
62 #define UFCR 0x90 /* FIFO Control Register */
63 #define USR1 0x94 /* Status Register 1 */
64 #define USR2 0x98 /* Status Register 2 */
65 #define UESC 0x9c /* Escape Character Register */
66 #define UTIM 0xa0 /* Escape Timer Register */
67 #define UBIR 0xa4 /* BRM Incremental Register */
68 #define UBMR 0xa8 /* BRM Modulator Register */
69 #define UBRC 0xac /* Baud Rate Count Register */
70 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
71 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
72 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
73
74 /* UART Control Register Bit Fields.*/
75 #define URXD_CHARRDY (1<<15)
76 #define URXD_ERR (1<<14)
77 #define URXD_OVRRUN (1<<13)
78 #define URXD_FRMERR (1<<12)
79 #define URXD_BRK (1<<11)
80 #define URXD_PRERR (1<<10)
81 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
82 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
83 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
84 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
85 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
86 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
87 #define UCR1_IREN (1<<7) /* Infrared interface enable */
88 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
89 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
90 #define UCR1_SNDBRK (1<<4) /* Send break */
91 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
92 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
93 #define UCR1_DOZE (1<<1) /* Doze */
94 #define UCR1_UARTEN (1<<0) /* UART enabled */
95 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
96 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
97 #define UCR2_CTSC (1<<13) /* CTS pin control */
98 #define UCR2_CTS (1<<12) /* Clear to send */
99 #define UCR2_ESCEN (1<<11) /* Escape enable */
100 #define UCR2_PREN (1<<8) /* Parity enable */
101 #define UCR2_PROE (1<<7) /* Parity odd/even */
102 #define UCR2_STPB (1<<6) /* Stop */
103 #define UCR2_WS (1<<5) /* Word size */
104 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
105 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
106 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
107 #define UCR2_RXEN (1<<1) /* Receiver enabled */
108 #define UCR2_SRST (1<<0) /* SW reset */
109 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
110 #define UCR3_PARERREN (1<<12) /* Parity enable */
111 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
112 #define UCR3_DSR (1<<10) /* Data set ready */
113 #define UCR3_DCD (1<<9) /* Data carrier detect */
114 #define UCR3_RI (1<<8) /* Ring indicator */
115 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
116 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
117 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
118 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
119 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
120 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
121 #define UCR3_BPEN (1<<0) /* Preset registers enable */
122 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
123 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
124 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
125 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
126 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
127 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
128 #define UCR4_IRSC (1<<5) /* IR special case */
129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
134 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
135 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
136 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
137 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
138 #define USR1_RTSS (1<<14) /* RTS pin status */
139 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
140 #define USR1_RTSD (1<<12) /* RTS delta */
141 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
142 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
143 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
144 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
145 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
146 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
147 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
148 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
149 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
150 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
151 #define USR2_IDLE (1<<12) /* Idle condition */
152 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
153 #define USR2_WAKE (1<<7) /* Wake */
154 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
155 #define USR2_TXDC (1<<3) /* Transmitter complete */
156 #define USR2_BRCD (1<<2) /* Break condition */
157 #define USR2_ORE (1<<1) /* Overrun error */
158 #define USR2_RDR (1<<0) /* Recv data ready */
159 #define UTS_FRCPERR (1<<13) /* Force parity error */
160 #define UTS_LOOP (1<<12) /* Loop tx and rx */
161 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
162 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
163 #define UTS_TXFULL (1<<4) /* TxFIFO full */
164 #define UTS_RXFULL (1<<3) /* RxFIFO full */
165 #define UTS_SOFTRST (1<<0) /* Software reset */
166
167 /* We've been assigned a range on the "Low-density serial ports" major */
168 #define SERIAL_IMX_MAJOR 207
169 #define MINOR_START 16
170 #define DEV_NAME "ttymxc"
171 #define MAX_INTERNAL_IRQ MXC_INTERNAL_IRQS
172
173 /*
174 * This determines how often we check the modem status signals
175 * for any change. They generally aren't connected to an IRQ
176 * so we have to poll them. We also check immediately before
177 * filling the TX fifo incase CTS has been dropped.
178 */
179 #define MCTRL_TIMEOUT (250*HZ/1000)
180
181 #define DRIVER_NAME "IMX-uart"
182
183 #define UART_NR 8
184
185 /* i.mx21 type uart runs on all i.mx except i.mx1 */
186 enum imx_uart_type {
187 IMX1_UART,
188 IMX21_UART,
189 };
190
191 /* device type dependent stuff */
192 struct imx_uart_data {
193 unsigned uts_reg;
194 enum imx_uart_type devtype;
195 };
196
197 struct imx_port {
198 struct uart_port port;
199 struct timer_list timer;
200 unsigned int old_status;
201 int txirq,rxirq,rtsirq;
202 unsigned int have_rtscts:1;
203 unsigned int use_irda:1;
204 unsigned int irda_inv_rx:1;
205 unsigned int irda_inv_tx:1;
206 unsigned short trcv_delay; /* transceiver delay */
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 struct imx_uart_data *devdata;
210 };
211
212 struct imx_port_ucrs {
213 unsigned int ucr1;
214 unsigned int ucr2;
215 unsigned int ucr3;
216 };
217
218 #ifdef CONFIG_IRDA
219 #define USE_IRDA(sport) ((sport)->use_irda)
220 #else
221 #define USE_IRDA(sport) (0)
222 #endif
223
224 static struct imx_uart_data imx_uart_devdata[] = {
225 [IMX1_UART] = {
226 .uts_reg = IMX1_UTS,
227 .devtype = IMX1_UART,
228 },
229 [IMX21_UART] = {
230 .uts_reg = IMX21_UTS,
231 .devtype = IMX21_UART,
232 },
233 };
234
235 static struct platform_device_id imx_uart_devtype[] = {
236 {
237 .name = "imx1-uart",
238 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
239 }, {
240 .name = "imx21-uart",
241 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
242 }, {
243 /* sentinel */
244 }
245 };
246 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
247
248 static struct of_device_id imx_uart_dt_ids[] = {
249 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
250 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
251 { /* sentinel */ }
252 };
253 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
254
255 static inline unsigned uts_reg(struct imx_port *sport)
256 {
257 return sport->devdata->uts_reg;
258 }
259
260 static inline int is_imx1_uart(struct imx_port *sport)
261 {
262 return sport->devdata->devtype == IMX1_UART;
263 }
264
265 static inline int is_imx21_uart(struct imx_port *sport)
266 {
267 return sport->devdata->devtype == IMX21_UART;
268 }
269
270 /*
271 * Save and restore functions for UCR1, UCR2 and UCR3 registers
272 */
273 static void imx_port_ucrs_save(struct uart_port *port,
274 struct imx_port_ucrs *ucr)
275 {
276 /* save control registers */
277 ucr->ucr1 = readl(port->membase + UCR1);
278 ucr->ucr2 = readl(port->membase + UCR2);
279 ucr->ucr3 = readl(port->membase + UCR3);
280 }
281
282 static void imx_port_ucrs_restore(struct uart_port *port,
283 struct imx_port_ucrs *ucr)
284 {
285 /* restore control registers */
286 writel(ucr->ucr1, port->membase + UCR1);
287 writel(ucr->ucr2, port->membase + UCR2);
288 writel(ucr->ucr3, port->membase + UCR3);
289 }
290
291 /*
292 * Handle any change of modem status signal since we were last called.
293 */
294 static void imx_mctrl_check(struct imx_port *sport)
295 {
296 unsigned int status, changed;
297
298 status = sport->port.ops->get_mctrl(&sport->port);
299 changed = status ^ sport->old_status;
300
301 if (changed == 0)
302 return;
303
304 sport->old_status = status;
305
306 if (changed & TIOCM_RI)
307 sport->port.icount.rng++;
308 if (changed & TIOCM_DSR)
309 sport->port.icount.dsr++;
310 if (changed & TIOCM_CAR)
311 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
312 if (changed & TIOCM_CTS)
313 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
314
315 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
316 }
317
318 /*
319 * This is our per-port timeout handler, for checking the
320 * modem status signals.
321 */
322 static void imx_timeout(unsigned long data)
323 {
324 struct imx_port *sport = (struct imx_port *)data;
325 unsigned long flags;
326
327 if (sport->port.state) {
328 spin_lock_irqsave(&sport->port.lock, flags);
329 imx_mctrl_check(sport);
330 spin_unlock_irqrestore(&sport->port.lock, flags);
331
332 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
333 }
334 }
335
336 /*
337 * interrupts disabled on entry
338 */
339 static void imx_stop_tx(struct uart_port *port)
340 {
341 struct imx_port *sport = (struct imx_port *)port;
342 unsigned long temp;
343
344 if (USE_IRDA(sport)) {
345 /* half duplex - wait for end of transmission */
346 int n = 256;
347 while ((--n > 0) &&
348 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
349 udelay(5);
350 barrier();
351 }
352 /*
353 * irda transceiver - wait a bit more to avoid
354 * cutoff, hardware dependent
355 */
356 udelay(sport->trcv_delay);
357
358 /*
359 * half duplex - reactivate receive mode,
360 * flush receive pipe echo crap
361 */
362 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
363 temp = readl(sport->port.membase + UCR1);
364 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
365 writel(temp, sport->port.membase + UCR1);
366
367 temp = readl(sport->port.membase + UCR4);
368 temp &= ~(UCR4_TCEN);
369 writel(temp, sport->port.membase + UCR4);
370
371 while (readl(sport->port.membase + URXD0) &
372 URXD_CHARRDY)
373 barrier();
374
375 temp = readl(sport->port.membase + UCR1);
376 temp |= UCR1_RRDYEN;
377 writel(temp, sport->port.membase + UCR1);
378
379 temp = readl(sport->port.membase + UCR4);
380 temp |= UCR4_DREN;
381 writel(temp, sport->port.membase + UCR4);
382 }
383 return;
384 }
385
386 temp = readl(sport->port.membase + UCR1);
387 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
388 }
389
390 /*
391 * interrupts disabled on entry
392 */
393 static void imx_stop_rx(struct uart_port *port)
394 {
395 struct imx_port *sport = (struct imx_port *)port;
396 unsigned long temp;
397
398 temp = readl(sport->port.membase + UCR2);
399 writel(temp &~ UCR2_RXEN, sport->port.membase + UCR2);
400 }
401
402 /*
403 * Set the modem control timer to fire immediately.
404 */
405 static void imx_enable_ms(struct uart_port *port)
406 {
407 struct imx_port *sport = (struct imx_port *)port;
408
409 mod_timer(&sport->timer, jiffies);
410 }
411
412 static inline void imx_transmit_buffer(struct imx_port *sport)
413 {
414 struct circ_buf *xmit = &sport->port.state->xmit;
415
416 while (!uart_circ_empty(xmit) &&
417 !(readl(sport->port.membase + uts_reg(sport))
418 & UTS_TXFULL)) {
419 /* send xmit->buf[xmit->tail]
420 * out the port here */
421 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
422 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
423 sport->port.icount.tx++;
424 }
425
426 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
427 uart_write_wakeup(&sport->port);
428
429 if (uart_circ_empty(xmit))
430 imx_stop_tx(&sport->port);
431 }
432
433 /*
434 * interrupts disabled on entry
435 */
436 static void imx_start_tx(struct uart_port *port)
437 {
438 struct imx_port *sport = (struct imx_port *)port;
439 unsigned long temp;
440
441 if (USE_IRDA(sport)) {
442 /* half duplex in IrDA mode; have to disable receive mode */
443 temp = readl(sport->port.membase + UCR4);
444 temp &= ~(UCR4_DREN);
445 writel(temp, sport->port.membase + UCR4);
446
447 temp = readl(sport->port.membase + UCR1);
448 temp &= ~(UCR1_RRDYEN);
449 writel(temp, sport->port.membase + UCR1);
450 }
451
452 temp = readl(sport->port.membase + UCR1);
453 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
454
455 if (USE_IRDA(sport)) {
456 temp = readl(sport->port.membase + UCR1);
457 temp |= UCR1_TRDYEN;
458 writel(temp, sport->port.membase + UCR1);
459
460 temp = readl(sport->port.membase + UCR4);
461 temp |= UCR4_TCEN;
462 writel(temp, sport->port.membase + UCR4);
463 }
464
465 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
466 imx_transmit_buffer(sport);
467 }
468
469 static irqreturn_t imx_rtsint(int irq, void *dev_id)
470 {
471 struct imx_port *sport = dev_id;
472 unsigned int val;
473 unsigned long flags;
474
475 spin_lock_irqsave(&sport->port.lock, flags);
476
477 writel(USR1_RTSD, sport->port.membase + USR1);
478 val = readl(sport->port.membase + USR1) & USR1_RTSS;
479 uart_handle_cts_change(&sport->port, !!val);
480 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
481
482 spin_unlock_irqrestore(&sport->port.lock, flags);
483 return IRQ_HANDLED;
484 }
485
486 static irqreturn_t imx_txint(int irq, void *dev_id)
487 {
488 struct imx_port *sport = dev_id;
489 struct circ_buf *xmit = &sport->port.state->xmit;
490 unsigned long flags;
491
492 spin_lock_irqsave(&sport->port.lock,flags);
493 if (sport->port.x_char)
494 {
495 /* Send next char */
496 writel(sport->port.x_char, sport->port.membase + URTX0);
497 goto out;
498 }
499
500 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
501 imx_stop_tx(&sport->port);
502 goto out;
503 }
504
505 imx_transmit_buffer(sport);
506
507 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
508 uart_write_wakeup(&sport->port);
509
510 out:
511 spin_unlock_irqrestore(&sport->port.lock,flags);
512 return IRQ_HANDLED;
513 }
514
515 static irqreturn_t imx_rxint(int irq, void *dev_id)
516 {
517 struct imx_port *sport = dev_id;
518 unsigned int rx,flg,ignored = 0;
519 struct tty_struct *tty = sport->port.state->port.tty;
520 unsigned long flags, temp;
521
522 spin_lock_irqsave(&sport->port.lock,flags);
523
524 while (readl(sport->port.membase + USR2) & USR2_RDR) {
525 flg = TTY_NORMAL;
526 sport->port.icount.rx++;
527
528 rx = readl(sport->port.membase + URXD0);
529
530 temp = readl(sport->port.membase + USR2);
531 if (temp & USR2_BRCD) {
532 writel(USR2_BRCD, sport->port.membase + USR2);
533 if (uart_handle_break(&sport->port))
534 continue;
535 }
536
537 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
538 continue;
539
540 if (unlikely(rx & URXD_ERR)) {
541 if (rx & URXD_BRK)
542 sport->port.icount.brk++;
543 else if (rx & URXD_PRERR)
544 sport->port.icount.parity++;
545 else if (rx & URXD_FRMERR)
546 sport->port.icount.frame++;
547 if (rx & URXD_OVRRUN)
548 sport->port.icount.overrun++;
549
550 if (rx & sport->port.ignore_status_mask) {
551 if (++ignored > 100)
552 goto out;
553 continue;
554 }
555
556 rx &= sport->port.read_status_mask;
557
558 if (rx & URXD_BRK)
559 flg = TTY_BREAK;
560 else if (rx & URXD_PRERR)
561 flg = TTY_PARITY;
562 else if (rx & URXD_FRMERR)
563 flg = TTY_FRAME;
564 if (rx & URXD_OVRRUN)
565 flg = TTY_OVERRUN;
566
567 #ifdef SUPPORT_SYSRQ
568 sport->port.sysrq = 0;
569 #endif
570 }
571
572 tty_insert_flip_char(tty, rx, flg);
573 }
574
575 out:
576 spin_unlock_irqrestore(&sport->port.lock,flags);
577 tty_flip_buffer_push(tty);
578 return IRQ_HANDLED;
579 }
580
581 static irqreturn_t imx_int(int irq, void *dev_id)
582 {
583 struct imx_port *sport = dev_id;
584 unsigned int sts;
585
586 sts = readl(sport->port.membase + USR1);
587
588 if (sts & USR1_RRDY)
589 imx_rxint(irq, dev_id);
590
591 if (sts & USR1_TRDY &&
592 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
593 imx_txint(irq, dev_id);
594
595 if (sts & USR1_RTSD)
596 imx_rtsint(irq, dev_id);
597
598 if (sts & USR1_AWAKE)
599 writel(USR1_AWAKE, sport->port.membase + USR1);
600
601 return IRQ_HANDLED;
602 }
603
604 /*
605 * Return TIOCSER_TEMT when transmitter is not busy.
606 */
607 static unsigned int imx_tx_empty(struct uart_port *port)
608 {
609 struct imx_port *sport = (struct imx_port *)port;
610
611 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
612 }
613
614 /*
615 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
616 */
617 static unsigned int imx_get_mctrl(struct uart_port *port)
618 {
619 struct imx_port *sport = (struct imx_port *)port;
620 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
621
622 if (readl(sport->port.membase + USR1) & USR1_RTSS)
623 tmp |= TIOCM_CTS;
624
625 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
626 tmp |= TIOCM_RTS;
627
628 return tmp;
629 }
630
631 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
632 {
633 struct imx_port *sport = (struct imx_port *)port;
634 unsigned long temp;
635
636 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
637
638 if (mctrl & TIOCM_RTS)
639 temp |= UCR2_CTS;
640
641 writel(temp, sport->port.membase + UCR2);
642 }
643
644 /*
645 * Interrupts always disabled.
646 */
647 static void imx_break_ctl(struct uart_port *port, int break_state)
648 {
649 struct imx_port *sport = (struct imx_port *)port;
650 unsigned long flags, temp;
651
652 spin_lock_irqsave(&sport->port.lock, flags);
653
654 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
655
656 if ( break_state != 0 )
657 temp |= UCR1_SNDBRK;
658
659 writel(temp, sport->port.membase + UCR1);
660
661 spin_unlock_irqrestore(&sport->port.lock, flags);
662 }
663
664 #define TXTL 2 /* reset default */
665 #define RXTL 1 /* reset default */
666
667 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
668 {
669 unsigned int val;
670 unsigned int ufcr_rfdiv;
671
672 /* set receiver / transmitter trigger level.
673 * RFDIV is set such way to satisfy requested uartclk value
674 */
675 val = TXTL << 10 | RXTL;
676 ufcr_rfdiv = (clk_get_rate(sport->clk_per) + sport->port.uartclk / 2)
677 / sport->port.uartclk;
678
679 if(!ufcr_rfdiv)
680 ufcr_rfdiv = 1;
681
682 val |= UFCR_RFDIV_REG(ufcr_rfdiv);
683
684 writel(val, sport->port.membase + UFCR);
685
686 return 0;
687 }
688
689 /* half the RX buffer size */
690 #define CTSTL 16
691
692 static int imx_startup(struct uart_port *port)
693 {
694 struct imx_port *sport = (struct imx_port *)port;
695 int retval;
696 unsigned long flags, temp;
697
698 imx_setup_ufcr(sport, 0);
699
700 /* disable the DREN bit (Data Ready interrupt enable) before
701 * requesting IRQs
702 */
703 temp = readl(sport->port.membase + UCR4);
704
705 if (USE_IRDA(sport))
706 temp |= UCR4_IRSC;
707
708 /* set the trigger level for CTS */
709 temp &= ~(UCR4_CTSTL_MASK<< UCR4_CTSTL_SHF);
710 temp |= CTSTL<< UCR4_CTSTL_SHF;
711
712 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
713
714 if (USE_IRDA(sport)) {
715 /* reset fifo's and state machines */
716 int i = 100;
717 temp = readl(sport->port.membase + UCR2);
718 temp &= ~UCR2_SRST;
719 writel(temp, sport->port.membase + UCR2);
720 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
721 (--i > 0)) {
722 udelay(1);
723 }
724 }
725
726 /*
727 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
728 * chips only have one interrupt.
729 */
730 if (sport->txirq > 0) {
731 retval = request_irq(sport->rxirq, imx_rxint, 0,
732 DRIVER_NAME, sport);
733 if (retval)
734 goto error_out1;
735
736 retval = request_irq(sport->txirq, imx_txint, 0,
737 DRIVER_NAME, sport);
738 if (retval)
739 goto error_out2;
740
741 /* do not use RTS IRQ on IrDA */
742 if (!USE_IRDA(sport)) {
743 retval = request_irq(sport->rtsirq, imx_rtsint,
744 (sport->rtsirq < MAX_INTERNAL_IRQ) ? 0 :
745 IRQF_TRIGGER_FALLING |
746 IRQF_TRIGGER_RISING,
747 DRIVER_NAME, sport);
748 if (retval)
749 goto error_out3;
750 }
751 } else {
752 retval = request_irq(sport->port.irq, imx_int, 0,
753 DRIVER_NAME, sport);
754 if (retval) {
755 free_irq(sport->port.irq, sport);
756 goto error_out1;
757 }
758 }
759
760 /*
761 * Finally, clear and enable interrupts
762 */
763 writel(USR1_RTSD, sport->port.membase + USR1);
764
765 temp = readl(sport->port.membase + UCR1);
766 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
767
768 if (USE_IRDA(sport)) {
769 temp |= UCR1_IREN;
770 temp &= ~(UCR1_RTSDEN);
771 }
772
773 writel(temp, sport->port.membase + UCR1);
774
775 temp = readl(sport->port.membase + UCR2);
776 temp |= (UCR2_RXEN | UCR2_TXEN);
777 writel(temp, sport->port.membase + UCR2);
778
779 if (USE_IRDA(sport)) {
780 /* clear RX-FIFO */
781 int i = 64;
782 while ((--i > 0) &&
783 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
784 barrier();
785 }
786 }
787
788 if (is_imx21_uart(sport)) {
789 temp = readl(sport->port.membase + UCR3);
790 temp |= IMX21_UCR3_RXDMUXSEL;
791 writel(temp, sport->port.membase + UCR3);
792 }
793
794 if (USE_IRDA(sport)) {
795 temp = readl(sport->port.membase + UCR4);
796 if (sport->irda_inv_rx)
797 temp |= UCR4_INVR;
798 else
799 temp &= ~(UCR4_INVR);
800 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
801
802 temp = readl(sport->port.membase + UCR3);
803 if (sport->irda_inv_tx)
804 temp |= UCR3_INVT;
805 else
806 temp &= ~(UCR3_INVT);
807 writel(temp, sport->port.membase + UCR3);
808 }
809
810 /*
811 * Enable modem status interrupts
812 */
813 spin_lock_irqsave(&sport->port.lock,flags);
814 imx_enable_ms(&sport->port);
815 spin_unlock_irqrestore(&sport->port.lock,flags);
816
817 if (USE_IRDA(sport)) {
818 struct imxuart_platform_data *pdata;
819 pdata = sport->port.dev->platform_data;
820 sport->irda_inv_rx = pdata->irda_inv_rx;
821 sport->irda_inv_tx = pdata->irda_inv_tx;
822 sport->trcv_delay = pdata->transceiver_delay;
823 if (pdata->irda_enable)
824 pdata->irda_enable(1);
825 }
826
827 return 0;
828
829 error_out3:
830 if (sport->txirq)
831 free_irq(sport->txirq, sport);
832 error_out2:
833 if (sport->rxirq)
834 free_irq(sport->rxirq, sport);
835 error_out1:
836 return retval;
837 }
838
839 static void imx_shutdown(struct uart_port *port)
840 {
841 struct imx_port *sport = (struct imx_port *)port;
842 unsigned long temp;
843
844 temp = readl(sport->port.membase + UCR2);
845 temp &= ~(UCR2_TXEN);
846 writel(temp, sport->port.membase + UCR2);
847
848 if (USE_IRDA(sport)) {
849 struct imxuart_platform_data *pdata;
850 pdata = sport->port.dev->platform_data;
851 if (pdata->irda_enable)
852 pdata->irda_enable(0);
853 }
854
855 /*
856 * Stop our timer.
857 */
858 del_timer_sync(&sport->timer);
859
860 /*
861 * Free the interrupts
862 */
863 if (sport->txirq > 0) {
864 if (!USE_IRDA(sport))
865 free_irq(sport->rtsirq, sport);
866 free_irq(sport->txirq, sport);
867 free_irq(sport->rxirq, sport);
868 } else
869 free_irq(sport->port.irq, sport);
870
871 /*
872 * Disable all interrupts, port and break condition.
873 */
874
875 temp = readl(sport->port.membase + UCR1);
876 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
877 if (USE_IRDA(sport))
878 temp &= ~(UCR1_IREN);
879
880 writel(temp, sport->port.membase + UCR1);
881 }
882
883 static void
884 imx_set_termios(struct uart_port *port, struct ktermios *termios,
885 struct ktermios *old)
886 {
887 struct imx_port *sport = (struct imx_port *)port;
888 unsigned long flags;
889 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
890 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
891 unsigned int div, ufcr;
892 unsigned long num, denom;
893 uint64_t tdiv64;
894
895 /*
896 * If we don't support modem control lines, don't allow
897 * these to be set.
898 */
899 if (0) {
900 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
901 termios->c_cflag |= CLOCAL;
902 }
903
904 /*
905 * We only support CS7 and CS8.
906 */
907 while ((termios->c_cflag & CSIZE) != CS7 &&
908 (termios->c_cflag & CSIZE) != CS8) {
909 termios->c_cflag &= ~CSIZE;
910 termios->c_cflag |= old_csize;
911 old_csize = CS8;
912 }
913
914 if ((termios->c_cflag & CSIZE) == CS8)
915 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
916 else
917 ucr2 = UCR2_SRST | UCR2_IRTS;
918
919 if (termios->c_cflag & CRTSCTS) {
920 if( sport->have_rtscts ) {
921 ucr2 &= ~UCR2_IRTS;
922 ucr2 |= UCR2_CTSC;
923 } else {
924 termios->c_cflag &= ~CRTSCTS;
925 }
926 }
927
928 if (termios->c_cflag & CSTOPB)
929 ucr2 |= UCR2_STPB;
930 if (termios->c_cflag & PARENB) {
931 ucr2 |= UCR2_PREN;
932 if (termios->c_cflag & PARODD)
933 ucr2 |= UCR2_PROE;
934 }
935
936 del_timer_sync(&sport->timer);
937
938 /*
939 * Ask the core to calculate the divisor for us.
940 */
941 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
942 quot = uart_get_divisor(port, baud);
943
944 spin_lock_irqsave(&sport->port.lock, flags);
945
946 sport->port.read_status_mask = 0;
947 if (termios->c_iflag & INPCK)
948 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
949 if (termios->c_iflag & (BRKINT | PARMRK))
950 sport->port.read_status_mask |= URXD_BRK;
951
952 /*
953 * Characters to ignore
954 */
955 sport->port.ignore_status_mask = 0;
956 if (termios->c_iflag & IGNPAR)
957 sport->port.ignore_status_mask |= URXD_PRERR;
958 if (termios->c_iflag & IGNBRK) {
959 sport->port.ignore_status_mask |= URXD_BRK;
960 /*
961 * If we're ignoring parity and break indicators,
962 * ignore overruns too (for real raw support).
963 */
964 if (termios->c_iflag & IGNPAR)
965 sport->port.ignore_status_mask |= URXD_OVRRUN;
966 }
967
968 /*
969 * Update the per-port timeout.
970 */
971 uart_update_timeout(port, termios->c_cflag, baud);
972
973 /*
974 * disable interrupts and drain transmitter
975 */
976 old_ucr1 = readl(sport->port.membase + UCR1);
977 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
978 sport->port.membase + UCR1);
979
980 while ( !(readl(sport->port.membase + USR2) & USR2_TXDC))
981 barrier();
982
983 /* then, disable everything */
984 old_txrxen = readl(sport->port.membase + UCR2);
985 writel(old_txrxen & ~( UCR2_TXEN | UCR2_RXEN),
986 sport->port.membase + UCR2);
987 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
988
989 if (USE_IRDA(sport)) {
990 /*
991 * use maximum available submodule frequency to
992 * avoid missing short pulses due to low sampling rate
993 */
994 div = 1;
995 } else {
996 div = sport->port.uartclk / (baud * 16);
997 if (div > 7)
998 div = 7;
999 if (!div)
1000 div = 1;
1001 }
1002
1003 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1004 1 << 16, 1 << 16, &num, &denom);
1005
1006 tdiv64 = sport->port.uartclk;
1007 tdiv64 *= num;
1008 do_div(tdiv64, denom * 16 * div);
1009 tty_termios_encode_baud_rate(termios,
1010 (speed_t)tdiv64, (speed_t)tdiv64);
1011
1012 num -= 1;
1013 denom -= 1;
1014
1015 ufcr = readl(sport->port.membase + UFCR);
1016 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1017 writel(ufcr, sport->port.membase + UFCR);
1018
1019 writel(num, sport->port.membase + UBIR);
1020 writel(denom, sport->port.membase + UBMR);
1021
1022 if (is_imx21_uart(sport))
1023 writel(sport->port.uartclk / div / 1000,
1024 sport->port.membase + IMX21_ONEMS);
1025
1026 writel(old_ucr1, sport->port.membase + UCR1);
1027
1028 /* set the parity, stop bits and data size */
1029 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1030
1031 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1032 imx_enable_ms(&sport->port);
1033
1034 spin_unlock_irqrestore(&sport->port.lock, flags);
1035 }
1036
1037 static const char *imx_type(struct uart_port *port)
1038 {
1039 struct imx_port *sport = (struct imx_port *)port;
1040
1041 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1042 }
1043
1044 /*
1045 * Release the memory region(s) being used by 'port'.
1046 */
1047 static void imx_release_port(struct uart_port *port)
1048 {
1049 struct platform_device *pdev = to_platform_device(port->dev);
1050 struct resource *mmres;
1051
1052 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1053 release_mem_region(mmres->start, resource_size(mmres));
1054 }
1055
1056 /*
1057 * Request the memory region(s) being used by 'port'.
1058 */
1059 static int imx_request_port(struct uart_port *port)
1060 {
1061 struct platform_device *pdev = to_platform_device(port->dev);
1062 struct resource *mmres;
1063 void *ret;
1064
1065 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1066 if (!mmres)
1067 return -ENODEV;
1068
1069 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1070
1071 return ret ? 0 : -EBUSY;
1072 }
1073
1074 /*
1075 * Configure/autoconfigure the port.
1076 */
1077 static void imx_config_port(struct uart_port *port, int flags)
1078 {
1079 struct imx_port *sport = (struct imx_port *)port;
1080
1081 if (flags & UART_CONFIG_TYPE &&
1082 imx_request_port(&sport->port) == 0)
1083 sport->port.type = PORT_IMX;
1084 }
1085
1086 /*
1087 * Verify the new serial_struct (for TIOCSSERIAL).
1088 * The only change we allow are to the flags and type, and
1089 * even then only between PORT_IMX and PORT_UNKNOWN
1090 */
1091 static int
1092 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1093 {
1094 struct imx_port *sport = (struct imx_port *)port;
1095 int ret = 0;
1096
1097 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1098 ret = -EINVAL;
1099 if (sport->port.irq != ser->irq)
1100 ret = -EINVAL;
1101 if (ser->io_type != UPIO_MEM)
1102 ret = -EINVAL;
1103 if (sport->port.uartclk / 16 != ser->baud_base)
1104 ret = -EINVAL;
1105 if ((void *)sport->port.mapbase != ser->iomem_base)
1106 ret = -EINVAL;
1107 if (sport->port.iobase != ser->port)
1108 ret = -EINVAL;
1109 if (ser->hub6 != 0)
1110 ret = -EINVAL;
1111 return ret;
1112 }
1113
1114 #if defined(CONFIG_CONSOLE_POLL)
1115 static int imx_poll_get_char(struct uart_port *port)
1116 {
1117 struct imx_port_ucrs old_ucr;
1118 unsigned int status;
1119 unsigned char c;
1120
1121 /* save control registers */
1122 imx_port_ucrs_save(port, &old_ucr);
1123
1124 /* disable interrupts */
1125 writel(UCR1_UARTEN, port->membase + UCR1);
1126 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1127 port->membase + UCR2);
1128 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1129 port->membase + UCR3);
1130
1131 /* poll */
1132 do {
1133 status = readl(port->membase + USR2);
1134 } while (~status & USR2_RDR);
1135
1136 /* read */
1137 c = readl(port->membase + URXD0);
1138
1139 /* restore control registers */
1140 imx_port_ucrs_restore(port, &old_ucr);
1141
1142 return c;
1143 }
1144
1145 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1146 {
1147 struct imx_port_ucrs old_ucr;
1148 unsigned int status;
1149
1150 /* save control registers */
1151 imx_port_ucrs_save(port, &old_ucr);
1152
1153 /* disable interrupts */
1154 writel(UCR1_UARTEN, port->membase + UCR1);
1155 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1156 port->membase + UCR2);
1157 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1158 port->membase + UCR3);
1159
1160 /* drain */
1161 do {
1162 status = readl(port->membase + USR1);
1163 } while (~status & USR1_TRDY);
1164
1165 /* write */
1166 writel(c, port->membase + URTX0);
1167
1168 /* flush */
1169 do {
1170 status = readl(port->membase + USR2);
1171 } while (~status & USR2_TXDC);
1172
1173 /* restore control registers */
1174 imx_port_ucrs_restore(port, &old_ucr);
1175 }
1176 #endif
1177
1178 static struct uart_ops imx_pops = {
1179 .tx_empty = imx_tx_empty,
1180 .set_mctrl = imx_set_mctrl,
1181 .get_mctrl = imx_get_mctrl,
1182 .stop_tx = imx_stop_tx,
1183 .start_tx = imx_start_tx,
1184 .stop_rx = imx_stop_rx,
1185 .enable_ms = imx_enable_ms,
1186 .break_ctl = imx_break_ctl,
1187 .startup = imx_startup,
1188 .shutdown = imx_shutdown,
1189 .set_termios = imx_set_termios,
1190 .type = imx_type,
1191 .release_port = imx_release_port,
1192 .request_port = imx_request_port,
1193 .config_port = imx_config_port,
1194 .verify_port = imx_verify_port,
1195 #if defined(CONFIG_CONSOLE_POLL)
1196 .poll_get_char = imx_poll_get_char,
1197 .poll_put_char = imx_poll_put_char,
1198 #endif
1199 };
1200
1201 static struct imx_port *imx_ports[UART_NR];
1202
1203 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1204 static void imx_console_putchar(struct uart_port *port, int ch)
1205 {
1206 struct imx_port *sport = (struct imx_port *)port;
1207
1208 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1209 barrier();
1210
1211 writel(ch, sport->port.membase + URTX0);
1212 }
1213
1214 /*
1215 * Interrupts are disabled on entering
1216 */
1217 static void
1218 imx_console_write(struct console *co, const char *s, unsigned int count)
1219 {
1220 struct imx_port *sport = imx_ports[co->index];
1221 struct imx_port_ucrs old_ucr;
1222 unsigned int ucr1;
1223
1224 /*
1225 * First, save UCR1/2/3 and then disable interrupts
1226 */
1227 imx_port_ucrs_save(&sport->port, &old_ucr);
1228 ucr1 = old_ucr.ucr1;
1229
1230 if (is_imx1_uart(sport))
1231 ucr1 |= IMX1_UCR1_UARTCLKEN;
1232 ucr1 |= UCR1_UARTEN;
1233 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1234
1235 writel(ucr1, sport->port.membase + UCR1);
1236
1237 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1238
1239 uart_console_write(&sport->port, s, count, imx_console_putchar);
1240
1241 /*
1242 * Finally, wait for transmitter to become empty
1243 * and restore UCR1/2/3
1244 */
1245 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1246
1247 imx_port_ucrs_restore(&sport->port, &old_ucr);
1248 }
1249
1250 /*
1251 * If the port was already initialised (eg, by a boot loader),
1252 * try to determine the current setup.
1253 */
1254 static void __init
1255 imx_console_get_options(struct imx_port *sport, int *baud,
1256 int *parity, int *bits)
1257 {
1258
1259 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1260 /* ok, the port was enabled */
1261 unsigned int ucr2, ubir,ubmr, uartclk;
1262 unsigned int baud_raw;
1263 unsigned int ucfr_rfdiv;
1264
1265 ucr2 = readl(sport->port.membase + UCR2);
1266
1267 *parity = 'n';
1268 if (ucr2 & UCR2_PREN) {
1269 if (ucr2 & UCR2_PROE)
1270 *parity = 'o';
1271 else
1272 *parity = 'e';
1273 }
1274
1275 if (ucr2 & UCR2_WS)
1276 *bits = 8;
1277 else
1278 *bits = 7;
1279
1280 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1281 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1282
1283 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1284 if (ucfr_rfdiv == 6)
1285 ucfr_rfdiv = 7;
1286 else
1287 ucfr_rfdiv = 6 - ucfr_rfdiv;
1288
1289 uartclk = clk_get_rate(sport->clk_per);
1290 uartclk /= ucfr_rfdiv;
1291
1292 { /*
1293 * The next code provides exact computation of
1294 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1295 * without need of float support or long long division,
1296 * which would be required to prevent 32bit arithmetic overflow
1297 */
1298 unsigned int mul = ubir + 1;
1299 unsigned int div = 16 * (ubmr + 1);
1300 unsigned int rem = uartclk % div;
1301
1302 baud_raw = (uartclk / div) * mul;
1303 baud_raw += (rem * mul + div / 2) / div;
1304 *baud = (baud_raw + 50) / 100 * 100;
1305 }
1306
1307 if(*baud != baud_raw)
1308 printk(KERN_INFO "Serial: Console IMX rounded baud rate from %d to %d\n",
1309 baud_raw, *baud);
1310 }
1311 }
1312
1313 static int __init
1314 imx_console_setup(struct console *co, char *options)
1315 {
1316 struct imx_port *sport;
1317 int baud = 9600;
1318 int bits = 8;
1319 int parity = 'n';
1320 int flow = 'n';
1321
1322 /*
1323 * Check whether an invalid uart number has been specified, and
1324 * if so, search for the first available port that does have
1325 * console support.
1326 */
1327 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1328 co->index = 0;
1329 sport = imx_ports[co->index];
1330 if(sport == NULL)
1331 return -ENODEV;
1332
1333 if (options)
1334 uart_parse_options(options, &baud, &parity, &bits, &flow);
1335 else
1336 imx_console_get_options(sport, &baud, &parity, &bits);
1337
1338 imx_setup_ufcr(sport, 0);
1339
1340 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1341 }
1342
1343 static struct uart_driver imx_reg;
1344 static struct console imx_console = {
1345 .name = DEV_NAME,
1346 .write = imx_console_write,
1347 .device = uart_console_device,
1348 .setup = imx_console_setup,
1349 .flags = CON_PRINTBUFFER,
1350 .index = -1,
1351 .data = &imx_reg,
1352 };
1353
1354 #define IMX_CONSOLE &imx_console
1355 #else
1356 #define IMX_CONSOLE NULL
1357 #endif
1358
1359 static struct uart_driver imx_reg = {
1360 .owner = THIS_MODULE,
1361 .driver_name = DRIVER_NAME,
1362 .dev_name = DEV_NAME,
1363 .major = SERIAL_IMX_MAJOR,
1364 .minor = MINOR_START,
1365 .nr = ARRAY_SIZE(imx_ports),
1366 .cons = IMX_CONSOLE,
1367 };
1368
1369 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1370 {
1371 struct imx_port *sport = platform_get_drvdata(dev);
1372 unsigned int val;
1373
1374 /* enable wakeup from i.MX UART */
1375 val = readl(sport->port.membase + UCR3);
1376 val |= UCR3_AWAKEN;
1377 writel(val, sport->port.membase + UCR3);
1378
1379 if (sport)
1380 uart_suspend_port(&imx_reg, &sport->port);
1381
1382 return 0;
1383 }
1384
1385 static int serial_imx_resume(struct platform_device *dev)
1386 {
1387 struct imx_port *sport = platform_get_drvdata(dev);
1388 unsigned int val;
1389
1390 /* disable wakeup from i.MX UART */
1391 val = readl(sport->port.membase + UCR3);
1392 val &= ~UCR3_AWAKEN;
1393 writel(val, sport->port.membase + UCR3);
1394
1395 if (sport)
1396 uart_resume_port(&imx_reg, &sport->port);
1397
1398 return 0;
1399 }
1400
1401 #ifdef CONFIG_OF
1402 /*
1403 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1404 * could successfully get all information from dt or a negative errno.
1405 */
1406 static int serial_imx_probe_dt(struct imx_port *sport,
1407 struct platform_device *pdev)
1408 {
1409 struct device_node *np = pdev->dev.of_node;
1410 const struct of_device_id *of_id =
1411 of_match_device(imx_uart_dt_ids, &pdev->dev);
1412 int ret;
1413
1414 if (!np)
1415 /* no device tree device */
1416 return 1;
1417
1418 ret = of_alias_get_id(np, "serial");
1419 if (ret < 0) {
1420 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1421 return ret;
1422 }
1423 sport->port.line = ret;
1424
1425 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1426 sport->have_rtscts = 1;
1427
1428 if (of_get_property(np, "fsl,irda-mode", NULL))
1429 sport->use_irda = 1;
1430
1431 sport->devdata = of_id->data;
1432
1433 return 0;
1434 }
1435 #else
1436 static inline int serial_imx_probe_dt(struct imx_port *sport,
1437 struct platform_device *pdev)
1438 {
1439 return 1;
1440 }
1441 #endif
1442
1443 static void serial_imx_probe_pdata(struct imx_port *sport,
1444 struct platform_device *pdev)
1445 {
1446 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1447
1448 sport->port.line = pdev->id;
1449 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1450
1451 if (!pdata)
1452 return;
1453
1454 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1455 sport->have_rtscts = 1;
1456
1457 if (pdata->flags & IMXUART_IRDA)
1458 sport->use_irda = 1;
1459 }
1460
1461 static int serial_imx_probe(struct platform_device *pdev)
1462 {
1463 struct imx_port *sport;
1464 struct imxuart_platform_data *pdata;
1465 void __iomem *base;
1466 int ret = 0;
1467 struct resource *res;
1468
1469 sport = kzalloc(sizeof(*sport), GFP_KERNEL);
1470 if (!sport)
1471 return -ENOMEM;
1472
1473 ret = serial_imx_probe_dt(sport, pdev);
1474 if (ret > 0)
1475 serial_imx_probe_pdata(sport, pdev);
1476 else if (ret < 0)
1477 goto free;
1478
1479 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1480 if (!res) {
1481 ret = -ENODEV;
1482 goto free;
1483 }
1484
1485 base = ioremap(res->start, PAGE_SIZE);
1486 if (!base) {
1487 ret = -ENOMEM;
1488 goto free;
1489 }
1490
1491 sport->port.dev = &pdev->dev;
1492 sport->port.mapbase = res->start;
1493 sport->port.membase = base;
1494 sport->port.type = PORT_IMX,
1495 sport->port.iotype = UPIO_MEM;
1496 sport->port.irq = platform_get_irq(pdev, 0);
1497 sport->rxirq = platform_get_irq(pdev, 0);
1498 sport->txirq = platform_get_irq(pdev, 1);
1499 sport->rtsirq = platform_get_irq(pdev, 2);
1500 sport->port.fifosize = 32;
1501 sport->port.ops = &imx_pops;
1502 sport->port.flags = UPF_BOOT_AUTOCONF;
1503 init_timer(&sport->timer);
1504 sport->timer.function = imx_timeout;
1505 sport->timer.data = (unsigned long)sport;
1506
1507 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1508 if (IS_ERR(sport->clk_ipg)) {
1509 ret = PTR_ERR(sport->clk_ipg);
1510 goto unmap;
1511 }
1512
1513 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1514 if (IS_ERR(sport->clk_per)) {
1515 ret = PTR_ERR(sport->clk_per);
1516 goto unmap;
1517 }
1518
1519 clk_prepare_enable(sport->clk_per);
1520 clk_prepare_enable(sport->clk_ipg);
1521
1522 sport->port.uartclk = clk_get_rate(sport->clk_per);
1523
1524 imx_ports[sport->port.line] = sport;
1525
1526 pdata = pdev->dev.platform_data;
1527 if (pdata && pdata->init) {
1528 ret = pdata->init(pdev);
1529 if (ret)
1530 goto clkput;
1531 }
1532
1533 ret = uart_add_one_port(&imx_reg, &sport->port);
1534 if (ret)
1535 goto deinit;
1536 platform_set_drvdata(pdev, &sport->port);
1537
1538 return 0;
1539 deinit:
1540 if (pdata && pdata->exit)
1541 pdata->exit(pdev);
1542 clkput:
1543 clk_disable_unprepare(sport->clk_per);
1544 clk_disable_unprepare(sport->clk_ipg);
1545 unmap:
1546 iounmap(sport->port.membase);
1547 free:
1548 kfree(sport);
1549
1550 return ret;
1551 }
1552
1553 static int serial_imx_remove(struct platform_device *pdev)
1554 {
1555 struct imxuart_platform_data *pdata;
1556 struct imx_port *sport = platform_get_drvdata(pdev);
1557
1558 pdata = pdev->dev.platform_data;
1559
1560 platform_set_drvdata(pdev, NULL);
1561
1562 uart_remove_one_port(&imx_reg, &sport->port);
1563
1564 clk_disable_unprepare(sport->clk_per);
1565 clk_disable_unprepare(sport->clk_ipg);
1566
1567 if (pdata && pdata->exit)
1568 pdata->exit(pdev);
1569
1570 iounmap(sport->port.membase);
1571 kfree(sport);
1572
1573 return 0;
1574 }
1575
1576 static struct platform_driver serial_imx_driver = {
1577 .probe = serial_imx_probe,
1578 .remove = serial_imx_remove,
1579
1580 .suspend = serial_imx_suspend,
1581 .resume = serial_imx_resume,
1582 .id_table = imx_uart_devtype,
1583 .driver = {
1584 .name = "imx-uart",
1585 .owner = THIS_MODULE,
1586 .of_match_table = imx_uart_dt_ids,
1587 },
1588 };
1589
1590 static int __init imx_serial_init(void)
1591 {
1592 int ret;
1593
1594 printk(KERN_INFO "Serial: IMX driver\n");
1595
1596 ret = uart_register_driver(&imx_reg);
1597 if (ret)
1598 return ret;
1599
1600 ret = platform_driver_register(&serial_imx_driver);
1601 if (ret != 0)
1602 uart_unregister_driver(&imx_reg);
1603
1604 return ret;
1605 }
1606
1607 static void __exit imx_serial_exit(void)
1608 {
1609 platform_driver_unregister(&serial_imx_driver);
1610 uart_unregister_driver(&imx_reg);
1611 }
1612
1613 module_init(imx_serial_init);
1614 module_exit(imx_serial_exit);
1615
1616 MODULE_AUTHOR("Sascha Hauer");
1617 MODULE_DESCRIPTION("IMX generic serial port driver");
1618 MODULE_LICENSE("GPL");
1619 MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
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