2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
25 #include <linux/dmi.h>
27 #include <linux/dmaengine.h>
28 #include <linux/pch_dma.h>
31 PCH_UART_HANDLED_RX_INT_SHIFT
,
32 PCH_UART_HANDLED_TX_INT_SHIFT
,
33 PCH_UART_HANDLED_RX_ERR_INT_SHIFT
,
34 PCH_UART_HANDLED_RX_TRG_INT_SHIFT
,
35 PCH_UART_HANDLED_MS_INT_SHIFT
,
43 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
45 /* Set the max number of UART port
46 * Intel EG20T PCH: 4 port
47 * OKI SEMICONDUCTOR ML7213 IOH: 3 port
51 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
52 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
53 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
54 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
55 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
56 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
57 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
59 #define PCH_UART_RBR 0x00
60 #define PCH_UART_THR 0x00
62 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
63 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
64 #define PCH_UART_IER_ERBFI 0x00000001
65 #define PCH_UART_IER_ETBEI 0x00000002
66 #define PCH_UART_IER_ELSI 0x00000004
67 #define PCH_UART_IER_EDSSI 0x00000008
69 #define PCH_UART_IIR_IP 0x00000001
70 #define PCH_UART_IIR_IID 0x00000006
71 #define PCH_UART_IIR_MSI 0x00000000
72 #define PCH_UART_IIR_TRI 0x00000002
73 #define PCH_UART_IIR_RRI 0x00000004
74 #define PCH_UART_IIR_REI 0x00000006
75 #define PCH_UART_IIR_TOI 0x00000008
76 #define PCH_UART_IIR_FIFO256 0x00000020
77 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
78 #define PCH_UART_IIR_FE 0x000000C0
80 #define PCH_UART_FCR_FIFOE 0x00000001
81 #define PCH_UART_FCR_RFR 0x00000002
82 #define PCH_UART_FCR_TFR 0x00000004
83 #define PCH_UART_FCR_DMS 0x00000008
84 #define PCH_UART_FCR_FIFO256 0x00000020
85 #define PCH_UART_FCR_RFTL 0x000000C0
87 #define PCH_UART_FCR_RFTL1 0x00000000
88 #define PCH_UART_FCR_RFTL64 0x00000040
89 #define PCH_UART_FCR_RFTL128 0x00000080
90 #define PCH_UART_FCR_RFTL224 0x000000C0
91 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
92 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
93 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
94 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
95 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
96 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
97 #define PCH_UART_FCR_RFTL_SHIFT 6
99 #define PCH_UART_LCR_WLS 0x00000003
100 #define PCH_UART_LCR_STB 0x00000004
101 #define PCH_UART_LCR_PEN 0x00000008
102 #define PCH_UART_LCR_EPS 0x00000010
103 #define PCH_UART_LCR_SP 0x00000020
104 #define PCH_UART_LCR_SB 0x00000040
105 #define PCH_UART_LCR_DLAB 0x00000080
106 #define PCH_UART_LCR_NP 0x00000000
107 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
108 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
109 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
110 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
113 #define PCH_UART_LCR_5BIT 0x00000000
114 #define PCH_UART_LCR_6BIT 0x00000001
115 #define PCH_UART_LCR_7BIT 0x00000002
116 #define PCH_UART_LCR_8BIT 0x00000003
118 #define PCH_UART_MCR_DTR 0x00000001
119 #define PCH_UART_MCR_RTS 0x00000002
120 #define PCH_UART_MCR_OUT 0x0000000C
121 #define PCH_UART_MCR_LOOP 0x00000010
122 #define PCH_UART_MCR_AFE 0x00000020
124 #define PCH_UART_LSR_DR 0x00000001
125 #define PCH_UART_LSR_ERR (1<<7)
127 #define PCH_UART_MSR_DCTS 0x00000001
128 #define PCH_UART_MSR_DDSR 0x00000002
129 #define PCH_UART_MSR_TERI 0x00000004
130 #define PCH_UART_MSR_DDCD 0x00000008
131 #define PCH_UART_MSR_CTS 0x00000010
132 #define PCH_UART_MSR_DSR 0x00000020
133 #define PCH_UART_MSR_RI 0x00000040
134 #define PCH_UART_MSR_DCD 0x00000080
135 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
136 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
138 #define PCH_UART_DLL 0x00
139 #define PCH_UART_DLM 0x01
141 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
142 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
143 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
144 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
145 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
147 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
148 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
149 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
150 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
151 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
152 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
153 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
154 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
155 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
156 #define PCH_UART_HAL_STB1 0
157 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
159 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
160 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
161 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
162 PCH_UART_HAL_CLR_RX_FIFO)
164 #define PCH_UART_HAL_DMA_MODE0 0
165 #define PCH_UART_HAL_FIFO_DIS 0
166 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
167 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
168 PCH_UART_FCR_FIFO256)
169 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
170 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
171 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
172 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
173 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
174 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
175 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
176 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
177 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
178 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
179 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
180 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
181 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
182 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
184 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
185 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
186 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
187 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
188 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
190 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
191 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
192 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
193 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
194 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
196 #define PCI_VENDOR_ID_ROHM 0x10DB
198 struct pch_uart_buffer
{
204 struct uart_port port
;
206 void __iomem
*membase
;
207 resource_size_t mapbase
;
209 struct pci_dev
*pdev
;
218 struct pch_uart_buffer rxbuf
;
222 unsigned int use_dma
;
223 unsigned int use_dma_flag
;
224 struct dma_async_tx_descriptor
*desc_tx
;
225 struct dma_async_tx_descriptor
*desc_rx
;
226 struct pch_dma_slave param_tx
;
227 struct pch_dma_slave param_rx
;
228 struct dma_chan
*chan_tx
;
229 struct dma_chan
*chan_rx
;
230 struct scatterlist
*sg_tx_p
;
232 struct scatterlist sg_rx
;
235 dma_addr_t rx_buf_dma
;
239 * struct pch_uart_driver_data - private data structure for UART-DMA
240 * @port_type: The number of DMA channel
241 * @line_no: UART port line number (0, 1, 2...)
243 struct pch_uart_driver_data
{
248 enum pch_uart_num_t
{
260 static struct pch_uart_driver_data drv_dat
[] = {
261 [pch_et20t_uart0
] = {PCH_UART_8LINE
, 0},
262 [pch_et20t_uart1
] = {PCH_UART_2LINE
, 1},
263 [pch_et20t_uart2
] = {PCH_UART_2LINE
, 2},
264 [pch_et20t_uart3
] = {PCH_UART_2LINE
, 3},
265 [pch_ml7213_uart0
] = {PCH_UART_8LINE
, 0},
266 [pch_ml7213_uart1
] = {PCH_UART_2LINE
, 1},
267 [pch_ml7213_uart2
] = {PCH_UART_2LINE
, 2},
268 [pch_ml7223_uart0
] = {PCH_UART_8LINE
, 0},
269 [pch_ml7223_uart1
] = {PCH_UART_2LINE
, 1},
272 static unsigned int default_baud
= 9600;
273 static const int trigger_level_256
[4] = { 1, 64, 128, 224 };
274 static const int trigger_level_64
[4] = { 1, 16, 32, 56 };
275 static const int trigger_level_16
[4] = { 1, 4, 8, 14 };
276 static const int trigger_level_1
[4] = { 1, 1, 1, 1 };
278 static void pch_uart_hal_request(struct pci_dev
*pdev
, int fifosize
,
281 struct eg20t_port
*priv
= pci_get_drvdata(pdev
);
283 priv
->trigger_level
= 1;
287 static unsigned int get_msr(struct eg20t_port
*priv
, void __iomem
*base
)
289 unsigned int msr
= ioread8(base
+ UART_MSR
);
290 priv
->dmsr
|= msr
& PCH_UART_MSR_DELTA
;
295 static void pch_uart_hal_enable_interrupt(struct eg20t_port
*priv
,
298 u8 ier
= ioread8(priv
->membase
+ UART_IER
);
299 ier
|= flag
& PCH_UART_IER_MASK
;
300 iowrite8(ier
, priv
->membase
+ UART_IER
);
303 static void pch_uart_hal_disable_interrupt(struct eg20t_port
*priv
,
306 u8 ier
= ioread8(priv
->membase
+ UART_IER
);
307 ier
&= ~(flag
& PCH_UART_IER_MASK
);
308 iowrite8(ier
, priv
->membase
+ UART_IER
);
311 static int pch_uart_hal_set_line(struct eg20t_port
*priv
, int baud
,
312 unsigned int parity
, unsigned int bits
,
315 unsigned int dll
, dlm
, lcr
;
318 div
= DIV_ROUND_CLOSEST(priv
->base_baud
/ 16, baud
);
319 if (div
< 0 || USHRT_MAX
<= div
) {
320 dev_err(priv
->port
.dev
, "Invalid Baud(div=0x%x)\n", div
);
324 dll
= (unsigned int)div
& 0x00FFU
;
325 dlm
= ((unsigned int)div
>> 8) & 0x00FFU
;
327 if (parity
& ~(PCH_UART_LCR_PEN
| PCH_UART_LCR_EPS
| PCH_UART_LCR_SP
)) {
328 dev_err(priv
->port
.dev
, "Invalid parity(0x%x)\n", parity
);
332 if (bits
& ~PCH_UART_LCR_WLS
) {
333 dev_err(priv
->port
.dev
, "Invalid bits(0x%x)\n", bits
);
337 if (stb
& ~PCH_UART_LCR_STB
) {
338 dev_err(priv
->port
.dev
, "Invalid STB(0x%x)\n", stb
);
346 dev_dbg(priv
->port
.dev
, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
347 __func__
, baud
, div
, lcr
, jiffies
);
348 iowrite8(PCH_UART_LCR_DLAB
, priv
->membase
+ UART_LCR
);
349 iowrite8(dll
, priv
->membase
+ PCH_UART_DLL
);
350 iowrite8(dlm
, priv
->membase
+ PCH_UART_DLM
);
351 iowrite8(lcr
, priv
->membase
+ UART_LCR
);
356 static int pch_uart_hal_fifo_reset(struct eg20t_port
*priv
,
359 if (flag
& ~(PCH_UART_FCR_TFR
| PCH_UART_FCR_RFR
)) {
360 dev_err(priv
->port
.dev
, "%s:Invalid flag(0x%x)\n",
365 iowrite8(PCH_UART_FCR_FIFOE
| priv
->fcr
, priv
->membase
+ UART_FCR
);
366 iowrite8(PCH_UART_FCR_FIFOE
| priv
->fcr
| flag
,
367 priv
->membase
+ UART_FCR
);
368 iowrite8(priv
->fcr
, priv
->membase
+ UART_FCR
);
373 static int pch_uart_hal_set_fifo(struct eg20t_port
*priv
,
374 unsigned int dmamode
,
375 unsigned int fifo_size
, unsigned int trigger
)
379 if (dmamode
& ~PCH_UART_FCR_DMS
) {
380 dev_err(priv
->port
.dev
, "%s:Invalid DMA Mode(0x%x)\n",
385 if (fifo_size
& ~(PCH_UART_FCR_FIFOE
| PCH_UART_FCR_FIFO256
)) {
386 dev_err(priv
->port
.dev
, "%s:Invalid FIFO SIZE(0x%x)\n",
387 __func__
, fifo_size
);
391 if (trigger
& ~PCH_UART_FCR_RFTL
) {
392 dev_err(priv
->port
.dev
, "%s:Invalid TRIGGER(0x%x)\n",
397 switch (priv
->fifo_size
) {
399 priv
->trigger_level
=
400 trigger_level_256
[trigger
>> PCH_UART_FCR_RFTL_SHIFT
];
403 priv
->trigger_level
=
404 trigger_level_64
[trigger
>> PCH_UART_FCR_RFTL_SHIFT
];
407 priv
->trigger_level
=
408 trigger_level_16
[trigger
>> PCH_UART_FCR_RFTL_SHIFT
];
411 priv
->trigger_level
=
412 trigger_level_1
[trigger
>> PCH_UART_FCR_RFTL_SHIFT
];
416 dmamode
| fifo_size
| trigger
| PCH_UART_FCR_RFR
| PCH_UART_FCR_TFR
;
417 iowrite8(PCH_UART_FCR_FIFOE
, priv
->membase
+ UART_FCR
);
418 iowrite8(PCH_UART_FCR_FIFOE
| PCH_UART_FCR_RFR
| PCH_UART_FCR_TFR
,
419 priv
->membase
+ UART_FCR
);
420 iowrite8(fcr
, priv
->membase
+ UART_FCR
);
426 static u8
pch_uart_hal_get_modem(struct eg20t_port
*priv
)
429 return get_msr(priv
, priv
->membase
);
432 static void pch_uart_hal_write(struct eg20t_port
*priv
,
433 const unsigned char *buf
, int tx_size
)
438 for (i
= 0; i
< tx_size
;) {
440 iowrite8(thr
, priv
->membase
+ PCH_UART_THR
);
444 static int pch_uart_hal_read(struct eg20t_port
*priv
, unsigned char *buf
,
450 lsr
= ioread8(priv
->membase
+ UART_LSR
);
451 for (i
= 0, lsr
= ioread8(priv
->membase
+ UART_LSR
);
452 i
< rx_size
&& lsr
& UART_LSR_DR
;
453 lsr
= ioread8(priv
->membase
+ UART_LSR
)) {
454 rbr
= ioread8(priv
->membase
+ PCH_UART_RBR
);
460 static unsigned int pch_uart_hal_get_iid(struct eg20t_port
*priv
)
465 iir
= ioread8(priv
->membase
+ UART_IIR
);
466 ret
= (iir
& (PCH_UART_IIR_IID
| PCH_UART_IIR_TOI
| PCH_UART_IIR_IP
));
470 static u8
pch_uart_hal_get_line_status(struct eg20t_port
*priv
)
472 return ioread8(priv
->membase
+ UART_LSR
);
475 static void pch_uart_hal_set_break(struct eg20t_port
*priv
, int on
)
479 lcr
= ioread8(priv
->membase
+ UART_LCR
);
481 lcr
|= PCH_UART_LCR_SB
;
483 lcr
&= ~PCH_UART_LCR_SB
;
485 iowrite8(lcr
, priv
->membase
+ UART_LCR
);
488 static int push_rx(struct eg20t_port
*priv
, const unsigned char *buf
,
491 struct uart_port
*port
;
492 struct tty_struct
*tty
;
495 tty
= tty_port_tty_get(&port
->state
->port
);
497 dev_dbg(priv
->port
.dev
, "%s:tty is busy now", __func__
);
501 tty_insert_flip_string(tty
, buf
, size
);
502 tty_flip_buffer_push(tty
);
508 static int pop_tx_x(struct eg20t_port
*priv
, unsigned char *buf
)
511 struct uart_port
*port
= &priv
->port
;
514 dev_dbg(priv
->port
.dev
, "%s:X character send %02x (%lu)\n",
515 __func__
, port
->x_char
, jiffies
);
516 buf
[0] = port
->x_char
;
526 static int dma_push_rx(struct eg20t_port
*priv
, int size
)
528 struct tty_struct
*tty
;
530 struct uart_port
*port
= &priv
->port
;
533 tty
= tty_port_tty_get(&port
->state
->port
);
535 dev_dbg(priv
->port
.dev
, "%s:tty is busy now", __func__
);
539 room
= tty_buffer_request_room(tty
, size
);
542 dev_warn(port
->dev
, "Rx overrun: dropping %u bytes\n",
547 tty_insert_flip_string(tty
, sg_virt(&priv
->sg_rx
), size
);
549 port
->icount
.rx
+= room
;
555 static void pch_free_dma(struct uart_port
*port
)
557 struct eg20t_port
*priv
;
558 priv
= container_of(port
, struct eg20t_port
, port
);
561 dma_release_channel(priv
->chan_tx
);
562 priv
->chan_tx
= NULL
;
565 dma_release_channel(priv
->chan_rx
);
566 priv
->chan_rx
= NULL
;
568 if (sg_dma_address(&priv
->sg_rx
))
569 dma_free_coherent(port
->dev
, port
->fifosize
,
570 sg_virt(&priv
->sg_rx
),
571 sg_dma_address(&priv
->sg_rx
));
576 static bool filter(struct dma_chan
*chan
, void *slave
)
578 struct pch_dma_slave
*param
= slave
;
580 if ((chan
->chan_id
== param
->chan_id
) && (param
->dma_dev
==
581 chan
->device
->dev
)) {
582 chan
->private = param
;
589 static void pch_request_dma(struct uart_port
*port
)
592 struct dma_chan
*chan
;
593 struct pci_dev
*dma_dev
;
594 struct pch_dma_slave
*param
;
595 struct eg20t_port
*priv
=
596 container_of(port
, struct eg20t_port
, port
);
598 dma_cap_set(DMA_SLAVE
, mask
);
600 dma_dev
= pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev
603 param
= &priv
->param_tx
;
604 param
->dma_dev
= &dma_dev
->dev
;
605 param
->chan_id
= priv
->port
.line
* 2; /* Tx = 0, 2, 4, ... */
607 param
->tx_reg
= port
->mapbase
+ UART_TX
;
608 chan
= dma_request_channel(mask
, filter
, param
);
610 dev_err(priv
->port
.dev
, "%s:dma_request_channel FAILS(Tx)\n",
614 priv
->chan_tx
= chan
;
617 param
= &priv
->param_rx
;
618 param
->dma_dev
= &dma_dev
->dev
;
619 param
->chan_id
= priv
->port
.line
* 2 + 1; /* Rx = Tx + 1 */
621 param
->rx_reg
= port
->mapbase
+ UART_RX
;
622 chan
= dma_request_channel(mask
, filter
, param
);
624 dev_err(priv
->port
.dev
, "%s:dma_request_channel FAILS(Rx)\n",
626 dma_release_channel(priv
->chan_tx
);
630 /* Get Consistent memory for DMA */
631 priv
->rx_buf_virt
= dma_alloc_coherent(port
->dev
, port
->fifosize
,
632 &priv
->rx_buf_dma
, GFP_KERNEL
);
633 priv
->chan_rx
= chan
;
636 static void pch_dma_rx_complete(void *arg
)
638 struct eg20t_port
*priv
= arg
;
639 struct uart_port
*port
= &priv
->port
;
640 struct tty_struct
*tty
= tty_port_tty_get(&port
->state
->port
);
644 dev_dbg(priv
->port
.dev
, "%s:tty is busy now", __func__
);
648 dma_sync_sg_for_cpu(port
->dev
, &priv
->sg_rx
, 1, DMA_FROM_DEVICE
);
649 count
= dma_push_rx(priv
, priv
->trigger_level
);
651 tty_flip_buffer_push(tty
);
653 async_tx_ack(priv
->desc_rx
);
654 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_RX_INT
);
657 static void pch_dma_tx_complete(void *arg
)
659 struct eg20t_port
*priv
= arg
;
660 struct uart_port
*port
= &priv
->port
;
661 struct circ_buf
*xmit
= &port
->state
->xmit
;
662 struct scatterlist
*sg
= priv
->sg_tx_p
;
665 for (i
= 0; i
< priv
->nent
; i
++, sg
++) {
666 xmit
->tail
+= sg_dma_len(sg
);
667 port
->icount
.tx
+= sg_dma_len(sg
);
669 xmit
->tail
&= UART_XMIT_SIZE
- 1;
670 async_tx_ack(priv
->desc_tx
);
671 dma_unmap_sg(port
->dev
, sg
, priv
->nent
, DMA_TO_DEVICE
);
672 priv
->tx_dma_use
= 0;
674 kfree(priv
->sg_tx_p
);
675 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
678 static int pop_tx(struct eg20t_port
*priv
, int size
)
681 struct uart_port
*port
= &priv
->port
;
682 struct circ_buf
*xmit
= &port
->state
->xmit
;
684 if (uart_tx_stopped(port
) || uart_circ_empty(xmit
) || count
>= size
)
689 CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
690 int sz
= min(size
- count
, cnt_to_end
);
691 pch_uart_hal_write(priv
, &xmit
->buf
[xmit
->tail
], sz
);
692 xmit
->tail
= (xmit
->tail
+ sz
) & (UART_XMIT_SIZE
- 1);
694 } while (!uart_circ_empty(xmit
) && count
< size
);
697 dev_dbg(priv
->port
.dev
, "%d characters. Remained %d characters.(%lu)\n",
698 count
, size
- count
, jiffies
);
703 static int handle_rx_to(struct eg20t_port
*priv
)
705 struct pch_uart_buffer
*buf
;
708 if (!priv
->start_rx
) {
709 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_RX_INT
);
714 rx_size
= pch_uart_hal_read(priv
, buf
->buf
, buf
->size
);
715 ret
= push_rx(priv
, buf
->buf
, rx_size
);
718 } while (rx_size
== buf
->size
);
720 return PCH_UART_HANDLED_RX_INT
;
723 static int handle_rx(struct eg20t_port
*priv
)
725 return handle_rx_to(priv
);
728 static int dma_handle_rx(struct eg20t_port
*priv
)
730 struct uart_port
*port
= &priv
->port
;
731 struct dma_async_tx_descriptor
*desc
;
732 struct scatterlist
*sg
;
734 priv
= container_of(port
, struct eg20t_port
, port
);
737 sg_init_table(&priv
->sg_rx
, 1); /* Initialize SG table */
739 sg_dma_len(sg
) = priv
->trigger_level
;
741 sg_set_page(&priv
->sg_rx
, virt_to_page(priv
->rx_buf_virt
),
742 sg_dma_len(sg
), (unsigned long)priv
->rx_buf_virt
&
745 sg_dma_address(sg
) = priv
->rx_buf_dma
;
747 desc
= priv
->chan_rx
->device
->device_prep_slave_sg(priv
->chan_rx
,
748 sg
, 1, DMA_FROM_DEVICE
,
749 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
754 priv
->desc_rx
= desc
;
755 desc
->callback
= pch_dma_rx_complete
;
756 desc
->callback_param
= priv
;
757 desc
->tx_submit(desc
);
758 dma_async_issue_pending(priv
->chan_rx
);
760 return PCH_UART_HANDLED_RX_INT
;
763 static unsigned int handle_tx(struct eg20t_port
*priv
)
765 struct uart_port
*port
= &priv
->port
;
766 struct circ_buf
*xmit
= &port
->state
->xmit
;
772 if (!priv
->start_tx
) {
773 dev_info(priv
->port
.dev
, "%s:Tx isn't started. (%lu)\n",
775 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
780 fifo_size
= max(priv
->fifo_size
, 1);
782 if (pop_tx_x(priv
, xmit
->buf
)) {
783 pch_uart_hal_write(priv
, xmit
->buf
, 1);
788 size
= min(xmit
->head
- xmit
->tail
, fifo_size
);
792 tx_size
= pop_tx(priv
, size
);
794 port
->icount
.tx
+= tx_size
;
798 priv
->tx_empty
= tx_empty
;
801 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
802 uart_write_wakeup(port
);
805 return PCH_UART_HANDLED_TX_INT
;
808 static unsigned int dma_handle_tx(struct eg20t_port
*priv
)
810 struct uart_port
*port
= &priv
->port
;
811 struct circ_buf
*xmit
= &port
->state
->xmit
;
812 struct scatterlist
*sg
;
816 struct dma_async_tx_descriptor
*desc
;
823 if (!priv
->start_tx
) {
824 dev_info(priv
->port
.dev
, "%s:Tx isn't started. (%lu)\n",
826 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
831 if (priv
->tx_dma_use
) {
832 dev_dbg(priv
->port
.dev
, "%s:Tx is not completed. (%lu)\n",
834 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
839 fifo_size
= max(priv
->fifo_size
, 1);
841 if (pop_tx_x(priv
, xmit
->buf
)) {
842 pch_uart_hal_write(priv
, xmit
->buf
, 1);
848 bytes
= min((int)CIRC_CNT(xmit
->head
, xmit
->tail
,
849 UART_XMIT_SIZE
), CIRC_CNT_TO_END(xmit
->head
,
850 xmit
->tail
, UART_XMIT_SIZE
));
852 dev_dbg(priv
->port
.dev
, "%s 0 bytes return\n", __func__
);
853 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
854 uart_write_wakeup(port
);
858 if (bytes
> fifo_size
) {
859 num
= bytes
/ fifo_size
+ 1;
861 rem
= bytes
% fifo_size
;
868 dev_dbg(priv
->port
.dev
, "%s num=%d size=%d rem=%d\n",
869 __func__
, num
, size
, rem
);
871 priv
->tx_dma_use
= 1;
873 priv
->sg_tx_p
= kzalloc(sizeof(struct scatterlist
)*num
, GFP_ATOMIC
);
875 sg_init_table(priv
->sg_tx_p
, num
); /* Initialize SG table */
878 for (i
= 0; i
< num
; i
++, sg
++) {
880 sg_set_page(sg
, virt_to_page(xmit
->buf
),
883 sg_set_page(sg
, virt_to_page(xmit
->buf
),
884 size
, fifo_size
* i
);
888 nent
= dma_map_sg(port
->dev
, sg
, num
, DMA_TO_DEVICE
);
890 dev_err(priv
->port
.dev
, "%s:dma_map_sg Failed\n", __func__
);
895 for (i
= 0; i
< nent
; i
++, sg
++) {
896 sg
->offset
= (xmit
->tail
& (UART_XMIT_SIZE
- 1)) +
898 sg_dma_address(sg
) = (sg_dma_address(sg
) &
899 ~(UART_XMIT_SIZE
- 1)) + sg
->offset
;
901 sg_dma_len(sg
) = rem
;
903 sg_dma_len(sg
) = size
;
906 desc
= priv
->chan_tx
->device
->device_prep_slave_sg(priv
->chan_tx
,
907 priv
->sg_tx_p
, nent
, DMA_TO_DEVICE
,
908 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
910 dev_err(priv
->port
.dev
, "%s:device_prep_slave_sg Failed\n",
914 dma_sync_sg_for_device(port
->dev
, priv
->sg_tx_p
, nent
, DMA_TO_DEVICE
);
915 priv
->desc_tx
= desc
;
916 desc
->callback
= pch_dma_tx_complete
;
917 desc
->callback_param
= priv
;
919 desc
->tx_submit(desc
);
921 dma_async_issue_pending(priv
->chan_tx
);
923 return PCH_UART_HANDLED_TX_INT
;
926 static void pch_uart_err_ir(struct eg20t_port
*priv
, unsigned int lsr
)
928 u8 fcr
= ioread8(priv
->membase
+ UART_FCR
);
931 fcr
|= UART_FCR_CLEAR_RCVR
;
932 iowrite8(fcr
, priv
->membase
+ UART_FCR
);
934 if (lsr
& PCH_UART_LSR_ERR
)
935 dev_err(&priv
->pdev
->dev
, "Error data in FIFO\n");
937 if (lsr
& UART_LSR_FE
)
938 dev_err(&priv
->pdev
->dev
, "Framing Error\n");
940 if (lsr
& UART_LSR_PE
)
941 dev_err(&priv
->pdev
->dev
, "Parity Error\n");
943 if (lsr
& UART_LSR_OE
)
944 dev_err(&priv
->pdev
->dev
, "Overrun Error\n");
947 static irqreturn_t
pch_uart_interrupt(int irq
, void *dev_id
)
949 struct eg20t_port
*priv
= dev_id
;
950 unsigned int handled
;
956 spin_lock_irqsave(&priv
->port
.lock
, flags
);
958 while ((iid
= pch_uart_hal_get_iid(priv
)) > 1) {
960 case PCH_UART_IID_RLS
: /* Receiver Line Status */
961 lsr
= pch_uart_hal_get_line_status(priv
);
962 if (lsr
& (PCH_UART_LSR_ERR
| UART_LSR_FE
|
963 UART_LSR_PE
| UART_LSR_OE
)) {
964 pch_uart_err_ir(priv
, lsr
);
965 ret
= PCH_UART_HANDLED_RX_ERR_INT
;
968 case PCH_UART_IID_RDR
: /* Received Data Ready */
970 pch_uart_hal_disable_interrupt(priv
,
971 PCH_UART_HAL_RX_INT
);
972 ret
= dma_handle_rx(priv
);
974 pch_uart_hal_enable_interrupt(priv
,
975 PCH_UART_HAL_RX_INT
);
977 ret
= handle_rx(priv
);
980 case PCH_UART_IID_RDR_TO
: /* Received Data Ready
982 ret
= handle_rx_to(priv
);
984 case PCH_UART_IID_THRE
: /* Transmitter Holding Register
987 ret
= dma_handle_tx(priv
);
989 ret
= handle_tx(priv
);
991 case PCH_UART_IID_MS
: /* Modem Status */
992 ret
= PCH_UART_HANDLED_MS_INT
;
994 default: /* Never junp to this label */
995 dev_err(priv
->port
.dev
, "%s:iid=%d (%lu)\n", __func__
,
1000 handled
|= (unsigned int)ret
;
1002 if (handled
== 0 && iid
<= 1) {
1003 if (priv
->int_dis_flag
)
1004 priv
->int_dis_flag
= 0;
1007 spin_unlock_irqrestore(&priv
->port
.lock
, flags
);
1008 return IRQ_RETVAL(handled
);
1011 /* This function tests whether the transmitter fifo and shifter for the port
1012 described by 'port' is empty. */
1013 static unsigned int pch_uart_tx_empty(struct uart_port
*port
)
1015 struct eg20t_port
*priv
;
1017 priv
= container_of(port
, struct eg20t_port
, port
);
1026 /* Returns the current state of modem control inputs. */
1027 static unsigned int pch_uart_get_mctrl(struct uart_port
*port
)
1029 struct eg20t_port
*priv
;
1031 unsigned int ret
= 0;
1033 priv
= container_of(port
, struct eg20t_port
, port
);
1034 modem
= pch_uart_hal_get_modem(priv
);
1036 if (modem
& UART_MSR_DCD
)
1039 if (modem
& UART_MSR_RI
)
1042 if (modem
& UART_MSR_DSR
)
1045 if (modem
& UART_MSR_CTS
)
1051 static void pch_uart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1054 struct eg20t_port
*priv
= container_of(port
, struct eg20t_port
, port
);
1056 if (mctrl
& TIOCM_DTR
)
1057 mcr
|= UART_MCR_DTR
;
1058 if (mctrl
& TIOCM_RTS
)
1059 mcr
|= UART_MCR_RTS
;
1060 if (mctrl
& TIOCM_LOOP
)
1061 mcr
|= UART_MCR_LOOP
;
1063 if (priv
->mcr
& UART_MCR_AFE
)
1064 mcr
|= UART_MCR_AFE
;
1067 iowrite8(mcr
, priv
->membase
+ UART_MCR
);
1070 static void pch_uart_stop_tx(struct uart_port
*port
)
1072 struct eg20t_port
*priv
;
1073 priv
= container_of(port
, struct eg20t_port
, port
);
1075 priv
->tx_dma_use
= 0;
1078 static void pch_uart_start_tx(struct uart_port
*port
)
1080 struct eg20t_port
*priv
;
1082 priv
= container_of(port
, struct eg20t_port
, port
);
1084 if (priv
->use_dma
) {
1085 if (priv
->tx_dma_use
) {
1086 dev_dbg(priv
->port
.dev
, "%s : Tx DMA is NOT empty.\n",
1093 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_TX_INT
);
1096 static void pch_uart_stop_rx(struct uart_port
*port
)
1098 struct eg20t_port
*priv
;
1099 priv
= container_of(port
, struct eg20t_port
, port
);
1101 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_RX_INT
);
1102 priv
->int_dis_flag
= 1;
1105 /* Enable the modem status interrupts. */
1106 static void pch_uart_enable_ms(struct uart_port
*port
)
1108 struct eg20t_port
*priv
;
1109 priv
= container_of(port
, struct eg20t_port
, port
);
1110 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_MS_INT
);
1113 /* Control the transmission of a break signal. */
1114 static void pch_uart_break_ctl(struct uart_port
*port
, int ctl
)
1116 struct eg20t_port
*priv
;
1117 unsigned long flags
;
1119 priv
= container_of(port
, struct eg20t_port
, port
);
1120 spin_lock_irqsave(&port
->lock
, flags
);
1121 pch_uart_hal_set_break(priv
, ctl
);
1122 spin_unlock_irqrestore(&port
->lock
, flags
);
1125 /* Grab any interrupt resources and initialise any low level driver state. */
1126 static int pch_uart_startup(struct uart_port
*port
)
1128 struct eg20t_port
*priv
;
1133 priv
= container_of(port
, struct eg20t_port
, port
);
1137 priv
->base_baud
= port
->uartclk
;
1139 port
->uartclk
= priv
->base_baud
;
1141 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_ALL_INT
);
1142 ret
= pch_uart_hal_set_line(priv
, default_baud
,
1143 PCH_UART_HAL_PARITY_NONE
, PCH_UART_HAL_8BIT
,
1148 switch (priv
->fifo_size
) {
1150 fifo_size
= PCH_UART_HAL_FIFO256
;
1153 fifo_size
= PCH_UART_HAL_FIFO64
;
1156 fifo_size
= PCH_UART_HAL_FIFO16
;
1159 fifo_size
= PCH_UART_HAL_FIFO_DIS
;
1163 switch (priv
->trigger
) {
1164 case PCH_UART_HAL_TRIGGER1
:
1167 case PCH_UART_HAL_TRIGGER_L
:
1168 trigger_level
= priv
->fifo_size
/ 4;
1170 case PCH_UART_HAL_TRIGGER_M
:
1171 trigger_level
= priv
->fifo_size
/ 2;
1173 case PCH_UART_HAL_TRIGGER_H
:
1175 trigger_level
= priv
->fifo_size
- (priv
->fifo_size
/ 8);
1179 priv
->trigger_level
= trigger_level
;
1180 ret
= pch_uart_hal_set_fifo(priv
, PCH_UART_HAL_DMA_MODE0
,
1181 fifo_size
, priv
->trigger
);
1185 ret
= request_irq(priv
->port
.irq
, pch_uart_interrupt
, IRQF_SHARED
,
1186 KBUILD_MODNAME
, priv
);
1191 pch_request_dma(port
);
1194 pch_uart_hal_enable_interrupt(priv
, PCH_UART_HAL_RX_INT
);
1195 uart_update_timeout(port
, CS8
, default_baud
);
1200 static void pch_uart_shutdown(struct uart_port
*port
)
1202 struct eg20t_port
*priv
;
1205 priv
= container_of(port
, struct eg20t_port
, port
);
1206 pch_uart_hal_disable_interrupt(priv
, PCH_UART_HAL_ALL_INT
);
1207 pch_uart_hal_fifo_reset(priv
, PCH_UART_HAL_CLR_ALL_FIFO
);
1208 ret
= pch_uart_hal_set_fifo(priv
, PCH_UART_HAL_DMA_MODE0
,
1209 PCH_UART_HAL_FIFO_DIS
, PCH_UART_HAL_TRIGGER1
);
1211 dev_err(priv
->port
.dev
,
1212 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret
);
1214 if (priv
->use_dma_flag
)
1217 free_irq(priv
->port
.irq
, priv
);
1220 /* Change the port parameters, including word length, parity, stop
1221 *bits. Update read_status_mask and ignore_status_mask to indicate
1222 *the types of events we are interested in receiving. */
1223 static void pch_uart_set_termios(struct uart_port
*port
,
1224 struct ktermios
*termios
, struct ktermios
*old
)
1228 unsigned int parity
, bits
, stb
;
1229 struct eg20t_port
*priv
;
1230 unsigned long flags
;
1232 priv
= container_of(port
, struct eg20t_port
, port
);
1233 switch (termios
->c_cflag
& CSIZE
) {
1235 bits
= PCH_UART_HAL_5BIT
;
1238 bits
= PCH_UART_HAL_6BIT
;
1241 bits
= PCH_UART_HAL_7BIT
;
1244 bits
= PCH_UART_HAL_8BIT
;
1247 if (termios
->c_cflag
& CSTOPB
)
1248 stb
= PCH_UART_HAL_STB2
;
1250 stb
= PCH_UART_HAL_STB1
;
1252 if (termios
->c_cflag
& PARENB
) {
1253 if (!(termios
->c_cflag
& PARODD
))
1254 parity
= PCH_UART_HAL_PARITY_ODD
;
1256 parity
= PCH_UART_HAL_PARITY_EVEN
;
1259 parity
= PCH_UART_HAL_PARITY_NONE
;
1262 /* Only UART0 has auto hardware flow function */
1263 if ((termios
->c_cflag
& CRTSCTS
) && (priv
->fifo_size
== 256))
1264 priv
->mcr
|= UART_MCR_AFE
;
1266 priv
->mcr
&= ~UART_MCR_AFE
;
1268 termios
->c_cflag
&= ~CMSPAR
; /* Mark/Space parity is not supported */
1270 baud
= uart_get_baud_rate(port
, termios
, old
, 0, port
->uartclk
/ 16);
1272 spin_lock_irqsave(&port
->lock
, flags
);
1274 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1275 rtn
= pch_uart_hal_set_line(priv
, baud
, parity
, bits
, stb
);
1279 /* Don't rewrite B0 */
1280 if (tty_termios_baud_rate(termios
))
1281 tty_termios_encode_baud_rate(termios
, baud
, baud
);
1284 spin_unlock_irqrestore(&port
->lock
, flags
);
1287 static const char *pch_uart_type(struct uart_port
*port
)
1289 return KBUILD_MODNAME
;
1292 static void pch_uart_release_port(struct uart_port
*port
)
1294 struct eg20t_port
*priv
;
1296 priv
= container_of(port
, struct eg20t_port
, port
);
1297 pci_iounmap(priv
->pdev
, priv
->membase
);
1298 pci_release_regions(priv
->pdev
);
1301 static int pch_uart_request_port(struct uart_port
*port
)
1303 struct eg20t_port
*priv
;
1305 void __iomem
*membase
;
1307 priv
= container_of(port
, struct eg20t_port
, port
);
1308 ret
= pci_request_regions(priv
->pdev
, KBUILD_MODNAME
);
1312 membase
= pci_iomap(priv
->pdev
, 1, 0);
1314 pci_release_regions(priv
->pdev
);
1317 priv
->membase
= port
->membase
= membase
;
1322 static void pch_uart_config_port(struct uart_port
*port
, int type
)
1324 struct eg20t_port
*priv
;
1326 priv
= container_of(port
, struct eg20t_port
, port
);
1327 if (type
& UART_CONFIG_TYPE
) {
1328 port
->type
= priv
->port_type
;
1329 pch_uart_request_port(port
);
1333 static int pch_uart_verify_port(struct uart_port
*port
,
1334 struct serial_struct
*serinfo
)
1336 struct eg20t_port
*priv
;
1338 priv
= container_of(port
, struct eg20t_port
, port
);
1339 if (serinfo
->flags
& UPF_LOW_LATENCY
) {
1340 dev_info(priv
->port
.dev
,
1341 "PCH UART : Use PIO Mode (without DMA)\n");
1343 serinfo
->flags
&= ~UPF_LOW_LATENCY
;
1345 #ifndef CONFIG_PCH_DMA
1346 dev_err(priv
->port
.dev
, "%s : PCH DMA is not Loaded.\n",
1351 priv
->use_dma_flag
= 1;
1352 dev_info(priv
->port
.dev
, "PCH UART : Use DMA Mode\n");
1358 static struct uart_ops pch_uart_ops
= {
1359 .tx_empty
= pch_uart_tx_empty
,
1360 .set_mctrl
= pch_uart_set_mctrl
,
1361 .get_mctrl
= pch_uart_get_mctrl
,
1362 .stop_tx
= pch_uart_stop_tx
,
1363 .start_tx
= pch_uart_start_tx
,
1364 .stop_rx
= pch_uart_stop_rx
,
1365 .enable_ms
= pch_uart_enable_ms
,
1366 .break_ctl
= pch_uart_break_ctl
,
1367 .startup
= pch_uart_startup
,
1368 .shutdown
= pch_uart_shutdown
,
1369 .set_termios
= pch_uart_set_termios
,
1370 /* .pm = pch_uart_pm, Not supported yet */
1371 /* .set_wake = pch_uart_set_wake, Not supported yet */
1372 .type
= pch_uart_type
,
1373 .release_port
= pch_uart_release_port
,
1374 .request_port
= pch_uart_request_port
,
1375 .config_port
= pch_uart_config_port
,
1376 .verify_port
= pch_uart_verify_port
1379 static struct uart_driver pch_uart_driver
= {
1380 .owner
= THIS_MODULE
,
1381 .driver_name
= KBUILD_MODNAME
,
1382 .dev_name
= PCH_UART_DRIVER_DEVICE
,
1388 static struct eg20t_port
*pch_uart_init_port(struct pci_dev
*pdev
,
1389 const struct pci_device_id
*id
)
1391 struct eg20t_port
*priv
;
1393 unsigned int iobase
;
1394 unsigned int mapbase
;
1395 unsigned char *rxbuf
;
1396 int fifosize
, base_baud
;
1398 struct pch_uart_driver_data
*board
;
1400 board
= &drv_dat
[id
->driver_data
];
1401 port_type
= board
->port_type
;
1403 priv
= kzalloc(sizeof(struct eg20t_port
), GFP_KERNEL
);
1405 goto init_port_alloc_err
;
1407 rxbuf
= (unsigned char *)__get_free_page(GFP_KERNEL
);
1409 goto init_port_free_txbuf
;
1411 base_baud
= 1843200; /* 1.8432MHz */
1413 /* quirk for CM-iTC board */
1414 if (strstr(dmi_get_system_info(DMI_BOARD_NAME
), "CM-iTC"))
1415 base_baud
= 192000000; /* 192.0MHz */
1417 switch (port_type
) {
1419 fifosize
= 256; /* EG20T/ML7213: UART0 */
1422 fifosize
= 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1425 dev_err(&pdev
->dev
, "Invalid Port Type(=%d)\n", port_type
);
1426 goto init_port_hal_free
;
1429 pci_enable_msi(pdev
);
1431 iobase
= pci_resource_start(pdev
, 0);
1432 mapbase
= pci_resource_start(pdev
, 1);
1433 priv
->mapbase
= mapbase
;
1434 priv
->iobase
= iobase
;
1437 priv
->rxbuf
.buf
= rxbuf
;
1438 priv
->rxbuf
.size
= PAGE_SIZE
;
1440 priv
->fifo_size
= fifosize
;
1441 priv
->base_baud
= base_baud
;
1442 priv
->port_type
= PORT_MAX_8250
+ port_type
+ 1;
1443 priv
->port
.dev
= &pdev
->dev
;
1444 priv
->port
.iobase
= iobase
;
1445 priv
->port
.membase
= NULL
;
1446 priv
->port
.mapbase
= mapbase
;
1447 priv
->port
.irq
= pdev
->irq
;
1448 priv
->port
.iotype
= UPIO_PORT
;
1449 priv
->port
.ops
= &pch_uart_ops
;
1450 priv
->port
.flags
= UPF_BOOT_AUTOCONF
;
1451 priv
->port
.fifosize
= fifosize
;
1452 priv
->port
.line
= board
->line_no
;
1453 priv
->trigger
= PCH_UART_HAL_TRIGGER_M
;
1455 spin_lock_init(&priv
->port
.lock
);
1457 pci_set_drvdata(pdev
, priv
);
1458 pch_uart_hal_request(pdev
, fifosize
, base_baud
);
1460 ret
= uart_add_one_port(&pch_uart_driver
, &priv
->port
);
1462 goto init_port_hal_free
;
1467 free_page((unsigned long)rxbuf
);
1468 init_port_free_txbuf
:
1470 init_port_alloc_err
:
1475 static void pch_uart_exit_port(struct eg20t_port
*priv
)
1477 uart_remove_one_port(&pch_uart_driver
, &priv
->port
);
1478 pci_set_drvdata(priv
->pdev
, NULL
);
1479 free_page((unsigned long)priv
->rxbuf
.buf
);
1482 static void pch_uart_pci_remove(struct pci_dev
*pdev
)
1484 struct eg20t_port
*priv
;
1486 priv
= (struct eg20t_port
*)pci_get_drvdata(pdev
);
1488 pci_disable_msi(pdev
);
1489 pch_uart_exit_port(priv
);
1490 pci_disable_device(pdev
);
1495 static int pch_uart_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1497 struct eg20t_port
*priv
= pci_get_drvdata(pdev
);
1499 uart_suspend_port(&pch_uart_driver
, &priv
->port
);
1501 pci_save_state(pdev
);
1502 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1506 static int pch_uart_pci_resume(struct pci_dev
*pdev
)
1508 struct eg20t_port
*priv
= pci_get_drvdata(pdev
);
1511 pci_set_power_state(pdev
, PCI_D0
);
1512 pci_restore_state(pdev
);
1514 ret
= pci_enable_device(pdev
);
1517 "%s-pci_enable_device failed(ret=%d) ", __func__
, ret
);
1521 uart_resume_port(&pch_uart_driver
, &priv
->port
);
1526 #define pch_uart_pci_suspend NULL
1527 #define pch_uart_pci_resume NULL
1530 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id
) = {
1531 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x8811),
1532 .driver_data
= pch_et20t_uart0
},
1533 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x8812),
1534 .driver_data
= pch_et20t_uart1
},
1535 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x8813),
1536 .driver_data
= pch_et20t_uart2
},
1537 {PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x8814),
1538 .driver_data
= pch_et20t_uart3
},
1539 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8027),
1540 .driver_data
= pch_ml7213_uart0
},
1541 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8028),
1542 .driver_data
= pch_ml7213_uart1
},
1543 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x8029),
1544 .driver_data
= pch_ml7213_uart2
},
1545 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x800C),
1546 .driver_data
= pch_ml7223_uart0
},
1547 {PCI_DEVICE(PCI_VENDOR_ID_ROHM
, 0x800D),
1548 .driver_data
= pch_ml7223_uart1
},
1552 static int __devinit
pch_uart_pci_probe(struct pci_dev
*pdev
,
1553 const struct pci_device_id
*id
)
1556 struct eg20t_port
*priv
;
1558 ret
= pci_enable_device(pdev
);
1562 priv
= pch_uart_init_port(pdev
, id
);
1565 goto probe_disable_device
;
1567 pci_set_drvdata(pdev
, priv
);
1571 probe_disable_device
:
1572 pci_disable_msi(pdev
);
1573 pci_disable_device(pdev
);
1578 static struct pci_driver pch_uart_pci_driver
= {
1580 .id_table
= pch_uart_pci_id
,
1581 .probe
= pch_uart_pci_probe
,
1582 .remove
= __devexit_p(pch_uart_pci_remove
),
1583 .suspend
= pch_uart_pci_suspend
,
1584 .resume
= pch_uart_pci_resume
,
1587 static int __init
pch_uart_module_init(void)
1591 /* register as UART driver */
1592 ret
= uart_register_driver(&pch_uart_driver
);
1596 /* register as PCI driver */
1597 ret
= pci_register_driver(&pch_uart_pci_driver
);
1599 uart_unregister_driver(&pch_uart_driver
);
1603 module_init(pch_uart_module_init
);
1605 static void __exit
pch_uart_module_exit(void)
1607 pci_unregister_driver(&pch_uart_pci_driver
);
1608 uart_unregister_driver(&pch_uart_driver
);
1610 module_exit(pch_uart_module_exit
);
1612 MODULE_LICENSE("GPL v2");
1613 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1614 module_param(default_baud
, uint
, S_IRUGO
);