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70f005f37de085f404e483b5e6daab8f2279b42b
[deliverable/linux.git] / drivers / tty / serial / sh-sci.c
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #define SUPPORT_SYSRQ
23 #endif
24
25 #undef DEBUG
26
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
41 #include <linux/mm.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85 };
86
87 struct sci_port {
88 struct uart_port port;
89
90 /* Platform configuration */
91 struct plat_sci_port *cfg;
92 unsigned int overrun_reg;
93 unsigned int overrun_mask;
94 unsigned int error_mask;
95 unsigned int error_clear;
96 unsigned int sampling_rate;
97 resource_size_t reg_size;
98
99 /* Break timer */
100 struct timer_list break_timer;
101 int break_flag;
102
103 /* Clocks */
104 struct clk *clks[SCI_NUM_CLKS];
105 unsigned long clk_rates[SCI_NUM_CLKS];
106
107 int irqs[SCIx_NR_IRQS];
108 char *irqstr[SCIx_NR_IRQS];
109
110 struct dma_chan *chan_tx;
111 struct dma_chan *chan_rx;
112
113 #ifdef CONFIG_SERIAL_SH_SCI_DMA
114 dma_cookie_t cookie_tx;
115 dma_cookie_t cookie_rx[2];
116 dma_cookie_t active_rx;
117 dma_addr_t tx_dma_addr;
118 unsigned int tx_dma_len;
119 struct scatterlist sg_rx[2];
120 void *rx_buf[2];
121 size_t buf_len_rx;
122 struct work_struct work_tx;
123 struct timer_list rx_timer;
124 unsigned int rx_timeout;
125 #endif
126 };
127
128 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
129
130 static struct sci_port sci_ports[SCI_NPORTS];
131 static struct uart_driver sci_uart_driver;
132
133 static inline struct sci_port *
134 to_sci_port(struct uart_port *uart)
135 {
136 return container_of(uart, struct sci_port, port);
137 }
138
139 struct plat_sci_reg {
140 u8 offset, size;
141 };
142
143 /* Helper for invalidating specific entries of an inherited map. */
144 #define sci_reg_invalid { .offset = 0, .size = 0 }
145
146 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
147 [SCIx_PROBE_REGTYPE] = {
148 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
149 },
150
151 /*
152 * Common SCI definitions, dependent on the port's regshift
153 * value.
154 */
155 [SCIx_SCI_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = sci_reg_invalid,
163 [SCFDR] = sci_reg_invalid,
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
168 [HSSRR] = sci_reg_invalid,
169 [SCPCR] = sci_reg_invalid,
170 [SCPDR] = sci_reg_invalid,
171 [SCDL] = sci_reg_invalid,
172 [SCCKS] = sci_reg_invalid,
173 },
174
175 /*
176 * Common definitions for legacy IrDA ports, dependent on
177 * regshift value.
178 */
179 [SCIx_IRDA_REGTYPE] = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
186 [SCFCR] = { 0x06, 8 },
187 [SCFDR] = { 0x07, 16 },
188 [SCTFDR] = sci_reg_invalid,
189 [SCRFDR] = sci_reg_invalid,
190 [SCSPTR] = sci_reg_invalid,
191 [SCLSR] = sci_reg_invalid,
192 [HSSRR] = sci_reg_invalid,
193 [SCPCR] = sci_reg_invalid,
194 [SCPDR] = sci_reg_invalid,
195 [SCDL] = sci_reg_invalid,
196 [SCCKS] = sci_reg_invalid,
197 },
198
199 /*
200 * Common SCIFA definitions.
201 */
202 [SCIx_SCIFA_REGTYPE] = {
203 [SCSMR] = { 0x00, 16 },
204 [SCBRR] = { 0x04, 8 },
205 [SCSCR] = { 0x08, 16 },
206 [SCxTDR] = { 0x20, 8 },
207 [SCxSR] = { 0x14, 16 },
208 [SCxRDR] = { 0x24, 8 },
209 [SCFCR] = { 0x18, 16 },
210 [SCFDR] = { 0x1c, 16 },
211 [SCTFDR] = sci_reg_invalid,
212 [SCRFDR] = sci_reg_invalid,
213 [SCSPTR] = sci_reg_invalid,
214 [SCLSR] = sci_reg_invalid,
215 [HSSRR] = sci_reg_invalid,
216 [SCPCR] = { 0x30, 16 },
217 [SCPDR] = { 0x34, 16 },
218 [SCDL] = sci_reg_invalid,
219 [SCCKS] = sci_reg_invalid,
220 },
221
222 /*
223 * Common SCIFB definitions.
224 */
225 [SCIx_SCIFB_REGTYPE] = {
226 [SCSMR] = { 0x00, 16 },
227 [SCBRR] = { 0x04, 8 },
228 [SCSCR] = { 0x08, 16 },
229 [SCxTDR] = { 0x40, 8 },
230 [SCxSR] = { 0x14, 16 },
231 [SCxRDR] = { 0x60, 8 },
232 [SCFCR] = { 0x18, 16 },
233 [SCFDR] = sci_reg_invalid,
234 [SCTFDR] = { 0x38, 16 },
235 [SCRFDR] = { 0x3c, 16 },
236 [SCSPTR] = sci_reg_invalid,
237 [SCLSR] = sci_reg_invalid,
238 [HSSRR] = sci_reg_invalid,
239 [SCPCR] = { 0x30, 16 },
240 [SCPDR] = { 0x34, 16 },
241 [SCDL] = sci_reg_invalid,
242 [SCCKS] = sci_reg_invalid,
243 },
244
245 /*
246 * Common SH-2(A) SCIF definitions for ports with FIFO data
247 * count registers.
248 */
249 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
250 [SCSMR] = { 0x00, 16 },
251 [SCBRR] = { 0x04, 8 },
252 [SCSCR] = { 0x08, 16 },
253 [SCxTDR] = { 0x0c, 8 },
254 [SCxSR] = { 0x10, 16 },
255 [SCxRDR] = { 0x14, 8 },
256 [SCFCR] = { 0x18, 16 },
257 [SCFDR] = { 0x1c, 16 },
258 [SCTFDR] = sci_reg_invalid,
259 [SCRFDR] = sci_reg_invalid,
260 [SCSPTR] = { 0x20, 16 },
261 [SCLSR] = { 0x24, 16 },
262 [HSSRR] = sci_reg_invalid,
263 [SCPCR] = sci_reg_invalid,
264 [SCPDR] = sci_reg_invalid,
265 [SCDL] = sci_reg_invalid,
266 [SCCKS] = sci_reg_invalid,
267 },
268
269 /*
270 * Common SH-3 SCIF definitions.
271 */
272 [SCIx_SH3_SCIF_REGTYPE] = {
273 [SCSMR] = { 0x00, 8 },
274 [SCBRR] = { 0x02, 8 },
275 [SCSCR] = { 0x04, 8 },
276 [SCxTDR] = { 0x06, 8 },
277 [SCxSR] = { 0x08, 16 },
278 [SCxRDR] = { 0x0a, 8 },
279 [SCFCR] = { 0x0c, 8 },
280 [SCFDR] = { 0x0e, 16 },
281 [SCTFDR] = sci_reg_invalid,
282 [SCRFDR] = sci_reg_invalid,
283 [SCSPTR] = sci_reg_invalid,
284 [SCLSR] = sci_reg_invalid,
285 [HSSRR] = sci_reg_invalid,
286 [SCPCR] = sci_reg_invalid,
287 [SCPDR] = sci_reg_invalid,
288 [SCDL] = sci_reg_invalid,
289 [SCCKS] = sci_reg_invalid,
290 },
291
292 /*
293 * Common SH-4(A) SCIF(B) definitions.
294 */
295 [SCIx_SH4_SCIF_REGTYPE] = {
296 [SCSMR] = { 0x00, 16 },
297 [SCBRR] = { 0x04, 8 },
298 [SCSCR] = { 0x08, 16 },
299 [SCxTDR] = { 0x0c, 8 },
300 [SCxSR] = { 0x10, 16 },
301 [SCxRDR] = { 0x14, 8 },
302 [SCFCR] = { 0x18, 16 },
303 [SCFDR] = { 0x1c, 16 },
304 [SCTFDR] = sci_reg_invalid,
305 [SCRFDR] = sci_reg_invalid,
306 [SCSPTR] = { 0x20, 16 },
307 [SCLSR] = { 0x24, 16 },
308 [HSSRR] = sci_reg_invalid,
309 [SCPCR] = sci_reg_invalid,
310 [SCPDR] = sci_reg_invalid,
311 [SCDL] = sci_reg_invalid,
312 [SCCKS] = sci_reg_invalid,
313 },
314
315 /*
316 * Common SCIF definitions for ports with a Baud Rate Generator for
317 * External Clock (BRG).
318 */
319 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
320 [SCSMR] = { 0x00, 16 },
321 [SCBRR] = { 0x04, 8 },
322 [SCSCR] = { 0x08, 16 },
323 [SCxTDR] = { 0x0c, 8 },
324 [SCxSR] = { 0x10, 16 },
325 [SCxRDR] = { 0x14, 8 },
326 [SCFCR] = { 0x18, 16 },
327 [SCFDR] = { 0x1c, 16 },
328 [SCTFDR] = sci_reg_invalid,
329 [SCRFDR] = sci_reg_invalid,
330 [SCSPTR] = { 0x20, 16 },
331 [SCLSR] = { 0x24, 16 },
332 [HSSRR] = sci_reg_invalid,
333 [SCPCR] = sci_reg_invalid,
334 [SCPDR] = sci_reg_invalid,
335 [SCDL] = { 0x30, 16 },
336 [SCCKS] = { 0x34, 16 },
337 },
338
339 /*
340 * Common HSCIF definitions.
341 */
342 [SCIx_HSCIF_REGTYPE] = {
343 [SCSMR] = { 0x00, 16 },
344 [SCBRR] = { 0x04, 8 },
345 [SCSCR] = { 0x08, 16 },
346 [SCxTDR] = { 0x0c, 8 },
347 [SCxSR] = { 0x10, 16 },
348 [SCxRDR] = { 0x14, 8 },
349 [SCFCR] = { 0x18, 16 },
350 [SCFDR] = { 0x1c, 16 },
351 [SCTFDR] = sci_reg_invalid,
352 [SCRFDR] = sci_reg_invalid,
353 [SCSPTR] = { 0x20, 16 },
354 [SCLSR] = { 0x24, 16 },
355 [HSSRR] = { 0x40, 16 },
356 [SCPCR] = sci_reg_invalid,
357 [SCPDR] = sci_reg_invalid,
358 [SCDL] = { 0x30, 16 },
359 [SCCKS] = { 0x34, 16 },
360 },
361
362 /*
363 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
364 * register.
365 */
366 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCTFDR] = sci_reg_invalid,
376 [SCRFDR] = sci_reg_invalid,
377 [SCSPTR] = sci_reg_invalid,
378 [SCLSR] = { 0x24, 16 },
379 [HSSRR] = sci_reg_invalid,
380 [SCPCR] = sci_reg_invalid,
381 [SCPDR] = sci_reg_invalid,
382 [SCDL] = sci_reg_invalid,
383 [SCCKS] = sci_reg_invalid,
384 },
385
386 /*
387 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
388 * count registers.
389 */
390 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
391 [SCSMR] = { 0x00, 16 },
392 [SCBRR] = { 0x04, 8 },
393 [SCSCR] = { 0x08, 16 },
394 [SCxTDR] = { 0x0c, 8 },
395 [SCxSR] = { 0x10, 16 },
396 [SCxRDR] = { 0x14, 8 },
397 [SCFCR] = { 0x18, 16 },
398 [SCFDR] = { 0x1c, 16 },
399 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
400 [SCRFDR] = { 0x20, 16 },
401 [SCSPTR] = { 0x24, 16 },
402 [SCLSR] = { 0x28, 16 },
403 [HSSRR] = sci_reg_invalid,
404 [SCPCR] = sci_reg_invalid,
405 [SCPDR] = sci_reg_invalid,
406 [SCDL] = sci_reg_invalid,
407 [SCCKS] = sci_reg_invalid,
408 },
409
410 /*
411 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
412 * registers.
413 */
414 [SCIx_SH7705_SCIF_REGTYPE] = {
415 [SCSMR] = { 0x00, 16 },
416 [SCBRR] = { 0x04, 8 },
417 [SCSCR] = { 0x08, 16 },
418 [SCxTDR] = { 0x20, 8 },
419 [SCxSR] = { 0x14, 16 },
420 [SCxRDR] = { 0x24, 8 },
421 [SCFCR] = { 0x18, 16 },
422 [SCFDR] = { 0x1c, 16 },
423 [SCTFDR] = sci_reg_invalid,
424 [SCRFDR] = sci_reg_invalid,
425 [SCSPTR] = sci_reg_invalid,
426 [SCLSR] = sci_reg_invalid,
427 [HSSRR] = sci_reg_invalid,
428 [SCPCR] = sci_reg_invalid,
429 [SCPDR] = sci_reg_invalid,
430 [SCDL] = sci_reg_invalid,
431 [SCCKS] = sci_reg_invalid,
432 },
433 };
434
435 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
436
437 /*
438 * The "offset" here is rather misleading, in that it refers to an enum
439 * value relative to the port mapping rather than the fixed offset
440 * itself, which needs to be manually retrieved from the platform's
441 * register map for the given port.
442 */
443 static unsigned int sci_serial_in(struct uart_port *p, int offset)
444 {
445 const struct plat_sci_reg *reg = sci_getreg(p, offset);
446
447 if (reg->size == 8)
448 return ioread8(p->membase + (reg->offset << p->regshift));
449 else if (reg->size == 16)
450 return ioread16(p->membase + (reg->offset << p->regshift));
451 else
452 WARN(1, "Invalid register access\n");
453
454 return 0;
455 }
456
457 static void sci_serial_out(struct uart_port *p, int offset, int value)
458 {
459 const struct plat_sci_reg *reg = sci_getreg(p, offset);
460
461 if (reg->size == 8)
462 iowrite8(value, p->membase + (reg->offset << p->regshift));
463 else if (reg->size == 16)
464 iowrite16(value, p->membase + (reg->offset << p->regshift));
465 else
466 WARN(1, "Invalid register access\n");
467 }
468
469 static int sci_probe_regmap(struct plat_sci_port *cfg)
470 {
471 switch (cfg->type) {
472 case PORT_SCI:
473 cfg->regtype = SCIx_SCI_REGTYPE;
474 break;
475 case PORT_IRDA:
476 cfg->regtype = SCIx_IRDA_REGTYPE;
477 break;
478 case PORT_SCIFA:
479 cfg->regtype = SCIx_SCIFA_REGTYPE;
480 break;
481 case PORT_SCIFB:
482 cfg->regtype = SCIx_SCIFB_REGTYPE;
483 break;
484 case PORT_SCIF:
485 /*
486 * The SH-4 is a bit of a misnomer here, although that's
487 * where this particular port layout originated. This
488 * configuration (or some slight variation thereof)
489 * remains the dominant model for all SCIFs.
490 */
491 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
492 break;
493 case PORT_HSCIF:
494 cfg->regtype = SCIx_HSCIF_REGTYPE;
495 break;
496 default:
497 pr_err("Can't probe register map for given port\n");
498 return -EINVAL;
499 }
500
501 return 0;
502 }
503
504 static void sci_port_enable(struct sci_port *sci_port)
505 {
506 unsigned int i;
507
508 if (!sci_port->port.dev)
509 return;
510
511 pm_runtime_get_sync(sci_port->port.dev);
512
513 for (i = 0; i < SCI_NUM_CLKS; i++) {
514 clk_prepare_enable(sci_port->clks[i]);
515 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
516 }
517 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
518 }
519
520 static void sci_port_disable(struct sci_port *sci_port)
521 {
522 unsigned int i;
523
524 if (!sci_port->port.dev)
525 return;
526
527 /* Cancel the break timer to ensure that the timer handler will not try
528 * to access the hardware with clocks and power disabled. Reset the
529 * break flag to make the break debouncing state machine ready for the
530 * next break.
531 */
532 del_timer_sync(&sci_port->break_timer);
533 sci_port->break_flag = 0;
534
535 for (i = SCI_NUM_CLKS; i-- > 0; )
536 clk_disable_unprepare(sci_port->clks[i]);
537
538 pm_runtime_put_sync(sci_port->port.dev);
539 }
540
541 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
542 {
543 /*
544 * Not all ports (such as SCIFA) will support REIE. Rather than
545 * special-casing the port type, we check the port initialization
546 * IRQ enable mask to see whether the IRQ is desired at all. If
547 * it's unset, it's logically inferred that there's no point in
548 * testing for it.
549 */
550 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
551 }
552
553 static void sci_start_tx(struct uart_port *port)
554 {
555 struct sci_port *s = to_sci_port(port);
556 unsigned short ctrl;
557
558 #ifdef CONFIG_SERIAL_SH_SCI_DMA
559 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
560 u16 new, scr = serial_port_in(port, SCSCR);
561 if (s->chan_tx)
562 new = scr | SCSCR_TDRQE;
563 else
564 new = scr & ~SCSCR_TDRQE;
565 if (new != scr)
566 serial_port_out(port, SCSCR, new);
567 }
568
569 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
570 dma_submit_error(s->cookie_tx)) {
571 s->cookie_tx = 0;
572 schedule_work(&s->work_tx);
573 }
574 #endif
575
576 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
577 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
578 ctrl = serial_port_in(port, SCSCR);
579 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
580 }
581 }
582
583 static void sci_stop_tx(struct uart_port *port)
584 {
585 unsigned short ctrl;
586
587 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
588 ctrl = serial_port_in(port, SCSCR);
589
590 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
591 ctrl &= ~SCSCR_TDRQE;
592
593 ctrl &= ~SCSCR_TIE;
594
595 serial_port_out(port, SCSCR, ctrl);
596 }
597
598 static void sci_start_rx(struct uart_port *port)
599 {
600 unsigned short ctrl;
601
602 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
603
604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
605 ctrl &= ~SCSCR_RDRQE;
606
607 serial_port_out(port, SCSCR, ctrl);
608 }
609
610 static void sci_stop_rx(struct uart_port *port)
611 {
612 unsigned short ctrl;
613
614 ctrl = serial_port_in(port, SCSCR);
615
616 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
617 ctrl &= ~SCSCR_RDRQE;
618
619 ctrl &= ~port_rx_irq_mask(port);
620
621 serial_port_out(port, SCSCR, ctrl);
622 }
623
624 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
625 {
626 if (port->type == PORT_SCI) {
627 /* Just store the mask */
628 serial_port_out(port, SCxSR, mask);
629 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
630 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
631 /* Only clear the status bits we want to clear */
632 serial_port_out(port, SCxSR,
633 serial_port_in(port, SCxSR) & mask);
634 } else {
635 /* Store the mask, clear parity/framing errors */
636 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
637 }
638 }
639
640 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
641 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
642
643 #ifdef CONFIG_CONSOLE_POLL
644 static int sci_poll_get_char(struct uart_port *port)
645 {
646 unsigned short status;
647 int c;
648
649 do {
650 status = serial_port_in(port, SCxSR);
651 if (status & SCxSR_ERRORS(port)) {
652 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
653 continue;
654 }
655 break;
656 } while (1);
657
658 if (!(status & SCxSR_RDxF(port)))
659 return NO_POLL_CHAR;
660
661 c = serial_port_in(port, SCxRDR);
662
663 /* Dummy read */
664 serial_port_in(port, SCxSR);
665 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
666
667 return c;
668 }
669 #endif
670
671 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
672 {
673 unsigned short status;
674
675 do {
676 status = serial_port_in(port, SCxSR);
677 } while (!(status & SCxSR_TDxE(port)));
678
679 serial_port_out(port, SCxTDR, c);
680 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
681 }
682 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
683 CONFIG_SERIAL_SH_SCI_EARLYCON */
684
685 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
686 {
687 struct sci_port *s = to_sci_port(port);
688 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
689
690 /*
691 * Use port-specific handler if provided.
692 */
693 if (s->cfg->ops && s->cfg->ops->init_pins) {
694 s->cfg->ops->init_pins(port, cflag);
695 return;
696 }
697
698 /*
699 * For the generic path SCSPTR is necessary. Bail out if that's
700 * unavailable, too.
701 */
702 if (!reg->size)
703 return;
704
705 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
706 ((!(cflag & CRTSCTS)))) {
707 unsigned short status;
708
709 status = serial_port_in(port, SCSPTR);
710 status &= ~SCSPTR_CTSIO;
711 status |= SCSPTR_RTSIO;
712 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
713 }
714 }
715
716 static int sci_txfill(struct uart_port *port)
717 {
718 const struct plat_sci_reg *reg;
719
720 reg = sci_getreg(port, SCTFDR);
721 if (reg->size)
722 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
723
724 reg = sci_getreg(port, SCFDR);
725 if (reg->size)
726 return serial_port_in(port, SCFDR) >> 8;
727
728 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
729 }
730
731 static int sci_txroom(struct uart_port *port)
732 {
733 return port->fifosize - sci_txfill(port);
734 }
735
736 static int sci_rxfill(struct uart_port *port)
737 {
738 const struct plat_sci_reg *reg;
739
740 reg = sci_getreg(port, SCRFDR);
741 if (reg->size)
742 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
743
744 reg = sci_getreg(port, SCFDR);
745 if (reg->size)
746 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
747
748 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
749 }
750
751 /*
752 * SCI helper for checking the state of the muxed port/RXD pins.
753 */
754 static inline int sci_rxd_in(struct uart_port *port)
755 {
756 struct sci_port *s = to_sci_port(port);
757
758 if (s->cfg->port_reg <= 0)
759 return 1;
760
761 /* Cast for ARM damage */
762 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
763 }
764
765 /* ********************************************************************** *
766 * the interrupt related routines *
767 * ********************************************************************** */
768
769 static void sci_transmit_chars(struct uart_port *port)
770 {
771 struct circ_buf *xmit = &port->state->xmit;
772 unsigned int stopped = uart_tx_stopped(port);
773 unsigned short status;
774 unsigned short ctrl;
775 int count;
776
777 status = serial_port_in(port, SCxSR);
778 if (!(status & SCxSR_TDxE(port))) {
779 ctrl = serial_port_in(port, SCSCR);
780 if (uart_circ_empty(xmit))
781 ctrl &= ~SCSCR_TIE;
782 else
783 ctrl |= SCSCR_TIE;
784 serial_port_out(port, SCSCR, ctrl);
785 return;
786 }
787
788 count = sci_txroom(port);
789
790 do {
791 unsigned char c;
792
793 if (port->x_char) {
794 c = port->x_char;
795 port->x_char = 0;
796 } else if (!uart_circ_empty(xmit) && !stopped) {
797 c = xmit->buf[xmit->tail];
798 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
799 } else {
800 break;
801 }
802
803 serial_port_out(port, SCxTDR, c);
804
805 port->icount.tx++;
806 } while (--count > 0);
807
808 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
809
810 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
811 uart_write_wakeup(port);
812 if (uart_circ_empty(xmit)) {
813 sci_stop_tx(port);
814 } else {
815 ctrl = serial_port_in(port, SCSCR);
816
817 if (port->type != PORT_SCI) {
818 serial_port_in(port, SCxSR); /* Dummy read */
819 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
820 }
821
822 ctrl |= SCSCR_TIE;
823 serial_port_out(port, SCSCR, ctrl);
824 }
825 }
826
827 /* On SH3, SCIF may read end-of-break as a space->mark char */
828 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
829
830 static void sci_receive_chars(struct uart_port *port)
831 {
832 struct sci_port *sci_port = to_sci_port(port);
833 struct tty_port *tport = &port->state->port;
834 int i, count, copied = 0;
835 unsigned short status;
836 unsigned char flag;
837
838 status = serial_port_in(port, SCxSR);
839 if (!(status & SCxSR_RDxF(port)))
840 return;
841
842 while (1) {
843 /* Don't copy more bytes than there is room for in the buffer */
844 count = tty_buffer_request_room(tport, sci_rxfill(port));
845
846 /* If for any reason we can't copy more data, we're done! */
847 if (count == 0)
848 break;
849
850 if (port->type == PORT_SCI) {
851 char c = serial_port_in(port, SCxRDR);
852 if (uart_handle_sysrq_char(port, c) ||
853 sci_port->break_flag)
854 count = 0;
855 else
856 tty_insert_flip_char(tport, c, TTY_NORMAL);
857 } else {
858 for (i = 0; i < count; i++) {
859 char c = serial_port_in(port, SCxRDR);
860
861 status = serial_port_in(port, SCxSR);
862 #if defined(CONFIG_CPU_SH3)
863 /* Skip "chars" during break */
864 if (sci_port->break_flag) {
865 if ((c == 0) &&
866 (status & SCxSR_FER(port))) {
867 count--; i--;
868 continue;
869 }
870
871 /* Nonzero => end-of-break */
872 dev_dbg(port->dev, "debounce<%02x>\n", c);
873 sci_port->break_flag = 0;
874
875 if (STEPFN(c)) {
876 count--; i--;
877 continue;
878 }
879 }
880 #endif /* CONFIG_CPU_SH3 */
881 if (uart_handle_sysrq_char(port, c)) {
882 count--; i--;
883 continue;
884 }
885
886 /* Store data and status */
887 if (status & SCxSR_FER(port)) {
888 flag = TTY_FRAME;
889 port->icount.frame++;
890 dev_notice(port->dev, "frame error\n");
891 } else if (status & SCxSR_PER(port)) {
892 flag = TTY_PARITY;
893 port->icount.parity++;
894 dev_notice(port->dev, "parity error\n");
895 } else
896 flag = TTY_NORMAL;
897
898 tty_insert_flip_char(tport, c, flag);
899 }
900 }
901
902 serial_port_in(port, SCxSR); /* dummy read */
903 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
904
905 copied += count;
906 port->icount.rx += count;
907 }
908
909 if (copied) {
910 /* Tell the rest of the system the news. New characters! */
911 tty_flip_buffer_push(tport);
912 } else {
913 serial_port_in(port, SCxSR); /* dummy read */
914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
915 }
916 }
917
918 #define SCI_BREAK_JIFFIES (HZ/20)
919
920 /*
921 * The sci generates interrupts during the break,
922 * 1 per millisecond or so during the break period, for 9600 baud.
923 * So dont bother disabling interrupts.
924 * But dont want more than 1 break event.
925 * Use a kernel timer to periodically poll the rx line until
926 * the break is finished.
927 */
928 static inline void sci_schedule_break_timer(struct sci_port *port)
929 {
930 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
931 }
932
933 /* Ensure that two consecutive samples find the break over. */
934 static void sci_break_timer(unsigned long data)
935 {
936 struct sci_port *port = (struct sci_port *)data;
937
938 if (sci_rxd_in(&port->port) == 0) {
939 port->break_flag = 1;
940 sci_schedule_break_timer(port);
941 } else if (port->break_flag == 1) {
942 /* break is over. */
943 port->break_flag = 2;
944 sci_schedule_break_timer(port);
945 } else
946 port->break_flag = 0;
947 }
948
949 static int sci_handle_errors(struct uart_port *port)
950 {
951 int copied = 0;
952 unsigned short status = serial_port_in(port, SCxSR);
953 struct tty_port *tport = &port->state->port;
954 struct sci_port *s = to_sci_port(port);
955
956 /* Handle overruns */
957 if (status & s->overrun_mask) {
958 port->icount.overrun++;
959
960 /* overrun error */
961 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
962 copied++;
963
964 dev_notice(port->dev, "overrun error\n");
965 }
966
967 if (status & SCxSR_FER(port)) {
968 if (sci_rxd_in(port) == 0) {
969 /* Notify of BREAK */
970 struct sci_port *sci_port = to_sci_port(port);
971
972 if (!sci_port->break_flag) {
973 port->icount.brk++;
974
975 sci_port->break_flag = 1;
976 sci_schedule_break_timer(sci_port);
977
978 /* Do sysrq handling. */
979 if (uart_handle_break(port))
980 return 0;
981
982 dev_dbg(port->dev, "BREAK detected\n");
983
984 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
985 copied++;
986 }
987
988 } else {
989 /* frame error */
990 port->icount.frame++;
991
992 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
993 copied++;
994
995 dev_notice(port->dev, "frame error\n");
996 }
997 }
998
999 if (status & SCxSR_PER(port)) {
1000 /* parity error */
1001 port->icount.parity++;
1002
1003 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1004 copied++;
1005
1006 dev_notice(port->dev, "parity error\n");
1007 }
1008
1009 if (copied)
1010 tty_flip_buffer_push(tport);
1011
1012 return copied;
1013 }
1014
1015 static int sci_handle_fifo_overrun(struct uart_port *port)
1016 {
1017 struct tty_port *tport = &port->state->port;
1018 struct sci_port *s = to_sci_port(port);
1019 const struct plat_sci_reg *reg;
1020 int copied = 0;
1021 u16 status;
1022
1023 reg = sci_getreg(port, s->overrun_reg);
1024 if (!reg->size)
1025 return 0;
1026
1027 status = serial_port_in(port, s->overrun_reg);
1028 if (status & s->overrun_mask) {
1029 status &= ~s->overrun_mask;
1030 serial_port_out(port, s->overrun_reg, status);
1031
1032 port->icount.overrun++;
1033
1034 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1035 tty_flip_buffer_push(tport);
1036
1037 dev_dbg(port->dev, "overrun error\n");
1038 copied++;
1039 }
1040
1041 return copied;
1042 }
1043
1044 static int sci_handle_breaks(struct uart_port *port)
1045 {
1046 int copied = 0;
1047 unsigned short status = serial_port_in(port, SCxSR);
1048 struct tty_port *tport = &port->state->port;
1049 struct sci_port *s = to_sci_port(port);
1050
1051 if (uart_handle_break(port))
1052 return 0;
1053
1054 if (!s->break_flag && status & SCxSR_BRK(port)) {
1055 #if defined(CONFIG_CPU_SH3)
1056 /* Debounce break */
1057 s->break_flag = 1;
1058 #endif
1059
1060 port->icount.brk++;
1061
1062 /* Notify of BREAK */
1063 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1064 copied++;
1065
1066 dev_dbg(port->dev, "BREAK detected\n");
1067 }
1068
1069 if (copied)
1070 tty_flip_buffer_push(tport);
1071
1072 copied += sci_handle_fifo_overrun(port);
1073
1074 return copied;
1075 }
1076
1077 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1078 static void sci_dma_tx_complete(void *arg)
1079 {
1080 struct sci_port *s = arg;
1081 struct uart_port *port = &s->port;
1082 struct circ_buf *xmit = &port->state->xmit;
1083 unsigned long flags;
1084
1085 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1086
1087 spin_lock_irqsave(&port->lock, flags);
1088
1089 xmit->tail += s->tx_dma_len;
1090 xmit->tail &= UART_XMIT_SIZE - 1;
1091
1092 port->icount.tx += s->tx_dma_len;
1093
1094 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1095 uart_write_wakeup(port);
1096
1097 if (!uart_circ_empty(xmit)) {
1098 s->cookie_tx = 0;
1099 schedule_work(&s->work_tx);
1100 } else {
1101 s->cookie_tx = -EINVAL;
1102 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1103 u16 ctrl = serial_port_in(port, SCSCR);
1104 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1105 }
1106 }
1107
1108 spin_unlock_irqrestore(&port->lock, flags);
1109 }
1110
1111 /* Locking: called with port lock held */
1112 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1113 {
1114 struct uart_port *port = &s->port;
1115 struct tty_port *tport = &port->state->port;
1116 int copied;
1117
1118 copied = tty_insert_flip_string(tport, buf, count);
1119 if (copied < count) {
1120 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1121 count - copied);
1122 port->icount.buf_overrun++;
1123 }
1124
1125 port->icount.rx += copied;
1126
1127 return copied;
1128 }
1129
1130 static int sci_dma_rx_find_active(struct sci_port *s)
1131 {
1132 unsigned int i;
1133
1134 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1135 if (s->active_rx == s->cookie_rx[i])
1136 return i;
1137
1138 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1139 s->active_rx);
1140 return -1;
1141 }
1142
1143 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1144 {
1145 struct dma_chan *chan = s->chan_rx;
1146 struct uart_port *port = &s->port;
1147 unsigned long flags;
1148
1149 spin_lock_irqsave(&port->lock, flags);
1150 s->chan_rx = NULL;
1151 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1152 spin_unlock_irqrestore(&port->lock, flags);
1153 dmaengine_terminate_all(chan);
1154 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1155 sg_dma_address(&s->sg_rx[0]));
1156 dma_release_channel(chan);
1157 if (enable_pio)
1158 sci_start_rx(port);
1159 }
1160
1161 static void sci_dma_rx_complete(void *arg)
1162 {
1163 struct sci_port *s = arg;
1164 struct dma_chan *chan = s->chan_rx;
1165 struct uart_port *port = &s->port;
1166 struct dma_async_tx_descriptor *desc;
1167 unsigned long flags;
1168 int active, count = 0;
1169
1170 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1171 s->active_rx);
1172
1173 spin_lock_irqsave(&port->lock, flags);
1174
1175 active = sci_dma_rx_find_active(s);
1176 if (active >= 0)
1177 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1178
1179 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1180
1181 if (count)
1182 tty_flip_buffer_push(&port->state->port);
1183
1184 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1185 DMA_DEV_TO_MEM,
1186 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1187 if (!desc)
1188 goto fail;
1189
1190 desc->callback = sci_dma_rx_complete;
1191 desc->callback_param = s;
1192 s->cookie_rx[active] = dmaengine_submit(desc);
1193 if (dma_submit_error(s->cookie_rx[active]))
1194 goto fail;
1195
1196 s->active_rx = s->cookie_rx[!active];
1197
1198 dma_async_issue_pending(chan);
1199
1200 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1201 __func__, s->cookie_rx[active], active, s->active_rx);
1202 spin_unlock_irqrestore(&port->lock, flags);
1203 return;
1204
1205 fail:
1206 spin_unlock_irqrestore(&port->lock, flags);
1207 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1208 sci_rx_dma_release(s, true);
1209 }
1210
1211 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1212 {
1213 struct dma_chan *chan = s->chan_tx;
1214 struct uart_port *port = &s->port;
1215 unsigned long flags;
1216
1217 spin_lock_irqsave(&port->lock, flags);
1218 s->chan_tx = NULL;
1219 s->cookie_tx = -EINVAL;
1220 spin_unlock_irqrestore(&port->lock, flags);
1221 dmaengine_terminate_all(chan);
1222 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1223 DMA_TO_DEVICE);
1224 dma_release_channel(chan);
1225 if (enable_pio)
1226 sci_start_tx(port);
1227 }
1228
1229 static void sci_submit_rx(struct sci_port *s)
1230 {
1231 struct dma_chan *chan = s->chan_rx;
1232 int i;
1233
1234 for (i = 0; i < 2; i++) {
1235 struct scatterlist *sg = &s->sg_rx[i];
1236 struct dma_async_tx_descriptor *desc;
1237
1238 desc = dmaengine_prep_slave_sg(chan,
1239 sg, 1, DMA_DEV_TO_MEM,
1240 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1241 if (!desc)
1242 goto fail;
1243
1244 desc->callback = sci_dma_rx_complete;
1245 desc->callback_param = s;
1246 s->cookie_rx[i] = dmaengine_submit(desc);
1247 if (dma_submit_error(s->cookie_rx[i]))
1248 goto fail;
1249
1250 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1251 s->cookie_rx[i], i);
1252 }
1253
1254 s->active_rx = s->cookie_rx[0];
1255
1256 dma_async_issue_pending(chan);
1257 return;
1258
1259 fail:
1260 if (i)
1261 dmaengine_terminate_all(chan);
1262 for (i = 0; i < 2; i++)
1263 s->cookie_rx[i] = -EINVAL;
1264 s->active_rx = -EINVAL;
1265 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1266 sci_rx_dma_release(s, true);
1267 }
1268
1269 static void work_fn_tx(struct work_struct *work)
1270 {
1271 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1272 struct dma_async_tx_descriptor *desc;
1273 struct dma_chan *chan = s->chan_tx;
1274 struct uart_port *port = &s->port;
1275 struct circ_buf *xmit = &port->state->xmit;
1276 dma_addr_t buf;
1277
1278 /*
1279 * DMA is idle now.
1280 * Port xmit buffer is already mapped, and it is one page... Just adjust
1281 * offsets and lengths. Since it is a circular buffer, we have to
1282 * transmit till the end, and then the rest. Take the port lock to get a
1283 * consistent xmit buffer state.
1284 */
1285 spin_lock_irq(&port->lock);
1286 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1287 s->tx_dma_len = min_t(unsigned int,
1288 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1289 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1290 spin_unlock_irq(&port->lock);
1291
1292 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1293 DMA_MEM_TO_DEV,
1294 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1295 if (!desc) {
1296 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1297 /* switch to PIO */
1298 sci_tx_dma_release(s, true);
1299 return;
1300 }
1301
1302 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1303 DMA_TO_DEVICE);
1304
1305 spin_lock_irq(&port->lock);
1306 desc->callback = sci_dma_tx_complete;
1307 desc->callback_param = s;
1308 spin_unlock_irq(&port->lock);
1309 s->cookie_tx = dmaengine_submit(desc);
1310 if (dma_submit_error(s->cookie_tx)) {
1311 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1312 /* switch to PIO */
1313 sci_tx_dma_release(s, true);
1314 return;
1315 }
1316
1317 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1318 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1319
1320 dma_async_issue_pending(chan);
1321 }
1322
1323 static void rx_timer_fn(unsigned long arg)
1324 {
1325 struct sci_port *s = (struct sci_port *)arg;
1326 struct dma_chan *chan = s->chan_rx;
1327 struct uart_port *port = &s->port;
1328 struct dma_tx_state state;
1329 enum dma_status status;
1330 unsigned long flags;
1331 unsigned int read;
1332 int active, count;
1333 u16 scr;
1334
1335 spin_lock_irqsave(&port->lock, flags);
1336
1337 dev_dbg(port->dev, "DMA Rx timed out\n");
1338
1339 active = sci_dma_rx_find_active(s);
1340 if (active < 0) {
1341 spin_unlock_irqrestore(&port->lock, flags);
1342 return;
1343 }
1344
1345 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1346 if (status == DMA_COMPLETE) {
1347 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1348 s->active_rx, active);
1349 spin_unlock_irqrestore(&port->lock, flags);
1350
1351 /* Let packet complete handler take care of the packet */
1352 return;
1353 }
1354
1355 dmaengine_pause(chan);
1356
1357 /*
1358 * sometimes DMA transfer doesn't stop even if it is stopped and
1359 * data keeps on coming until transaction is complete so check
1360 * for DMA_COMPLETE again
1361 * Let packet complete handler take care of the packet
1362 */
1363 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1364 if (status == DMA_COMPLETE) {
1365 spin_unlock_irqrestore(&port->lock, flags);
1366 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1367 return;
1368 }
1369
1370 /* Handle incomplete DMA receive */
1371 dmaengine_terminate_all(s->chan_rx);
1372 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1373 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1374 s->active_rx);
1375
1376 if (read) {
1377 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1378 if (count)
1379 tty_flip_buffer_push(&port->state->port);
1380 }
1381
1382 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1383 sci_submit_rx(s);
1384
1385 /* Direct new serial port interrupts back to CPU */
1386 scr = serial_port_in(port, SCSCR);
1387 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1388 scr &= ~SCSCR_RDRQE;
1389 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1390 }
1391 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1392
1393 spin_unlock_irqrestore(&port->lock, flags);
1394 }
1395
1396 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1397 enum dma_transfer_direction dir,
1398 unsigned int id)
1399 {
1400 dma_cap_mask_t mask;
1401 struct dma_chan *chan;
1402 struct dma_slave_config cfg;
1403 int ret;
1404
1405 dma_cap_zero(mask);
1406 dma_cap_set(DMA_SLAVE, mask);
1407
1408 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1409 (void *)(unsigned long)id, port->dev,
1410 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1411 if (!chan) {
1412 dev_warn(port->dev,
1413 "dma_request_slave_channel_compat failed\n");
1414 return NULL;
1415 }
1416
1417 memset(&cfg, 0, sizeof(cfg));
1418 cfg.direction = dir;
1419 if (dir == DMA_MEM_TO_DEV) {
1420 cfg.dst_addr = port->mapbase +
1421 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1422 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1423 } else {
1424 cfg.src_addr = port->mapbase +
1425 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1426 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1427 }
1428
1429 ret = dmaengine_slave_config(chan, &cfg);
1430 if (ret) {
1431 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1432 dma_release_channel(chan);
1433 return NULL;
1434 }
1435
1436 return chan;
1437 }
1438
1439 static void sci_request_dma(struct uart_port *port)
1440 {
1441 struct sci_port *s = to_sci_port(port);
1442 struct dma_chan *chan;
1443
1444 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1445
1446 if (!port->dev->of_node &&
1447 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1448 return;
1449
1450 s->cookie_tx = -EINVAL;
1451 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1452 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1453 if (chan) {
1454 s->chan_tx = chan;
1455 /* UART circular tx buffer is an aligned page. */
1456 s->tx_dma_addr = dma_map_single(chan->device->dev,
1457 port->state->xmit.buf,
1458 UART_XMIT_SIZE,
1459 DMA_TO_DEVICE);
1460 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1461 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1462 dma_release_channel(chan);
1463 s->chan_tx = NULL;
1464 } else {
1465 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1466 __func__, UART_XMIT_SIZE,
1467 port->state->xmit.buf, &s->tx_dma_addr);
1468 }
1469
1470 INIT_WORK(&s->work_tx, work_fn_tx);
1471 }
1472
1473 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1474 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1475 if (chan) {
1476 unsigned int i;
1477 dma_addr_t dma;
1478 void *buf;
1479
1480 s->chan_rx = chan;
1481
1482 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1483 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1484 &dma, GFP_KERNEL);
1485 if (!buf) {
1486 dev_warn(port->dev,
1487 "Failed to allocate Rx dma buffer, using PIO\n");
1488 dma_release_channel(chan);
1489 s->chan_rx = NULL;
1490 return;
1491 }
1492
1493 for (i = 0; i < 2; i++) {
1494 struct scatterlist *sg = &s->sg_rx[i];
1495
1496 sg_init_table(sg, 1);
1497 s->rx_buf[i] = buf;
1498 sg_dma_address(sg) = dma;
1499 sg_dma_len(sg) = s->buf_len_rx;
1500
1501 buf += s->buf_len_rx;
1502 dma += s->buf_len_rx;
1503 }
1504
1505 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1506
1507 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1508 sci_submit_rx(s);
1509 }
1510 }
1511
1512 static void sci_free_dma(struct uart_port *port)
1513 {
1514 struct sci_port *s = to_sci_port(port);
1515
1516 if (s->chan_tx)
1517 sci_tx_dma_release(s, false);
1518 if (s->chan_rx)
1519 sci_rx_dma_release(s, false);
1520 }
1521 #else
1522 static inline void sci_request_dma(struct uart_port *port)
1523 {
1524 }
1525
1526 static inline void sci_free_dma(struct uart_port *port)
1527 {
1528 }
1529 #endif
1530
1531 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1532 {
1533 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1534 struct uart_port *port = ptr;
1535 struct sci_port *s = to_sci_port(port);
1536
1537 if (s->chan_rx) {
1538 u16 scr = serial_port_in(port, SCSCR);
1539 u16 ssr = serial_port_in(port, SCxSR);
1540
1541 /* Disable future Rx interrupts */
1542 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1543 disable_irq_nosync(irq);
1544 scr |= SCSCR_RDRQE;
1545 } else {
1546 scr &= ~SCSCR_RIE;
1547 sci_submit_rx(s);
1548 }
1549 serial_port_out(port, SCSCR, scr);
1550 /* Clear current interrupt */
1551 serial_port_out(port, SCxSR,
1552 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1553 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1554 jiffies, s->rx_timeout);
1555 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1556
1557 return IRQ_HANDLED;
1558 }
1559 #endif
1560
1561 /* I think sci_receive_chars has to be called irrespective
1562 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1563 * to be disabled?
1564 */
1565 sci_receive_chars(ptr);
1566
1567 return IRQ_HANDLED;
1568 }
1569
1570 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1571 {
1572 struct uart_port *port = ptr;
1573 unsigned long flags;
1574
1575 spin_lock_irqsave(&port->lock, flags);
1576 sci_transmit_chars(port);
1577 spin_unlock_irqrestore(&port->lock, flags);
1578
1579 return IRQ_HANDLED;
1580 }
1581
1582 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1583 {
1584 struct uart_port *port = ptr;
1585 struct sci_port *s = to_sci_port(port);
1586
1587 /* Handle errors */
1588 if (port->type == PORT_SCI) {
1589 if (sci_handle_errors(port)) {
1590 /* discard character in rx buffer */
1591 serial_port_in(port, SCxSR);
1592 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1593 }
1594 } else {
1595 sci_handle_fifo_overrun(port);
1596 if (!s->chan_rx)
1597 sci_receive_chars(ptr);
1598 }
1599
1600 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1601
1602 /* Kick the transmission */
1603 if (!s->chan_tx)
1604 sci_tx_interrupt(irq, ptr);
1605
1606 return IRQ_HANDLED;
1607 }
1608
1609 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1610 {
1611 struct uart_port *port = ptr;
1612
1613 /* Handle BREAKs */
1614 sci_handle_breaks(port);
1615 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1616
1617 return IRQ_HANDLED;
1618 }
1619
1620 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1621 {
1622 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1623 struct uart_port *port = ptr;
1624 struct sci_port *s = to_sci_port(port);
1625 irqreturn_t ret = IRQ_NONE;
1626
1627 ssr_status = serial_port_in(port, SCxSR);
1628 scr_status = serial_port_in(port, SCSCR);
1629 if (s->overrun_reg == SCxSR)
1630 orer_status = ssr_status;
1631 else {
1632 if (sci_getreg(port, s->overrun_reg)->size)
1633 orer_status = serial_port_in(port, s->overrun_reg);
1634 }
1635
1636 err_enabled = scr_status & port_rx_irq_mask(port);
1637
1638 /* Tx Interrupt */
1639 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1640 !s->chan_tx)
1641 ret = sci_tx_interrupt(irq, ptr);
1642
1643 /*
1644 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1645 * DR flags
1646 */
1647 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1648 (scr_status & SCSCR_RIE))
1649 ret = sci_rx_interrupt(irq, ptr);
1650
1651 /* Error Interrupt */
1652 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1653 ret = sci_er_interrupt(irq, ptr);
1654
1655 /* Break Interrupt */
1656 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1657 ret = sci_br_interrupt(irq, ptr);
1658
1659 /* Overrun Interrupt */
1660 if (orer_status & s->overrun_mask) {
1661 sci_handle_fifo_overrun(port);
1662 ret = IRQ_HANDLED;
1663 }
1664
1665 return ret;
1666 }
1667
1668 static const struct sci_irq_desc {
1669 const char *desc;
1670 irq_handler_t handler;
1671 } sci_irq_desc[] = {
1672 /*
1673 * Split out handlers, the default case.
1674 */
1675 [SCIx_ERI_IRQ] = {
1676 .desc = "rx err",
1677 .handler = sci_er_interrupt,
1678 },
1679
1680 [SCIx_RXI_IRQ] = {
1681 .desc = "rx full",
1682 .handler = sci_rx_interrupt,
1683 },
1684
1685 [SCIx_TXI_IRQ] = {
1686 .desc = "tx empty",
1687 .handler = sci_tx_interrupt,
1688 },
1689
1690 [SCIx_BRI_IRQ] = {
1691 .desc = "break",
1692 .handler = sci_br_interrupt,
1693 },
1694
1695 /*
1696 * Special muxed handler.
1697 */
1698 [SCIx_MUX_IRQ] = {
1699 .desc = "mux",
1700 .handler = sci_mpxed_interrupt,
1701 },
1702 };
1703
1704 static int sci_request_irq(struct sci_port *port)
1705 {
1706 struct uart_port *up = &port->port;
1707 int i, j, ret = 0;
1708
1709 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1710 const struct sci_irq_desc *desc;
1711 int irq;
1712
1713 if (SCIx_IRQ_IS_MUXED(port)) {
1714 i = SCIx_MUX_IRQ;
1715 irq = up->irq;
1716 } else {
1717 irq = port->irqs[i];
1718
1719 /*
1720 * Certain port types won't support all of the
1721 * available interrupt sources.
1722 */
1723 if (unlikely(irq < 0))
1724 continue;
1725 }
1726
1727 desc = sci_irq_desc + i;
1728 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1729 dev_name(up->dev), desc->desc);
1730 if (!port->irqstr[j])
1731 goto out_nomem;
1732
1733 ret = request_irq(irq, desc->handler, up->irqflags,
1734 port->irqstr[j], port);
1735 if (unlikely(ret)) {
1736 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1737 goto out_noirq;
1738 }
1739 }
1740
1741 return 0;
1742
1743 out_noirq:
1744 while (--i >= 0)
1745 free_irq(port->irqs[i], port);
1746
1747 out_nomem:
1748 while (--j >= 0)
1749 kfree(port->irqstr[j]);
1750
1751 return ret;
1752 }
1753
1754 static void sci_free_irq(struct sci_port *port)
1755 {
1756 int i;
1757
1758 /*
1759 * Intentionally in reverse order so we iterate over the muxed
1760 * IRQ first.
1761 */
1762 for (i = 0; i < SCIx_NR_IRQS; i++) {
1763 int irq = port->irqs[i];
1764
1765 /*
1766 * Certain port types won't support all of the available
1767 * interrupt sources.
1768 */
1769 if (unlikely(irq < 0))
1770 continue;
1771
1772 free_irq(port->irqs[i], port);
1773 kfree(port->irqstr[i]);
1774
1775 if (SCIx_IRQ_IS_MUXED(port)) {
1776 /* If there's only one IRQ, we're done. */
1777 return;
1778 }
1779 }
1780 }
1781
1782 static unsigned int sci_tx_empty(struct uart_port *port)
1783 {
1784 unsigned short status = serial_port_in(port, SCxSR);
1785 unsigned short in_tx_fifo = sci_txfill(port);
1786
1787 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1788 }
1789
1790 /*
1791 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1792 * CTS/RTS is supported in hardware by at least one port and controlled
1793 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1794 * handled via the ->init_pins() op, which is a bit of a one-way street,
1795 * lacking any ability to defer pin control -- this will later be
1796 * converted over to the GPIO framework).
1797 *
1798 * Other modes (such as loopback) are supported generically on certain
1799 * port types, but not others. For these it's sufficient to test for the
1800 * existence of the support register and simply ignore the port type.
1801 */
1802 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1803 {
1804 if (mctrl & TIOCM_LOOP) {
1805 const struct plat_sci_reg *reg;
1806
1807 /*
1808 * Standard loopback mode for SCFCR ports.
1809 */
1810 reg = sci_getreg(port, SCFCR);
1811 if (reg->size)
1812 serial_port_out(port, SCFCR,
1813 serial_port_in(port, SCFCR) |
1814 SCFCR_LOOP);
1815 }
1816 }
1817
1818 static unsigned int sci_get_mctrl(struct uart_port *port)
1819 {
1820 /*
1821 * CTS/RTS is handled in hardware when supported, while nothing
1822 * else is wired up. Keep it simple and simply assert DSR/CAR.
1823 */
1824 return TIOCM_DSR | TIOCM_CAR;
1825 }
1826
1827 static void sci_break_ctl(struct uart_port *port, int break_state)
1828 {
1829 struct sci_port *s = to_sci_port(port);
1830 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1831 unsigned short scscr, scsptr;
1832
1833 /* check wheter the port has SCSPTR */
1834 if (!reg->size) {
1835 /*
1836 * Not supported by hardware. Most parts couple break and rx
1837 * interrupts together, with break detection always enabled.
1838 */
1839 return;
1840 }
1841
1842 scsptr = serial_port_in(port, SCSPTR);
1843 scscr = serial_port_in(port, SCSCR);
1844
1845 if (break_state == -1) {
1846 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1847 scscr &= ~SCSCR_TE;
1848 } else {
1849 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1850 scscr |= SCSCR_TE;
1851 }
1852
1853 serial_port_out(port, SCSPTR, scsptr);
1854 serial_port_out(port, SCSCR, scscr);
1855 }
1856
1857 static int sci_startup(struct uart_port *port)
1858 {
1859 struct sci_port *s = to_sci_port(port);
1860 unsigned long flags;
1861 int ret;
1862
1863 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1864
1865 ret = sci_request_irq(s);
1866 if (unlikely(ret < 0))
1867 return ret;
1868
1869 sci_request_dma(port);
1870
1871 spin_lock_irqsave(&port->lock, flags);
1872 sci_start_tx(port);
1873 sci_start_rx(port);
1874 spin_unlock_irqrestore(&port->lock, flags);
1875
1876 return 0;
1877 }
1878
1879 static void sci_shutdown(struct uart_port *port)
1880 {
1881 struct sci_port *s = to_sci_port(port);
1882 unsigned long flags;
1883
1884 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1885
1886 spin_lock_irqsave(&port->lock, flags);
1887 sci_stop_rx(port);
1888 sci_stop_tx(port);
1889 spin_unlock_irqrestore(&port->lock, flags);
1890
1891 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1892 if (s->chan_rx) {
1893 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1894 port->line);
1895 del_timer_sync(&s->rx_timer);
1896 }
1897 #endif
1898
1899 sci_free_dma(port);
1900 sci_free_irq(s);
1901 }
1902
1903 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1904 unsigned int *srr)
1905 {
1906 unsigned long freq = s->clk_rates[SCI_SCK];
1907 unsigned int min_sr, max_sr, sr;
1908 int err, min_err = INT_MAX;
1909
1910 if (s->port.type != PORT_HSCIF)
1911 freq *= 2;
1912 if (s->sampling_rate) {
1913 /* SCI(F) has a fixed sampling rate */
1914 min_sr = max_sr = s->sampling_rate;
1915 } else {
1916 /* HSCIF has a variable 1/(8..32) sampling rate */
1917 min_sr = 8;
1918 max_sr = 32;
1919 }
1920
1921 for (sr = max_sr; sr >= min_sr; sr--) {
1922 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1923 if (abs(err) >= abs(min_err))
1924 continue;
1925
1926 min_err = err;
1927 *srr = sr - 1;
1928
1929 if (!err)
1930 break;
1931 }
1932
1933 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1934 *srr + 1);
1935 return min_err;
1936 }
1937
1938 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1939 unsigned long freq, unsigned int *dlr,
1940 unsigned int *srr)
1941 {
1942 unsigned int min_sr, max_sr, sr, dl;
1943 int err, min_err = INT_MAX;
1944
1945 if (s->port.type != PORT_HSCIF)
1946 freq *= 2;
1947 if (s->sampling_rate) {
1948 /* SCIF has a fixed sampling rate */
1949 min_sr = max_sr = s->sampling_rate;
1950 } else {
1951 /* HSCIF has a variable 1/(8..32) sampling rate */
1952 min_sr = 8;
1953 max_sr = 32;
1954 }
1955
1956 for (sr = max_sr; sr >= min_sr; sr--) {
1957 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1958 dl = clamp(dl, 1U, 65535U);
1959
1960 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1961 if (abs(err) >= abs(min_err))
1962 continue;
1963
1964 min_err = err;
1965 *dlr = dl;
1966 *srr = sr - 1;
1967
1968 if (!err)
1969 break;
1970 }
1971
1972 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
1973 min_err, *dlr, *srr + 1);
1974 return min_err;
1975 }
1976
1977 /* calculate sample rate, BRR, and clock select */
1978 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1979 unsigned int *brr, unsigned int *srr,
1980 unsigned int *cks)
1981 {
1982 unsigned int min_sr, max_sr, sr, br, prediv, scrate, c;
1983 unsigned long freq = s->clk_rates[SCI_FCK];
1984 int err, min_err = INT_MAX;
1985
1986 if (s->port.type != PORT_HSCIF)
1987 freq *= 2;
1988 if (s->sampling_rate) {
1989 min_sr = max_sr = s->sampling_rate;
1990 } else {
1991 /* HSCIF has a variable sample rate */
1992 min_sr = 8;
1993 max_sr = 32;
1994 }
1995
1996 /*
1997 * Find the combination of sample rate and clock select with the
1998 * smallest deviation from the desired baud rate.
1999 * Prefer high sample rates to maximise the receive margin.
2000 *
2001 * M: Receive margin (%)
2002 * N: Ratio of bit rate to clock (N = sampling rate)
2003 * D: Clock duty (D = 0 to 1.0)
2004 * L: Frame length (L = 9 to 12)
2005 * F: Absolute value of clock frequency deviation
2006 *
2007 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2008 * (|D - 0.5| / N * (1 + F))|
2009 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2010 */
2011 for (sr = max_sr; sr >= min_sr; sr--) {
2012 for (c = 0; c <= 3; c++) {
2013 /* integerized formulas from HSCIF documentation */
2014 prediv = sr * (1 << (2 * c + 1));
2015
2016 /*
2017 * We need to calculate:
2018 *
2019 * br = freq / (prediv * bps) clamped to [1..256]
2020 * err = freq / (br * prediv) - bps
2021 *
2022 * Watch out for overflow when calculating the desired
2023 * sampling clock rate!
2024 */
2025 if (bps > UINT_MAX / prediv)
2026 break;
2027
2028 scrate = prediv * bps;
2029 br = DIV_ROUND_CLOSEST(freq, scrate);
2030 br = clamp(br, 1U, 256U);
2031
2032 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2033 if (abs(err) >= abs(min_err))
2034 continue;
2035
2036 min_err = err;
2037 *brr = br - 1;
2038 *srr = sr - 1;
2039 *cks = c;
2040
2041 if (!err)
2042 goto found;
2043 }
2044 }
2045
2046 found:
2047 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2048 min_err, *brr, *srr + 1, *cks);
2049 return min_err;
2050 }
2051
2052 static void sci_reset(struct uart_port *port)
2053 {
2054 const struct plat_sci_reg *reg;
2055 unsigned int status;
2056
2057 do {
2058 status = serial_port_in(port, SCxSR);
2059 } while (!(status & SCxSR_TEND(port)));
2060
2061 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2062
2063 reg = sci_getreg(port, SCFCR);
2064 if (reg->size)
2065 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2066 }
2067
2068 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2069 struct ktermios *old)
2070 {
2071 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
2072 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2073 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2074 struct sci_port *s = to_sci_port(port);
2075 const struct plat_sci_reg *reg;
2076 int min_err = INT_MAX, err;
2077 unsigned long max_freq = 0;
2078 int best_clk = -1;
2079
2080 if ((termios->c_cflag & CSIZE) == CS7)
2081 smr_val |= SCSMR_CHR;
2082 if (termios->c_cflag & PARENB)
2083 smr_val |= SCSMR_PE;
2084 if (termios->c_cflag & PARODD)
2085 smr_val |= SCSMR_PE | SCSMR_ODD;
2086 if (termios->c_cflag & CSTOPB)
2087 smr_val |= SCSMR_STOP;
2088
2089 /*
2090 * earlyprintk comes here early on with port->uartclk set to zero.
2091 * the clock framework is not up and running at this point so here
2092 * we assume that 115200 is the maximum baud rate. please note that
2093 * the baud rate is not programmed during earlyprintk - it is assumed
2094 * that the previous boot loader has enabled required clocks and
2095 * setup the baud rate generator hardware for us already.
2096 */
2097 if (!port->uartclk) {
2098 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2099 goto done;
2100 }
2101
2102 for (i = 0; i < SCI_NUM_CLKS; i++)
2103 max_freq = max(max_freq, s->clk_rates[i]);
2104
2105 baud = uart_get_baud_rate(port, termios, old, 0,
2106 max_freq / max(s->sampling_rate, 8U));
2107 if (!baud)
2108 goto done;
2109
2110 /*
2111 * There can be multiple sources for the sampling clock. Find the one
2112 * that gives us the smallest deviation from the desired baud rate.
2113 */
2114
2115 /* Optional Undivided External Clock */
2116 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2117 port->type != PORT_SCIFB) {
2118 err = sci_sck_calc(s, baud, &srr1);
2119 if (abs(err) < abs(min_err)) {
2120 best_clk = SCI_SCK;
2121 scr_val = SCSCR_CKE1;
2122 sccks = SCCKS_CKS;
2123 min_err = err;
2124 srr = srr1;
2125 if (!err)
2126 goto done;
2127 }
2128 }
2129
2130 /* Optional BRG Frequency Divided External Clock */
2131 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2132 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2133 &srr1);
2134 if (abs(err) < abs(min_err)) {
2135 best_clk = SCI_SCIF_CLK;
2136 scr_val = SCSCR_CKE1;
2137 sccks = 0;
2138 min_err = err;
2139 dl = dl1;
2140 srr = srr1;
2141 if (!err)
2142 goto done;
2143 }
2144 }
2145
2146 /* Optional BRG Frequency Divided Internal Clock */
2147 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2148 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2149 &srr1);
2150 if (abs(err) < abs(min_err)) {
2151 best_clk = SCI_BRG_INT;
2152 scr_val = SCSCR_CKE1;
2153 sccks = SCCKS_XIN;
2154 min_err = err;
2155 dl = dl1;
2156 srr = srr1;
2157 if (!min_err)
2158 goto done;
2159 }
2160 }
2161
2162 /* Divided Functional Clock using standard Bit Rate Register */
2163 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2164 if (abs(err) < abs(min_err)) {
2165 best_clk = SCI_FCK;
2166 scr_val = 0;
2167 min_err = err;
2168 brr = brr1;
2169 srr = srr1;
2170 cks = cks1;
2171 }
2172
2173 done:
2174 if (best_clk >= 0)
2175 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2176 s->clks[best_clk], baud, min_err);
2177
2178 sci_port_enable(s);
2179
2180 /*
2181 * Program the optional External Baud Rate Generator (BRG) first.
2182 * It controls the mux to select (H)SCK or frequency divided clock.
2183 */
2184 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2185 serial_port_out(port, SCDL, dl);
2186 serial_port_out(port, SCCKS, sccks);
2187 }
2188
2189 sci_reset(port);
2190
2191 uart_update_timeout(port, termios->c_cflag, baud);
2192
2193 if (best_clk >= 0) {
2194 smr_val |= cks;
2195 dev_dbg(port->dev,
2196 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2197 scr_val, smr_val, brr, sccks, dl, srr);
2198 serial_port_out(port, SCSCR, scr_val);
2199 serial_port_out(port, SCSMR, smr_val);
2200 serial_port_out(port, SCBRR, brr);
2201 if (sci_getreg(port, HSSRR)->size)
2202 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2203
2204 /* Wait one bit interval */
2205 udelay((1000000 + (baud - 1)) / baud);
2206 } else {
2207 /* Don't touch the bit rate configuration */
2208 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2209 smr_val |= serial_port_in(port, SCSMR) &
2210 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2211 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2212 serial_port_out(port, SCSCR, scr_val);
2213 serial_port_out(port, SCSMR, smr_val);
2214 }
2215
2216 sci_init_pins(port, termios->c_cflag);
2217
2218 reg = sci_getreg(port, SCFCR);
2219 if (reg->size) {
2220 unsigned short ctrl = serial_port_in(port, SCFCR);
2221
2222 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2223 if (termios->c_cflag & CRTSCTS)
2224 ctrl |= SCFCR_MCE;
2225 else
2226 ctrl &= ~SCFCR_MCE;
2227 }
2228
2229 /*
2230 * As we've done a sci_reset() above, ensure we don't
2231 * interfere with the FIFOs while toggling MCE. As the
2232 * reset values could still be set, simply mask them out.
2233 */
2234 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2235
2236 serial_port_out(port, SCFCR, ctrl);
2237 }
2238
2239 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2240 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2241 serial_port_out(port, SCSCR, scr_val);
2242
2243 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2244 /*
2245 * Calculate delay for 2 DMA buffers (4 FIFO).
2246 * See serial_core.c::uart_update_timeout().
2247 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2248 * function calculates 1 jiffie for the data plus 5 jiffies for the
2249 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2250 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2251 * value obtained by this formula is too small. Therefore, if the value
2252 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2253 */
2254 if (s->chan_rx) {
2255 unsigned int bits;
2256
2257 /* byte size and parity */
2258 switch (termios->c_cflag & CSIZE) {
2259 case CS5:
2260 bits = 7;
2261 break;
2262 case CS6:
2263 bits = 8;
2264 break;
2265 case CS7:
2266 bits = 9;
2267 break;
2268 default:
2269 bits = 10;
2270 break;
2271 }
2272
2273 if (termios->c_cflag & CSTOPB)
2274 bits++;
2275 if (termios->c_cflag & PARENB)
2276 bits++;
2277 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2278 (baud / 10), 10);
2279 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2280 s->rx_timeout * 1000 / HZ, port->timeout);
2281 if (s->rx_timeout < msecs_to_jiffies(20))
2282 s->rx_timeout = msecs_to_jiffies(20);
2283 }
2284 #endif
2285
2286 if ((termios->c_cflag & CREAD) != 0)
2287 sci_start_rx(port);
2288
2289 sci_port_disable(s);
2290 }
2291
2292 static void sci_pm(struct uart_port *port, unsigned int state,
2293 unsigned int oldstate)
2294 {
2295 struct sci_port *sci_port = to_sci_port(port);
2296
2297 switch (state) {
2298 case UART_PM_STATE_OFF:
2299 sci_port_disable(sci_port);
2300 break;
2301 default:
2302 sci_port_enable(sci_port);
2303 break;
2304 }
2305 }
2306
2307 static const char *sci_type(struct uart_port *port)
2308 {
2309 switch (port->type) {
2310 case PORT_IRDA:
2311 return "irda";
2312 case PORT_SCI:
2313 return "sci";
2314 case PORT_SCIF:
2315 return "scif";
2316 case PORT_SCIFA:
2317 return "scifa";
2318 case PORT_SCIFB:
2319 return "scifb";
2320 case PORT_HSCIF:
2321 return "hscif";
2322 }
2323
2324 return NULL;
2325 }
2326
2327 static int sci_remap_port(struct uart_port *port)
2328 {
2329 struct sci_port *sport = to_sci_port(port);
2330
2331 /*
2332 * Nothing to do if there's already an established membase.
2333 */
2334 if (port->membase)
2335 return 0;
2336
2337 if (port->flags & UPF_IOREMAP) {
2338 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2339 if (unlikely(!port->membase)) {
2340 dev_err(port->dev, "can't remap port#%d\n", port->line);
2341 return -ENXIO;
2342 }
2343 } else {
2344 /*
2345 * For the simple (and majority of) cases where we don't
2346 * need to do any remapping, just cast the cookie
2347 * directly.
2348 */
2349 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2350 }
2351
2352 return 0;
2353 }
2354
2355 static void sci_release_port(struct uart_port *port)
2356 {
2357 struct sci_port *sport = to_sci_port(port);
2358
2359 if (port->flags & UPF_IOREMAP) {
2360 iounmap(port->membase);
2361 port->membase = NULL;
2362 }
2363
2364 release_mem_region(port->mapbase, sport->reg_size);
2365 }
2366
2367 static int sci_request_port(struct uart_port *port)
2368 {
2369 struct resource *res;
2370 struct sci_port *sport = to_sci_port(port);
2371 int ret;
2372
2373 res = request_mem_region(port->mapbase, sport->reg_size,
2374 dev_name(port->dev));
2375 if (unlikely(res == NULL)) {
2376 dev_err(port->dev, "request_mem_region failed.");
2377 return -EBUSY;
2378 }
2379
2380 ret = sci_remap_port(port);
2381 if (unlikely(ret != 0)) {
2382 release_resource(res);
2383 return ret;
2384 }
2385
2386 return 0;
2387 }
2388
2389 static void sci_config_port(struct uart_port *port, int flags)
2390 {
2391 if (flags & UART_CONFIG_TYPE) {
2392 struct sci_port *sport = to_sci_port(port);
2393
2394 port->type = sport->cfg->type;
2395 sci_request_port(port);
2396 }
2397 }
2398
2399 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2400 {
2401 if (ser->baud_base < 2400)
2402 /* No paper tape reader for Mitch.. */
2403 return -EINVAL;
2404
2405 return 0;
2406 }
2407
2408 static struct uart_ops sci_uart_ops = {
2409 .tx_empty = sci_tx_empty,
2410 .set_mctrl = sci_set_mctrl,
2411 .get_mctrl = sci_get_mctrl,
2412 .start_tx = sci_start_tx,
2413 .stop_tx = sci_stop_tx,
2414 .stop_rx = sci_stop_rx,
2415 .break_ctl = sci_break_ctl,
2416 .startup = sci_startup,
2417 .shutdown = sci_shutdown,
2418 .set_termios = sci_set_termios,
2419 .pm = sci_pm,
2420 .type = sci_type,
2421 .release_port = sci_release_port,
2422 .request_port = sci_request_port,
2423 .config_port = sci_config_port,
2424 .verify_port = sci_verify_port,
2425 #ifdef CONFIG_CONSOLE_POLL
2426 .poll_get_char = sci_poll_get_char,
2427 .poll_put_char = sci_poll_put_char,
2428 #endif
2429 };
2430
2431 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2432 {
2433 const char *clk_names[] = {
2434 [SCI_FCK] = "fck",
2435 [SCI_SCK] = "sck",
2436 [SCI_BRG_INT] = "brg_int",
2437 [SCI_SCIF_CLK] = "scif_clk",
2438 };
2439 struct clk *clk;
2440 unsigned int i;
2441
2442 if (sci_port->cfg->type == PORT_HSCIF)
2443 clk_names[SCI_SCK] = "hsck";
2444
2445 for (i = 0; i < SCI_NUM_CLKS; i++) {
2446 clk = devm_clk_get(dev, clk_names[i]);
2447 if (PTR_ERR(clk) == -EPROBE_DEFER)
2448 return -EPROBE_DEFER;
2449
2450 if (IS_ERR(clk) && i == SCI_FCK) {
2451 /*
2452 * "fck" used to be called "sci_ick", and we need to
2453 * maintain DT backward compatibility.
2454 */
2455 clk = devm_clk_get(dev, "sci_ick");
2456 if (PTR_ERR(clk) == -EPROBE_DEFER)
2457 return -EPROBE_DEFER;
2458
2459 if (!IS_ERR(clk))
2460 goto found;
2461
2462 /*
2463 * Not all SH platforms declare a clock lookup entry
2464 * for SCI devices, in which case we need to get the
2465 * global "peripheral_clk" clock.
2466 */
2467 clk = devm_clk_get(dev, "peripheral_clk");
2468 if (!IS_ERR(clk))
2469 goto found;
2470
2471 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2472 PTR_ERR(clk));
2473 return PTR_ERR(clk);
2474 }
2475
2476 found:
2477 if (IS_ERR(clk))
2478 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2479 PTR_ERR(clk));
2480 else
2481 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2482 clk, clk);
2483 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2484 }
2485 return 0;
2486 }
2487
2488 static int sci_init_single(struct platform_device *dev,
2489 struct sci_port *sci_port, unsigned int index,
2490 struct plat_sci_port *p, bool early)
2491 {
2492 struct uart_port *port = &sci_port->port;
2493 const struct resource *res;
2494 unsigned int i;
2495 int ret;
2496
2497 sci_port->cfg = p;
2498
2499 port->ops = &sci_uart_ops;
2500 port->iotype = UPIO_MEM;
2501 port->line = index;
2502
2503 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2504 if (res == NULL)
2505 return -ENOMEM;
2506
2507 port->mapbase = res->start;
2508 sci_port->reg_size = resource_size(res);
2509
2510 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2511 sci_port->irqs[i] = platform_get_irq(dev, i);
2512
2513 /* The SCI generates several interrupts. They can be muxed together or
2514 * connected to different interrupt lines. In the muxed case only one
2515 * interrupt resource is specified. In the non-muxed case three or four
2516 * interrupt resources are specified, as the BRI interrupt is optional.
2517 */
2518 if (sci_port->irqs[0] < 0)
2519 return -ENXIO;
2520
2521 if (sci_port->irqs[1] < 0) {
2522 sci_port->irqs[1] = sci_port->irqs[0];
2523 sci_port->irqs[2] = sci_port->irqs[0];
2524 sci_port->irqs[3] = sci_port->irqs[0];
2525 }
2526
2527 if (p->regtype == SCIx_PROBE_REGTYPE) {
2528 ret = sci_probe_regmap(p);
2529 if (unlikely(ret))
2530 return ret;
2531 }
2532
2533 switch (p->type) {
2534 case PORT_SCIFB:
2535 port->fifosize = 256;
2536 sci_port->overrun_reg = SCxSR;
2537 sci_port->overrun_mask = SCIFA_ORER;
2538 sci_port->sampling_rate = 16;
2539 break;
2540 case PORT_HSCIF:
2541 port->fifosize = 128;
2542 sci_port->overrun_reg = SCLSR;
2543 sci_port->overrun_mask = SCLSR_ORER;
2544 sci_port->sampling_rate = 0;
2545 break;
2546 case PORT_SCIFA:
2547 port->fifosize = 64;
2548 sci_port->overrun_reg = SCxSR;
2549 sci_port->overrun_mask = SCIFA_ORER;
2550 sci_port->sampling_rate = 16;
2551 break;
2552 case PORT_SCIF:
2553 port->fifosize = 16;
2554 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2555 sci_port->overrun_reg = SCxSR;
2556 sci_port->overrun_mask = SCIFA_ORER;
2557 sci_port->sampling_rate = 16;
2558 } else {
2559 sci_port->overrun_reg = SCLSR;
2560 sci_port->overrun_mask = SCLSR_ORER;
2561 sci_port->sampling_rate = 32;
2562 }
2563 break;
2564 default:
2565 port->fifosize = 1;
2566 sci_port->overrun_reg = SCxSR;
2567 sci_port->overrun_mask = SCI_ORER;
2568 sci_port->sampling_rate = 32;
2569 break;
2570 }
2571
2572 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2573 * match the SoC datasheet, this should be investigated. Let platform
2574 * data override the sampling rate for now.
2575 */
2576 if (p->sampling_rate)
2577 sci_port->sampling_rate = p->sampling_rate;
2578
2579 if (!early) {
2580 ret = sci_init_clocks(sci_port, &dev->dev);
2581 if (ret < 0)
2582 return ret;
2583
2584 port->dev = &dev->dev;
2585
2586 pm_runtime_enable(&dev->dev);
2587 }
2588
2589 sci_port->break_timer.data = (unsigned long)sci_port;
2590 sci_port->break_timer.function = sci_break_timer;
2591 init_timer(&sci_port->break_timer);
2592
2593 /*
2594 * Establish some sensible defaults for the error detection.
2595 */
2596 if (p->type == PORT_SCI) {
2597 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2598 sci_port->error_clear = SCI_ERROR_CLEAR;
2599 } else {
2600 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2601 sci_port->error_clear = SCIF_ERROR_CLEAR;
2602 }
2603
2604 /*
2605 * Make the error mask inclusive of overrun detection, if
2606 * supported.
2607 */
2608 if (sci_port->overrun_reg == SCxSR) {
2609 sci_port->error_mask |= sci_port->overrun_mask;
2610 sci_port->error_clear &= ~sci_port->overrun_mask;
2611 }
2612
2613 port->type = p->type;
2614 port->flags = UPF_FIXED_PORT | p->flags;
2615 port->regshift = p->regshift;
2616
2617 /*
2618 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2619 * for the multi-IRQ ports, which is where we are primarily
2620 * concerned with the shutdown path synchronization.
2621 *
2622 * For the muxed case there's nothing more to do.
2623 */
2624 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2625 port->irqflags = 0;
2626
2627 port->serial_in = sci_serial_in;
2628 port->serial_out = sci_serial_out;
2629
2630 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2631 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2632 p->dma_slave_tx, p->dma_slave_rx);
2633
2634 return 0;
2635 }
2636
2637 static void sci_cleanup_single(struct sci_port *port)
2638 {
2639 pm_runtime_disable(port->port.dev);
2640 }
2641
2642 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2643 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2644 static void serial_console_putchar(struct uart_port *port, int ch)
2645 {
2646 sci_poll_put_char(port, ch);
2647 }
2648
2649 /*
2650 * Print a string to the serial port trying not to disturb
2651 * any possible real use of the port...
2652 */
2653 static void serial_console_write(struct console *co, const char *s,
2654 unsigned count)
2655 {
2656 struct sci_port *sci_port = &sci_ports[co->index];
2657 struct uart_port *port = &sci_port->port;
2658 unsigned short bits, ctrl, ctrl_temp;
2659 unsigned long flags;
2660 int locked = 1;
2661
2662 local_irq_save(flags);
2663 #if defined(SUPPORT_SYSRQ)
2664 if (port->sysrq)
2665 locked = 0;
2666 else
2667 #endif
2668 if (oops_in_progress)
2669 locked = spin_trylock(&port->lock);
2670 else
2671 spin_lock(&port->lock);
2672
2673 /* first save SCSCR then disable interrupts, keep clock source */
2674 ctrl = serial_port_in(port, SCSCR);
2675 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2676 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2677 serial_port_out(port, SCSCR, ctrl_temp);
2678
2679 uart_console_write(port, s, count, serial_console_putchar);
2680
2681 /* wait until fifo is empty and last bit has been transmitted */
2682 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2683 while ((serial_port_in(port, SCxSR) & bits) != bits)
2684 cpu_relax();
2685
2686 /* restore the SCSCR */
2687 serial_port_out(port, SCSCR, ctrl);
2688
2689 if (locked)
2690 spin_unlock(&port->lock);
2691 local_irq_restore(flags);
2692 }
2693
2694 static int serial_console_setup(struct console *co, char *options)
2695 {
2696 struct sci_port *sci_port;
2697 struct uart_port *port;
2698 int baud = 115200;
2699 int bits = 8;
2700 int parity = 'n';
2701 int flow = 'n';
2702 int ret;
2703
2704 /*
2705 * Refuse to handle any bogus ports.
2706 */
2707 if (co->index < 0 || co->index >= SCI_NPORTS)
2708 return -ENODEV;
2709
2710 sci_port = &sci_ports[co->index];
2711 port = &sci_port->port;
2712
2713 /*
2714 * Refuse to handle uninitialized ports.
2715 */
2716 if (!port->ops)
2717 return -ENODEV;
2718
2719 ret = sci_remap_port(port);
2720 if (unlikely(ret != 0))
2721 return ret;
2722
2723 if (options)
2724 uart_parse_options(options, &baud, &parity, &bits, &flow);
2725
2726 return uart_set_options(port, co, baud, parity, bits, flow);
2727 }
2728
2729 static struct console serial_console = {
2730 .name = "ttySC",
2731 .device = uart_console_device,
2732 .write = serial_console_write,
2733 .setup = serial_console_setup,
2734 .flags = CON_PRINTBUFFER,
2735 .index = -1,
2736 .data = &sci_uart_driver,
2737 };
2738
2739 static struct console early_serial_console = {
2740 .name = "early_ttySC",
2741 .write = serial_console_write,
2742 .flags = CON_PRINTBUFFER,
2743 .index = -1,
2744 };
2745
2746 static char early_serial_buf[32];
2747
2748 static int sci_probe_earlyprintk(struct platform_device *pdev)
2749 {
2750 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2751
2752 if (early_serial_console.data)
2753 return -EEXIST;
2754
2755 early_serial_console.index = pdev->id;
2756
2757 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2758
2759 serial_console_setup(&early_serial_console, early_serial_buf);
2760
2761 if (!strstr(early_serial_buf, "keep"))
2762 early_serial_console.flags |= CON_BOOT;
2763
2764 register_console(&early_serial_console);
2765 return 0;
2766 }
2767
2768 #define SCI_CONSOLE (&serial_console)
2769
2770 #else
2771 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2772 {
2773 return -EINVAL;
2774 }
2775
2776 #define SCI_CONSOLE NULL
2777
2778 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
2779
2780 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2781
2782 static struct uart_driver sci_uart_driver = {
2783 .owner = THIS_MODULE,
2784 .driver_name = "sci",
2785 .dev_name = "ttySC",
2786 .major = SCI_MAJOR,
2787 .minor = SCI_MINOR_START,
2788 .nr = SCI_NPORTS,
2789 .cons = SCI_CONSOLE,
2790 };
2791
2792 static int sci_remove(struct platform_device *dev)
2793 {
2794 struct sci_port *port = platform_get_drvdata(dev);
2795
2796 uart_remove_one_port(&sci_uart_driver, &port->port);
2797
2798 sci_cleanup_single(port);
2799
2800 return 0;
2801 }
2802
2803
2804 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2805 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2806 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
2807
2808 static const struct of_device_id of_sci_match[] = {
2809 /* SoC-specific types */
2810 {
2811 .compatible = "renesas,scif-r7s72100",
2812 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2813 },
2814 /* Family-specific types */
2815 {
2816 .compatible = "renesas,rcar-gen1-scif",
2817 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2818 }, {
2819 .compatible = "renesas,rcar-gen2-scif",
2820 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2821 }, {
2822 .compatible = "renesas,rcar-gen3-scif",
2823 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2824 },
2825 /* Generic types */
2826 {
2827 .compatible = "renesas,scif",
2828 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
2829 }, {
2830 .compatible = "renesas,scifa",
2831 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
2832 }, {
2833 .compatible = "renesas,scifb",
2834 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
2835 }, {
2836 .compatible = "renesas,hscif",
2837 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
2838 }, {
2839 .compatible = "renesas,sci",
2840 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
2841 }, {
2842 /* Terminator */
2843 },
2844 };
2845 MODULE_DEVICE_TABLE(of, of_sci_match);
2846
2847 static struct plat_sci_port *
2848 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2849 {
2850 struct device_node *np = pdev->dev.of_node;
2851 const struct of_device_id *match;
2852 struct plat_sci_port *p;
2853 int id;
2854
2855 if (!IS_ENABLED(CONFIG_OF) || !np)
2856 return NULL;
2857
2858 match = of_match_node(of_sci_match, np);
2859 if (!match)
2860 return NULL;
2861
2862 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2863 if (!p)
2864 return NULL;
2865
2866 /* Get the line number from the aliases node. */
2867 id = of_alias_get_id(np, "serial");
2868 if (id < 0) {
2869 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2870 return NULL;
2871 }
2872
2873 *dev_id = id;
2874
2875 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2876 p->type = SCI_OF_TYPE(match->data);
2877 p->regtype = SCI_OF_REGTYPE(match->data);
2878 p->scscr = SCSCR_RE | SCSCR_TE;
2879
2880 return p;
2881 }
2882
2883 static int sci_probe_single(struct platform_device *dev,
2884 unsigned int index,
2885 struct plat_sci_port *p,
2886 struct sci_port *sciport)
2887 {
2888 int ret;
2889
2890 /* Sanity check */
2891 if (unlikely(index >= SCI_NPORTS)) {
2892 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2893 index+1, SCI_NPORTS);
2894 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2895 return -EINVAL;
2896 }
2897
2898 ret = sci_init_single(dev, sciport, index, p, false);
2899 if (ret)
2900 return ret;
2901
2902 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2903 if (ret) {
2904 sci_cleanup_single(sciport);
2905 return ret;
2906 }
2907
2908 return 0;
2909 }
2910
2911 static int sci_probe(struct platform_device *dev)
2912 {
2913 struct plat_sci_port *p;
2914 struct sci_port *sp;
2915 unsigned int dev_id;
2916 int ret;
2917
2918 /*
2919 * If we've come here via earlyprintk initialization, head off to
2920 * the special early probe. We don't have sufficient device state
2921 * to make it beyond this yet.
2922 */
2923 if (is_early_platform_device(dev))
2924 return sci_probe_earlyprintk(dev);
2925
2926 if (dev->dev.of_node) {
2927 p = sci_parse_dt(dev, &dev_id);
2928 if (p == NULL)
2929 return -EINVAL;
2930 } else {
2931 p = dev->dev.platform_data;
2932 if (p == NULL) {
2933 dev_err(&dev->dev, "no platform data supplied\n");
2934 return -EINVAL;
2935 }
2936
2937 dev_id = dev->id;
2938 }
2939
2940 sp = &sci_ports[dev_id];
2941 platform_set_drvdata(dev, sp);
2942
2943 ret = sci_probe_single(dev, dev_id, p, sp);
2944 if (ret)
2945 return ret;
2946
2947 #ifdef CONFIG_SH_STANDARD_BIOS
2948 sh_bios_gdb_detach();
2949 #endif
2950
2951 return 0;
2952 }
2953
2954 static __maybe_unused int sci_suspend(struct device *dev)
2955 {
2956 struct sci_port *sport = dev_get_drvdata(dev);
2957
2958 if (sport)
2959 uart_suspend_port(&sci_uart_driver, &sport->port);
2960
2961 return 0;
2962 }
2963
2964 static __maybe_unused int sci_resume(struct device *dev)
2965 {
2966 struct sci_port *sport = dev_get_drvdata(dev);
2967
2968 if (sport)
2969 uart_resume_port(&sci_uart_driver, &sport->port);
2970
2971 return 0;
2972 }
2973
2974 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2975
2976 static struct platform_driver sci_driver = {
2977 .probe = sci_probe,
2978 .remove = sci_remove,
2979 .driver = {
2980 .name = "sh-sci",
2981 .pm = &sci_dev_pm_ops,
2982 .of_match_table = of_match_ptr(of_sci_match),
2983 },
2984 };
2985
2986 static int __init sci_init(void)
2987 {
2988 int ret;
2989
2990 pr_info("%s\n", banner);
2991
2992 ret = uart_register_driver(&sci_uart_driver);
2993 if (likely(ret == 0)) {
2994 ret = platform_driver_register(&sci_driver);
2995 if (unlikely(ret))
2996 uart_unregister_driver(&sci_uart_driver);
2997 }
2998
2999 return ret;
3000 }
3001
3002 static void __exit sci_exit(void)
3003 {
3004 platform_driver_unregister(&sci_driver);
3005 uart_unregister_driver(&sci_uart_driver);
3006 }
3007
3008 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3009 early_platform_init_buffer("earlyprintk", &sci_driver,
3010 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3011 #endif
3012 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3013 static struct __init plat_sci_port port_cfg;
3014
3015 static int __init early_console_setup(struct earlycon_device *device,
3016 int type)
3017 {
3018 if (!device->port.membase)
3019 return -ENODEV;
3020
3021 device->port.serial_in = sci_serial_in;
3022 device->port.serial_out = sci_serial_out;
3023 device->port.type = type;
3024 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3025 sci_ports[0].cfg = &port_cfg;
3026 sci_ports[0].cfg->type = type;
3027 sci_probe_regmap(sci_ports[0].cfg);
3028 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3029 SCSCR_RE | SCSCR_TE;
3030 sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3031
3032 device->con->write = serial_console_write;
3033 return 0;
3034 }
3035 static int __init sci_early_console_setup(struct earlycon_device *device,
3036 const char *opt)
3037 {
3038 return early_console_setup(device, PORT_SCI);
3039 }
3040 static int __init scif_early_console_setup(struct earlycon_device *device,
3041 const char *opt)
3042 {
3043 return early_console_setup(device, PORT_SCIF);
3044 }
3045 static int __init scifa_early_console_setup(struct earlycon_device *device,
3046 const char *opt)
3047 {
3048 return early_console_setup(device, PORT_SCIFA);
3049 }
3050 static int __init scifb_early_console_setup(struct earlycon_device *device,
3051 const char *opt)
3052 {
3053 return early_console_setup(device, PORT_SCIFB);
3054 }
3055 static int __init hscif_early_console_setup(struct earlycon_device *device,
3056 const char *opt)
3057 {
3058 return early_console_setup(device, PORT_HSCIF);
3059 }
3060
3061 EARLYCON_DECLARE(sci, sci_early_console_setup);
3062 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3063 EARLYCON_DECLARE(scif, scif_early_console_setup);
3064 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3065 EARLYCON_DECLARE(scifa, scifa_early_console_setup);
3066 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3067 EARLYCON_DECLARE(scifb, scifb_early_console_setup);
3068 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3069 EARLYCON_DECLARE(hscif, hscif_early_console_setup);
3070 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3071 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3072
3073 module_init(sci_init);
3074 module_exit(sci_exit);
3075
3076 MODULE_LICENSE("GPL");
3077 MODULE_ALIAS("platform:sh-sci");
3078 MODULE_AUTHOR("Paul Mundt");
3079 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux kernel - Deliverables
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