2 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
4 * Device driver for Microgate SyncLink ISA and PCI
5 * high speed multiprotocol serial adapters.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
14 * Original release 01/11/99
16 * This code is released under the GNU General Public License (GPL)
18 * This driver is primarily intended for use in synchronous
19 * HDLC mode. Asynchronous mode is also provided.
21 * When operating in synchronous mode, each call to mgsl_write()
22 * contains exactly one complete HDLC frame. Calling mgsl_put_char
23 * will start assembling an HDLC frame that will not be sent until
24 * mgsl_flush_chars or mgsl_write is called.
26 * Synchronous receive data is reported as complete frames. To accomplish
27 * this, the TTY flip buffer is bypassed (too small to hold largest
28 * frame and may fragment frames) and the line discipline
29 * receive entry point is called directly.
31 * This driver has been tested with a slightly modified ppp.c driver
32 * for synchronous PPP.
35 * Added interface for syncppp.c driver (an alternate synchronous PPP
36 * implementation that also supports Cisco HDLC). Each device instance
37 * registers as a tty device AND a network device (if dosyncppp option
38 * is set for the device). The functionality is determined by which
39 * device interface is opened.
41 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
42 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
45 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
49 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
50 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
51 * OF THE POSSIBILITY OF SUCH DAMAGE.
55 # define BREAKPOINT() asm(" int $3");
57 # define BREAKPOINT() { }
60 #define MAX_ISA_DEVICES 10
61 #define MAX_PCI_DEVICES 10
62 #define MAX_TOTAL_DEVICES 20
64 #include <linux/module.h>
65 #include <linux/errno.h>
66 #include <linux/signal.h>
67 #include <linux/sched.h>
68 #include <linux/timer.h>
69 #include <linux/interrupt.h>
70 #include <linux/pci.h>
71 #include <linux/tty.h>
72 #include <linux/tty_flip.h>
73 #include <linux/serial.h>
74 #include <linux/major.h>
75 #include <linux/string.h>
76 #include <linux/fcntl.h>
77 #include <linux/ptrace.h>
78 #include <linux/ioport.h>
80 #include <linux/seq_file.h>
81 #include <linux/slab.h>
82 #include <linux/delay.h>
83 #include <linux/netdevice.h>
84 #include <linux/vmalloc.h>
85 #include <linux/init.h>
86 #include <linux/ioctl.h>
87 #include <linux/synclink.h>
92 #include <linux/bitops.h>
93 #include <asm/types.h>
94 #include <linux/termios.h>
95 #include <linux/workqueue.h>
96 #include <linux/hdlc.h>
97 #include <linux/dma-mapping.h>
99 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_MODULE))
100 #define SYNCLINK_GENERIC_HDLC 1
102 #define SYNCLINK_GENERIC_HDLC 0
105 #define GET_USER(error,value,addr) error = get_user(value,addr)
106 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
107 #define PUT_USER(error,value,addr) error = put_user(value,addr)
108 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
110 #include <asm/uaccess.h>
112 #define RCLRVALUE 0xffff
114 static MGSL_PARAMS default_params
= {
115 MGSL_MODE_HDLC
, /* unsigned long mode */
116 0, /* unsigned char loopback; */
117 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
118 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
119 0, /* unsigned long clock_speed; */
120 0xff, /* unsigned char addr_filter; */
121 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
122 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
123 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
124 9600, /* unsigned long data_rate; */
125 8, /* unsigned char data_bits; */
126 1, /* unsigned char stop_bits; */
127 ASYNC_PARITY_NONE
/* unsigned char parity; */
130 #define SHARED_MEM_ADDRESS_SIZE 0x40000
131 #define BUFFERLISTSIZE 4096
132 #define DMABUFFERSIZE 4096
133 #define MAXRXFRAMES 7
135 typedef struct _DMABUFFERENTRY
137 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
138 volatile u16 count
; /* buffer size/data count */
139 volatile u16 status
; /* Control/status field */
140 volatile u16 rcc
; /* character count field */
141 u16 reserved
; /* padding required by 16C32 */
142 u32 link
; /* 32-bit flat link to next buffer entry */
143 char *virt_addr
; /* virtual address of data buffer */
144 u32 phys_entry
; /* physical address of this buffer entry */
146 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
148 /* The queue of BH actions to be performed */
151 #define BH_TRANSMIT 2
154 #define IO_PIN_SHUTDOWN_LIMIT 100
156 struct _input_signal_events
{
167 /* transmit holding buffer definitions*/
168 #define MAX_TX_HOLDING_BUFFERS 5
169 struct tx_holding_buffer
{
171 unsigned char * buffer
;
176 * Device instance data structure
181 struct tty_port port
;
185 struct mgsl_icount icount
;
188 int x_char
; /* xon/xoff character */
189 u16 read_status_mask
;
190 u16 ignore_status_mask
;
191 unsigned char *xmit_buf
;
196 wait_queue_head_t status_event_wait_q
;
197 wait_queue_head_t event_wait_q
;
198 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
199 struct mgsl_struct
*next_device
; /* device list link */
201 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
202 struct work_struct task
; /* task structure for scheduling bh */
204 u32 EventMask
; /* event trigger mask */
205 u32 RecordedEvents
; /* pending events */
207 u32 max_frame_size
; /* as set by device config */
211 bool bh_running
; /* Protection from multiple */
215 int dcd_chkcount
; /* check counts to prevent */
216 int cts_chkcount
; /* too many IRQs if a signal */
217 int dsr_chkcount
; /* is floating */
220 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
221 u32 buffer_list_phys
;
222 dma_addr_t buffer_list_dma_addr
;
224 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
225 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
226 unsigned int current_rx_buffer
;
228 int num_tx_dma_buffers
; /* number of tx dma frames required */
229 int tx_dma_buffers_used
;
230 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
231 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
232 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
233 int current_tx_buffer
; /* next tx dma buffer to be loaded */
235 unsigned char *intermediate_rxbuffer
;
237 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
238 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
239 int put_tx_holding_index
; /* next tx holding buffer to store user request */
240 int tx_holding_count
; /* number of tx holding buffers waiting */
241 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
245 bool rx_rcc_underrun
;
254 char device_name
[25]; /* device instance name */
256 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
257 unsigned char bus
; /* expansion bus number (zero based) */
258 unsigned char function
; /* PCI device number */
260 unsigned int io_base
; /* base I/O address of adapter */
261 unsigned int io_addr_size
; /* size of the I/O address range */
262 bool io_addr_requested
; /* true if I/O address requested */
264 unsigned int irq_level
; /* interrupt level */
265 unsigned long irq_flags
;
266 bool irq_requested
; /* true if IRQ requested */
268 unsigned int dma_level
; /* DMA channel */
269 bool dma_requested
; /* true if dma channel requested */
275 MGSL_PARAMS params
; /* communications parameters */
277 unsigned char serial_signals
; /* current serial signal states */
279 bool irq_occurred
; /* for diagnostics use */
280 unsigned int init_error
; /* Initialization startup error (DIAGS) */
281 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
284 unsigned char* memory_base
; /* shared memory address (PCI only) */
285 u32 phys_memory_base
;
286 bool shared_mem_requested
;
288 unsigned char* lcr_base
; /* local config registers (PCI only) */
291 bool lcr_mem_requested
;
295 bool drop_rts_on_tx_done
;
297 bool loopmode_insert_requested
;
298 bool loopmode_send_done_requested
;
300 struct _input_signal_events input_signal_events
;
302 /* generic HDLC device parts */
306 #if SYNCLINK_GENERIC_HDLC
307 struct net_device
*netdev
;
311 #define MGSL_MAGIC 0x5401
314 * The size of the serial xmit buffer is 1 page, or 4096 bytes
316 #ifndef SERIAL_XMIT_SIZE
317 #define SERIAL_XMIT_SIZE 4096
321 * These macros define the offsets used in calculating the
322 * I/O address of the specified USC registers.
326 #define DCPIN 2 /* Bit 1 of I/O address */
327 #define SDPIN 4 /* Bit 2 of I/O address */
329 #define DCAR 0 /* DMA command/address register */
330 #define CCAR SDPIN /* channel command/address register */
331 #define DATAREG DCPIN + SDPIN /* serial data register */
336 * These macros define the register address (ordinal number)
337 * used for writing address/value pairs to the USC.
340 #define CMR 0x02 /* Channel mode Register */
341 #define CCSR 0x04 /* Channel Command/status Register */
342 #define CCR 0x06 /* Channel Control Register */
343 #define PSR 0x08 /* Port status Register */
344 #define PCR 0x0a /* Port Control Register */
345 #define TMDR 0x0c /* Test mode Data Register */
346 #define TMCR 0x0e /* Test mode Control Register */
347 #define CMCR 0x10 /* Clock mode Control Register */
348 #define HCR 0x12 /* Hardware Configuration Register */
349 #define IVR 0x14 /* Interrupt Vector Register */
350 #define IOCR 0x16 /* Input/Output Control Register */
351 #define ICR 0x18 /* Interrupt Control Register */
352 #define DCCR 0x1a /* Daisy Chain Control Register */
353 #define MISR 0x1c /* Misc Interrupt status Register */
354 #define SICR 0x1e /* status Interrupt Control Register */
355 #define RDR 0x20 /* Receive Data Register */
356 #define RMR 0x22 /* Receive mode Register */
357 #define RCSR 0x24 /* Receive Command/status Register */
358 #define RICR 0x26 /* Receive Interrupt Control Register */
359 #define RSR 0x28 /* Receive Sync Register */
360 #define RCLR 0x2a /* Receive count Limit Register */
361 #define RCCR 0x2c /* Receive Character count Register */
362 #define TC0R 0x2e /* Time Constant 0 Register */
363 #define TDR 0x30 /* Transmit Data Register */
364 #define TMR 0x32 /* Transmit mode Register */
365 #define TCSR 0x34 /* Transmit Command/status Register */
366 #define TICR 0x36 /* Transmit Interrupt Control Register */
367 #define TSR 0x38 /* Transmit Sync Register */
368 #define TCLR 0x3a /* Transmit count Limit Register */
369 #define TCCR 0x3c /* Transmit Character count Register */
370 #define TC1R 0x3e /* Time Constant 1 Register */
374 * MACRO DEFINITIONS FOR DMA REGISTERS
377 #define DCR 0x06 /* DMA Control Register (shared) */
378 #define DACR 0x08 /* DMA Array count Register (shared) */
379 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
380 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
381 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
382 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
383 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
385 #define TDMR 0x02 /* Transmit DMA mode Register */
386 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
387 #define TBCR 0x2a /* Transmit Byte count Register */
388 #define TARL 0x2c /* Transmit Address Register (low) */
389 #define TARU 0x2e /* Transmit Address Register (high) */
390 #define NTBCR 0x3a /* Next Transmit Byte count Register */
391 #define NTARL 0x3c /* Next Transmit Address Register (low) */
392 #define NTARU 0x3e /* Next Transmit Address Register (high) */
394 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
395 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
396 #define RBCR 0xaa /* Receive Byte count Register */
397 #define RARL 0xac /* Receive Address Register (low) */
398 #define RARU 0xae /* Receive Address Register (high) */
399 #define NRBCR 0xba /* Next Receive Byte count Register */
400 #define NRARL 0xbc /* Next Receive Address Register (low) */
401 #define NRARU 0xbe /* Next Receive Address Register (high) */
405 * MACRO DEFINITIONS FOR MODEM STATUS BITS
408 #define MODEMSTATUS_DTR 0x80
409 #define MODEMSTATUS_DSR 0x40
410 #define MODEMSTATUS_RTS 0x20
411 #define MODEMSTATUS_CTS 0x10
412 #define MODEMSTATUS_RI 0x04
413 #define MODEMSTATUS_DCD 0x01
417 * Channel Command/Address Register (CCAR) Command Codes
420 #define RTCmd_Null 0x0000
421 #define RTCmd_ResetHighestIus 0x1000
422 #define RTCmd_TriggerChannelLoadDma 0x2000
423 #define RTCmd_TriggerRxDma 0x2800
424 #define RTCmd_TriggerTxDma 0x3000
425 #define RTCmd_TriggerRxAndTxDma 0x3800
426 #define RTCmd_PurgeRxFifo 0x4800
427 #define RTCmd_PurgeTxFifo 0x5000
428 #define RTCmd_PurgeRxAndTxFifo 0x5800
429 #define RTCmd_LoadRcc 0x6800
430 #define RTCmd_LoadTcc 0x7000
431 #define RTCmd_LoadRccAndTcc 0x7800
432 #define RTCmd_LoadTC0 0x8800
433 #define RTCmd_LoadTC1 0x9000
434 #define RTCmd_LoadTC0AndTC1 0x9800
435 #define RTCmd_SerialDataLSBFirst 0xa000
436 #define RTCmd_SerialDataMSBFirst 0xa800
437 #define RTCmd_SelectBigEndian 0xb000
438 #define RTCmd_SelectLittleEndian 0xb800
442 * DMA Command/Address Register (DCAR) Command Codes
445 #define DmaCmd_Null 0x0000
446 #define DmaCmd_ResetTxChannel 0x1000
447 #define DmaCmd_ResetRxChannel 0x1200
448 #define DmaCmd_StartTxChannel 0x2000
449 #define DmaCmd_StartRxChannel 0x2200
450 #define DmaCmd_ContinueTxChannel 0x3000
451 #define DmaCmd_ContinueRxChannel 0x3200
452 #define DmaCmd_PauseTxChannel 0x4000
453 #define DmaCmd_PauseRxChannel 0x4200
454 #define DmaCmd_AbortTxChannel 0x5000
455 #define DmaCmd_AbortRxChannel 0x5200
456 #define DmaCmd_InitTxChannel 0x7000
457 #define DmaCmd_InitRxChannel 0x7200
458 #define DmaCmd_ResetHighestDmaIus 0x8000
459 #define DmaCmd_ResetAllChannels 0x9000
460 #define DmaCmd_StartAllChannels 0xa000
461 #define DmaCmd_ContinueAllChannels 0xb000
462 #define DmaCmd_PauseAllChannels 0xc000
463 #define DmaCmd_AbortAllChannels 0xd000
464 #define DmaCmd_InitAllChannels 0xf000
466 #define TCmd_Null 0x0000
467 #define TCmd_ClearTxCRC 0x2000
468 #define TCmd_SelectTicrTtsaData 0x4000
469 #define TCmd_SelectTicrTxFifostatus 0x5000
470 #define TCmd_SelectTicrIntLevel 0x6000
471 #define TCmd_SelectTicrdma_level 0x7000
472 #define TCmd_SendFrame 0x8000
473 #define TCmd_SendAbort 0x9000
474 #define TCmd_EnableDleInsertion 0xc000
475 #define TCmd_DisableDleInsertion 0xd000
476 #define TCmd_ClearEofEom 0xe000
477 #define TCmd_SetEofEom 0xf000
479 #define RCmd_Null 0x0000
480 #define RCmd_ClearRxCRC 0x2000
481 #define RCmd_EnterHuntmode 0x3000
482 #define RCmd_SelectRicrRtsaData 0x4000
483 #define RCmd_SelectRicrRxFifostatus 0x5000
484 #define RCmd_SelectRicrIntLevel 0x6000
485 #define RCmd_SelectRicrdma_level 0x7000
488 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
491 #define RECEIVE_STATUS BIT5
492 #define RECEIVE_DATA BIT4
493 #define TRANSMIT_STATUS BIT3
494 #define TRANSMIT_DATA BIT2
500 * Receive status Bits in Receive Command/status Register RCSR
503 #define RXSTATUS_SHORT_FRAME BIT8
504 #define RXSTATUS_CODE_VIOLATION BIT8
505 #define RXSTATUS_EXITED_HUNT BIT7
506 #define RXSTATUS_IDLE_RECEIVED BIT6
507 #define RXSTATUS_BREAK_RECEIVED BIT5
508 #define RXSTATUS_ABORT_RECEIVED BIT5
509 #define RXSTATUS_RXBOUND BIT4
510 #define RXSTATUS_CRC_ERROR BIT3
511 #define RXSTATUS_FRAMING_ERROR BIT3
512 #define RXSTATUS_ABORT BIT2
513 #define RXSTATUS_PARITY_ERROR BIT2
514 #define RXSTATUS_OVERRUN BIT1
515 #define RXSTATUS_DATA_AVAILABLE BIT0
516 #define RXSTATUS_ALL 0x01f6
517 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
520 * Values for setting transmit idle mode in
521 * Transmit Control/status Register (TCSR)
523 #define IDLEMODE_FLAGS 0x0000
524 #define IDLEMODE_ALT_ONE_ZERO 0x0100
525 #define IDLEMODE_ZERO 0x0200
526 #define IDLEMODE_ONE 0x0300
527 #define IDLEMODE_ALT_MARK_SPACE 0x0500
528 #define IDLEMODE_SPACE 0x0600
529 #define IDLEMODE_MARK 0x0700
530 #define IDLEMODE_MASK 0x0700
533 * IUSC revision identifiers
535 #define IUSC_SL1660 0x4d44
536 #define IUSC_PRE_SL1660 0x4553
539 * Transmit status Bits in Transmit Command/status Register (TCSR)
542 #define TCSR_PRESERVE 0x0F00
544 #define TCSR_UNDERWAIT BIT11
545 #define TXSTATUS_PREAMBLE_SENT BIT7
546 #define TXSTATUS_IDLE_SENT BIT6
547 #define TXSTATUS_ABORT_SENT BIT5
548 #define TXSTATUS_EOF_SENT BIT4
549 #define TXSTATUS_EOM_SENT BIT4
550 #define TXSTATUS_CRC_SENT BIT3
551 #define TXSTATUS_ALL_SENT BIT2
552 #define TXSTATUS_UNDERRUN BIT1
553 #define TXSTATUS_FIFO_EMPTY BIT0
554 #define TXSTATUS_ALL 0x00fa
555 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
558 #define MISCSTATUS_RXC_LATCHED BIT15
559 #define MISCSTATUS_RXC BIT14
560 #define MISCSTATUS_TXC_LATCHED BIT13
561 #define MISCSTATUS_TXC BIT12
562 #define MISCSTATUS_RI_LATCHED BIT11
563 #define MISCSTATUS_RI BIT10
564 #define MISCSTATUS_DSR_LATCHED BIT9
565 #define MISCSTATUS_DSR BIT8
566 #define MISCSTATUS_DCD_LATCHED BIT7
567 #define MISCSTATUS_DCD BIT6
568 #define MISCSTATUS_CTS_LATCHED BIT5
569 #define MISCSTATUS_CTS BIT4
570 #define MISCSTATUS_RCC_UNDERRUN BIT3
571 #define MISCSTATUS_DPLL_NO_SYNC BIT2
572 #define MISCSTATUS_BRG1_ZERO BIT1
573 #define MISCSTATUS_BRG0_ZERO BIT0
575 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
576 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
578 #define SICR_RXC_ACTIVE BIT15
579 #define SICR_RXC_INACTIVE BIT14
580 #define SICR_RXC (BIT15|BIT14)
581 #define SICR_TXC_ACTIVE BIT13
582 #define SICR_TXC_INACTIVE BIT12
583 #define SICR_TXC (BIT13|BIT12)
584 #define SICR_RI_ACTIVE BIT11
585 #define SICR_RI_INACTIVE BIT10
586 #define SICR_RI (BIT11|BIT10)
587 #define SICR_DSR_ACTIVE BIT9
588 #define SICR_DSR_INACTIVE BIT8
589 #define SICR_DSR (BIT9|BIT8)
590 #define SICR_DCD_ACTIVE BIT7
591 #define SICR_DCD_INACTIVE BIT6
592 #define SICR_DCD (BIT7|BIT6)
593 #define SICR_CTS_ACTIVE BIT5
594 #define SICR_CTS_INACTIVE BIT4
595 #define SICR_CTS (BIT5|BIT4)
596 #define SICR_RCC_UNDERFLOW BIT3
597 #define SICR_DPLL_NO_SYNC BIT2
598 #define SICR_BRG1_ZERO BIT1
599 #define SICR_BRG0_ZERO BIT0
601 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
602 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
603 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
604 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
605 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
607 #define usc_EnableInterrupts( a, b ) \
608 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
610 #define usc_DisableInterrupts( a, b ) \
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
613 #define usc_EnableMasterIrqBit(a) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
616 #define usc_DisableMasterIrqBit(a) \
617 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
619 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
622 * Transmit status Bits in Transmit Control status Register (TCSR)
623 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
626 #define TXSTATUS_PREAMBLE_SENT BIT7
627 #define TXSTATUS_IDLE_SENT BIT6
628 #define TXSTATUS_ABORT_SENT BIT5
629 #define TXSTATUS_EOF BIT4
630 #define TXSTATUS_CRC_SENT BIT3
631 #define TXSTATUS_ALL_SENT BIT2
632 #define TXSTATUS_UNDERRUN BIT1
633 #define TXSTATUS_FIFO_EMPTY BIT0
635 #define DICR_MASTER BIT15
636 #define DICR_TRANSMIT BIT0
637 #define DICR_RECEIVE BIT1
639 #define usc_EnableDmaInterrupts(a,b) \
640 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
642 #define usc_DisableDmaInterrupts(a,b) \
643 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
645 #define usc_EnableStatusIrqs(a,b) \
646 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
648 #define usc_DisablestatusIrqs(a,b) \
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
651 /* Transmit status Bits in Transmit Control status Register (TCSR) */
652 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
655 #define DISABLE_UNCONDITIONAL 0
656 #define DISABLE_END_OF_FRAME 1
657 #define ENABLE_UNCONDITIONAL 2
658 #define ENABLE_AUTO_CTS 3
659 #define ENABLE_AUTO_DCD 3
660 #define usc_EnableTransmitter(a,b) \
661 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
662 #define usc_EnableReceiver(a,b) \
663 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
665 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
666 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
667 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
669 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
670 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
671 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
672 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
673 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
675 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
676 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
678 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
680 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
681 static void usc_start_receiver( struct mgsl_struct
*info
);
682 static void usc_stop_receiver( struct mgsl_struct
*info
);
684 static void usc_start_transmitter( struct mgsl_struct
*info
);
685 static void usc_stop_transmitter( struct mgsl_struct
*info
);
686 static void usc_set_txidle( struct mgsl_struct
*info
);
687 static void usc_load_txfifo( struct mgsl_struct
*info
);
689 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
690 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
692 static void usc_get_serial_signals( struct mgsl_struct
*info
);
693 static void usc_set_serial_signals( struct mgsl_struct
*info
);
695 static void usc_reset( struct mgsl_struct
*info
);
697 static void usc_set_sync_mode( struct mgsl_struct
*info
);
698 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
699 static void usc_set_async_mode( struct mgsl_struct
*info
);
700 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
702 static void usc_loopback_frame( struct mgsl_struct
*info
);
704 static void mgsl_tx_timeout(unsigned long context
);
707 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
708 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
709 static int usc_loopmode_active( struct mgsl_struct
* info
);
710 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
712 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
714 #if SYNCLINK_GENERIC_HDLC
715 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
716 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
717 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
718 static int hdlcdev_init(struct mgsl_struct
*info
);
719 static void hdlcdev_exit(struct mgsl_struct
*info
);
723 * Defines a BUS descriptor value for the PCI adapter
724 * local bus address ranges.
727 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
738 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
741 * Adapter diagnostic routines
743 static bool mgsl_register_test( struct mgsl_struct
*info
);
744 static bool mgsl_irq_test( struct mgsl_struct
*info
);
745 static bool mgsl_dma_test( struct mgsl_struct
*info
);
746 static bool mgsl_memory_test( struct mgsl_struct
*info
);
747 static int mgsl_adapter_test( struct mgsl_struct
*info
);
750 * device and resource management routines
752 static int mgsl_claim_resources(struct mgsl_struct
*info
);
753 static void mgsl_release_resources(struct mgsl_struct
*info
);
754 static void mgsl_add_device(struct mgsl_struct
*info
);
755 static struct mgsl_struct
* mgsl_allocate_device(void);
758 * DMA buffer manupulation functions.
760 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
761 static bool mgsl_get_rx_frame( struct mgsl_struct
*info
);
762 static bool mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
763 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
764 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
765 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
766 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
767 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
770 * DMA and Shared Memory buffer allocation and formatting
772 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
773 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
774 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
775 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
776 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
777 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
778 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
779 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
780 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
781 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
782 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
);
783 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
786 * Bottom half interrupt handlers
788 static void mgsl_bh_handler(struct work_struct
*work
);
789 static void mgsl_bh_receive(struct mgsl_struct
*info
);
790 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
791 static void mgsl_bh_status(struct mgsl_struct
*info
);
794 * Interrupt handler routines and dispatch table.
796 static void mgsl_isr_null( struct mgsl_struct
*info
);
797 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
798 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
799 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
800 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
801 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
802 static void mgsl_isr_misc( struct mgsl_struct
*info
);
803 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
804 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
806 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
808 static isr_dispatch_func UscIsrTable
[7] =
813 mgsl_isr_transmit_data
,
814 mgsl_isr_transmit_status
,
815 mgsl_isr_receive_data
,
816 mgsl_isr_receive_status
820 * ioctl call handlers
822 static int tiocmget(struct tty_struct
*tty
);
823 static int tiocmset(struct tty_struct
*tty
,
824 unsigned int set
, unsigned int clear
);
825 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
826 __user
*user_icount
);
827 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
828 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
829 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
830 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
831 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
832 static int mgsl_txabort(struct mgsl_struct
* info
);
833 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
834 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
835 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
837 /* set non-zero on successful registration with PCI subsystem */
838 static bool pci_registered
;
841 * Global linked list of SyncLink devices
843 static struct mgsl_struct
*mgsl_device_list
;
844 static int mgsl_device_count
;
847 * Set this param to non-zero to load eax with the
848 * .text section address and breakpoint on module load.
849 * This is useful for use with gdb and add-symbol-file command.
851 static bool break_on_load
;
854 * Driver major number, defaults to zero to get auto
855 * assigned major number. May be forced as module parameter.
860 * Array of user specified options for ISA adapters.
862 static int io
[MAX_ISA_DEVICES
];
863 static int irq
[MAX_ISA_DEVICES
];
864 static int dma
[MAX_ISA_DEVICES
];
865 static int debug_level
;
866 static int maxframe
[MAX_TOTAL_DEVICES
];
867 static int txdmabufs
[MAX_TOTAL_DEVICES
];
868 static int txholdbufs
[MAX_TOTAL_DEVICES
];
870 module_param(break_on_load
, bool, 0);
871 module_param(ttymajor
, int, 0);
872 module_param_array(io
, int, NULL
, 0);
873 module_param_array(irq
, int, NULL
, 0);
874 module_param_array(dma
, int, NULL
, 0);
875 module_param(debug_level
, int, 0);
876 module_param_array(maxframe
, int, NULL
, 0);
877 module_param_array(txdmabufs
, int, NULL
, 0);
878 module_param_array(txholdbufs
, int, NULL
, 0);
880 static char *driver_name
= "SyncLink serial driver";
881 static char *driver_version
= "$Revision: 4.38 $";
883 static int synclink_init_one (struct pci_dev
*dev
,
884 const struct pci_device_id
*ent
);
885 static void synclink_remove_one (struct pci_dev
*dev
);
887 static struct pci_device_id synclink_pci_tbl
[] = {
888 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
889 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
890 { 0, }, /* terminate list */
892 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
894 MODULE_LICENSE("GPL");
896 static struct pci_driver synclink_pci_driver
= {
898 .id_table
= synclink_pci_tbl
,
899 .probe
= synclink_init_one
,
900 .remove
= synclink_remove_one
,
903 static struct tty_driver
*serial_driver
;
905 /* number of characters left in xmit buffer before we ask for more */
906 #define WAKEUP_CHARS 256
909 static void mgsl_change_params(struct mgsl_struct
*info
);
910 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
913 * 1st function defined in .text section. Calling this function in
914 * init_module() followed by a breakpoint allows a remote debugger
915 * (gdb) to get the .text address for the add-symbol-file command.
916 * This allows remote debugging of dynamically loadable modules.
918 static void* mgsl_get_text_ptr(void)
920 return mgsl_get_text_ptr
;
923 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
924 char *name
, const char *routine
)
926 #ifdef MGSL_PARANOIA_CHECK
927 static const char *badmagic
=
928 "Warning: bad magic number for mgsl struct (%s) in %s\n";
929 static const char *badinfo
=
930 "Warning: null mgsl_struct for (%s) in %s\n";
933 printk(badinfo
, name
, routine
);
936 if (info
->magic
!= MGSL_MAGIC
) {
937 printk(badmagic
, name
, routine
);
948 * line discipline callback wrappers
950 * The wrappers maintain line discipline references
951 * while calling into the line discipline.
953 * ldisc_receive_buf - pass receive data to line discipline
956 static void ldisc_receive_buf(struct tty_struct
*tty
,
957 const __u8
*data
, char *flags
, int count
)
959 struct tty_ldisc
*ld
;
962 ld
= tty_ldisc_ref(tty
);
964 if (ld
->ops
->receive_buf
)
965 ld
->ops
->receive_buf(tty
, data
, flags
, count
);
970 /* mgsl_stop() throttle (stop) transmitter
972 * Arguments: tty pointer to tty info structure
975 static void mgsl_stop(struct tty_struct
*tty
)
977 struct mgsl_struct
*info
= tty
->driver_data
;
980 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
983 if ( debug_level
>= DEBUG_LEVEL_INFO
)
984 printk("mgsl_stop(%s)\n",info
->device_name
);
986 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
987 if (info
->tx_enabled
)
988 usc_stop_transmitter(info
);
989 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
991 } /* end of mgsl_stop() */
993 /* mgsl_start() release (start) transmitter
995 * Arguments: tty pointer to tty info structure
998 static void mgsl_start(struct tty_struct
*tty
)
1000 struct mgsl_struct
*info
= tty
->driver_data
;
1001 unsigned long flags
;
1003 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1006 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1007 printk("mgsl_start(%s)\n",info
->device_name
);
1009 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1010 if (!info
->tx_enabled
)
1011 usc_start_transmitter(info
);
1012 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1014 } /* end of mgsl_start() */
1017 * Bottom half work queue access functions
1020 /* mgsl_bh_action() Return next bottom half action to perform.
1021 * Return Value: BH action code or 0 if nothing to do.
1023 static int mgsl_bh_action(struct mgsl_struct
*info
)
1025 unsigned long flags
;
1028 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1030 if (info
->pending_bh
& BH_RECEIVE
) {
1031 info
->pending_bh
&= ~BH_RECEIVE
;
1033 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1034 info
->pending_bh
&= ~BH_TRANSMIT
;
1036 } else if (info
->pending_bh
& BH_STATUS
) {
1037 info
->pending_bh
&= ~BH_STATUS
;
1042 /* Mark BH routine as complete */
1043 info
->bh_running
= false;
1044 info
->bh_requested
= false;
1047 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1053 * Perform bottom half processing of work items queued by ISR.
1055 static void mgsl_bh_handler(struct work_struct
*work
)
1057 struct mgsl_struct
*info
=
1058 container_of(work
, struct mgsl_struct
, task
);
1061 if ( debug_level
>= DEBUG_LEVEL_BH
)
1062 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1063 __FILE__
,__LINE__
,info
->device_name
);
1065 info
->bh_running
= true;
1067 while((action
= mgsl_bh_action(info
)) != 0) {
1069 /* Process work item */
1070 if ( debug_level
>= DEBUG_LEVEL_BH
)
1071 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1072 __FILE__
,__LINE__
,action
);
1077 mgsl_bh_receive(info
);
1080 mgsl_bh_transmit(info
);
1083 mgsl_bh_status(info
);
1086 /* unknown work item ID */
1087 printk("Unknown work item ID=%08X!\n", action
);
1092 if ( debug_level
>= DEBUG_LEVEL_BH
)
1093 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1094 __FILE__
,__LINE__
,info
->device_name
);
1097 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1099 bool (*get_rx_frame
)(struct mgsl_struct
*info
) =
1100 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1102 if ( debug_level
>= DEBUG_LEVEL_BH
)
1103 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1104 __FILE__
,__LINE__
,info
->device_name
);
1108 if (info
->rx_rcc_underrun
) {
1109 unsigned long flags
;
1110 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1111 usc_start_receiver(info
);
1112 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1115 } while(get_rx_frame(info
));
1118 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1120 struct tty_struct
*tty
= info
->port
.tty
;
1121 unsigned long flags
;
1123 if ( debug_level
>= DEBUG_LEVEL_BH
)
1124 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1125 __FILE__
,__LINE__
,info
->device_name
);
1130 /* if transmitter idle and loopmode_send_done_requested
1131 * then start echoing RxD to TxD
1133 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1134 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1135 usc_loopmode_send_done( info
);
1136 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1139 static void mgsl_bh_status(struct mgsl_struct
*info
)
1141 if ( debug_level
>= DEBUG_LEVEL_BH
)
1142 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1143 __FILE__
,__LINE__
,info
->device_name
);
1145 info
->ri_chkcount
= 0;
1146 info
->dsr_chkcount
= 0;
1147 info
->dcd_chkcount
= 0;
1148 info
->cts_chkcount
= 0;
1151 /* mgsl_isr_receive_status()
1153 * Service a receive status interrupt. The type of status
1154 * interrupt is indicated by the state of the RCSR.
1155 * This is only used for HDLC mode.
1157 * Arguments: info pointer to device instance data
1158 * Return Value: None
1160 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1162 u16 status
= usc_InReg( info
, RCSR
);
1164 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1165 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1166 __FILE__
,__LINE__
,status
);
1168 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1169 info
->loopmode_insert_requested
&&
1170 usc_loopmode_active(info
) )
1172 ++info
->icount
.rxabort
;
1173 info
->loopmode_insert_requested
= false;
1175 /* clear CMR:13 to start echoing RxD to TxD */
1176 info
->cmr_value
&= ~BIT13
;
1177 usc_OutReg(info
, CMR
, info
->cmr_value
);
1179 /* disable received abort irq (no longer required) */
1180 usc_OutReg(info
, RICR
,
1181 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1184 if (status
& (RXSTATUS_EXITED_HUNT
| RXSTATUS_IDLE_RECEIVED
)) {
1185 if (status
& RXSTATUS_EXITED_HUNT
)
1186 info
->icount
.exithunt
++;
1187 if (status
& RXSTATUS_IDLE_RECEIVED
)
1188 info
->icount
.rxidle
++;
1189 wake_up_interruptible(&info
->event_wait_q
);
1192 if (status
& RXSTATUS_OVERRUN
){
1193 info
->icount
.rxover
++;
1194 usc_process_rxoverrun_sync( info
);
1197 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1198 usc_UnlatchRxstatusBits( info
, status
);
1200 } /* end of mgsl_isr_receive_status() */
1202 /* mgsl_isr_transmit_status()
1204 * Service a transmit status interrupt
1205 * HDLC mode :end of transmit frame
1206 * Async mode:all data is sent
1207 * transmit status is indicated by bits in the TCSR.
1209 * Arguments: info pointer to device instance data
1210 * Return Value: None
1212 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1214 u16 status
= usc_InReg( info
, TCSR
);
1216 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1217 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1218 __FILE__
,__LINE__
,status
);
1220 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1221 usc_UnlatchTxstatusBits( info
, status
);
1223 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1225 /* finished sending HDLC abort. This may leave */
1226 /* the TxFifo with data from the aborted frame */
1227 /* so purge the TxFifo. Also shutdown the DMA */
1228 /* channel in case there is data remaining in */
1229 /* the DMA buffer */
1230 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1231 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1234 if ( status
& TXSTATUS_EOF_SENT
)
1235 info
->icount
.txok
++;
1236 else if ( status
& TXSTATUS_UNDERRUN
)
1237 info
->icount
.txunder
++;
1238 else if ( status
& TXSTATUS_ABORT_SENT
)
1239 info
->icount
.txabort
++;
1241 info
->icount
.txunder
++;
1243 info
->tx_active
= false;
1244 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1245 del_timer(&info
->tx_timer
);
1247 if ( info
->drop_rts_on_tx_done
) {
1248 usc_get_serial_signals( info
);
1249 if ( info
->serial_signals
& SerialSignal_RTS
) {
1250 info
->serial_signals
&= ~SerialSignal_RTS
;
1251 usc_set_serial_signals( info
);
1253 info
->drop_rts_on_tx_done
= false;
1256 #if SYNCLINK_GENERIC_HDLC
1258 hdlcdev_tx_done(info
);
1262 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1263 usc_stop_transmitter(info
);
1266 info
->pending_bh
|= BH_TRANSMIT
;
1269 } /* end of mgsl_isr_transmit_status() */
1271 /* mgsl_isr_io_pin()
1273 * Service an Input/Output pin interrupt. The type of
1274 * interrupt is indicated by bits in the MISR
1276 * Arguments: info pointer to device instance data
1277 * Return Value: None
1279 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1281 struct mgsl_icount
*icount
;
1282 u16 status
= usc_InReg( info
, MISR
);
1284 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1285 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1286 __FILE__
,__LINE__
,status
);
1288 usc_ClearIrqPendingBits( info
, IO_PIN
);
1289 usc_UnlatchIostatusBits( info
, status
);
1291 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1292 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1293 icount
= &info
->icount
;
1294 /* update input line counters */
1295 if (status
& MISCSTATUS_RI_LATCHED
) {
1296 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1297 usc_DisablestatusIrqs(info
,SICR_RI
);
1299 if ( status
& MISCSTATUS_RI
)
1300 info
->input_signal_events
.ri_up
++;
1302 info
->input_signal_events
.ri_down
++;
1304 if (status
& MISCSTATUS_DSR_LATCHED
) {
1305 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1306 usc_DisablestatusIrqs(info
,SICR_DSR
);
1308 if ( status
& MISCSTATUS_DSR
)
1309 info
->input_signal_events
.dsr_up
++;
1311 info
->input_signal_events
.dsr_down
++;
1313 if (status
& MISCSTATUS_DCD_LATCHED
) {
1314 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1315 usc_DisablestatusIrqs(info
,SICR_DCD
);
1317 if (status
& MISCSTATUS_DCD
) {
1318 info
->input_signal_events
.dcd_up
++;
1320 info
->input_signal_events
.dcd_down
++;
1321 #if SYNCLINK_GENERIC_HDLC
1322 if (info
->netcount
) {
1323 if (status
& MISCSTATUS_DCD
)
1324 netif_carrier_on(info
->netdev
);
1326 netif_carrier_off(info
->netdev
);
1330 if (status
& MISCSTATUS_CTS_LATCHED
)
1332 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1333 usc_DisablestatusIrqs(info
,SICR_CTS
);
1335 if ( status
& MISCSTATUS_CTS
)
1336 info
->input_signal_events
.cts_up
++;
1338 info
->input_signal_events
.cts_down
++;
1340 wake_up_interruptible(&info
->status_event_wait_q
);
1341 wake_up_interruptible(&info
->event_wait_q
);
1343 if (tty_port_check_carrier(&info
->port
) &&
1344 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1345 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1346 printk("%s CD now %s...", info
->device_name
,
1347 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1348 if (status
& MISCSTATUS_DCD
)
1349 wake_up_interruptible(&info
->port
.open_wait
);
1351 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1352 printk("doing serial hangup...");
1354 tty_hangup(info
->port
.tty
);
1358 if (tty_port_cts_enabled(&info
->port
) &&
1359 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1360 if (info
->port
.tty
->hw_stopped
) {
1361 if (status
& MISCSTATUS_CTS
) {
1362 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1363 printk("CTS tx start...");
1365 info
->port
.tty
->hw_stopped
= 0;
1366 usc_start_transmitter(info
);
1367 info
->pending_bh
|= BH_TRANSMIT
;
1371 if (!(status
& MISCSTATUS_CTS
)) {
1372 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1373 printk("CTS tx stop...");
1375 info
->port
.tty
->hw_stopped
= 1;
1376 usc_stop_transmitter(info
);
1382 info
->pending_bh
|= BH_STATUS
;
1384 /* for diagnostics set IRQ flag */
1385 if ( status
& MISCSTATUS_TXC_LATCHED
){
1386 usc_OutReg( info
, SICR
,
1387 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1388 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1389 info
->irq_occurred
= true;
1392 } /* end of mgsl_isr_io_pin() */
1394 /* mgsl_isr_transmit_data()
1396 * Service a transmit data interrupt (async mode only).
1398 * Arguments: info pointer to device instance data
1399 * Return Value: None
1401 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1403 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1404 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1405 __FILE__
,__LINE__
,info
->xmit_cnt
);
1407 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1409 if (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
) {
1410 usc_stop_transmitter(info
);
1414 if ( info
->xmit_cnt
)
1415 usc_load_txfifo( info
);
1417 info
->tx_active
= false;
1419 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1420 info
->pending_bh
|= BH_TRANSMIT
;
1422 } /* end of mgsl_isr_transmit_data() */
1424 /* mgsl_isr_receive_data()
1426 * Service a receive data interrupt. This occurs
1427 * when operating in asynchronous interrupt transfer mode.
1428 * The receive data FIFO is flushed to the receive data buffers.
1430 * Arguments: info pointer to device instance data
1431 * Return Value: None
1433 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1438 unsigned char DataByte
;
1439 struct mgsl_icount
*icount
= &info
->icount
;
1441 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1442 printk("%s(%d):mgsl_isr_receive_data\n",
1445 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1447 /* select FIFO status for RICR readback */
1448 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1450 /* clear the Wordstatus bit so that status readback */
1451 /* only reflects the status of this byte */
1452 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1454 /* flush the receive FIFO */
1456 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1459 /* read one byte from RxFIFO */
1460 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1461 info
->io_base
+ CCAR
);
1462 DataByte
= inb( info
->io_base
+ CCAR
);
1464 /* get the status of the received byte */
1465 status
= usc_InReg(info
, RCSR
);
1466 if ( status
& (RXSTATUS_FRAMING_ERROR
| RXSTATUS_PARITY_ERROR
|
1467 RXSTATUS_OVERRUN
| RXSTATUS_BREAK_RECEIVED
) )
1468 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1473 if ( status
& (RXSTATUS_FRAMING_ERROR
| RXSTATUS_PARITY_ERROR
|
1474 RXSTATUS_OVERRUN
| RXSTATUS_BREAK_RECEIVED
) ) {
1475 printk("rxerr=%04X\n",status
);
1476 /* update error statistics */
1477 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1478 status
&= ~(RXSTATUS_FRAMING_ERROR
| RXSTATUS_PARITY_ERROR
);
1480 } else if (status
& RXSTATUS_PARITY_ERROR
)
1482 else if (status
& RXSTATUS_FRAMING_ERROR
)
1484 else if (status
& RXSTATUS_OVERRUN
) {
1485 /* must issue purge fifo cmd before */
1486 /* 16C32 accepts more receive chars */
1487 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1491 /* discard char if tty control flags say so */
1492 if (status
& info
->ignore_status_mask
)
1495 status
&= info
->read_status_mask
;
1497 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1499 if (info
->port
.flags
& ASYNC_SAK
)
1500 do_SAK(info
->port
.tty
);
1501 } else if (status
& RXSTATUS_PARITY_ERROR
)
1503 else if (status
& RXSTATUS_FRAMING_ERROR
)
1505 } /* end of if (error) */
1506 tty_insert_flip_char(&info
->port
, DataByte
, flag
);
1507 if (status
& RXSTATUS_OVERRUN
) {
1508 /* Overrun is special, since it's
1509 * reported immediately, and doesn't
1510 * affect the current character
1512 work
+= tty_insert_flip_char(&info
->port
, 0, TTY_OVERRUN
);
1516 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1517 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1518 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1519 icount
->parity
,icount
->frame
,icount
->overrun
);
1523 tty_flip_buffer_push(&info
->port
);
1528 * Service a miscellaneous interrupt source.
1530 * Arguments: info pointer to device extension (instance data)
1531 * Return Value: None
1533 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1535 u16 status
= usc_InReg( info
, MISR
);
1537 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1538 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1539 __FILE__
,__LINE__
,status
);
1541 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1542 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1544 /* turn off receiver and rx DMA */
1545 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1546 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1547 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1548 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
| RECEIVE_STATUS
);
1549 usc_DisableInterrupts(info
, RECEIVE_DATA
| RECEIVE_STATUS
);
1551 /* schedule BH handler to restart receiver */
1552 info
->pending_bh
|= BH_RECEIVE
;
1553 info
->rx_rcc_underrun
= true;
1556 usc_ClearIrqPendingBits( info
, MISC
);
1557 usc_UnlatchMiscstatusBits( info
, status
);
1559 } /* end of mgsl_isr_misc() */
1563 * Services undefined interrupt vectors from the
1564 * USC. (hence this function SHOULD never be called)
1566 * Arguments: info pointer to device extension (instance data)
1567 * Return Value: None
1569 static void mgsl_isr_null( struct mgsl_struct
*info
)
1572 } /* end of mgsl_isr_null() */
1574 /* mgsl_isr_receive_dma()
1576 * Service a receive DMA channel interrupt.
1577 * For this driver there are two sources of receive DMA interrupts
1578 * as identified in the Receive DMA mode Register (RDMR):
1580 * BIT3 EOA/EOL End of List, all receive buffers in receive
1581 * buffer list have been filled (no more free buffers
1582 * available). The DMA controller has shut down.
1584 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1585 * DMA buffer is terminated in response to completion
1586 * of a good frame or a frame with errors. The status
1587 * of the frame is stored in the buffer entry in the
1588 * list of receive buffer entries.
1590 * Arguments: info pointer to device instance data
1591 * Return Value: None
1593 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1597 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1598 usc_OutDmaReg( info
, CDIR
, BIT9
| BIT1
);
1600 /* Read the receive DMA status to identify interrupt type. */
1601 /* This also clears the status bits. */
1602 status
= usc_InDmaReg( info
, RDMR
);
1604 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1605 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1606 __FILE__
,__LINE__
,info
->device_name
,status
);
1608 info
->pending_bh
|= BH_RECEIVE
;
1610 if ( status
& BIT3
) {
1611 info
->rx_overflow
= true;
1612 info
->icount
.buf_overrun
++;
1615 } /* end of mgsl_isr_receive_dma() */
1617 /* mgsl_isr_transmit_dma()
1619 * This function services a transmit DMA channel interrupt.
1621 * For this driver there is one source of transmit DMA interrupts
1622 * as identified in the Transmit DMA Mode Register (TDMR):
1624 * BIT2 EOB End of Buffer. This interrupt occurs when a
1625 * transmit DMA buffer has been emptied.
1627 * The driver maintains enough transmit DMA buffers to hold at least
1628 * one max frame size transmit frame. When operating in a buffered
1629 * transmit mode, there may be enough transmit DMA buffers to hold at
1630 * least two or more max frame size frames. On an EOB condition,
1631 * determine if there are any queued transmit buffers and copy into
1632 * transmit DMA buffers if we have room.
1634 * Arguments: info pointer to device instance data
1635 * Return Value: None
1637 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1641 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1642 usc_OutDmaReg(info
, CDIR
, BIT8
| BIT0
);
1644 /* Read the transmit DMA status to identify interrupt type. */
1645 /* This also clears the status bits. */
1647 status
= usc_InDmaReg( info
, TDMR
);
1649 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1650 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1651 __FILE__
,__LINE__
,info
->device_name
,status
);
1653 if ( status
& BIT2
) {
1654 --info
->tx_dma_buffers_used
;
1656 /* if there are transmit frames queued,
1657 * try to load the next one
1659 if ( load_next_tx_holding_buffer(info
) ) {
1660 /* if call returns non-zero value, we have
1661 * at least one free tx holding buffer
1663 info
->pending_bh
|= BH_TRANSMIT
;
1667 } /* end of mgsl_isr_transmit_dma() */
1671 * Interrupt service routine entry point.
1675 * irq interrupt number that caused interrupt
1676 * dev_id device ID supplied during interrupt registration
1678 * Return Value: None
1680 static irqreturn_t
mgsl_interrupt(int dummy
, void *dev_id
)
1682 struct mgsl_struct
*info
= dev_id
;
1686 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1687 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)entry.\n",
1688 __FILE__
, __LINE__
, info
->irq_level
);
1690 spin_lock(&info
->irq_spinlock
);
1693 /* Read the interrupt vectors from hardware. */
1694 UscVector
= usc_InReg(info
, IVR
) >> 9;
1695 DmaVector
= usc_InDmaReg(info
, DIVR
);
1697 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1698 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1699 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1701 if ( !UscVector
&& !DmaVector
)
1704 /* Dispatch interrupt vector */
1706 (*UscIsrTable
[UscVector
])(info
);
1707 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1708 mgsl_isr_transmit_dma(info
);
1710 mgsl_isr_receive_dma(info
);
1712 if ( info
->isr_overflow
) {
1713 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1714 __FILE__
, __LINE__
, info
->device_name
, info
->irq_level
);
1715 usc_DisableMasterIrqBit(info
);
1716 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1721 /* Request bottom half processing if there's something
1722 * for it to do and the bh is not already running
1725 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1726 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1727 printk("%s(%d):%s queueing bh task.\n",
1728 __FILE__
,__LINE__
,info
->device_name
);
1729 schedule_work(&info
->task
);
1730 info
->bh_requested
= true;
1733 spin_unlock(&info
->irq_spinlock
);
1735 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1736 printk(KERN_DEBUG
"%s(%d):mgsl_interrupt(%d)exit.\n",
1737 __FILE__
, __LINE__
, info
->irq_level
);
1740 } /* end of mgsl_interrupt() */
1744 * Initialize and start device.
1746 * Arguments: info pointer to device instance data
1747 * Return Value: 0 if success, otherwise error code
1749 static int startup(struct mgsl_struct
* info
)
1753 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1754 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1756 if (tty_port_initialized(&info
->port
))
1759 if (!info
->xmit_buf
) {
1760 /* allocate a page of memory for a transmit buffer */
1761 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1762 if (!info
->xmit_buf
) {
1763 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1764 __FILE__
,__LINE__
,info
->device_name
);
1769 info
->pending_bh
= 0;
1771 memset(&info
->icount
, 0, sizeof(info
->icount
));
1773 setup_timer(&info
->tx_timer
, mgsl_tx_timeout
, (unsigned long)info
);
1775 /* Allocate and claim adapter resources */
1776 retval
= mgsl_claim_resources(info
);
1778 /* perform existence check and diagnostics */
1780 retval
= mgsl_adapter_test(info
);
1783 if (capable(CAP_SYS_ADMIN
) && info
->port
.tty
)
1784 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1785 mgsl_release_resources(info
);
1789 /* program hardware for current parameters */
1790 mgsl_change_params(info
);
1793 clear_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1795 tty_port_set_initialized(&info
->port
, 1);
1798 } /* end of startup() */
1802 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1804 * Arguments: info pointer to device instance data
1805 * Return Value: None
1807 static void shutdown(struct mgsl_struct
* info
)
1809 unsigned long flags
;
1811 if (!tty_port_initialized(&info
->port
))
1814 if (debug_level
>= DEBUG_LEVEL_INFO
)
1815 printk("%s(%d):mgsl_shutdown(%s)\n",
1816 __FILE__
,__LINE__
, info
->device_name
);
1818 /* clear status wait queue because status changes */
1819 /* can't happen after shutting down the hardware */
1820 wake_up_interruptible(&info
->status_event_wait_q
);
1821 wake_up_interruptible(&info
->event_wait_q
);
1823 del_timer_sync(&info
->tx_timer
);
1825 if (info
->xmit_buf
) {
1826 free_page((unsigned long) info
->xmit_buf
);
1827 info
->xmit_buf
= NULL
;
1830 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1831 usc_DisableMasterIrqBit(info
);
1832 usc_stop_receiver(info
);
1833 usc_stop_transmitter(info
);
1834 usc_DisableInterrupts(info
,RECEIVE_DATA
| RECEIVE_STATUS
|
1835 TRANSMIT_DATA
| TRANSMIT_STATUS
| IO_PIN
| MISC
);
1836 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1838 /* Disable DMAEN (Port 7, Bit 14) */
1839 /* This disconnects the DMA request signal from the ISA bus */
1840 /* on the ISA adapter. This has no effect for the PCI adapter */
1841 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1843 /* Disable INTEN (Port 6, Bit12) */
1844 /* This disconnects the IRQ request signal to the ISA bus */
1845 /* on the ISA adapter. This has no effect for the PCI adapter */
1846 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1848 if (!info
->port
.tty
|| info
->port
.tty
->termios
.c_cflag
& HUPCL
) {
1849 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
1850 usc_set_serial_signals(info
);
1853 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1855 mgsl_release_resources(info
);
1858 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
1860 tty_port_set_initialized(&info
->port
, 0);
1861 } /* end of shutdown() */
1863 static void mgsl_program_hw(struct mgsl_struct
*info
)
1865 unsigned long flags
;
1867 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1869 usc_stop_receiver(info
);
1870 usc_stop_transmitter(info
);
1871 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1873 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1874 info
->params
.mode
== MGSL_MODE_RAW
||
1876 usc_set_sync_mode(info
);
1878 usc_set_async_mode(info
);
1880 usc_set_serial_signals(info
);
1882 info
->dcd_chkcount
= 0;
1883 info
->cts_chkcount
= 0;
1884 info
->ri_chkcount
= 0;
1885 info
->dsr_chkcount
= 0;
1887 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1888 usc_EnableInterrupts(info
, IO_PIN
);
1889 usc_get_serial_signals(info
);
1891 if (info
->netcount
|| info
->port
.tty
->termios
.c_cflag
& CREAD
)
1892 usc_start_receiver(info
);
1894 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1897 /* Reconfigure adapter based on new parameters
1899 static void mgsl_change_params(struct mgsl_struct
*info
)
1904 if (!info
->port
.tty
)
1907 if (debug_level
>= DEBUG_LEVEL_INFO
)
1908 printk("%s(%d):mgsl_change_params(%s)\n",
1909 __FILE__
,__LINE__
, info
->device_name
);
1911 cflag
= info
->port
.tty
->termios
.c_cflag
;
1913 /* if B0 rate (hangup) specified then negate RTS and DTR */
1914 /* otherwise assert RTS and DTR */
1916 info
->serial_signals
|= SerialSignal_RTS
| SerialSignal_DTR
;
1918 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
1920 /* byte size and parity */
1922 switch (cflag
& CSIZE
) {
1923 case CS5
: info
->params
.data_bits
= 5; break;
1924 case CS6
: info
->params
.data_bits
= 6; break;
1925 case CS7
: info
->params
.data_bits
= 7; break;
1926 case CS8
: info
->params
.data_bits
= 8; break;
1927 /* Never happens, but GCC is too dumb to figure it out */
1928 default: info
->params
.data_bits
= 7; break;
1932 info
->params
.stop_bits
= 2;
1934 info
->params
.stop_bits
= 1;
1936 info
->params
.parity
= ASYNC_PARITY_NONE
;
1937 if (cflag
& PARENB
) {
1939 info
->params
.parity
= ASYNC_PARITY_ODD
;
1941 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1944 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1948 /* calculate number of jiffies to transmit a full
1949 * FIFO (32 bytes) at specified data rate
1951 bits_per_char
= info
->params
.data_bits
+
1952 info
->params
.stop_bits
+ 1;
1954 /* if port data rate is set to 460800 or less then
1955 * allow tty settings to override, otherwise keep the
1956 * current data rate.
1958 if (info
->params
.data_rate
<= 460800)
1959 info
->params
.data_rate
= tty_get_baud_rate(info
->port
.tty
);
1961 if ( info
->params
.data_rate
) {
1962 info
->timeout
= (32*HZ
*bits_per_char
) /
1963 info
->params
.data_rate
;
1965 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
1967 tty_port_set_cts_flow(&info
->port
, cflag
& CRTSCTS
);
1968 tty_port_set_check_carrier(&info
->port
, ~cflag
& CLOCAL
);
1970 /* process tty input control flags */
1972 info
->read_status_mask
= RXSTATUS_OVERRUN
;
1973 if (I_INPCK(info
->port
.tty
))
1974 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1975 if (I_BRKINT(info
->port
.tty
) || I_PARMRK(info
->port
.tty
))
1976 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1978 if (I_IGNPAR(info
->port
.tty
))
1979 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1980 if (I_IGNBRK(info
->port
.tty
)) {
1981 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1982 /* If ignoring parity and break indicators, ignore
1983 * overruns too. (For real raw support).
1985 if (I_IGNPAR(info
->port
.tty
))
1986 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
1989 mgsl_program_hw(info
);
1991 } /* end of mgsl_change_params() */
1995 * Add a character to the transmit buffer.
1997 * Arguments: tty pointer to tty information structure
1998 * ch character to add to transmit buffer
2000 * Return Value: None
2002 static int mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2004 struct mgsl_struct
*info
= tty
->driver_data
;
2005 unsigned long flags
;
2008 if (debug_level
>= DEBUG_LEVEL_INFO
) {
2009 printk(KERN_DEBUG
"%s(%d):mgsl_put_char(%d) on %s\n",
2010 __FILE__
, __LINE__
, ch
, info
->device_name
);
2013 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2016 if (!info
->xmit_buf
)
2019 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
2021 if ((info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2022 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2023 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2024 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2029 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
2032 } /* end of mgsl_put_char() */
2034 /* mgsl_flush_chars()
2036 * Enable transmitter so remaining characters in the
2037 * transmit buffer are sent.
2039 * Arguments: tty pointer to tty information structure
2040 * Return Value: None
2042 static void mgsl_flush_chars(struct tty_struct
*tty
)
2044 struct mgsl_struct
*info
= tty
->driver_data
;
2045 unsigned long flags
;
2047 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2048 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2049 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2051 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2054 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2058 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2059 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2060 __FILE__
,__LINE__
,info
->device_name
);
2062 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2064 if (!info
->tx_active
) {
2065 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2066 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2067 /* operating in synchronous (frame oriented) mode */
2068 /* copy data from circular xmit_buf to */
2069 /* transmit DMA buffer. */
2070 mgsl_load_tx_dma_buffer(info
,
2071 info
->xmit_buf
,info
->xmit_cnt
);
2073 usc_start_transmitter(info
);
2076 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2078 } /* end of mgsl_flush_chars() */
2082 * Send a block of data
2086 * tty pointer to tty information structure
2087 * buf pointer to buffer containing send data
2088 * count size of send data in bytes
2090 * Return Value: number of characters written
2092 static int mgsl_write(struct tty_struct
* tty
,
2093 const unsigned char *buf
, int count
)
2096 struct mgsl_struct
*info
= tty
->driver_data
;
2097 unsigned long flags
;
2099 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2100 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2101 __FILE__
,__LINE__
,info
->device_name
,count
);
2103 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2106 if (!info
->xmit_buf
)
2109 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2110 info
->params
.mode
== MGSL_MODE_RAW
) {
2111 /* operating in synchronous (frame oriented) mode */
2112 if (info
->tx_active
) {
2114 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2118 /* transmitter is actively sending data -
2119 * if we have multiple transmit dma and
2120 * holding buffers, attempt to queue this
2121 * frame for transmission at a later time.
2123 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2124 /* no tx holding buffers available */
2129 /* queue transmit frame request */
2131 save_tx_buffer_request(info
,buf
,count
);
2133 /* if we have sufficient tx dma buffers,
2134 * load the next buffered tx request
2136 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2137 load_next_tx_holding_buffer(info
);
2138 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2142 /* if operating in HDLC LoopMode and the adapter */
2143 /* has yet to be inserted into the loop, we can't */
2146 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2147 !usc_loopmode_active(info
) )
2153 if ( info
->xmit_cnt
) {
2154 /* Send accumulated from send_char() calls */
2155 /* as frame and wait before accepting more data. */
2158 /* copy data from circular xmit_buf to */
2159 /* transmit DMA buffer. */
2160 mgsl_load_tx_dma_buffer(info
,
2161 info
->xmit_buf
,info
->xmit_cnt
);
2162 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2163 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2164 __FILE__
,__LINE__
,info
->device_name
);
2166 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2167 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2168 __FILE__
,__LINE__
,info
->device_name
);
2170 info
->xmit_cnt
= count
;
2171 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2175 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2176 c
= min_t(int, count
,
2177 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2178 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2180 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2183 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2184 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2185 (SERIAL_XMIT_SIZE
-1));
2186 info
->xmit_cnt
+= c
;
2187 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2194 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2195 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2196 if (!info
->tx_active
)
2197 usc_start_transmitter(info
);
2198 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2201 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2202 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2203 __FILE__
,__LINE__
,info
->device_name
,ret
);
2207 } /* end of mgsl_write() */
2209 /* mgsl_write_room()
2211 * Return the count of free bytes in transmit buffer
2213 * Arguments: tty pointer to tty info structure
2214 * Return Value: None
2216 static int mgsl_write_room(struct tty_struct
*tty
)
2218 struct mgsl_struct
*info
= tty
->driver_data
;
2221 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2223 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2227 if (debug_level
>= DEBUG_LEVEL_INFO
)
2228 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2229 __FILE__
,__LINE__
, info
->device_name
,ret
);
2231 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2232 info
->params
.mode
== MGSL_MODE_RAW
) {
2233 /* operating in synchronous (frame oriented) mode */
2234 if ( info
->tx_active
)
2237 return HDLC_MAX_FRAME_SIZE
;
2242 } /* end of mgsl_write_room() */
2244 /* mgsl_chars_in_buffer()
2246 * Return the count of bytes in transmit buffer
2248 * Arguments: tty pointer to tty info structure
2249 * Return Value: None
2251 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2253 struct mgsl_struct
*info
= tty
->driver_data
;
2255 if (debug_level
>= DEBUG_LEVEL_INFO
)
2256 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2257 __FILE__
,__LINE__
, info
->device_name
);
2259 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2262 if (debug_level
>= DEBUG_LEVEL_INFO
)
2263 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2264 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2266 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2267 info
->params
.mode
== MGSL_MODE_RAW
) {
2268 /* operating in synchronous (frame oriented) mode */
2269 if ( info
->tx_active
)
2270 return info
->max_frame_size
;
2275 return info
->xmit_cnt
;
2276 } /* end of mgsl_chars_in_buffer() */
2278 /* mgsl_flush_buffer()
2280 * Discard all data in the send buffer
2282 * Arguments: tty pointer to tty info structure
2283 * Return Value: None
2285 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2287 struct mgsl_struct
*info
= tty
->driver_data
;
2288 unsigned long flags
;
2290 if (debug_level
>= DEBUG_LEVEL_INFO
)
2291 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2292 __FILE__
,__LINE__
, info
->device_name
);
2294 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2297 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2298 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2299 del_timer(&info
->tx_timer
);
2300 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2305 /* mgsl_send_xchar()
2307 * Send a high-priority XON/XOFF character
2309 * Arguments: tty pointer to tty info structure
2310 * ch character to send
2311 * Return Value: None
2313 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2315 struct mgsl_struct
*info
= tty
->driver_data
;
2316 unsigned long flags
;
2318 if (debug_level
>= DEBUG_LEVEL_INFO
)
2319 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2320 __FILE__
,__LINE__
, info
->device_name
, ch
);
2322 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2327 /* Make sure transmit interrupts are on */
2328 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2329 if (!info
->tx_enabled
)
2330 usc_start_transmitter(info
);
2331 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2333 } /* end of mgsl_send_xchar() */
2337 * Signal remote device to throttle send data (our receive data)
2339 * Arguments: tty pointer to tty info structure
2340 * Return Value: None
2342 static void mgsl_throttle(struct tty_struct
* tty
)
2344 struct mgsl_struct
*info
= tty
->driver_data
;
2345 unsigned long flags
;
2347 if (debug_level
>= DEBUG_LEVEL_INFO
)
2348 printk("%s(%d):mgsl_throttle(%s) entry\n",
2349 __FILE__
,__LINE__
, info
->device_name
);
2351 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2355 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2357 if (C_CRTSCTS(tty
)) {
2358 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2359 info
->serial_signals
&= ~SerialSignal_RTS
;
2360 usc_set_serial_signals(info
);
2361 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2363 } /* end of mgsl_throttle() */
2365 /* mgsl_unthrottle()
2367 * Signal remote device to stop throttling send data (our receive data)
2369 * Arguments: tty pointer to tty info structure
2370 * Return Value: None
2372 static void mgsl_unthrottle(struct tty_struct
* tty
)
2374 struct mgsl_struct
*info
= tty
->driver_data
;
2375 unsigned long flags
;
2377 if (debug_level
>= DEBUG_LEVEL_INFO
)
2378 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2379 __FILE__
,__LINE__
, info
->device_name
);
2381 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2388 mgsl_send_xchar(tty
, START_CHAR(tty
));
2391 if (C_CRTSCTS(tty
)) {
2392 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2393 info
->serial_signals
|= SerialSignal_RTS
;
2394 usc_set_serial_signals(info
);
2395 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2398 } /* end of mgsl_unthrottle() */
2402 * get the current serial parameters information
2404 * Arguments: info pointer to device instance data
2405 * user_icount pointer to buffer to hold returned stats
2407 * Return Value: 0 if success, otherwise error code
2409 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2413 if (debug_level
>= DEBUG_LEVEL_INFO
)
2414 printk("%s(%d):mgsl_get_params(%s)\n",
2415 __FILE__
,__LINE__
, info
->device_name
);
2418 memset(&info
->icount
, 0, sizeof(info
->icount
));
2420 mutex_lock(&info
->port
.mutex
);
2421 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2422 mutex_unlock(&info
->port
.mutex
);
2429 } /* end of mgsl_get_stats() */
2431 /* mgsl_get_params()
2433 * get the current serial parameters information
2435 * Arguments: info pointer to device instance data
2436 * user_params pointer to buffer to hold returned params
2438 * Return Value: 0 if success, otherwise error code
2440 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2443 if (debug_level
>= DEBUG_LEVEL_INFO
)
2444 printk("%s(%d):mgsl_get_params(%s)\n",
2445 __FILE__
,__LINE__
, info
->device_name
);
2447 mutex_lock(&info
->port
.mutex
);
2448 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2449 mutex_unlock(&info
->port
.mutex
);
2451 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2452 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2453 __FILE__
,__LINE__
,info
->device_name
);
2459 } /* end of mgsl_get_params() */
2461 /* mgsl_set_params()
2463 * set the serial parameters
2467 * info pointer to device instance data
2468 * new_params user buffer containing new serial params
2470 * Return Value: 0 if success, otherwise error code
2472 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2474 unsigned long flags
;
2475 MGSL_PARAMS tmp_params
;
2478 if (debug_level
>= DEBUG_LEVEL_INFO
)
2479 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2480 info
->device_name
);
2481 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2483 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2484 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2485 __FILE__
,__LINE__
,info
->device_name
);
2489 mutex_lock(&info
->port
.mutex
);
2490 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2491 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2492 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2494 mgsl_change_params(info
);
2495 mutex_unlock(&info
->port
.mutex
);
2499 } /* end of mgsl_set_params() */
2501 /* mgsl_get_txidle()
2503 * get the current transmit idle mode
2505 * Arguments: info pointer to device instance data
2506 * idle_mode pointer to buffer to hold returned idle mode
2508 * Return Value: 0 if success, otherwise error code
2510 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2514 if (debug_level
>= DEBUG_LEVEL_INFO
)
2515 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2516 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2518 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2520 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2521 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2522 __FILE__
,__LINE__
,info
->device_name
);
2528 } /* end of mgsl_get_txidle() */
2530 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2532 * Arguments: info pointer to device instance data
2533 * idle_mode new idle mode
2535 * Return Value: 0 if success, otherwise error code
2537 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2539 unsigned long flags
;
2541 if (debug_level
>= DEBUG_LEVEL_INFO
)
2542 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2543 info
->device_name
, idle_mode
);
2545 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2546 info
->idle_mode
= idle_mode
;
2547 usc_set_txidle( info
);
2548 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2551 } /* end of mgsl_set_txidle() */
2555 * enable or disable the transmitter
2559 * info pointer to device instance data
2560 * enable 1 = enable, 0 = disable
2562 * Return Value: 0 if success, otherwise error code
2564 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2566 unsigned long flags
;
2568 if (debug_level
>= DEBUG_LEVEL_INFO
)
2569 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2570 info
->device_name
, enable
);
2572 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2574 if ( !info
->tx_enabled
) {
2576 usc_start_transmitter(info
);
2577 /*--------------------------------------------------
2578 * if HDLC/SDLC Loop mode, attempt to insert the
2579 * station in the 'loop' by setting CMR:13. Upon
2580 * receipt of the next GoAhead (RxAbort) sequence,
2581 * the OnLoop indicator (CCSR:7) should go active
2582 * to indicate that we are on the loop
2583 *--------------------------------------------------*/
2584 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2585 usc_loopmode_insert_request( info
);
2588 if ( info
->tx_enabled
)
2589 usc_stop_transmitter(info
);
2591 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2594 } /* end of mgsl_txenable() */
2596 /* mgsl_txabort() abort send HDLC frame
2598 * Arguments: info pointer to device instance data
2599 * Return Value: 0 if success, otherwise error code
2601 static int mgsl_txabort(struct mgsl_struct
* info
)
2603 unsigned long flags
;
2605 if (debug_level
>= DEBUG_LEVEL_INFO
)
2606 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2609 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2610 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2612 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2613 usc_loopmode_cancel_transmit( info
);
2615 usc_TCmd(info
,TCmd_SendAbort
);
2617 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2620 } /* end of mgsl_txabort() */
2622 /* mgsl_rxenable() enable or disable the receiver
2624 * Arguments: info pointer to device instance data
2625 * enable 1 = enable, 0 = disable
2626 * Return Value: 0 if success, otherwise error code
2628 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2630 unsigned long flags
;
2632 if (debug_level
>= DEBUG_LEVEL_INFO
)
2633 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2634 info
->device_name
, enable
);
2636 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2638 if ( !info
->rx_enabled
)
2639 usc_start_receiver(info
);
2641 if ( info
->rx_enabled
)
2642 usc_stop_receiver(info
);
2644 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2647 } /* end of mgsl_rxenable() */
2649 /* mgsl_wait_event() wait for specified event to occur
2651 * Arguments: info pointer to device instance data
2652 * mask pointer to bitmask of events to wait for
2653 * Return Value: 0 if successful and bit mask updated with
2654 * of events triggerred,
2655 * otherwise error code
2657 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2659 unsigned long flags
;
2662 struct mgsl_icount cprev
, cnow
;
2665 struct _input_signal_events oldsigs
, newsigs
;
2666 DECLARE_WAITQUEUE(wait
, current
);
2668 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2673 if (debug_level
>= DEBUG_LEVEL_INFO
)
2674 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2675 info
->device_name
, mask
);
2677 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2679 /* return immediately if state matches requested events */
2680 usc_get_serial_signals(info
);
2681 s
= info
->serial_signals
;
2683 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2684 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2685 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2686 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2688 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2692 /* save current irq counts */
2693 cprev
= info
->icount
;
2694 oldsigs
= info
->input_signal_events
;
2696 /* enable hunt and idle irqs if needed */
2697 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2698 u16 oldreg
= usc_InReg(info
,RICR
);
2699 u16 newreg
= oldreg
+
2700 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2701 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2702 if (oldreg
!= newreg
)
2703 usc_OutReg(info
, RICR
, newreg
);
2706 set_current_state(TASK_INTERRUPTIBLE
);
2707 add_wait_queue(&info
->event_wait_q
, &wait
);
2709 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2714 if (signal_pending(current
)) {
2719 /* get current irq counts */
2720 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2721 cnow
= info
->icount
;
2722 newsigs
= info
->input_signal_events
;
2723 set_current_state(TASK_INTERRUPTIBLE
);
2724 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2726 /* if no change, wait aborted for some reason */
2727 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2728 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2729 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2730 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2731 newsigs
.cts_up
== oldsigs
.cts_up
&&
2732 newsigs
.cts_down
== oldsigs
.cts_down
&&
2733 newsigs
.ri_up
== oldsigs
.ri_up
&&
2734 newsigs
.ri_down
== oldsigs
.ri_down
&&
2735 cnow
.exithunt
== cprev
.exithunt
&&
2736 cnow
.rxidle
== cprev
.rxidle
) {
2742 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2743 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2744 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2745 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2746 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2747 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2748 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2749 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2750 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2751 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2759 remove_wait_queue(&info
->event_wait_q
, &wait
);
2760 set_current_state(TASK_RUNNING
);
2762 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2763 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2764 if (!waitqueue_active(&info
->event_wait_q
)) {
2765 /* disable enable exit hunt mode/idle rcvd IRQs */
2766 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2767 ~(RXSTATUS_EXITED_HUNT
| RXSTATUS_IDLE_RECEIVED
));
2769 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2773 PUT_USER(rc
, events
, mask_ptr
);
2777 } /* end of mgsl_wait_event() */
2779 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2781 unsigned long flags
;
2783 struct mgsl_icount cprev
, cnow
;
2784 DECLARE_WAITQUEUE(wait
, current
);
2786 /* save current irq counts */
2787 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2788 cprev
= info
->icount
;
2789 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2790 set_current_state(TASK_INTERRUPTIBLE
);
2791 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2795 if (signal_pending(current
)) {
2800 /* get new irq counts */
2801 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2802 cnow
= info
->icount
;
2803 set_current_state(TASK_INTERRUPTIBLE
);
2804 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2806 /* if no change, wait aborted for some reason */
2807 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2808 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2813 /* check for change in caller specified modem input */
2814 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2815 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2816 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2817 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2824 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2825 set_current_state(TASK_RUNNING
);
2829 /* return the state of the serial control and status signals
2831 static int tiocmget(struct tty_struct
*tty
)
2833 struct mgsl_struct
*info
= tty
->driver_data
;
2834 unsigned int result
;
2835 unsigned long flags
;
2837 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2838 usc_get_serial_signals(info
);
2839 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2841 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2842 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2843 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2844 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2845 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2846 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2848 if (debug_level
>= DEBUG_LEVEL_INFO
)
2849 printk("%s(%d):%s tiocmget() value=%08X\n",
2850 __FILE__
,__LINE__
, info
->device_name
, result
);
2854 /* set modem control signals (DTR/RTS)
2856 static int tiocmset(struct tty_struct
*tty
,
2857 unsigned int set
, unsigned int clear
)
2859 struct mgsl_struct
*info
= tty
->driver_data
;
2860 unsigned long flags
;
2862 if (debug_level
>= DEBUG_LEVEL_INFO
)
2863 printk("%s(%d):%s tiocmset(%x,%x)\n",
2864 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2866 if (set
& TIOCM_RTS
)
2867 info
->serial_signals
|= SerialSignal_RTS
;
2868 if (set
& TIOCM_DTR
)
2869 info
->serial_signals
|= SerialSignal_DTR
;
2870 if (clear
& TIOCM_RTS
)
2871 info
->serial_signals
&= ~SerialSignal_RTS
;
2872 if (clear
& TIOCM_DTR
)
2873 info
->serial_signals
&= ~SerialSignal_DTR
;
2875 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2876 usc_set_serial_signals(info
);
2877 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2882 /* mgsl_break() Set or clear transmit break condition
2884 * Arguments: tty pointer to tty instance data
2885 * break_state -1=set break condition, 0=clear
2886 * Return Value: error code
2888 static int mgsl_break(struct tty_struct
*tty
, int break_state
)
2890 struct mgsl_struct
* info
= tty
->driver_data
;
2891 unsigned long flags
;
2893 if (debug_level
>= DEBUG_LEVEL_INFO
)
2894 printk("%s(%d):mgsl_break(%s,%d)\n",
2895 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2897 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2900 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2901 if (break_state
== -1)
2902 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2904 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2905 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2908 } /* end of mgsl_break() */
2911 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2912 * Return: write counters to the user passed counter struct
2913 * NB: both 1->0 and 0->1 transitions are counted except for
2914 * RI where only 0->1 is counted.
2916 static int msgl_get_icount(struct tty_struct
*tty
,
2917 struct serial_icounter_struct
*icount
)
2920 struct mgsl_struct
* info
= tty
->driver_data
;
2921 struct mgsl_icount cnow
; /* kernel counter temps */
2922 unsigned long flags
;
2924 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2925 cnow
= info
->icount
;
2926 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2928 icount
->cts
= cnow
.cts
;
2929 icount
->dsr
= cnow
.dsr
;
2930 icount
->rng
= cnow
.rng
;
2931 icount
->dcd
= cnow
.dcd
;
2932 icount
->rx
= cnow
.rx
;
2933 icount
->tx
= cnow
.tx
;
2934 icount
->frame
= cnow
.frame
;
2935 icount
->overrun
= cnow
.overrun
;
2936 icount
->parity
= cnow
.parity
;
2937 icount
->brk
= cnow
.brk
;
2938 icount
->buf_overrun
= cnow
.buf_overrun
;
2942 /* mgsl_ioctl() Service an IOCTL request
2946 * tty pointer to tty instance data
2947 * cmd IOCTL command code
2948 * arg command argument/context
2950 * Return Value: 0 if success, otherwise error code
2952 static int mgsl_ioctl(struct tty_struct
*tty
,
2953 unsigned int cmd
, unsigned long arg
)
2955 struct mgsl_struct
* info
= tty
->driver_data
;
2957 if (debug_level
>= DEBUG_LEVEL_INFO
)
2958 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2959 info
->device_name
, cmd
);
2961 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2964 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2965 (cmd
!= TIOCMIWAIT
)) {
2966 if (tty_io_error(tty
))
2970 return mgsl_ioctl_common(info
, cmd
, arg
);
2973 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2975 void __user
*argp
= (void __user
*)arg
;
2978 case MGSL_IOCGPARAMS
:
2979 return mgsl_get_params(info
, argp
);
2980 case MGSL_IOCSPARAMS
:
2981 return mgsl_set_params(info
, argp
);
2982 case MGSL_IOCGTXIDLE
:
2983 return mgsl_get_txidle(info
, argp
);
2984 case MGSL_IOCSTXIDLE
:
2985 return mgsl_set_txidle(info
,(int)arg
);
2986 case MGSL_IOCTXENABLE
:
2987 return mgsl_txenable(info
,(int)arg
);
2988 case MGSL_IOCRXENABLE
:
2989 return mgsl_rxenable(info
,(int)arg
);
2990 case MGSL_IOCTXABORT
:
2991 return mgsl_txabort(info
);
2992 case MGSL_IOCGSTATS
:
2993 return mgsl_get_stats(info
, argp
);
2994 case MGSL_IOCWAITEVENT
:
2995 return mgsl_wait_event(info
, argp
);
2996 case MGSL_IOCLOOPTXDONE
:
2997 return mgsl_loopmode_send_done(info
);
2998 /* Wait for modem input (DCD,RI,DSR,CTS) change
2999 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3002 return modem_input_wait(info
,(int)arg
);
3005 return -ENOIOCTLCMD
;
3010 /* mgsl_set_termios()
3012 * Set new termios settings
3016 * tty pointer to tty structure
3017 * termios pointer to buffer to hold returned old termios
3019 * Return Value: None
3021 static void mgsl_set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
3023 struct mgsl_struct
*info
= tty
->driver_data
;
3024 unsigned long flags
;
3026 if (debug_level
>= DEBUG_LEVEL_INFO
)
3027 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3028 tty
->driver
->name
);
3030 mgsl_change_params(info
);
3032 /* Handle transition to B0 status */
3033 if ((old_termios
->c_cflag
& CBAUD
) && !C_BAUD(tty
)) {
3034 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
3035 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3036 usc_set_serial_signals(info
);
3037 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3040 /* Handle transition away from B0 status */
3041 if (!(old_termios
->c_cflag
& CBAUD
) && C_BAUD(tty
)) {
3042 info
->serial_signals
|= SerialSignal_DTR
;
3043 if (!C_CRTSCTS(tty
) || !tty_throttled(tty
))
3044 info
->serial_signals
|= SerialSignal_RTS
;
3045 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3046 usc_set_serial_signals(info
);
3047 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3050 /* Handle turning off CRTSCTS */
3051 if (old_termios
->c_cflag
& CRTSCTS
&& !C_CRTSCTS(tty
)) {
3052 tty
->hw_stopped
= 0;
3056 } /* end of mgsl_set_termios() */
3060 * Called when port is closed. Wait for remaining data to be
3061 * sent. Disable port and free resources.
3065 * tty pointer to open tty structure
3066 * filp pointer to open file object
3068 * Return Value: None
3070 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3072 struct mgsl_struct
* info
= tty
->driver_data
;
3074 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3077 if (debug_level
>= DEBUG_LEVEL_INFO
)
3078 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3079 __FILE__
,__LINE__
, info
->device_name
, info
->port
.count
);
3081 if (tty_port_close_start(&info
->port
, tty
, filp
) == 0)
3084 mutex_lock(&info
->port
.mutex
);
3085 if (tty_port_initialized(&info
->port
))
3086 mgsl_wait_until_sent(tty
, info
->timeout
);
3087 mgsl_flush_buffer(tty
);
3088 tty_ldisc_flush(tty
);
3090 mutex_unlock(&info
->port
.mutex
);
3092 tty_port_close_end(&info
->port
, tty
);
3093 info
->port
.tty
= NULL
;
3095 if (debug_level
>= DEBUG_LEVEL_INFO
)
3096 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3097 tty
->driver
->name
, info
->port
.count
);
3099 } /* end of mgsl_close() */
3101 /* mgsl_wait_until_sent()
3103 * Wait until the transmitter is empty.
3107 * tty pointer to tty info structure
3108 * timeout time to wait for send completion
3110 * Return Value: None
3112 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3114 struct mgsl_struct
* info
= tty
->driver_data
;
3115 unsigned long orig_jiffies
, char_time
;
3120 if (debug_level
>= DEBUG_LEVEL_INFO
)
3121 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3122 __FILE__
,__LINE__
, info
->device_name
);
3124 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3127 if (!tty_port_initialized(&info
->port
))
3130 orig_jiffies
= jiffies
;
3132 /* Set check interval to 1/5 of estimated time to
3133 * send a character, and make it at least 1. The check
3134 * interval should also be less than the timeout.
3135 * Note: use tight timings here to satisfy the NIST-PCTS.
3138 if ( info
->params
.data_rate
) {
3139 char_time
= info
->timeout
/(32 * 5);
3146 char_time
= min_t(unsigned long, char_time
, timeout
);
3148 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3149 info
->params
.mode
== MGSL_MODE_RAW
) {
3150 while (info
->tx_active
) {
3151 msleep_interruptible(jiffies_to_msecs(char_time
));
3152 if (signal_pending(current
))
3154 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3158 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3160 msleep_interruptible(jiffies_to_msecs(char_time
));
3161 if (signal_pending(current
))
3163 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3169 if (debug_level
>= DEBUG_LEVEL_INFO
)
3170 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3171 __FILE__
,__LINE__
, info
->device_name
);
3173 } /* end of mgsl_wait_until_sent() */
3177 * Called by tty_hangup() when a hangup is signaled.
3178 * This is the same as to closing all open files for the port.
3180 * Arguments: tty pointer to associated tty object
3181 * Return Value: None
3183 static void mgsl_hangup(struct tty_struct
*tty
)
3185 struct mgsl_struct
* info
= tty
->driver_data
;
3187 if (debug_level
>= DEBUG_LEVEL_INFO
)
3188 printk("%s(%d):mgsl_hangup(%s)\n",
3189 __FILE__
,__LINE__
, info
->device_name
);
3191 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3194 mgsl_flush_buffer(tty
);
3197 info
->port
.count
= 0;
3198 tty_port_set_active(&info
->port
, 0);
3199 info
->port
.tty
= NULL
;
3201 wake_up_interruptible(&info
->port
.open_wait
);
3203 } /* end of mgsl_hangup() */
3208 * Return true if carrier is raised
3211 static int carrier_raised(struct tty_port
*port
)
3213 unsigned long flags
;
3214 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3216 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3217 usc_get_serial_signals(info
);
3218 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3219 return (info
->serial_signals
& SerialSignal_DCD
) ? 1 : 0;
3222 static void dtr_rts(struct tty_port
*port
, int on
)
3224 struct mgsl_struct
*info
= container_of(port
, struct mgsl_struct
, port
);
3225 unsigned long flags
;
3227 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3229 info
->serial_signals
|= SerialSignal_RTS
| SerialSignal_DTR
;
3231 info
->serial_signals
&= ~(SerialSignal_RTS
| SerialSignal_DTR
);
3232 usc_set_serial_signals(info
);
3233 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3237 /* block_til_ready()
3239 * Block the current process until the specified port
3240 * is ready to be opened.
3244 * tty pointer to tty info structure
3245 * filp pointer to open file object
3246 * info pointer to device instance data
3248 * Return Value: 0 if success, otherwise error code
3250 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3251 struct mgsl_struct
*info
)
3253 DECLARE_WAITQUEUE(wait
, current
);
3255 bool do_clocal
= false;
3256 unsigned long flags
;
3258 struct tty_port
*port
= &info
->port
;
3260 if (debug_level
>= DEBUG_LEVEL_INFO
)
3261 printk("%s(%d):block_til_ready on %s\n",
3262 __FILE__
,__LINE__
, tty
->driver
->name
);
3264 if (filp
->f_flags
& O_NONBLOCK
|| tty_io_error(tty
)) {
3265 /* nonblock mode is set or port is not enabled */
3266 tty_port_set_active(port
, 1);
3273 /* Wait for carrier detect and the line to become
3274 * free (i.e., not in use by the callout). While we are in
3275 * this loop, port->count is dropped by one, so that
3276 * mgsl_close() knows when to free things. We restore it upon
3277 * exit, either normal or abnormal.
3281 add_wait_queue(&port
->open_wait
, &wait
);
3283 if (debug_level
>= DEBUG_LEVEL_INFO
)
3284 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3285 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3287 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3289 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3290 port
->blocked_open
++;
3293 if (C_BAUD(tty
) && tty_port_initialized(port
))
3294 tty_port_raise_dtr_rts(port
);
3296 set_current_state(TASK_INTERRUPTIBLE
);
3298 if (tty_hung_up_p(filp
) || !tty_port_initialized(port
)) {
3299 retval
= (port
->flags
& ASYNC_HUP_NOTIFY
) ?
3300 -EAGAIN
: -ERESTARTSYS
;
3304 dcd
= tty_port_carrier_raised(&info
->port
);
3305 if (do_clocal
|| dcd
)
3308 if (signal_pending(current
)) {
3309 retval
= -ERESTARTSYS
;
3313 if (debug_level
>= DEBUG_LEVEL_INFO
)
3314 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3315 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3322 set_current_state(TASK_RUNNING
);
3323 remove_wait_queue(&port
->open_wait
, &wait
);
3325 /* FIXME: Racy on hangup during close wait */
3326 if (!tty_hung_up_p(filp
))
3328 port
->blocked_open
--;
3330 if (debug_level
>= DEBUG_LEVEL_INFO
)
3331 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3332 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3335 tty_port_set_active(port
, 1);
3339 } /* end of block_til_ready() */
3341 static int mgsl_install(struct tty_driver
*driver
, struct tty_struct
*tty
)
3343 struct mgsl_struct
*info
;
3344 int line
= tty
->index
;
3346 /* verify range of specified line number */
3347 if (line
>= mgsl_device_count
) {
3348 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3349 __FILE__
, __LINE__
, line
);
3353 /* find the info structure for the specified line */
3354 info
= mgsl_device_list
;
3355 while (info
&& info
->line
!= line
)
3356 info
= info
->next_device
;
3357 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3359 tty
->driver_data
= info
;
3361 return tty_port_install(&info
->port
, driver
, tty
);
3366 * Called when a port is opened. Init and enable port.
3367 * Perform serial-specific initialization for the tty structure.
3369 * Arguments: tty pointer to tty info structure
3370 * filp associated file pointer
3372 * Return Value: 0 if success, otherwise error code
3374 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3376 struct mgsl_struct
*info
= tty
->driver_data
;
3377 unsigned long flags
;
3380 info
->port
.tty
= tty
;
3382 if (debug_level
>= DEBUG_LEVEL_INFO
)
3383 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3384 __FILE__
,__LINE__
,tty
->driver
->name
, info
->port
.count
);
3386 info
->port
.low_latency
= (info
->port
.flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3388 spin_lock_irqsave(&info
->netlock
, flags
);
3389 if (info
->netcount
) {
3391 spin_unlock_irqrestore(&info
->netlock
, flags
);
3395 spin_unlock_irqrestore(&info
->netlock
, flags
);
3397 if (info
->port
.count
== 1) {
3398 /* 1st open on this device, init hardware */
3399 retval
= startup(info
);
3404 retval
= block_til_ready(tty
, filp
, info
);
3406 if (debug_level
>= DEBUG_LEVEL_INFO
)
3407 printk("%s(%d):block_til_ready(%s) returned %d\n",
3408 __FILE__
,__LINE__
, info
->device_name
, retval
);
3412 if (debug_level
>= DEBUG_LEVEL_INFO
)
3413 printk("%s(%d):mgsl_open(%s) success\n",
3414 __FILE__
,__LINE__
, info
->device_name
);
3419 if (tty
->count
== 1)
3420 info
->port
.tty
= NULL
; /* tty layer will release tty struct */
3421 if(info
->port
.count
)
3427 } /* end of mgsl_open() */
3430 * /proc fs routines....
3433 static inline void line_info(struct seq_file
*m
, struct mgsl_struct
*info
)
3436 unsigned long flags
;
3438 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3439 seq_printf(m
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3440 info
->device_name
, info
->io_base
, info
->irq_level
,
3441 info
->phys_memory_base
, info
->phys_lcr_base
);
3443 seq_printf(m
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3444 info
->device_name
, info
->io_base
,
3445 info
->irq_level
, info
->dma_level
);
3448 /* output current serial signal states */
3449 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3450 usc_get_serial_signals(info
);
3451 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3455 if (info
->serial_signals
& SerialSignal_RTS
)
3456 strcat(stat_buf
, "|RTS");
3457 if (info
->serial_signals
& SerialSignal_CTS
)
3458 strcat(stat_buf
, "|CTS");
3459 if (info
->serial_signals
& SerialSignal_DTR
)
3460 strcat(stat_buf
, "|DTR");
3461 if (info
->serial_signals
& SerialSignal_DSR
)
3462 strcat(stat_buf
, "|DSR");
3463 if (info
->serial_signals
& SerialSignal_DCD
)
3464 strcat(stat_buf
, "|CD");
3465 if (info
->serial_signals
& SerialSignal_RI
)
3466 strcat(stat_buf
, "|RI");
3468 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3469 info
->params
.mode
== MGSL_MODE_RAW
) {
3470 seq_printf(m
, " HDLC txok:%d rxok:%d",
3471 info
->icount
.txok
, info
->icount
.rxok
);
3472 if (info
->icount
.txunder
)
3473 seq_printf(m
, " txunder:%d", info
->icount
.txunder
);
3474 if (info
->icount
.txabort
)
3475 seq_printf(m
, " txabort:%d", info
->icount
.txabort
);
3476 if (info
->icount
.rxshort
)
3477 seq_printf(m
, " rxshort:%d", info
->icount
.rxshort
);
3478 if (info
->icount
.rxlong
)
3479 seq_printf(m
, " rxlong:%d", info
->icount
.rxlong
);
3480 if (info
->icount
.rxover
)
3481 seq_printf(m
, " rxover:%d", info
->icount
.rxover
);
3482 if (info
->icount
.rxcrc
)
3483 seq_printf(m
, " rxcrc:%d", info
->icount
.rxcrc
);
3485 seq_printf(m
, " ASYNC tx:%d rx:%d",
3486 info
->icount
.tx
, info
->icount
.rx
);
3487 if (info
->icount
.frame
)
3488 seq_printf(m
, " fe:%d", info
->icount
.frame
);
3489 if (info
->icount
.parity
)
3490 seq_printf(m
, " pe:%d", info
->icount
.parity
);
3491 if (info
->icount
.brk
)
3492 seq_printf(m
, " brk:%d", info
->icount
.brk
);
3493 if (info
->icount
.overrun
)
3494 seq_printf(m
, " oe:%d", info
->icount
.overrun
);
3497 /* Append serial signal status to end */
3498 seq_printf(m
, " %s\n", stat_buf
+1);
3500 seq_printf(m
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3501 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3504 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3506 u16 Tcsr
= usc_InReg( info
, TCSR
);
3507 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3508 u16 Ticr
= usc_InReg( info
, TICR
);
3509 u16 Rscr
= usc_InReg( info
, RCSR
);
3510 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3511 u16 Ricr
= usc_InReg( info
, RICR
);
3512 u16 Icr
= usc_InReg( info
, ICR
);
3513 u16 Dccr
= usc_InReg( info
, DCCR
);
3514 u16 Tmr
= usc_InReg( info
, TMR
);
3515 u16 Tccr
= usc_InReg( info
, TCCR
);
3516 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3517 seq_printf(m
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3518 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3519 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3521 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3524 /* Called to print information about devices */
3525 static int mgsl_proc_show(struct seq_file
*m
, void *v
)
3527 struct mgsl_struct
*info
;
3529 seq_printf(m
, "synclink driver:%s\n", driver_version
);
3531 info
= mgsl_device_list
;
3534 info
= info
->next_device
;
3539 static int mgsl_proc_open(struct inode
*inode
, struct file
*file
)
3541 return single_open(file
, mgsl_proc_show
, NULL
);
3544 static const struct file_operations mgsl_proc_fops
= {
3545 .owner
= THIS_MODULE
,
3546 .open
= mgsl_proc_open
,
3548 .llseek
= seq_lseek
,
3549 .release
= single_release
,
3552 /* mgsl_allocate_dma_buffers()
3554 * Allocate and format DMA buffers (ISA adapter)
3555 * or format shared memory buffers (PCI adapter).
3557 * Arguments: info pointer to device instance data
3558 * Return Value: 0 if success, otherwise error
3560 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3562 unsigned short BuffersPerFrame
;
3564 info
->last_mem_alloc
= 0;
3566 /* Calculate the number of DMA buffers necessary to hold the */
3567 /* largest allowable frame size. Note: If the max frame size is */
3568 /* not an even multiple of the DMA buffer size then we need to */
3569 /* round the buffer count per frame up one. */
3571 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3572 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3575 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3577 * The PCI adapter has 256KBytes of shared memory to use.
3578 * This is 64 PAGE_SIZE buffers.
3580 * The first page is used for padding at this time so the
3581 * buffer list does not begin at offset 0 of the PCI
3582 * adapter's shared memory.
3584 * The 2nd page is used for the buffer list. A 4K buffer
3585 * list can hold 128 DMA_BUFFER structures at 32 bytes
3588 * This leaves 62 4K pages.
3590 * The next N pages are used for transmit frame(s). We
3591 * reserve enough 4K page blocks to hold the required
3592 * number of transmit dma buffers (num_tx_dma_buffers),
3593 * each of MaxFrameSize size.
3595 * Of the remaining pages (62-N), determine how many can
3596 * be used to receive full MaxFrameSize inbound frames
3598 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3599 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3601 /* Calculate the number of PAGE_SIZE buffers needed for */
3602 /* receive and transmit DMA buffers. */
3605 /* Calculate the number of DMA buffers necessary to */
3606 /* hold 7 max size receive frames and one max size transmit frame. */
3607 /* The receive buffer count is bumped by one so we avoid an */
3608 /* End of List condition if all receive buffers are used when */
3609 /* using linked list DMA buffers. */
3611 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3612 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3615 * limit total TxBuffers & RxBuffers to 62 4K total
3616 * (ala PCI Allocation)
3619 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3620 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3624 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3625 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3626 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3628 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3629 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3630 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3631 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3632 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3633 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3637 mgsl_reset_rx_dma_buffers( info
);
3638 mgsl_reset_tx_dma_buffers( info
);
3642 } /* end of mgsl_allocate_dma_buffers() */
3645 * mgsl_alloc_buffer_list_memory()
3647 * Allocate a common DMA buffer for use as the
3648 * receive and transmit buffer lists.
3650 * A buffer list is a set of buffer entries where each entry contains
3651 * a pointer to an actual buffer and a pointer to the next buffer entry
3652 * (plus some other info about the buffer).
3654 * The buffer entries for a list are built to form a circular list so
3655 * that when the entire list has been traversed you start back at the
3658 * This function allocates memory for just the buffer entries.
3659 * The links (pointer to next entry) are filled in with the physical
3660 * address of the next entry so the adapter can navigate the list
3661 * using bus master DMA. The pointers to the actual buffers are filled
3662 * out later when the actual buffers are allocated.
3664 * Arguments: info pointer to device instance data
3665 * Return Value: 0 if success, otherwise error
3667 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3671 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3672 /* PCI adapter uses shared memory. */
3673 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3674 info
->buffer_list_phys
= info
->last_mem_alloc
;
3675 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3677 /* ISA adapter uses system memory. */
3678 /* The buffer lists are allocated as a common buffer that both */
3679 /* the processor and adapter can access. This allows the driver to */
3680 /* inspect portions of the buffer while other portions are being */
3681 /* updated by the adapter using Bus Master DMA. */
3683 info
->buffer_list
= dma_alloc_coherent(NULL
, BUFFERLISTSIZE
, &info
->buffer_list_dma_addr
, GFP_KERNEL
);
3684 if (info
->buffer_list
== NULL
)
3686 info
->buffer_list_phys
= (u32
)(info
->buffer_list_dma_addr
);
3689 /* We got the memory for the buffer entry lists. */
3690 /* Initialize the memory block to all zeros. */
3691 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3693 /* Save virtual address pointers to the receive and */
3694 /* transmit buffer lists. (Receive 1st). These pointers will */
3695 /* be used by the processor to access the lists. */
3696 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3697 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3698 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3701 * Build the links for the buffer entry lists such that
3702 * two circular lists are built. (Transmit and Receive).
3704 * Note: the links are physical addresses
3705 * which are read by the adapter to determine the next
3706 * buffer entry to use.
3709 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3710 /* calculate and store physical address of this buffer entry */
3711 info
->rx_buffer_list
[i
].phys_entry
=
3712 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3714 /* calculate and store physical address of */
3715 /* next entry in cirular list of entries */
3717 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3719 if ( i
< info
->rx_buffer_count
- 1 )
3720 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3723 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3724 /* calculate and store physical address of this buffer entry */
3725 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3726 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3728 /* calculate and store physical address of */
3729 /* next entry in cirular list of entries */
3731 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3732 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3734 if ( i
< info
->tx_buffer_count
- 1 )
3735 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3740 } /* end of mgsl_alloc_buffer_list_memory() */
3742 /* Free DMA buffers allocated for use as the
3743 * receive and transmit buffer lists.
3746 * The data transfer buffers associated with the buffer list
3747 * MUST be freed before freeing the buffer list itself because
3748 * the buffer list contains the information necessary to free
3749 * the individual buffers!
3751 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3753 if (info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3754 dma_free_coherent(NULL
, BUFFERLISTSIZE
, info
->buffer_list
, info
->buffer_list_dma_addr
);
3756 info
->buffer_list
= NULL
;
3757 info
->rx_buffer_list
= NULL
;
3758 info
->tx_buffer_list
= NULL
;
3760 } /* end of mgsl_free_buffer_list_memory() */
3763 * mgsl_alloc_frame_memory()
3765 * Allocate the frame DMA buffers used by the specified buffer list.
3766 * Each DMA buffer will be one memory page in size. This is necessary
3767 * because memory can fragment enough that it may be impossible
3772 * info pointer to device instance data
3773 * BufferList pointer to list of buffer entries
3774 * Buffercount count of buffer entries in buffer list
3776 * Return Value: 0 if success, otherwise -ENOMEM
3778 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3783 /* Allocate page sized buffers for the receive buffer list */
3785 for ( i
= 0; i
< Buffercount
; i
++ ) {
3786 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3787 /* PCI adapter uses shared memory buffers. */
3788 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3789 phys_addr
= info
->last_mem_alloc
;
3790 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3792 /* ISA adapter uses system memory. */
3793 BufferList
[i
].virt_addr
= dma_alloc_coherent(NULL
, DMABUFFERSIZE
, &BufferList
[i
].dma_addr
, GFP_KERNEL
);
3794 if (BufferList
[i
].virt_addr
== NULL
)
3796 phys_addr
= (u32
)(BufferList
[i
].dma_addr
);
3798 BufferList
[i
].phys_addr
= phys_addr
;
3803 } /* end of mgsl_alloc_frame_memory() */
3806 * mgsl_free_frame_memory()
3808 * Free the buffers associated with
3809 * each buffer entry of a buffer list.
3813 * info pointer to device instance data
3814 * BufferList pointer to list of buffer entries
3815 * Buffercount count of buffer entries in buffer list
3817 * Return Value: None
3819 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3824 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3825 if ( BufferList
[i
].virt_addr
) {
3826 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3827 dma_free_coherent(NULL
, DMABUFFERSIZE
, BufferList
[i
].virt_addr
, BufferList
[i
].dma_addr
);
3828 BufferList
[i
].virt_addr
= NULL
;
3833 } /* end of mgsl_free_frame_memory() */
3835 /* mgsl_free_dma_buffers()
3839 * Arguments: info pointer to device instance data
3840 * Return Value: None
3842 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3844 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3845 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3846 mgsl_free_buffer_list_memory( info
);
3848 } /* end of mgsl_free_dma_buffers() */
3852 * mgsl_alloc_intermediate_rxbuffer_memory()
3854 * Allocate a buffer large enough to hold max_frame_size. This buffer
3855 * is used to pass an assembled frame to the line discipline.
3859 * info pointer to device instance data
3861 * Return Value: 0 if success, otherwise -ENOMEM
3863 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3865 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
3866 if ( info
->intermediate_rxbuffer
== NULL
)
3868 /* unused flag buffer to satisfy receive_buf calling interface */
3869 info
->flag_buf
= kzalloc(info
->max_frame_size
, GFP_KERNEL
);
3870 if (!info
->flag_buf
) {
3871 kfree(info
->intermediate_rxbuffer
);
3872 info
->intermediate_rxbuffer
= NULL
;
3877 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3880 * mgsl_free_intermediate_rxbuffer_memory()
3885 * info pointer to device instance data
3887 * Return Value: None
3889 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3891 kfree(info
->intermediate_rxbuffer
);
3892 info
->intermediate_rxbuffer
= NULL
;
3893 kfree(info
->flag_buf
);
3894 info
->flag_buf
= NULL
;
3896 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
3899 * mgsl_alloc_intermediate_txbuffer_memory()
3901 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
3902 * This buffer is used to load transmit frames into the adapter's dma transfer
3903 * buffers when there is sufficient space.
3907 * info pointer to device instance data
3909 * Return Value: 0 if success, otherwise -ENOMEM
3911 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3915 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3916 printk("%s %s(%d) allocating %d tx holding buffers\n",
3917 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
3919 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
3921 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3922 info
->tx_holding_buffers
[i
].buffer
=
3923 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3924 if (info
->tx_holding_buffers
[i
].buffer
== NULL
) {
3925 for (--i
; i
>= 0; i
--) {
3926 kfree(info
->tx_holding_buffers
[i
].buffer
);
3927 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3935 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
3938 * mgsl_free_intermediate_txbuffer_memory()
3943 * info pointer to device instance data
3945 * Return Value: None
3947 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
3951 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
3952 kfree(info
->tx_holding_buffers
[i
].buffer
);
3953 info
->tx_holding_buffers
[i
].buffer
= NULL
;
3956 info
->get_tx_holding_index
= 0;
3957 info
->put_tx_holding_index
= 0;
3958 info
->tx_holding_count
= 0;
3960 } /* end of mgsl_free_intermediate_txbuffer_memory() */
3964 * load_next_tx_holding_buffer()
3966 * attempts to load the next buffered tx request into the
3971 * info pointer to device instance data
3973 * Return Value: true if next buffered tx request loaded
3974 * into adapter's tx dma buffer,
3977 static bool load_next_tx_holding_buffer(struct mgsl_struct
*info
)
3981 if ( info
->tx_holding_count
) {
3982 /* determine if we have enough tx dma buffers
3983 * to accommodate the next tx frame
3985 struct tx_holding_buffer
*ptx
=
3986 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
3987 int num_free
= num_free_tx_dma_buffers(info
);
3988 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
3989 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
3992 if (num_needed
<= num_free
) {
3993 info
->xmit_cnt
= ptx
->buffer_size
;
3994 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
3996 --info
->tx_holding_count
;
3997 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
3998 info
->get_tx_holding_index
=0;
4000 /* restart transmit timer */
4001 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4011 * save_tx_buffer_request()
4013 * attempt to store transmit frame request for later transmission
4017 * info pointer to device instance data
4018 * Buffer pointer to buffer containing frame to load
4019 * BufferSize size in bytes of frame in Buffer
4021 * Return Value: 1 if able to store, 0 otherwise
4023 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4025 struct tx_holding_buffer
*ptx
;
4027 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4028 return 0; /* all buffers in use */
4031 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4032 ptx
->buffer_size
= BufferSize
;
4033 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4035 ++info
->tx_holding_count
;
4036 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4037 info
->put_tx_holding_index
=0;
4042 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4044 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4045 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4046 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4049 info
->io_addr_requested
= true;
4051 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4052 info
->device_name
, info
) < 0 ) {
4053 printk( "%s(%d):Can't request interrupt on device %s IRQ=%d\n",
4054 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4057 info
->irq_requested
= true;
4059 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4060 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4061 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4062 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4065 info
->shared_mem_requested
= true;
4066 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4067 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4068 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4071 info
->lcr_mem_requested
= true;
4073 info
->memory_base
= ioremap_nocache(info
->phys_memory_base
,
4075 if (!info
->memory_base
) {
4076 printk( "%s(%d):Can't map shared memory on device %s MemAddr=%08X\n",
4077 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4081 if ( !mgsl_memory_test(info
) ) {
4082 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4083 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4087 info
->lcr_base
= ioremap_nocache(info
->phys_lcr_base
,
4089 if (!info
->lcr_base
) {
4090 printk( "%s(%d):Can't map LCR memory on device %s MemAddr=%08X\n",
4091 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4094 info
->lcr_base
+= info
->lcr_offset
;
4097 /* claim DMA channel */
4099 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4100 printk( "%s(%d):Can't request DMA channel on device %s DMA=%d\n",
4101 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4102 mgsl_release_resources( info
);
4105 info
->dma_requested
= true;
4107 /* ISA adapter uses bus master DMA */
4108 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4109 enable_dma(info
->dma_level
);
4112 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4113 printk( "%s(%d):Can't allocate DMA buffers on device %s DMA=%d\n",
4114 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4120 mgsl_release_resources(info
);
4123 } /* end of mgsl_claim_resources() */
4125 static void mgsl_release_resources(struct mgsl_struct
*info
)
4127 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4128 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4129 __FILE__
,__LINE__
,info
->device_name
);
4131 if ( info
->irq_requested
) {
4132 free_irq(info
->irq_level
, info
);
4133 info
->irq_requested
= false;
4135 if ( info
->dma_requested
) {
4136 disable_dma(info
->dma_level
);
4137 free_dma(info
->dma_level
);
4138 info
->dma_requested
= false;
4140 mgsl_free_dma_buffers(info
);
4141 mgsl_free_intermediate_rxbuffer_memory(info
);
4142 mgsl_free_intermediate_txbuffer_memory(info
);
4144 if ( info
->io_addr_requested
) {
4145 release_region(info
->io_base
,info
->io_addr_size
);
4146 info
->io_addr_requested
= false;
4148 if ( info
->shared_mem_requested
) {
4149 release_mem_region(info
->phys_memory_base
,0x40000);
4150 info
->shared_mem_requested
= false;
4152 if ( info
->lcr_mem_requested
) {
4153 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4154 info
->lcr_mem_requested
= false;
4156 if (info
->memory_base
){
4157 iounmap(info
->memory_base
);
4158 info
->memory_base
= NULL
;
4160 if (info
->lcr_base
){
4161 iounmap(info
->lcr_base
- info
->lcr_offset
);
4162 info
->lcr_base
= NULL
;
4165 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4166 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4167 __FILE__
,__LINE__
,info
->device_name
);
4169 } /* end of mgsl_release_resources() */
4171 /* mgsl_add_device()
4173 * Add the specified device instance data structure to the
4174 * global linked list of devices and increment the device count.
4176 * Arguments: info pointer to device instance data
4177 * Return Value: None
4179 static void mgsl_add_device( struct mgsl_struct
*info
)
4181 info
->next_device
= NULL
;
4182 info
->line
= mgsl_device_count
;
4183 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4185 if (info
->line
< MAX_TOTAL_DEVICES
) {
4186 if (maxframe
[info
->line
])
4187 info
->max_frame_size
= maxframe
[info
->line
];
4189 if (txdmabufs
[info
->line
]) {
4190 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4191 if (info
->num_tx_dma_buffers
< 1)
4192 info
->num_tx_dma_buffers
= 1;
4195 if (txholdbufs
[info
->line
]) {
4196 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4197 if (info
->num_tx_holding_buffers
< 1)
4198 info
->num_tx_holding_buffers
= 1;
4199 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4200 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4204 mgsl_device_count
++;
4206 if ( !mgsl_device_list
)
4207 mgsl_device_list
= info
;
4209 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4210 while( current_dev
->next_device
)
4211 current_dev
= current_dev
->next_device
;
4212 current_dev
->next_device
= info
;
4215 if ( info
->max_frame_size
< 4096 )
4216 info
->max_frame_size
= 4096;
4217 else if ( info
->max_frame_size
> 65535 )
4218 info
->max_frame_size
= 65535;
4220 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4221 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4222 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4223 info
->phys_memory_base
, info
->phys_lcr_base
,
4224 info
->max_frame_size
);
4226 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4227 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4228 info
->max_frame_size
);
4231 #if SYNCLINK_GENERIC_HDLC
4235 } /* end of mgsl_add_device() */
4237 static const struct tty_port_operations mgsl_port_ops
= {
4238 .carrier_raised
= carrier_raised
,
4243 /* mgsl_allocate_device()
4245 * Allocate and initialize a device instance structure
4248 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4250 static struct mgsl_struct
* mgsl_allocate_device(void)
4252 struct mgsl_struct
*info
;
4254 info
= kzalloc(sizeof(struct mgsl_struct
),
4258 printk("Error can't allocate device instance data\n");
4260 tty_port_init(&info
->port
);
4261 info
->port
.ops
= &mgsl_port_ops
;
4262 info
->magic
= MGSL_MAGIC
;
4263 INIT_WORK(&info
->task
, mgsl_bh_handler
);
4264 info
->max_frame_size
= 4096;
4265 info
->port
.close_delay
= 5*HZ
/10;
4266 info
->port
.closing_wait
= 30*HZ
;
4267 init_waitqueue_head(&info
->status_event_wait_q
);
4268 init_waitqueue_head(&info
->event_wait_q
);
4269 spin_lock_init(&info
->irq_spinlock
);
4270 spin_lock_init(&info
->netlock
);
4271 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4272 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4273 info
->num_tx_dma_buffers
= 1;
4274 info
->num_tx_holding_buffers
= 0;
4279 } /* end of mgsl_allocate_device()*/
4281 static const struct tty_operations mgsl_ops
= {
4282 .install
= mgsl_install
,
4284 .close
= mgsl_close
,
4285 .write
= mgsl_write
,
4286 .put_char
= mgsl_put_char
,
4287 .flush_chars
= mgsl_flush_chars
,
4288 .write_room
= mgsl_write_room
,
4289 .chars_in_buffer
= mgsl_chars_in_buffer
,
4290 .flush_buffer
= mgsl_flush_buffer
,
4291 .ioctl
= mgsl_ioctl
,
4292 .throttle
= mgsl_throttle
,
4293 .unthrottle
= mgsl_unthrottle
,
4294 .send_xchar
= mgsl_send_xchar
,
4295 .break_ctl
= mgsl_break
,
4296 .wait_until_sent
= mgsl_wait_until_sent
,
4297 .set_termios
= mgsl_set_termios
,
4299 .start
= mgsl_start
,
4300 .hangup
= mgsl_hangup
,
4301 .tiocmget
= tiocmget
,
4302 .tiocmset
= tiocmset
,
4303 .get_icount
= msgl_get_icount
,
4304 .proc_fops
= &mgsl_proc_fops
,
4308 * perform tty device initialization
4310 static int mgsl_init_tty(void)
4314 serial_driver
= alloc_tty_driver(128);
4318 serial_driver
->driver_name
= "synclink";
4319 serial_driver
->name
= "ttySL";
4320 serial_driver
->major
= ttymajor
;
4321 serial_driver
->minor_start
= 64;
4322 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4323 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4324 serial_driver
->init_termios
= tty_std_termios
;
4325 serial_driver
->init_termios
.c_cflag
=
4326 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4327 serial_driver
->init_termios
.c_ispeed
= 9600;
4328 serial_driver
->init_termios
.c_ospeed
= 9600;
4329 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4330 tty_set_operations(serial_driver
, &mgsl_ops
);
4331 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4332 printk("%s(%d):Couldn't register serial driver\n",
4334 put_tty_driver(serial_driver
);
4335 serial_driver
= NULL
;
4339 printk("%s %s, tty major#%d\n",
4340 driver_name
, driver_version
,
4341 serial_driver
->major
);
4345 /* enumerate user specified ISA adapters
4347 static void mgsl_enum_isa_devices(void)
4349 struct mgsl_struct
*info
;
4352 /* Check for user specified ISA devices */
4354 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4355 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4356 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4357 io
[i
], irq
[i
], dma
[i
] );
4359 info
= mgsl_allocate_device();
4361 /* error allocating device instance data */
4362 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4363 printk( "can't allocate device instance data.\n");
4367 /* Copy user configuration info to device instance data */
4368 info
->io_base
= (unsigned int)io
[i
];
4369 info
->irq_level
= (unsigned int)irq
[i
];
4370 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4371 info
->dma_level
= (unsigned int)dma
[i
];
4372 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4373 info
->io_addr_size
= 16;
4374 info
->irq_flags
= 0;
4376 mgsl_add_device( info
);
4380 static void synclink_cleanup(void)
4383 struct mgsl_struct
*info
;
4384 struct mgsl_struct
*tmp
;
4386 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4388 if (serial_driver
) {
4389 rc
= tty_unregister_driver(serial_driver
);
4391 printk("%s(%d) failed to unregister tty driver err=%d\n",
4392 __FILE__
,__LINE__
,rc
);
4393 put_tty_driver(serial_driver
);
4396 info
= mgsl_device_list
;
4398 #if SYNCLINK_GENERIC_HDLC
4401 mgsl_release_resources(info
);
4403 info
= info
->next_device
;
4404 tty_port_destroy(&tmp
->port
);
4409 pci_unregister_driver(&synclink_pci_driver
);
4412 static int __init
synclink_init(void)
4416 if (break_on_load
) {
4417 mgsl_get_text_ptr();
4421 printk("%s %s\n", driver_name
, driver_version
);
4423 mgsl_enum_isa_devices();
4424 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4425 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4427 pci_registered
= true;
4429 if ((rc
= mgsl_init_tty()) < 0)
4439 static void __exit
synclink_exit(void)
4444 module_init(synclink_init
);
4445 module_exit(synclink_exit
);
4450 * Issue a USC Receive/Transmit command to the
4451 * Channel Command/Address Register (CCAR).
4455 * The command is encoded in the most significant 5 bits <15..11>
4456 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4457 * and Bits <6..0> must be written as zeros.
4461 * info pointer to device information structure
4462 * Cmd command mask (use symbolic macros)
4468 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4470 /* output command to CCAR in bits <15..11> */
4471 /* preserve bits <10..7>, bits <6..0> must be zero */
4473 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4475 /* Read to flush write to CCAR */
4476 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4477 inw( info
->io_base
+ CCAR
);
4479 } /* end of usc_RTCmd() */
4484 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4488 * info pointer to device information structure
4489 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4495 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4497 /* write command mask to DCAR */
4498 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4500 /* Read to flush write to DCAR */
4501 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4502 inw( info
->io_base
);
4504 } /* end of usc_DmaCmd() */
4509 * Write a 16-bit value to a USC DMA register
4513 * info pointer to device info structure
4514 * RegAddr register address (number) for write
4515 * RegValue 16-bit value to write to register
4522 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4524 /* Note: The DCAR is located at the adapter base address */
4525 /* Note: must preserve state of BIT8 in DCAR */
4527 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4528 outw( RegValue
, info
->io_base
);
4530 /* Read to flush write to DCAR */
4531 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4532 inw( info
->io_base
);
4534 } /* end of usc_OutDmaReg() */
4539 * Read a 16-bit value from a DMA register
4543 * info pointer to device info structure
4544 * RegAddr register address (number) to read from
4548 * The 16-bit value read from register
4551 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4553 /* Note: The DCAR is located at the adapter base address */
4554 /* Note: must preserve state of BIT8 in DCAR */
4556 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4557 return inw( info
->io_base
);
4559 } /* end of usc_InDmaReg() */
4565 * Write a 16-bit value to a USC serial channel register
4569 * info pointer to device info structure
4570 * RegAddr register address (number) to write to
4571 * RegValue 16-bit value to write to register
4578 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4580 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4581 outw( RegValue
, info
->io_base
+ CCAR
);
4583 /* Read to flush write to CCAR */
4584 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4585 inw( info
->io_base
+ CCAR
);
4587 } /* end of usc_OutReg() */
4592 * Reads a 16-bit value from a USC serial channel register
4596 * info pointer to device extension
4597 * RegAddr register address (number) to read from
4601 * 16-bit value read from register
4603 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4605 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4606 return inw( info
->io_base
+ CCAR
);
4608 } /* end of usc_InReg() */
4610 /* usc_set_sdlc_mode()
4612 * Set up the adapter for SDLC DMA communications.
4614 * Arguments: info pointer to device instance data
4615 * Return Value: NONE
4617 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4623 * determine if the IUSC on the adapter is pre-SL1660. If
4624 * not, take advantage of the UnderWait feature of more
4625 * modern chips. If an underrun occurs and this bit is set,
4626 * the transmitter will idle the programmed idle pattern
4627 * until the driver has time to service the underrun. Otherwise,
4628 * the dma controller may get the cycles previously requested
4629 * and begin transmitting queued tx data.
4631 usc_OutReg(info
,TMCR
,0x1f);
4632 RegValue
=usc_InReg(info
,TMDR
);
4633 PreSL1660
= (RegValue
== IUSC_PRE_SL1660
);
4635 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4638 ** Channel Mode Register (CMR)
4640 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4641 ** <13> 0 0 = Transmit Disabled (initially)
4642 ** <12> 0 1 = Consecutive Idles share common 0
4643 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4644 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4645 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4647 ** 1000 1110 0000 0110 = 0x8e06
4651 /*--------------------------------------------------
4652 * ignore user options for UnderRun Actions and
4654 *--------------------------------------------------*/
4658 /* Channel mode Register (CMR)
4660 * <15..14> 00 Tx Sub modes, Underrun Action
4661 * <13> 0 1 = Send Preamble before opening flag
4662 * <12> 0 1 = Consecutive Idles share common 0
4663 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4664 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4665 * <3..0> 0110 Receiver mode = HDLC/SDLC
4667 * 0000 0110 0000 0110 = 0x0606
4669 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4670 RegValue
= 0x0001; /* Set Receive mode = external sync */
4672 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4673 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4677 * CMR <15> 0 Don't send CRC on Tx Underrun
4678 * CMR <14> x undefined
4679 * CMR <13> 0 Send preamble before openning sync
4680 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4683 * CMR <11-8) 0100 MonoSync
4685 * 0x00 0100 xxxx xxxx 04xx
4693 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4695 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4697 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4698 RegValue
|= BIT15
| BIT14
;
4701 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4705 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4706 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4709 if ( info
->params
.addr_filter
!= 0xff )
4711 /* set up receive address filtering */
4712 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4716 usc_OutReg( info
, CMR
, RegValue
);
4717 info
->cmr_value
= RegValue
;
4719 /* Receiver mode Register (RMR)
4721 * <15..13> 000 encoding
4722 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4723 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4724 * <9> 0 1 = Include Receive chars in CRC
4725 * <8> 1 1 = Use Abort/PE bit as abort indicator
4726 * <7..6> 00 Even parity
4727 * <5> 0 parity disabled
4728 * <4..2> 000 Receive Char Length = 8 bits
4729 * <1..0> 00 Disable Receiver
4731 * 0000 0101 0000 0000 = 0x0500
4736 switch ( info
->params
.encoding
) {
4737 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4738 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4739 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
| BIT13
; break;
4740 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4741 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
| BIT13
; break;
4742 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
| BIT14
; break;
4743 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
| BIT14
| BIT13
; break;
4746 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4748 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4749 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4751 usc_OutReg( info
, RMR
, RegValue
);
4753 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4754 /* When an opening flag of an SDLC frame is recognized the */
4755 /* Receive Character count (RCC) is loaded with the value in */
4756 /* RCLR. The RCC is decremented for each received byte. The */
4757 /* value of RCC is stored after the closing flag of the frame */
4758 /* allowing the frame size to be computed. */
4760 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4762 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4764 /* Receive Interrupt Control Register (RICR)
4766 * <15..8> ? RxFIFO DMA Request Level
4767 * <7> 0 Exited Hunt IA (Interrupt Arm)
4768 * <6> 0 Idle Received IA
4769 * <5> 0 Break/Abort IA
4771 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4773 * <1> 1 Rx Overrun IA
4774 * <0> 0 Select TC0 value for readback
4776 * 0000 0000 0000 1000 = 0x000a
4779 /* Carry over the Exit Hunt and Idle Received bits */
4780 /* in case they have been armed by usc_ArmEvents. */
4782 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4784 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4785 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4787 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4789 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4791 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4792 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4794 /* Transmit mode Register (TMR)
4796 * <15..13> 000 encoding
4797 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4798 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4799 * <9> 0 1 = Tx CRC Enabled
4800 * <8> 0 1 = Append CRC to end of transmit frame
4801 * <7..6> 00 Transmit parity Even
4802 * <5> 0 Transmit parity Disabled
4803 * <4..2> 000 Tx Char Length = 8 bits
4804 * <1..0> 00 Disable Transmitter
4806 * 0000 0100 0000 0000 = 0x0400
4811 switch ( info
->params
.encoding
) {
4812 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4813 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4814 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
| BIT13
; break;
4815 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4816 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
| BIT13
; break;
4817 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
| BIT14
; break;
4818 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
| BIT14
| BIT13
; break;
4821 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4822 RegValue
|= BIT9
| BIT8
;
4823 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4824 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4826 usc_OutReg( info
, TMR
, RegValue
);
4828 usc_set_txidle( info
);
4831 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4833 /* Transmit Interrupt Control Register (TICR)
4835 * <15..8> ? Transmit FIFO DMA Level
4836 * <7> 0 Present IA (Interrupt Arm)
4837 * <6> 0 Idle Sent IA
4838 * <5> 1 Abort Sent IA
4839 * <4> 1 EOF/EOM Sent IA
4841 * <2> 1 1 = Wait for SW Trigger to Start Frame
4842 * <1> 1 Tx Underrun IA
4843 * <0> 0 TC0 constant on read back
4845 * 0000 0000 0011 0110 = 0x0036
4848 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4849 usc_OutReg( info
, TICR
, 0x0736 );
4851 usc_OutReg( info
, TICR
, 0x1436 );
4853 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4854 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4857 ** Transmit Command/Status Register (TCSR)
4859 ** <15..12> 0000 TCmd
4860 ** <11> 0/1 UnderWait
4861 ** <10..08> 000 TxIdle
4865 ** <4> x EOF/EOM Sent
4871 ** 0000 0000 0000 0000 = 0x0000
4873 info
->tcsr_value
= 0;
4876 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4878 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4880 /* Clock mode Control Register (CMCR)
4882 * <15..14> 00 counter 1 Source = Disabled
4883 * <13..12> 00 counter 0 Source = Disabled
4884 * <11..10> 11 BRG1 Input is TxC Pin
4885 * <9..8> 11 BRG0 Input is TxC Pin
4886 * <7..6> 01 DPLL Input is BRG1 Output
4887 * <5..3> XXX TxCLK comes from Port 0
4888 * <2..0> XXX RxCLK comes from Port 1
4890 * 0000 1111 0111 0111 = 0x0f77
4895 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4896 RegValue
|= 0x0003; /* RxCLK from DPLL */
4897 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4898 RegValue
|= 0x0004; /* RxCLK from BRG0 */
4899 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4900 RegValue
|= 0x0006; /* RxCLK from TXC Input */
4902 RegValue
|= 0x0007; /* RxCLK from Port1 */
4904 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4905 RegValue
|= 0x0018; /* TxCLK from DPLL */
4906 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4907 RegValue
|= 0x0020; /* TxCLK from BRG0 */
4908 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4909 RegValue
|= 0x0038; /* RxCLK from TXC Input */
4911 RegValue
|= 0x0030; /* TxCLK from Port0 */
4913 usc_OutReg( info
, CMCR
, RegValue
);
4916 /* Hardware Configuration Register (HCR)
4918 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4919 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4920 * <12> 0 CVOK:0=report code violation in biphase
4921 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4922 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4923 * <7..6> 00 reserved
4924 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4926 * <3..2> 00 reserved
4927 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4933 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
| HDLC_FLAG_TXC_DPLL
) ) {
4938 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4939 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4941 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4942 XtalSpeed
= 11059200;
4944 XtalSpeed
= 14745600;
4946 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4950 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4957 /* Tc = (Xtal/Speed) - 1 */
4958 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4959 /* then rounding up gives a more precise time constant. Instead */
4960 /* of rounding up and then subtracting 1 we just don't subtract */
4961 /* the one in this case. */
4963 /*--------------------------------------------------
4964 * ejz: for DPLL mode, application should use the
4965 * same clock speed as the partner system, even
4966 * though clocking is derived from the input RxData.
4967 * In case the user uses a 0 for the clock speed,
4968 * default to 0xffffffff and don't try to divide by
4970 *--------------------------------------------------*/
4971 if ( info
->params
.clock_speed
)
4973 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
4974 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
4975 / info
->params
.clock_speed
) )
4982 /* Write 16-bit Time Constant for BRG1 */
4983 usc_OutReg( info
, TC1R
, Tc
);
4985 RegValue
|= BIT4
; /* enable BRG1 */
4987 switch ( info
->params
.encoding
) {
4988 case HDLC_ENCODING_NRZ
:
4989 case HDLC_ENCODING_NRZB
:
4990 case HDLC_ENCODING_NRZI_MARK
:
4991 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
4992 case HDLC_ENCODING_BIPHASE_MARK
:
4993 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
4994 case HDLC_ENCODING_BIPHASE_LEVEL
:
4995 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
| BIT8
; break;
4999 usc_OutReg( info
, HCR
, RegValue
);
5002 /* Channel Control/status Register (CCSR)
5004 * <15> X RCC FIFO Overflow status (RO)
5005 * <14> X RCC FIFO Not Empty status (RO)
5006 * <13> 0 1 = Clear RCC FIFO (WO)
5007 * <12> X DPLL Sync (RW)
5008 * <11> X DPLL 2 Missed Clocks status (RO)
5009 * <10> X DPLL 1 Missed Clock status (RO)
5010 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5011 * <7> X SDLC Loop On status (RO)
5012 * <6> X SDLC Loop Send status (RO)
5013 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5014 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5015 * <1..0> 00 reserved
5017 * 0000 0000 0010 0000 = 0x0020
5020 usc_OutReg( info
, CCSR
, 0x1020 );
5023 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5024 usc_OutReg( info
, SICR
,
5025 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5029 /* enable Master Interrupt Enable bit (MIE) */
5030 usc_EnableMasterIrqBit( info
);
5032 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
| RECEIVE_DATA
|
5033 TRANSMIT_STATUS
| TRANSMIT_DATA
| MISC
);
5035 /* arm RCC underflow interrupt */
5036 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5037 usc_EnableInterrupts(info
, MISC
);
5040 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5041 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5042 info
->mbre_bit
= BIT8
;
5043 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5045 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5046 /* Enable DMAEN (Port 7, Bit 14) */
5047 /* This connects the DMA request signal to the ISA bus */
5048 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5051 /* DMA Control Register (DCR)
5053 * <15..14> 10 Priority mode = Alternating Tx/Rx
5054 * 01 Rx has priority
5055 * 00 Tx has priority
5057 * <13> 1 Enable Priority Preempt per DCR<15..14>
5058 * (WARNING DCR<11..10> must be 00 when this is 1)
5059 * 0 Choose activate channel per DCR<11..10>
5061 * <12> 0 Little Endian for Array/List
5062 * <11..10> 00 Both Channels can use each bus grant
5063 * <9..6> 0000 reserved
5064 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5065 * <4> 0 1 = drive D/C and S/D pins
5066 * <3> 1 1 = Add one wait state to all DMA cycles.
5067 * <2> 0 1 = Strobe /UAS on every transfer.
5068 * <1..0> 11 Addr incrementing only affects LS24 bits
5070 * 0110 0000 0000 1011 = 0x600b
5073 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5074 /* PCI adapter does not need DMA wait state */
5075 usc_OutDmaReg( info
, DCR
, 0xa00b );
5078 usc_OutDmaReg( info
, DCR
, 0x800b );
5081 /* Receive DMA mode Register (RDMR)
5083 * <15..14> 11 DMA mode = Linked List Buffer mode
5084 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5085 * <12> 1 Clear count of List Entry after fetching
5086 * <11..10> 00 Address mode = Increment
5087 * <9> 1 Terminate Buffer on RxBound
5088 * <8> 0 Bus Width = 16bits
5089 * <7..0> ? status Bits (write as 0s)
5091 * 1111 0010 0000 0000 = 0xf200
5094 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5097 /* Transmit DMA mode Register (TDMR)
5099 * <15..14> 11 DMA mode = Linked List Buffer mode
5100 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5101 * <12> 1 Clear count of List Entry after fetching
5102 * <11..10> 00 Address mode = Increment
5103 * <9> 1 Terminate Buffer on end of frame
5104 * <8> 0 Bus Width = 16bits
5105 * <7..0> ? status Bits (Read Only so write as 0)
5107 * 1111 0010 0000 0000 = 0xf200
5110 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5113 /* DMA Interrupt Control Register (DICR)
5115 * <15> 1 DMA Interrupt Enable
5116 * <14> 0 1 = Disable IEO from USC
5117 * <13> 0 1 = Don't provide vector during IntAck
5118 * <12> 1 1 = Include status in Vector
5119 * <10..2> 0 reserved, Must be 0s
5120 * <1> 0 1 = Rx DMA Interrupt Enabled
5121 * <0> 0 1 = Tx DMA Interrupt Enabled
5123 * 1001 0000 0000 0000 = 0x9000
5126 usc_OutDmaReg( info
, DICR
, 0x9000 );
5128 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5129 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5130 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5132 /* Channel Control Register (CCR)
5134 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5135 * <13> 0 Trigger Tx on SW Command Disabled
5136 * <12> 0 Flag Preamble Disabled
5137 * <11..10> 00 Preamble Length
5138 * <9..8> 00 Preamble Pattern
5139 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5140 * <5> 0 Trigger Rx on SW Command Disabled
5143 * 1000 0000 1000 0000 = 0x8080
5148 switch ( info
->params
.preamble_length
) {
5149 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5150 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5151 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
| BIT10
; break;
5154 switch ( info
->params
.preamble
) {
5155 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
| BIT12
; break;
5156 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5157 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5158 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
| BIT8
; break;
5161 usc_OutReg( info
, CCR
, RegValue
);
5165 * Burst/Dwell Control Register
5167 * <15..8> 0x20 Maximum number of transfers per bus grant
5168 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5171 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5172 /* don't limit bus occupancy on PCI adapter */
5173 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5176 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5178 usc_stop_transmitter(info
);
5179 usc_stop_receiver(info
);
5181 } /* end of usc_set_sdlc_mode() */
5183 /* usc_enable_loopback()
5185 * Set the 16C32 for internal loopback mode.
5186 * The TxCLK and RxCLK signals are generated from the BRG0 and
5187 * the TxD is looped back to the RxD internally.
5189 * Arguments: info pointer to device instance data
5190 * enable 1 = enable loopback, 0 = disable
5191 * Return Value: None
5193 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5196 /* blank external TXD output */
5197 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
| BIT6
));
5199 /* Clock mode Control Register (CMCR)
5201 * <15..14> 00 counter 1 Disabled
5202 * <13..12> 00 counter 0 Disabled
5203 * <11..10> 11 BRG1 Input is TxC Pin
5204 * <9..8> 11 BRG0 Input is TxC Pin
5205 * <7..6> 01 DPLL Input is BRG1 Output
5206 * <5..3> 100 TxCLK comes from BRG0
5207 * <2..0> 100 RxCLK comes from BRG0
5209 * 0000 1111 0110 0100 = 0x0f64
5212 usc_OutReg( info
, CMCR
, 0x0f64 );
5214 /* Write 16-bit Time Constant for BRG0 */
5215 /* use clock speed if available, otherwise use 8 for diagnostics */
5216 if (info
->params
.clock_speed
) {
5217 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5218 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5220 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5222 usc_OutReg(info
, TC0R
, (u16
)8);
5224 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5225 mode = Continuous Set Bit 0 to enable BRG0. */
5226 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5228 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5229 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5231 /* set Internal Data loopback mode */
5232 info
->loopback_bits
= 0x300;
5233 outw( 0x0300, info
->io_base
+ CCAR
);
5235 /* enable external TXD output */
5236 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
| BIT6
));
5238 /* clear Internal Data loopback mode */
5239 info
->loopback_bits
= 0;
5240 outw( 0,info
->io_base
+ CCAR
);
5243 } /* end of usc_enable_loopback() */
5245 /* usc_enable_aux_clock()
5247 * Enabled the AUX clock output at the specified frequency.
5251 * info pointer to device extension
5252 * data_rate data rate of clock in bits per second
5253 * A data rate of 0 disables the AUX clock.
5255 * Return Value: None
5257 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5263 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5264 XtalSpeed
= 11059200;
5266 XtalSpeed
= 14745600;
5269 /* Tc = (Xtal/Speed) - 1 */
5270 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5271 /* then rounding up gives a more precise time constant. Instead */
5272 /* of rounding up and then subtracting 1 we just don't subtract */
5273 /* the one in this case. */
5276 Tc
= (u16
)(XtalSpeed
/data_rate
);
5277 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5280 /* Write 16-bit Time Constant for BRG0 */
5281 usc_OutReg( info
, TC0R
, Tc
);
5284 * Hardware Configuration Register (HCR)
5285 * Clear Bit 1, BRG0 mode = Continuous
5286 * Set Bit 0 to enable BRG0.
5289 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5291 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5292 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5294 /* data rate == 0 so turn off BRG0 */
5295 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5298 } /* end of usc_enable_aux_clock() */
5302 * usc_process_rxoverrun_sync()
5304 * This function processes a receive overrun by resetting the
5305 * receive DMA buffers and issuing a Purge Rx FIFO command
5306 * to allow the receiver to continue receiving.
5310 * info pointer to device extension
5312 * Return Value: None
5314 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5318 int frame_start_index
;
5319 bool start_of_frame_found
= false;
5320 bool end_of_frame_found
= false;
5321 bool reprogram_dma
= false;
5323 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5326 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5327 usc_RCmd( info
, RCmd_EnterHuntmode
);
5328 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5330 /* CurrentRxBuffer points to the 1st buffer of the next */
5331 /* possibly available receive frame. */
5333 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5335 /* Search for an unfinished string of buffers. This means */
5336 /* that a receive frame started (at least one buffer with */
5337 /* count set to zero) but there is no terminiting buffer */
5338 /* (status set to non-zero). */
5340 while( !buffer_list
[end_index
].count
)
5342 /* Count field has been reset to zero by 16C32. */
5343 /* This buffer is currently in use. */
5345 if ( !start_of_frame_found
)
5347 start_of_frame_found
= true;
5348 frame_start_index
= end_index
;
5349 end_of_frame_found
= false;
5352 if ( buffer_list
[end_index
].status
)
5354 /* Status field has been set by 16C32. */
5355 /* This is the last buffer of a received frame. */
5357 /* We want to leave the buffers for this frame intact. */
5358 /* Move on to next possible frame. */
5360 start_of_frame_found
= false;
5361 end_of_frame_found
= true;
5364 /* advance to next buffer entry in linked list */
5366 if ( end_index
== info
->rx_buffer_count
)
5369 if ( start_index
== end_index
)
5371 /* The entire list has been searched with all Counts == 0 and */
5372 /* all Status == 0. The receive buffers are */
5373 /* completely screwed, reset all receive buffers! */
5374 mgsl_reset_rx_dma_buffers( info
);
5375 frame_start_index
= 0;
5376 start_of_frame_found
= false;
5377 reprogram_dma
= true;
5382 if ( start_of_frame_found
&& !end_of_frame_found
)
5384 /* There is an unfinished string of receive DMA buffers */
5385 /* as a result of the receiver overrun. */
5387 /* Reset the buffers for the unfinished frame */
5388 /* and reprogram the receive DMA controller to start */
5389 /* at the 1st buffer of unfinished frame. */
5391 start_index
= frame_start_index
;
5395 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5397 /* Adjust index for wrap around. */
5398 if ( start_index
== info
->rx_buffer_count
)
5401 } while( start_index
!= end_index
);
5403 reprogram_dma
= true;
5406 if ( reprogram_dma
)
5408 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5409 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5410 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5412 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5414 /* This empties the receive FIFO and loads the RCC with RCLR */
5415 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5417 /* program 16C32 with physical address of 1st DMA buffer entry */
5418 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5419 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5420 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5422 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5423 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5424 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5426 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5427 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5429 usc_OutDmaReg( info
, RDIAR
, BIT3
| BIT2
);
5430 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5431 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5432 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5433 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5435 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5439 /* This empties the receive FIFO and loads the RCC with RCLR */
5440 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5441 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5444 } /* end of usc_process_rxoverrun_sync() */
5446 /* usc_stop_receiver()
5448 * Disable USC receiver
5450 * Arguments: info pointer to device instance data
5451 * Return Value: None
5453 static void usc_stop_receiver( struct mgsl_struct
*info
)
5455 if (debug_level
>= DEBUG_LEVEL_ISR
)
5456 printk("%s(%d):usc_stop_receiver(%s)\n",
5457 __FILE__
,__LINE__
, info
->device_name
);
5459 /* Disable receive DMA channel. */
5460 /* This also disables receive DMA channel interrupts */
5461 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5463 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5464 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5465 usc_DisableInterrupts( info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5467 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5469 /* This empties the receive FIFO and loads the RCC with RCLR */
5470 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5471 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5473 info
->rx_enabled
= false;
5474 info
->rx_overflow
= false;
5475 info
->rx_rcc_underrun
= false;
5477 } /* end of stop_receiver() */
5479 /* usc_start_receiver()
5481 * Enable the USC receiver
5483 * Arguments: info pointer to device instance data
5484 * Return Value: None
5486 static void usc_start_receiver( struct mgsl_struct
*info
)
5490 if (debug_level
>= DEBUG_LEVEL_ISR
)
5491 printk("%s(%d):usc_start_receiver(%s)\n",
5492 __FILE__
,__LINE__
, info
->device_name
);
5494 mgsl_reset_rx_dma_buffers( info
);
5495 usc_stop_receiver( info
);
5497 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5498 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5500 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5501 info
->params
.mode
== MGSL_MODE_RAW
) {
5502 /* DMA mode Transfers */
5503 /* Program the DMA controller. */
5504 /* Enable the DMA controller end of buffer interrupt. */
5506 /* program 16C32 with physical address of 1st DMA buffer entry */
5507 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5508 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5509 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5511 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5512 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5513 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5515 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5516 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5518 usc_OutDmaReg( info
, RDIAR
, BIT3
| BIT2
);
5519 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5520 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5521 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5522 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5524 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5526 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5527 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
| RECEIVE_STATUS
);
5528 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5530 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5531 usc_RCmd( info
, RCmd_EnterHuntmode
);
5533 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5536 usc_OutReg( info
, CCSR
, 0x1020 );
5538 info
->rx_enabled
= true;
5540 } /* end of usc_start_receiver() */
5542 /* usc_start_transmitter()
5544 * Enable the USC transmitter and send a transmit frame if
5545 * one is loaded in the DMA buffers.
5547 * Arguments: info pointer to device instance data
5548 * Return Value: None
5550 static void usc_start_transmitter( struct mgsl_struct
*info
)
5553 unsigned int FrameSize
;
5555 if (debug_level
>= DEBUG_LEVEL_ISR
)
5556 printk("%s(%d):usc_start_transmitter(%s)\n",
5557 __FILE__
,__LINE__
, info
->device_name
);
5559 if ( info
->xmit_cnt
) {
5561 /* If auto RTS enabled and RTS is inactive, then assert */
5562 /* RTS and set a flag indicating that the driver should */
5563 /* negate RTS when the transmission completes. */
5565 info
->drop_rts_on_tx_done
= false;
5567 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5568 usc_get_serial_signals( info
);
5569 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5570 info
->serial_signals
|= SerialSignal_RTS
;
5571 usc_set_serial_signals( info
);
5572 info
->drop_rts_on_tx_done
= true;
5577 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5578 if ( !info
->tx_active
) {
5579 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5580 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5581 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5582 usc_load_txfifo(info
);
5585 /* Disable transmit DMA controller while programming. */
5586 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5588 /* Transmit DMA buffer is loaded, so program USC */
5589 /* to send the frame contained in the buffers. */
5591 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5593 /* if operating in Raw sync mode, reset the rcc component
5594 * of the tx dma buffer entry, otherwise, the serial controller
5595 * will send a closing sync char after this count.
5597 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5598 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5600 /* Program the Transmit Character Length Register (TCLR) */
5601 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5602 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5604 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5606 /* Program the address of the 1st DMA Buffer Entry in linked list */
5607 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5608 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5609 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5611 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5612 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5613 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5615 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5616 info
->num_tx_dma_buffers
> 1 ) {
5617 /* When running external sync mode, attempt to 'stream' transmit */
5618 /* by filling tx dma buffers as they become available. To do this */
5619 /* we need to enable Tx DMA EOB Status interrupts : */
5621 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5622 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5624 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5625 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5628 /* Initialize Transmit DMA Channel */
5629 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5631 usc_TCmd( info
, TCmd_SendFrame
);
5633 mod_timer(&info
->tx_timer
, jiffies
+
5634 msecs_to_jiffies(5000));
5636 info
->tx_active
= true;
5639 if ( !info
->tx_enabled
) {
5640 info
->tx_enabled
= true;
5641 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5642 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5644 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5647 } /* end of usc_start_transmitter() */
5649 /* usc_stop_transmitter()
5651 * Stops the transmitter and DMA
5653 * Arguments: info pointer to device isntance data
5654 * Return Value: None
5656 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5658 if (debug_level
>= DEBUG_LEVEL_ISR
)
5659 printk("%s(%d):usc_stop_transmitter(%s)\n",
5660 __FILE__
,__LINE__
, info
->device_name
);
5662 del_timer(&info
->tx_timer
);
5664 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5665 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5666 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5668 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5669 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5670 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5672 info
->tx_enabled
= false;
5673 info
->tx_active
= false;
5675 } /* end of usc_stop_transmitter() */
5677 /* usc_load_txfifo()
5679 * Fill the transmit FIFO until the FIFO is full or
5680 * there is no more data to load.
5682 * Arguments: info pointer to device extension (instance data)
5683 * Return Value: None
5685 static void usc_load_txfifo( struct mgsl_struct
*info
)
5690 if ( !info
->xmit_cnt
&& !info
->x_char
)
5693 /* Select transmit FIFO status readback in TICR */
5694 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5696 /* load the Transmit FIFO until FIFOs full or all data sent */
5698 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5699 /* there is more space in the transmit FIFO and */
5700 /* there is more data in transmit buffer */
5702 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5703 /* write a 16-bit word from transmit buffer to 16C32 */
5705 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5706 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5707 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5708 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5710 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5712 info
->xmit_cnt
-= 2;
5713 info
->icount
.tx
+= 2;
5715 /* only 1 byte left to transmit or 1 FIFO slot left */
5717 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5718 info
->io_base
+ CCAR
);
5721 /* transmit pending high priority char */
5722 outw( info
->x_char
,info
->io_base
+ CCAR
);
5725 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5726 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5733 } /* end of usc_load_txfifo() */
5737 * Reset the adapter to a known state and prepare it for further use.
5739 * Arguments: info pointer to device instance data
5740 * Return Value: None
5742 static void usc_reset( struct mgsl_struct
*info
)
5744 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5748 /* Set BIT30 of Misc Control Register */
5749 /* (Local Control Register 0x50) to force reset of USC. */
5751 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5752 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5754 info
->misc_ctrl_value
|= BIT30
;
5755 *MiscCtrl
= info
->misc_ctrl_value
;
5758 * Force at least 170ns delay before clearing
5759 * reset bit. Each read from LCR takes at least
5760 * 30ns so 10 times for 300ns to be safe.
5763 readval
= *MiscCtrl
;
5765 info
->misc_ctrl_value
&= ~BIT30
;
5766 *MiscCtrl
= info
->misc_ctrl_value
;
5768 *LCR0BRDR
= BUS_DESCRIPTOR(
5769 1, // Write Strobe Hold (0-3)
5770 2, // Write Strobe Delay (0-3)
5771 2, // Read Strobe Delay (0-3)
5772 0, // NWDD (Write data-data) (0-3)
5773 4, // NWAD (Write Addr-data) (0-31)
5774 0, // NXDA (Read/Write Data-Addr) (0-3)
5775 0, // NRDD (Read Data-Data) (0-3)
5776 5 // NRAD (Read Addr-Data) (0-31)
5780 outb( 0,info
->io_base
+ 8 );
5784 info
->loopback_bits
= 0;
5785 info
->usc_idle_mode
= 0;
5788 * Program the Bus Configuration Register (BCR)
5790 * <15> 0 Don't use separate address
5791 * <14..6> 0 reserved
5792 * <5..4> 00 IAckmode = Default, don't care
5793 * <3> 1 Bus Request Totem Pole output
5794 * <2> 1 Use 16 Bit data bus
5795 * <1> 0 IRQ Totem Pole output
5796 * <0> 0 Don't Shift Right Addr
5798 * 0000 0000 0000 1100 = 0x000c
5800 * By writing to io_base + SDPIN the Wait/Ack pin is
5801 * programmed to work as a Wait pin.
5804 outw( 0x000c,info
->io_base
+ SDPIN
);
5807 outw( 0,info
->io_base
);
5808 outw( 0,info
->io_base
+ CCAR
);
5810 /* select little endian byte ordering */
5811 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5814 /* Port Control Register (PCR)
5816 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5817 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5818 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5819 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5820 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5821 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5822 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5823 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5825 * 1111 0000 1111 0101 = 0xf0f5
5828 usc_OutReg( info
, PCR
, 0xf0f5 );
5832 * Input/Output Control Register
5834 * <15..14> 00 CTS is active low input
5835 * <13..12> 00 DCD is active low input
5836 * <11..10> 00 TxREQ pin is input (DSR)
5837 * <9..8> 00 RxREQ pin is input (RI)
5838 * <7..6> 00 TxD is output (Transmit Data)
5839 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5840 * <2..0> 100 RxC is Output (drive with BRG0)
5842 * 0000 0000 0000 0100 = 0x0004
5845 usc_OutReg( info
, IOCR
, 0x0004 );
5847 } /* end of usc_reset() */
5849 /* usc_set_async_mode()
5851 * Program adapter for asynchronous communications.
5853 * Arguments: info pointer to device instance data
5854 * Return Value: None
5856 static void usc_set_async_mode( struct mgsl_struct
*info
)
5860 /* disable interrupts while programming USC */
5861 usc_DisableMasterIrqBit( info
);
5863 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5864 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5866 usc_loopback_frame( info
);
5868 /* Channel mode Register (CMR)
5870 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5871 * <13..12> 00 00 = 16X Clock
5872 * <11..8> 0000 Transmitter mode = Asynchronous
5873 * <7..6> 00 reserved?
5874 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5875 * <3..0> 0000 Receiver mode = Asynchronous
5877 * 0000 0000 0000 0000 = 0x0
5881 if ( info
->params
.stop_bits
!= 1 )
5883 usc_OutReg( info
, CMR
, RegValue
);
5886 /* Receiver mode Register (RMR)
5888 * <15..13> 000 encoding = None
5889 * <12..08> 00000 reserved (Sync Only)
5890 * <7..6> 00 Even parity
5891 * <5> 0 parity disabled
5892 * <4..2> 000 Receive Char Length = 8 bits
5893 * <1..0> 00 Disable Receiver
5895 * 0000 0000 0000 0000 = 0x0
5900 if ( info
->params
.data_bits
!= 8 )
5901 RegValue
|= BIT4
| BIT3
| BIT2
;
5903 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5905 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5909 usc_OutReg( info
, RMR
, RegValue
);
5912 /* Set IRQ trigger level */
5914 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
5917 /* Receive Interrupt Control Register (RICR)
5919 * <15..8> ? RxFIFO IRQ Request Level
5921 * Note: For async mode the receive FIFO level must be set
5922 * to 0 to avoid the situation where the FIFO contains fewer bytes
5923 * than the trigger level and no more data is expected.
5925 * <7> 0 Exited Hunt IA (Interrupt Arm)
5926 * <6> 0 Idle Received IA
5927 * <5> 0 Break/Abort IA
5929 * <3> 0 Queued status reflects oldest byte in FIFO
5931 * <1> 0 Rx Overrun IA
5932 * <0> 0 Select TC0 value for readback
5934 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5937 usc_OutReg( info
, RICR
, 0x0000 );
5939 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5940 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
5943 /* Transmit mode Register (TMR)
5945 * <15..13> 000 encoding = None
5946 * <12..08> 00000 reserved (Sync Only)
5947 * <7..6> 00 Transmit parity Even
5948 * <5> 0 Transmit parity Disabled
5949 * <4..2> 000 Tx Char Length = 8 bits
5950 * <1..0> 00 Disable Transmitter
5952 * 0000 0000 0000 0000 = 0x0
5957 if ( info
->params
.data_bits
!= 8 )
5958 RegValue
|= BIT4
| BIT3
| BIT2
;
5960 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5962 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5966 usc_OutReg( info
, TMR
, RegValue
);
5968 usc_set_txidle( info
);
5971 /* Set IRQ trigger level */
5973 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
5976 /* Transmit Interrupt Control Register (TICR)
5978 * <15..8> ? Transmit FIFO IRQ Level
5979 * <7> 0 Present IA (Interrupt Arm)
5980 * <6> 1 Idle Sent IA
5981 * <5> 0 Abort Sent IA
5982 * <4> 0 EOF/EOM Sent IA
5984 * <2> 0 1 = Wait for SW Trigger to Start Frame
5985 * <1> 0 Tx Underrun IA
5986 * <0> 0 TC0 constant on read back
5988 * 0000 0000 0100 0000 = 0x0040
5991 usc_OutReg( info
, TICR
, 0x1f40 );
5993 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5994 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5996 usc_enable_async_clock( info
, info
->params
.data_rate
);
5999 /* Channel Control/status Register (CCSR)
6001 * <15> X RCC FIFO Overflow status (RO)
6002 * <14> X RCC FIFO Not Empty status (RO)
6003 * <13> 0 1 = Clear RCC FIFO (WO)
6004 * <12> X DPLL in Sync status (RO)
6005 * <11> X DPLL 2 Missed Clocks status (RO)
6006 * <10> X DPLL 1 Missed Clock status (RO)
6007 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6008 * <7> X SDLC Loop On status (RO)
6009 * <6> X SDLC Loop Send status (RO)
6010 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6011 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6012 * <1..0> 00 reserved
6014 * 0000 0000 0010 0000 = 0x0020
6017 usc_OutReg( info
, CCSR
, 0x0020 );
6019 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6020 RECEIVE_DATA
+ RECEIVE_STATUS
);
6022 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6023 RECEIVE_DATA
+ RECEIVE_STATUS
);
6025 usc_EnableMasterIrqBit( info
);
6027 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6028 /* Enable INTEN (Port 6, Bit12) */
6029 /* This connects the IRQ request signal to the ISA bus */
6030 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6033 if (info
->params
.loopback
) {
6034 info
->loopback_bits
= 0x300;
6035 outw(0x0300, info
->io_base
+ CCAR
);
6038 } /* end of usc_set_async_mode() */
6040 /* usc_loopback_frame()
6042 * Loop back a small (2 byte) dummy SDLC frame.
6043 * Interrupts and DMA are NOT used. The purpose of this is to
6044 * clear any 'stale' status info left over from running in async mode.
6046 * The 16C32 shows the strange behaviour of marking the 1st
6047 * received SDLC frame with a CRC error even when there is no
6048 * CRC error. To get around this a small dummy from of 2 bytes
6049 * is looped back when switching from async to sync mode.
6051 * Arguments: info pointer to device instance data
6052 * Return Value: None
6054 static void usc_loopback_frame( struct mgsl_struct
*info
)
6057 unsigned long oldmode
= info
->params
.mode
;
6059 info
->params
.mode
= MGSL_MODE_HDLC
;
6061 usc_DisableMasterIrqBit( info
);
6063 usc_set_sdlc_mode( info
);
6064 usc_enable_loopback( info
, 1 );
6066 /* Write 16-bit Time Constant for BRG0 */
6067 usc_OutReg( info
, TC0R
, 0 );
6069 /* Channel Control Register (CCR)
6071 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6072 * <13> 0 Trigger Tx on SW Command Disabled
6073 * <12> 0 Flag Preamble Disabled
6074 * <11..10> 00 Preamble Length = 8-Bits
6075 * <9..8> 01 Preamble Pattern = flags
6076 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6077 * <5> 0 Trigger Rx on SW Command Disabled
6080 * 0000 0001 0000 0000 = 0x0100
6083 usc_OutReg( info
, CCR
, 0x0100 );
6085 /* SETUP RECEIVER */
6086 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6087 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6089 /* SETUP TRANSMITTER */
6090 /* Program the Transmit Character Length Register (TCLR) */
6091 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6092 usc_OutReg( info
, TCLR
, 2 );
6093 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6095 /* unlatch Tx status bits, and start transmit channel. */
6096 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6097 outw(0,info
->io_base
+ DATAREG
);
6099 /* ENABLE TRANSMITTER */
6100 usc_TCmd( info
, TCmd_SendFrame
);
6101 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6103 /* WAIT FOR RECEIVE COMPLETE */
6104 for (i
=0 ; i
<1000 ; i
++)
6105 if (usc_InReg( info
, RCSR
) & (BIT8
| BIT4
| BIT3
| BIT1
))
6108 /* clear Internal Data loopback mode */
6109 usc_enable_loopback(info
, 0);
6111 usc_EnableMasterIrqBit(info
);
6113 info
->params
.mode
= oldmode
;
6115 } /* end of usc_loopback_frame() */
6117 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6119 * Arguments: info pointer to adapter info structure
6120 * Return Value: None
6122 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6124 usc_loopback_frame( info
);
6125 usc_set_sdlc_mode( info
);
6127 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6128 /* Enable INTEN (Port 6, Bit12) */
6129 /* This connects the IRQ request signal to the ISA bus */
6130 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6133 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6135 if (info
->params
.loopback
)
6136 usc_enable_loopback(info
,1);
6138 } /* end of mgsl_set_sync_mode() */
6140 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6142 * Arguments: info pointer to device instance data
6143 * Return Value: None
6145 static void usc_set_txidle( struct mgsl_struct
*info
)
6147 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6149 /* Map API idle mode to USC register bits */
6151 switch( info
->idle_mode
){
6152 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6153 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6154 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6155 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6156 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6157 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6158 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6161 info
->usc_idle_mode
= usc_idle_mode
;
6162 //usc_OutReg(info, TCSR, usc_idle_mode);
6163 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6164 info
->tcsr_value
+= usc_idle_mode
;
6165 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6168 * if SyncLink WAN adapter is running in external sync mode, the
6169 * transmitter has been set to Monosync in order to try to mimic
6170 * a true raw outbound bit stream. Monosync still sends an open/close
6171 * sync char at the start/end of a frame. Try to match those sync
6172 * patterns to the idle mode set here
6174 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6175 unsigned char syncpat
= 0;
6176 switch( info
->idle_mode
) {
6177 case HDLC_TXIDLE_FLAGS
:
6180 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6183 case HDLC_TXIDLE_ZEROS
:
6184 case HDLC_TXIDLE_SPACE
:
6187 case HDLC_TXIDLE_ONES
:
6188 case HDLC_TXIDLE_MARK
:
6191 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6196 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6199 } /* end of usc_set_txidle() */
6201 /* usc_get_serial_signals()
6203 * Query the adapter for the state of the V24 status (input) signals.
6205 * Arguments: info pointer to device instance data
6206 * Return Value: None
6208 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6212 /* clear all serial signals except RTS and DTR */
6213 info
->serial_signals
&= SerialSignal_RTS
| SerialSignal_DTR
;
6215 /* Read the Misc Interrupt status Register (MISR) to get */
6216 /* the V24 status signals. */
6218 status
= usc_InReg( info
, MISR
);
6220 /* set serial signal bits to reflect MISR */
6222 if ( status
& MISCSTATUS_CTS
)
6223 info
->serial_signals
|= SerialSignal_CTS
;
6225 if ( status
& MISCSTATUS_DCD
)
6226 info
->serial_signals
|= SerialSignal_DCD
;
6228 if ( status
& MISCSTATUS_RI
)
6229 info
->serial_signals
|= SerialSignal_RI
;
6231 if ( status
& MISCSTATUS_DSR
)
6232 info
->serial_signals
|= SerialSignal_DSR
;
6234 } /* end of usc_get_serial_signals() */
6236 /* usc_set_serial_signals()
6238 * Set the state of RTS and DTR based on contents of
6239 * serial_signals member of device extension.
6241 * Arguments: info pointer to device instance data
6242 * Return Value: None
6244 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6247 unsigned char V24Out
= info
->serial_signals
;
6249 /* get the current value of the Port Control Register (PCR) */
6251 Control
= usc_InReg( info
, PCR
);
6253 if ( V24Out
& SerialSignal_RTS
)
6258 if ( V24Out
& SerialSignal_DTR
)
6263 usc_OutReg( info
, PCR
, Control
);
6265 } /* end of usc_set_serial_signals() */
6267 /* usc_enable_async_clock()
6269 * Enable the async clock at the specified frequency.
6271 * Arguments: info pointer to device instance data
6272 * data_rate data rate of clock in bps
6273 * 0 disables the AUX clock.
6274 * Return Value: None
6276 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6280 * Clock mode Control Register (CMCR)
6282 * <15..14> 00 counter 1 Disabled
6283 * <13..12> 00 counter 0 Disabled
6284 * <11..10> 11 BRG1 Input is TxC Pin
6285 * <9..8> 11 BRG0 Input is TxC Pin
6286 * <7..6> 01 DPLL Input is BRG1 Output
6287 * <5..3> 100 TxCLK comes from BRG0
6288 * <2..0> 100 RxCLK comes from BRG0
6290 * 0000 1111 0110 0100 = 0x0f64
6293 usc_OutReg( info
, CMCR
, 0x0f64 );
6297 * Write 16-bit Time Constant for BRG0
6298 * Time Constant = (ClkSpeed / data_rate) - 1
6299 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6302 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6303 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6305 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6309 * Hardware Configuration Register (HCR)
6310 * Clear Bit 1, BRG0 mode = Continuous
6311 * Set Bit 0 to enable BRG0.
6314 usc_OutReg( info
, HCR
,
6315 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6318 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6320 usc_OutReg( info
, IOCR
,
6321 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6323 /* data rate == 0 so turn off BRG0 */
6324 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6327 } /* end of usc_enable_async_clock() */
6330 * Buffer Structures:
6332 * Normal memory access uses virtual addresses that can make discontiguous
6333 * physical memory pages appear to be contiguous in the virtual address
6334 * space (the processors memory mapping handles the conversions).
6336 * DMA transfers require physically contiguous memory. This is because
6337 * the DMA system controller and DMA bus masters deal with memory using
6338 * only physical addresses.
6340 * This causes a problem under Windows NT when large DMA buffers are
6341 * needed. Fragmentation of the nonpaged pool prevents allocations of
6342 * physically contiguous buffers larger than the PAGE_SIZE.
6344 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6345 * allows DMA transfers to physically discontiguous buffers. Information
6346 * about each data transfer buffer is contained in a memory structure
6347 * called a 'buffer entry'. A list of buffer entries is maintained
6348 * to track and control the use of the data transfer buffers.
6350 * To support this strategy we will allocate sufficient PAGE_SIZE
6351 * contiguous memory buffers to allow for the total required buffer
6354 * The 16C32 accesses the list of buffer entries using Bus Master
6355 * DMA. Control information is read from the buffer entries by the
6356 * 16C32 to control data transfers. status information is written to
6357 * the buffer entries by the 16C32 to indicate the status of completed
6360 * The CPU writes control information to the buffer entries to control
6361 * the 16C32 and reads status information from the buffer entries to
6362 * determine information about received and transmitted frames.
6364 * Because the CPU and 16C32 (adapter) both need simultaneous access
6365 * to the buffer entries, the buffer entry memory is allocated with
6366 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6367 * entry list to PAGE_SIZE.
6369 * The actual data buffers on the other hand will only be accessed
6370 * by the CPU or the adapter but not by both simultaneously. This allows
6371 * Scatter/Gather packet based DMA procedures for using physically
6372 * discontiguous pages.
6376 * mgsl_reset_tx_dma_buffers()
6378 * Set the count for all transmit buffers to 0 to indicate the
6379 * buffer is available for use and set the current buffer to the
6380 * first buffer. This effectively makes all buffers free and
6381 * discards any data in buffers.
6383 * Arguments: info pointer to device instance data
6384 * Return Value: None
6386 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6390 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6391 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6394 info
->current_tx_buffer
= 0;
6395 info
->start_tx_dma_buffer
= 0;
6396 info
->tx_dma_buffers_used
= 0;
6398 info
->get_tx_holding_index
= 0;
6399 info
->put_tx_holding_index
= 0;
6400 info
->tx_holding_count
= 0;
6402 } /* end of mgsl_reset_tx_dma_buffers() */
6405 * num_free_tx_dma_buffers()
6407 * returns the number of free tx dma buffers available
6409 * Arguments: info pointer to device instance data
6410 * Return Value: number of free tx dma buffers
6412 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6414 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6418 * mgsl_reset_rx_dma_buffers()
6420 * Set the count for all receive buffers to DMABUFFERSIZE
6421 * and set the current buffer to the first buffer. This effectively
6422 * makes all buffers free and discards any data in buffers.
6424 * Arguments: info pointer to device instance data
6425 * Return Value: None
6427 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6431 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6432 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6433 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6434 // info->rx_buffer_list[i].status = 0;
6437 info
->current_rx_buffer
= 0;
6439 } /* end of mgsl_reset_rx_dma_buffers() */
6442 * mgsl_free_rx_frame_buffers()
6444 * Free the receive buffers used by a received SDLC
6445 * frame such that the buffers can be reused.
6449 * info pointer to device instance data
6450 * StartIndex index of 1st receive buffer of frame
6451 * EndIndex index of last receive buffer of frame
6453 * Return Value: None
6455 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6458 DMABUFFERENTRY
*pBufEntry
;
6461 /* Starting with 1st buffer entry of the frame clear the status */
6462 /* field and set the count field to DMA Buffer Size. */
6467 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6469 if ( Index
== EndIndex
) {
6470 /* This is the last buffer of the frame! */
6474 /* reset current buffer for reuse */
6475 // pBufEntry->status = 0;
6476 // pBufEntry->count = DMABUFFERSIZE;
6477 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6479 /* advance to next buffer entry in linked list */
6481 if ( Index
== info
->rx_buffer_count
)
6485 /* set current buffer to next buffer after last buffer of frame */
6486 info
->current_rx_buffer
= Index
;
6488 } /* end of free_rx_frame_buffers() */
6490 /* mgsl_get_rx_frame()
6492 * This function attempts to return a received SDLC frame from the
6493 * receive DMA buffers. Only frames received without errors are returned.
6495 * Arguments: info pointer to device extension
6496 * Return Value: true if frame returned, otherwise false
6498 static bool mgsl_get_rx_frame(struct mgsl_struct
*info
)
6500 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6501 unsigned short status
;
6502 DMABUFFERENTRY
*pBufEntry
;
6503 unsigned int framesize
= 0;
6504 bool ReturnCode
= false;
6505 unsigned long flags
;
6506 struct tty_struct
*tty
= info
->port
.tty
;
6507 bool return_frame
= false;
6510 * current_rx_buffer points to the 1st buffer of the next available
6511 * receive frame. To find the last buffer of the frame look for
6512 * a non-zero status field in the buffer entries. (The status
6513 * field is set by the 16C32 after completing a receive frame.
6516 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6518 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6520 * If the count field of the buffer entry is non-zero then
6521 * this buffer has not been used. (The 16C32 clears the count
6522 * field when it starts using the buffer.) If an unused buffer
6523 * is encountered then there are no frames available.
6526 if ( info
->rx_buffer_list
[EndIndex
].count
)
6529 /* advance to next buffer entry in linked list */
6531 if ( EndIndex
== info
->rx_buffer_count
)
6534 /* if entire list searched then no frame available */
6535 if ( EndIndex
== StartIndex
) {
6536 /* If this occurs then something bad happened,
6537 * all buffers have been 'used' but none mark
6538 * the end of a frame. Reset buffers and receiver.
6541 if ( info
->rx_enabled
){
6542 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6543 usc_start_receiver(info
);
6544 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6551 /* check status of receive frame */
6553 status
= info
->rx_buffer_list
[EndIndex
].status
;
6555 if ( status
& (RXSTATUS_SHORT_FRAME
| RXSTATUS_OVERRUN
|
6556 RXSTATUS_CRC_ERROR
| RXSTATUS_ABORT
) ) {
6557 if ( status
& RXSTATUS_SHORT_FRAME
)
6558 info
->icount
.rxshort
++;
6559 else if ( status
& RXSTATUS_ABORT
)
6560 info
->icount
.rxabort
++;
6561 else if ( status
& RXSTATUS_OVERRUN
)
6562 info
->icount
.rxover
++;
6564 info
->icount
.rxcrc
++;
6565 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6566 return_frame
= true;
6569 #if SYNCLINK_GENERIC_HDLC
6571 info
->netdev
->stats
.rx_errors
++;
6572 info
->netdev
->stats
.rx_frame_errors
++;
6576 return_frame
= true;
6578 if ( return_frame
) {
6579 /* receive frame has no errors, get frame size.
6580 * The frame size is the starting value of the RCC (which was
6581 * set to 0xffff) minus the ending value of the RCC (decremented
6582 * once for each receive character) minus 2 for the 16-bit CRC.
6585 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6587 /* adjust frame size for CRC if any */
6588 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6590 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6594 if ( debug_level
>= DEBUG_LEVEL_BH
)
6595 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6596 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6598 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6599 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6600 min_t(int, framesize
, DMABUFFERSIZE
),0);
6603 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6604 ((framesize
+1) > info
->max_frame_size
) ) ||
6605 (framesize
> info
->max_frame_size
) )
6606 info
->icount
.rxlong
++;
6608 /* copy dma buffer(s) to contiguous intermediate buffer */
6609 int copy_count
= framesize
;
6610 int index
= StartIndex
;
6611 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6613 if ( !(status
& RXSTATUS_CRC_ERROR
))
6614 info
->icount
.rxok
++;
6618 if ( copy_count
> DMABUFFERSIZE
)
6619 partial_count
= DMABUFFERSIZE
;
6621 partial_count
= copy_count
;
6623 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6624 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6625 ptmp
+= partial_count
;
6626 copy_count
-= partial_count
;
6628 if ( ++index
== info
->rx_buffer_count
)
6632 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6634 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6638 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6639 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6640 __FILE__
,__LINE__
,info
->device_name
,
6644 #if SYNCLINK_GENERIC_HDLC
6646 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6649 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6652 /* Free the buffers used by this frame. */
6653 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6659 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6660 /* The receiver needs to restarted because of
6661 * a receive overflow (buffer or FIFO). If the
6662 * receive buffers are now empty, then restart receiver.
6665 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6666 info
->rx_buffer_list
[EndIndex
].count
) {
6667 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6668 usc_start_receiver(info
);
6669 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6675 } /* end of mgsl_get_rx_frame() */
6677 /* mgsl_get_raw_rx_frame()
6679 * This function attempts to return a received frame from the
6680 * receive DMA buffers when running in external loop mode. In this mode,
6681 * we will return at most one DMABUFFERSIZE frame to the application.
6682 * The USC receiver is triggering off of DCD going active to start a new
6683 * frame, and DCD going inactive to terminate the frame (similar to
6684 * processing a closing flag character).
6686 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6687 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6688 * status field and the RCC field will indicate the length of the
6689 * entire received frame. We take this RCC field and get the modulus
6690 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6691 * last Rx DMA buffer and return that last portion of the frame.
6693 * Arguments: info pointer to device extension
6694 * Return Value: true if frame returned, otherwise false
6696 static bool mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6698 unsigned int CurrentIndex
, NextIndex
;
6699 unsigned short status
;
6700 DMABUFFERENTRY
*pBufEntry
;
6701 unsigned int framesize
= 0;
6702 bool ReturnCode
= false;
6703 unsigned long flags
;
6704 struct tty_struct
*tty
= info
->port
.tty
;
6707 * current_rx_buffer points to the 1st buffer of the next available
6708 * receive frame. The status field is set by the 16C32 after
6709 * completing a receive frame. If the status field of this buffer
6710 * is zero, either the USC is still filling this buffer or this
6711 * is one of a series of buffers making up a received frame.
6713 * If the count field of this buffer is zero, the USC is either
6714 * using this buffer or has used this buffer. Look at the count
6715 * field of the next buffer. If that next buffer's count is
6716 * non-zero, the USC is still actively using the current buffer.
6717 * Otherwise, if the next buffer's count field is zero, the
6718 * current buffer is complete and the USC is using the next
6721 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6723 if ( NextIndex
== info
->rx_buffer_count
)
6726 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6727 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6728 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6730 * Either the status field of this dma buffer is non-zero
6731 * (indicating the last buffer of a receive frame) or the next
6732 * buffer is marked as in use -- implying this buffer is complete
6733 * and an intermediate buffer for this received frame.
6736 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6738 if ( status
& (RXSTATUS_SHORT_FRAME
| RXSTATUS_OVERRUN
|
6739 RXSTATUS_CRC_ERROR
| RXSTATUS_ABORT
) ) {
6740 if ( status
& RXSTATUS_SHORT_FRAME
)
6741 info
->icount
.rxshort
++;
6742 else if ( status
& RXSTATUS_ABORT
)
6743 info
->icount
.rxabort
++;
6744 else if ( status
& RXSTATUS_OVERRUN
)
6745 info
->icount
.rxover
++;
6747 info
->icount
.rxcrc
++;
6751 * A receive frame is available, get frame size and status.
6753 * The frame size is the starting value of the RCC (which was
6754 * set to 0xffff) minus the ending value of the RCC (decremented
6755 * once for each receive character) minus 2 or 4 for the 16-bit
6758 * If the status field is zero, this is an intermediate buffer.
6761 * If the DMA Buffer Entry's Status field is non-zero, the
6762 * receive operation completed normally (ie: DCD dropped). The
6763 * RCC field is valid and holds the received frame size.
6764 * It is possible that the RCC field will be zero on a DMA buffer
6765 * entry with a non-zero status. This can occur if the total
6766 * frame size (number of bytes between the time DCD goes active
6767 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6768 * case the 16C32 has underrun on the RCC count and appears to
6769 * stop updating this counter to let us know the actual received
6770 * frame size. If this happens (non-zero status and zero RCC),
6771 * simply return the entire RxDMA Buffer
6775 * In the event that the final RxDMA Buffer is
6776 * terminated with a non-zero status and the RCC
6777 * field is zero, we interpret this as the RCC
6778 * having underflowed (received frame > 65535 bytes).
6780 * Signal the event to the user by passing back
6781 * a status of RxStatus_CrcError returning the full
6782 * buffer and let the app figure out what data is
6785 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6786 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6788 framesize
= DMABUFFERSIZE
;
6791 framesize
= DMABUFFERSIZE
;
6794 if ( framesize
> DMABUFFERSIZE
) {
6796 * if running in raw sync mode, ISR handler for
6797 * End Of Buffer events terminates all buffers at 4K.
6798 * If this frame size is said to be >4K, get the
6799 * actual number of bytes of the frame in this buffer.
6801 framesize
= framesize
% DMABUFFERSIZE
;
6805 if ( debug_level
>= DEBUG_LEVEL_BH
)
6806 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6807 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6809 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6810 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6811 min_t(int, framesize
, DMABUFFERSIZE
),0);
6814 /* copy dma buffer(s) to contiguous intermediate buffer */
6815 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6817 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6818 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6819 info
->icount
.rxok
++;
6821 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6824 /* Free the buffers used by this frame. */
6825 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6831 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6832 /* The receiver needs to restarted because of
6833 * a receive overflow (buffer or FIFO). If the
6834 * receive buffers are now empty, then restart receiver.
6837 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6838 info
->rx_buffer_list
[CurrentIndex
].count
) {
6839 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6840 usc_start_receiver(info
);
6841 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6847 } /* end of mgsl_get_raw_rx_frame() */
6849 /* mgsl_load_tx_dma_buffer()
6851 * Load the transmit DMA buffer with the specified data.
6855 * info pointer to device extension
6856 * Buffer pointer to buffer containing frame to load
6857 * BufferSize size in bytes of frame in Buffer
6859 * Return Value: None
6861 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6862 const char *Buffer
, unsigned int BufferSize
)
6864 unsigned short Copycount
;
6866 DMABUFFERENTRY
*pBufEntry
;
6868 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6869 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6871 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6872 /* set CMR:13 to start transmit when
6873 * next GoAhead (abort) is received
6875 info
->cmr_value
|= BIT13
;
6878 /* begin loading the frame in the next available tx dma
6879 * buffer, remember it's starting location for setting
6880 * up tx dma operation
6882 i
= info
->current_tx_buffer
;
6883 info
->start_tx_dma_buffer
= i
;
6885 /* Setup the status and RCC (Frame Size) fields of the 1st */
6886 /* buffer entry in the transmit DMA buffer list. */
6888 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
6889 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
6890 info
->tx_buffer_list
[i
].count
= BufferSize
;
6892 /* Copy frame data from 1st source buffer to the DMA buffers. */
6893 /* The frame data may span multiple DMA buffers. */
6895 while( BufferSize
){
6896 /* Get a pointer to next DMA buffer entry. */
6897 pBufEntry
= &info
->tx_buffer_list
[i
++];
6899 if ( i
== info
->tx_buffer_count
)
6902 /* Calculate the number of bytes that can be copied from */
6903 /* the source buffer to this DMA buffer. */
6904 if ( BufferSize
> DMABUFFERSIZE
)
6905 Copycount
= DMABUFFERSIZE
;
6907 Copycount
= BufferSize
;
6909 /* Actually copy data from source buffer to DMA buffer. */
6910 /* Also set the data count for this individual DMA buffer. */
6911 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6912 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
6914 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
6916 pBufEntry
->count
= Copycount
;
6918 /* Advance source pointer and reduce remaining data count. */
6919 Buffer
+= Copycount
;
6920 BufferSize
-= Copycount
;
6922 ++info
->tx_dma_buffers_used
;
6925 /* remember next available tx dma buffer */
6926 info
->current_tx_buffer
= i
;
6928 } /* end of mgsl_load_tx_dma_buffer() */
6931 * mgsl_register_test()
6933 * Performs a register test of the 16C32.
6935 * Arguments: info pointer to device instance data
6936 * Return Value: true if test passed, otherwise false
6938 static bool mgsl_register_test( struct mgsl_struct
*info
)
6940 static unsigned short BitPatterns
[] =
6941 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6942 static unsigned int Patterncount
= ARRAY_SIZE(BitPatterns
);
6945 unsigned long flags
;
6947 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6950 /* Verify the reset state of some registers. */
6952 if ( (usc_InReg( info
, SICR
) != 0) ||
6953 (usc_InReg( info
, IVR
) != 0) ||
6954 (usc_InDmaReg( info
, DIVR
) != 0) ){
6959 /* Write bit patterns to various registers but do it out of */
6960 /* sync, then read back and verify values. */
6962 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
6963 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
6964 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
6965 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
6966 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
6967 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
6968 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
6970 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
6971 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
6972 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
6973 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
6974 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
6975 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
6983 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6987 } /* end of mgsl_register_test() */
6989 /* mgsl_irq_test() Perform interrupt test of the 16C32.
6991 * Arguments: info pointer to device instance data
6992 * Return Value: true if test passed, otherwise false
6994 static bool mgsl_irq_test( struct mgsl_struct
*info
)
6996 unsigned long EndTime
;
6997 unsigned long flags
;
6999 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7003 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7004 * The ISR sets irq_occurred to true.
7007 info
->irq_occurred
= false;
7009 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7010 /* Enable INTEN (Port 6, Bit12) */
7011 /* This connects the IRQ request signal to the ISA bus */
7012 /* on the ISA adapter. This has no effect for the PCI adapter */
7013 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7015 usc_EnableMasterIrqBit(info
);
7016 usc_EnableInterrupts(info
, IO_PIN
);
7017 usc_ClearIrqPendingBits(info
, IO_PIN
);
7019 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7020 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7022 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7025 while( EndTime
-- && !info
->irq_occurred
) {
7026 msleep_interruptible(10);
7029 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7031 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7033 return info
->irq_occurred
;
7035 } /* end of mgsl_irq_test() */
7039 * Perform a DMA test of the 16C32. A small frame is
7040 * transmitted via DMA from a transmit buffer to a receive buffer
7041 * using single buffer DMA mode.
7043 * Arguments: info pointer to device instance data
7044 * Return Value: true if test passed, otherwise false
7046 static bool mgsl_dma_test( struct mgsl_struct
*info
)
7048 unsigned short FifoLevel
;
7049 unsigned long phys_addr
;
7050 unsigned int FrameSize
;
7054 unsigned short status
=0;
7055 unsigned long EndTime
;
7056 unsigned long flags
;
7057 MGSL_PARAMS tmp_params
;
7059 /* save current port options */
7060 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7061 /* load default port options */
7062 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7064 #define TESTFRAMESIZE 40
7066 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7068 /* setup 16C32 for SDLC DMA transfer mode */
7071 usc_set_sdlc_mode(info
);
7072 usc_enable_loopback(info
,1);
7074 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7075 * field of the buffer entry after fetching buffer address. This
7076 * way we can detect a DMA failure for a DMA read (which should be
7077 * non-destructive to system memory) before we try and write to
7078 * memory (where a failure could corrupt system memory).
7081 /* Receive DMA mode Register (RDMR)
7083 * <15..14> 11 DMA mode = Linked List Buffer mode
7084 * <13> 1 RSBinA/L = store Rx status Block in List entry
7085 * <12> 0 1 = Clear count of List Entry after fetching
7086 * <11..10> 00 Address mode = Increment
7087 * <9> 1 Terminate Buffer on RxBound
7088 * <8> 0 Bus Width = 16bits
7089 * <7..0> ? status Bits (write as 0s)
7091 * 1110 0010 0000 0000 = 0xe200
7094 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7096 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7099 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7101 FrameSize
= TESTFRAMESIZE
;
7103 /* setup 1st transmit buffer entry: */
7104 /* with frame size and transmit control word */
7106 info
->tx_buffer_list
[0].count
= FrameSize
;
7107 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7108 info
->tx_buffer_list
[0].status
= 0x4000;
7110 /* build a transmit frame in 1st transmit DMA buffer */
7112 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7113 for (i
= 0; i
< FrameSize
; i
++ )
7116 /* setup 1st receive buffer entry: */
7117 /* clear status, set max receive buffer size */
7119 info
->rx_buffer_list
[0].status
= 0;
7120 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7122 /* zero out the 1st receive buffer */
7124 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7126 /* Set count field of next buffer entries to prevent */
7127 /* 16C32 from using buffers after the 1st one. */
7129 info
->tx_buffer_list
[1].count
= 0;
7130 info
->rx_buffer_list
[1].count
= 0;
7133 /***************************/
7134 /* Program 16C32 receiver. */
7135 /***************************/
7137 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7139 /* setup DMA transfers */
7140 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7142 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7143 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7144 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7145 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7147 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7148 usc_InDmaReg( info
, RDMR
);
7149 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7151 /* Enable Receiver (RMR <1..0> = 10) */
7152 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7154 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7157 /*************************************************************/
7158 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7159 /*************************************************************/
7161 /* Wait 100ms for interrupt. */
7162 EndTime
= jiffies
+ msecs_to_jiffies(100);
7165 if (time_after(jiffies
, EndTime
)) {
7170 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7171 status
= usc_InDmaReg( info
, RDMR
);
7172 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7174 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7175 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7176 /* BUSY (BIT 5) is active (channel still active). */
7177 /* This means the buffer entry read has completed. */
7183 /******************************/
7184 /* Program 16C32 transmitter. */
7185 /******************************/
7187 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7189 /* Program the Transmit Character Length Register (TCLR) */
7190 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7192 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7193 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7195 /* Program the address of the 1st DMA Buffer Entry in linked list */
7197 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7198 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7199 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7201 /* unlatch Tx status bits, and start transmit channel. */
7203 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7204 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7206 /* wait for DMA controller to fill transmit FIFO */
7208 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7210 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7213 /**********************************/
7214 /* WAIT FOR TRANSMIT FIFO TO FILL */
7215 /**********************************/
7218 EndTime
= jiffies
+ msecs_to_jiffies(100);
7221 if (time_after(jiffies
, EndTime
)) {
7226 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7227 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7228 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7230 if ( FifoLevel
< 16 )
7233 if ( FrameSize
< 32 ) {
7234 /* This frame is smaller than the entire transmit FIFO */
7235 /* so wait for the entire frame to be loaded. */
7236 if ( FifoLevel
<= (32 - FrameSize
) )
7244 /* Enable 16C32 transmitter. */
7246 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7248 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7249 usc_TCmd( info
, TCmd_SendFrame
);
7250 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7252 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7255 /******************************/
7256 /* WAIT FOR TRANSMIT COMPLETE */
7257 /******************************/
7260 EndTime
= jiffies
+ msecs_to_jiffies(100);
7262 /* While timer not expired wait for transmit complete */
7264 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7265 status
= usc_InReg( info
, TCSR
);
7266 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7268 while ( !(status
& (BIT6
| BIT5
| BIT4
| BIT2
| BIT1
)) ) {
7269 if (time_after(jiffies
, EndTime
)) {
7274 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7275 status
= usc_InReg( info
, TCSR
);
7276 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7282 /* CHECK FOR TRANSMIT ERRORS */
7283 if ( status
& (BIT5
| BIT1
) )
7288 /* WAIT FOR RECEIVE COMPLETE */
7291 EndTime
= jiffies
+ msecs_to_jiffies(100);
7293 /* Wait for 16C32 to write receive status to buffer entry. */
7294 status
=info
->rx_buffer_list
[0].status
;
7295 while ( status
== 0 ) {
7296 if (time_after(jiffies
, EndTime
)) {
7300 status
=info
->rx_buffer_list
[0].status
;
7306 /* CHECK FOR RECEIVE ERRORS */
7307 status
= info
->rx_buffer_list
[0].status
;
7309 if ( status
& (BIT8
| BIT3
| BIT1
) ) {
7310 /* receive error has occurred */
7313 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7314 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7320 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7322 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7324 /* restore current port options */
7325 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7329 } /* end of mgsl_dma_test() */
7331 /* mgsl_adapter_test()
7333 * Perform the register, IRQ, and DMA tests for the 16C32.
7335 * Arguments: info pointer to device instance data
7336 * Return Value: 0 if success, otherwise -ENODEV
7338 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7340 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7341 printk( "%s(%d):Testing device %s\n",
7342 __FILE__
,__LINE__
,info
->device_name
);
7344 if ( !mgsl_register_test( info
) ) {
7345 info
->init_error
= DiagStatus_AddressFailure
;
7346 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7347 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7351 if ( !mgsl_irq_test( info
) ) {
7352 info
->init_error
= DiagStatus_IrqFailure
;
7353 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7354 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7358 if ( !mgsl_dma_test( info
) ) {
7359 info
->init_error
= DiagStatus_DmaFailure
;
7360 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7361 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7365 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7366 printk( "%s(%d):device %s passed diagnostics\n",
7367 __FILE__
,__LINE__
,info
->device_name
);
7371 } /* end of mgsl_adapter_test() */
7373 /* mgsl_memory_test()
7375 * Test the shared memory on a PCI adapter.
7377 * Arguments: info pointer to device instance data
7378 * Return Value: true if test passed, otherwise false
7380 static bool mgsl_memory_test( struct mgsl_struct
*info
)
7382 static unsigned long BitPatterns
[] =
7383 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7384 unsigned long Patterncount
= ARRAY_SIZE(BitPatterns
);
7386 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7387 unsigned long * TestAddr
;
7389 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7392 TestAddr
= (unsigned long *)info
->memory_base
;
7394 /* Test data lines with test pattern at one location. */
7396 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7397 *TestAddr
= BitPatterns
[i
];
7398 if ( *TestAddr
!= BitPatterns
[i
] )
7402 /* Test address lines with incrementing pattern over */
7403 /* entire address range. */
7405 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7410 TestAddr
= (unsigned long *)info
->memory_base
;
7412 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7413 if ( *TestAddr
!= i
* 4 )
7418 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7422 } /* End Of mgsl_memory_test() */
7425 /* mgsl_load_pci_memory()
7427 * Load a large block of data into the PCI shared memory.
7428 * Use this instead of memcpy() or memmove() to move data
7429 * into the PCI shared memory.
7433 * This function prevents the PCI9050 interface chip from hogging
7434 * the adapter local bus, which can starve the 16C32 by preventing
7435 * 16C32 bus master cycles.
7437 * The PCI9050 documentation says that the 9050 will always release
7438 * control of the local bus after completing the current read
7439 * or write operation.
7441 * It appears that as long as the PCI9050 write FIFO is full, the
7442 * PCI9050 treats all of the writes as a single burst transaction
7443 * and will not release the bus. This causes DMA latency problems
7444 * at high speeds when copying large data blocks to the shared
7447 * This function in effect, breaks the a large shared memory write
7448 * into multiple transations by interleaving a shared memory read
7449 * which will flush the write FIFO and 'complete' the write
7450 * transation. This allows any pending DMA request to gain control
7451 * of the local bus in a timely fasion.
7455 * TargetPtr pointer to target address in PCI shared memory
7456 * SourcePtr pointer to source buffer for data
7457 * count count in bytes of data to copy
7459 * Return Value: None
7461 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7462 unsigned short count
)
7464 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7465 #define PCI_LOAD_INTERVAL 64
7467 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7468 unsigned short Index
;
7469 unsigned long Dummy
;
7471 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7473 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7474 Dummy
= *((volatile unsigned long *)TargetPtr
);
7475 TargetPtr
+= PCI_LOAD_INTERVAL
;
7476 SourcePtr
+= PCI_LOAD_INTERVAL
;
7479 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7481 } /* End Of mgsl_load_pci_memory() */
7483 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7488 printk("%s tx data:\n",info
->device_name
);
7490 printk("%s rx data:\n",info
->device_name
);
7498 for(i
=0;i
<linecount
;i
++)
7499 printk("%02X ",(unsigned char)data
[i
]);
7502 for(i
=0;i
<linecount
;i
++) {
7503 if (data
[i
]>=040 && data
[i
]<=0176)
7504 printk("%c",data
[i
]);
7513 } /* end of mgsl_trace_block() */
7515 /* mgsl_tx_timeout()
7517 * called when HDLC frame times out
7518 * update stats and do tx completion processing
7520 * Arguments: context pointer to device instance data
7521 * Return Value: None
7523 static void mgsl_tx_timeout(unsigned long context
)
7525 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7526 unsigned long flags
;
7528 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7529 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7530 __FILE__
,__LINE__
,info
->device_name
);
7531 if(info
->tx_active
&&
7532 (info
->params
.mode
== MGSL_MODE_HDLC
||
7533 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7534 info
->icount
.txtimeout
++;
7536 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7537 info
->tx_active
= false;
7538 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7540 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7541 usc_loopmode_cancel_transmit( info
);
7543 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7545 #if SYNCLINK_GENERIC_HDLC
7547 hdlcdev_tx_done(info
);
7550 mgsl_bh_transmit(info
);
7552 } /* end of mgsl_tx_timeout() */
7554 /* signal that there are no more frames to send, so that
7555 * line is 'released' by echoing RxD to TxD when current
7556 * transmission is complete (or immediately if no tx in progress).
7558 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7560 unsigned long flags
;
7562 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7563 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7564 if (info
->tx_active
)
7565 info
->loopmode_send_done_requested
= true;
7567 usc_loopmode_send_done(info
);
7569 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7574 /* release the line by echoing RxD to TxD
7575 * upon completion of a transmit frame
7577 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7579 info
->loopmode_send_done_requested
= false;
7580 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7581 info
->cmr_value
&= ~BIT13
;
7582 usc_OutReg(info
, CMR
, info
->cmr_value
);
7585 /* abort a transmit in progress while in HDLC LoopMode
7587 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7589 /* reset tx dma channel and purge TxFifo */
7590 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7591 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7592 usc_loopmode_send_done( info
);
7595 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7596 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7597 * we must clear CMR:13 to begin repeating TxData to RxData
7599 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7601 info
->loopmode_insert_requested
= true;
7603 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7604 * begin repeating TxData on RxData (complete insertion)
7606 usc_OutReg( info
, RICR
,
7607 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7609 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7610 info
->cmr_value
|= BIT13
;
7611 usc_OutReg(info
, CMR
, info
->cmr_value
);
7614 /* return 1 if station is inserted into the loop, otherwise 0
7616 static int usc_loopmode_active( struct mgsl_struct
* info
)
7618 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7621 #if SYNCLINK_GENERIC_HDLC
7624 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7625 * set encoding and frame check sequence (FCS) options
7627 * dev pointer to network device structure
7628 * encoding serial encoding setting
7629 * parity FCS setting
7631 * returns 0 if success, otherwise error code
7633 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7634 unsigned short parity
)
7636 struct mgsl_struct
*info
= dev_to_port(dev
);
7637 unsigned char new_encoding
;
7638 unsigned short new_crctype
;
7640 /* return error if TTY interface open */
7641 if (info
->port
.count
)
7646 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7647 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7648 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7649 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7650 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7651 default: return -EINVAL
;
7656 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7657 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7658 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7659 default: return -EINVAL
;
7662 info
->params
.encoding
= new_encoding
;
7663 info
->params
.crc_type
= new_crctype
;
7665 /* if network interface up, reprogram hardware */
7667 mgsl_program_hw(info
);
7673 * called by generic HDLC layer to send frame
7675 * skb socket buffer containing HDLC frame
7676 * dev pointer to network device structure
7678 static netdev_tx_t
hdlcdev_xmit(struct sk_buff
*skb
,
7679 struct net_device
*dev
)
7681 struct mgsl_struct
*info
= dev_to_port(dev
);
7682 unsigned long flags
;
7684 if (debug_level
>= DEBUG_LEVEL_INFO
)
7685 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7687 /* stop sending until this frame completes */
7688 netif_stop_queue(dev
);
7690 /* copy data to device buffers */
7691 info
->xmit_cnt
= skb
->len
;
7692 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7694 /* update network statistics */
7695 dev
->stats
.tx_packets
++;
7696 dev
->stats
.tx_bytes
+= skb
->len
;
7698 /* done with socket buffer, so free it */
7701 /* save start time for transmit timeout detection */
7702 dev
->trans_start
= jiffies
;
7704 /* start hardware transmitter if necessary */
7705 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7706 if (!info
->tx_active
)
7707 usc_start_transmitter(info
);
7708 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7710 return NETDEV_TX_OK
;
7714 * called by network layer when interface enabled
7715 * claim resources and initialize hardware
7717 * dev pointer to network device structure
7719 * returns 0 if success, otherwise error code
7721 static int hdlcdev_open(struct net_device
*dev
)
7723 struct mgsl_struct
*info
= dev_to_port(dev
);
7725 unsigned long flags
;
7727 if (debug_level
>= DEBUG_LEVEL_INFO
)
7728 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7730 /* generic HDLC layer open processing */
7731 rc
= hdlc_open(dev
);
7735 /* arbitrate between network and tty opens */
7736 spin_lock_irqsave(&info
->netlock
, flags
);
7737 if (info
->port
.count
!= 0 || info
->netcount
!= 0) {
7738 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7739 spin_unlock_irqrestore(&info
->netlock
, flags
);
7743 spin_unlock_irqrestore(&info
->netlock
, flags
);
7745 /* claim resources and init adapter */
7746 if ((rc
= startup(info
)) != 0) {
7747 spin_lock_irqsave(&info
->netlock
, flags
);
7749 spin_unlock_irqrestore(&info
->netlock
, flags
);
7753 /* assert RTS and DTR, apply hardware settings */
7754 info
->serial_signals
|= SerialSignal_RTS
| SerialSignal_DTR
;
7755 mgsl_program_hw(info
);
7757 /* enable network layer transmit */
7758 dev
->trans_start
= jiffies
;
7759 netif_start_queue(dev
);
7761 /* inform generic HDLC layer of current DCD status */
7762 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7763 usc_get_serial_signals(info
);
7764 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7765 if (info
->serial_signals
& SerialSignal_DCD
)
7766 netif_carrier_on(dev
);
7768 netif_carrier_off(dev
);
7773 * called by network layer when interface is disabled
7774 * shutdown hardware and release resources
7776 * dev pointer to network device structure
7778 * returns 0 if success, otherwise error code
7780 static int hdlcdev_close(struct net_device
*dev
)
7782 struct mgsl_struct
*info
= dev_to_port(dev
);
7783 unsigned long flags
;
7785 if (debug_level
>= DEBUG_LEVEL_INFO
)
7786 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7788 netif_stop_queue(dev
);
7790 /* shutdown adapter and release resources */
7795 spin_lock_irqsave(&info
->netlock
, flags
);
7797 spin_unlock_irqrestore(&info
->netlock
, flags
);
7803 * called by network layer to process IOCTL call to network device
7805 * dev pointer to network device structure
7806 * ifr pointer to network interface request structure
7807 * cmd IOCTL command code
7809 * returns 0 if success, otherwise error code
7811 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7813 const size_t size
= sizeof(sync_serial_settings
);
7814 sync_serial_settings new_line
;
7815 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7816 struct mgsl_struct
*info
= dev_to_port(dev
);
7819 if (debug_level
>= DEBUG_LEVEL_INFO
)
7820 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7822 /* return error if TTY interface open */
7823 if (info
->port
.count
)
7826 if (cmd
!= SIOCWANDEV
)
7827 return hdlc_ioctl(dev
, ifr
, cmd
);
7829 switch(ifr
->ifr_settings
.type
) {
7830 case IF_GET_IFACE
: /* return current sync_serial_settings */
7832 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7833 if (ifr
->ifr_settings
.size
< size
) {
7834 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7838 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7839 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7840 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7841 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7843 memset(&new_line
, 0, sizeof(new_line
));
7845 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7846 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7847 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7848 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7849 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7852 new_line
.clock_rate
= info
->params
.clock_speed
;
7853 new_line
.loopback
= info
->params
.loopback
? 1:0;
7855 if (copy_to_user(line
, &new_line
, size
))
7859 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7861 if(!capable(CAP_NET_ADMIN
))
7863 if (copy_from_user(&new_line
, line
, size
))
7866 switch (new_line
.clock_type
)
7868 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7869 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7870 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7871 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7872 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7873 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7874 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7875 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7876 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
7877 default: return -EINVAL
;
7880 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
7883 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7884 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7885 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7886 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7887 info
->params
.flags
|= flags
;
7889 info
->params
.loopback
= new_line
.loopback
;
7891 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
7892 info
->params
.clock_speed
= new_line
.clock_rate
;
7894 info
->params
.clock_speed
= 0;
7896 /* if network interface up, reprogram hardware */
7898 mgsl_program_hw(info
);
7902 return hdlc_ioctl(dev
, ifr
, cmd
);
7907 * called by network layer when transmit timeout is detected
7909 * dev pointer to network device structure
7911 static void hdlcdev_tx_timeout(struct net_device
*dev
)
7913 struct mgsl_struct
*info
= dev_to_port(dev
);
7914 unsigned long flags
;
7916 if (debug_level
>= DEBUG_LEVEL_INFO
)
7917 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
7919 dev
->stats
.tx_errors
++;
7920 dev
->stats
.tx_aborted_errors
++;
7922 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7923 usc_stop_transmitter(info
);
7924 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7926 netif_wake_queue(dev
);
7930 * called by device driver when transmit completes
7931 * reenable network layer transmit if stopped
7933 * info pointer to device instance information
7935 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
7937 if (netif_queue_stopped(info
->netdev
))
7938 netif_wake_queue(info
->netdev
);
7942 * called by device driver when frame received
7943 * pass frame to network layer
7945 * info pointer to device instance information
7946 * buf pointer to buffer contianing frame data
7947 * size count of data bytes in buf
7949 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
7951 struct sk_buff
*skb
= dev_alloc_skb(size
);
7952 struct net_device
*dev
= info
->netdev
;
7954 if (debug_level
>= DEBUG_LEVEL_INFO
)
7955 printk("hdlcdev_rx(%s)\n", dev
->name
);
7958 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n",
7960 dev
->stats
.rx_dropped
++;
7964 memcpy(skb_put(skb
, size
), buf
, size
);
7966 skb
->protocol
= hdlc_type_trans(skb
, dev
);
7968 dev
->stats
.rx_packets
++;
7969 dev
->stats
.rx_bytes
+= size
;
7974 static const struct net_device_ops hdlcdev_ops
= {
7975 .ndo_open
= hdlcdev_open
,
7976 .ndo_stop
= hdlcdev_close
,
7977 .ndo_change_mtu
= hdlc_change_mtu
,
7978 .ndo_start_xmit
= hdlc_start_xmit
,
7979 .ndo_do_ioctl
= hdlcdev_ioctl
,
7980 .ndo_tx_timeout
= hdlcdev_tx_timeout
,
7984 * called by device driver when adding device instance
7985 * do generic HDLC initialization
7987 * info pointer to device instance information
7989 * returns 0 if success, otherwise error code
7991 static int hdlcdev_init(struct mgsl_struct
*info
)
7994 struct net_device
*dev
;
7997 /* allocate and initialize network and HDLC layer objects */
7999 dev
= alloc_hdlcdev(info
);
8001 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8005 /* for network layer reporting purposes only */
8006 dev
->base_addr
= info
->io_base
;
8007 dev
->irq
= info
->irq_level
;
8008 dev
->dma
= info
->dma_level
;
8010 /* network layer callbacks and settings */
8011 dev
->netdev_ops
= &hdlcdev_ops
;
8012 dev
->watchdog_timeo
= 10 * HZ
;
8013 dev
->tx_queue_len
= 50;
8015 /* generic HDLC layer callbacks and settings */
8016 hdlc
= dev_to_hdlc(dev
);
8017 hdlc
->attach
= hdlcdev_attach
;
8018 hdlc
->xmit
= hdlcdev_xmit
;
8020 /* register objects with HDLC layer */
8021 rc
= register_hdlc_device(dev
);
8023 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8033 * called by device driver when removing device instance
8034 * do generic HDLC cleanup
8036 * info pointer to device instance information
8038 static void hdlcdev_exit(struct mgsl_struct
*info
)
8040 unregister_hdlc_device(info
->netdev
);
8041 free_netdev(info
->netdev
);
8042 info
->netdev
= NULL
;
8045 #endif /* CONFIG_HDLC */
8048 static int synclink_init_one (struct pci_dev
*dev
,
8049 const struct pci_device_id
*ent
)
8051 struct mgsl_struct
*info
;
8053 if (pci_enable_device(dev
)) {
8054 printk("error enabling pci device %p\n", dev
);
8058 info
= mgsl_allocate_device();
8060 printk("can't allocate device instance data.\n");
8064 /* Copy user configuration info to device instance data */
8066 info
->io_base
= pci_resource_start(dev
, 2);
8067 info
->irq_level
= dev
->irq
;
8068 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8070 /* Because veremap only works on page boundaries we must map
8071 * a larger area than is actually implemented for the LCR
8072 * memory range. We map a full page starting at the page boundary.
8074 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8075 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8076 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8078 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8079 info
->io_addr_size
= 8;
8080 info
->irq_flags
= IRQF_SHARED
;
8082 if (dev
->device
== 0x0210) {
8083 /* Version 1 PCI9030 based universal PCI adapter */
8084 info
->misc_ctrl_value
= 0x007c4080;
8085 info
->hw_version
= 1;
8087 /* Version 0 PCI9050 based 5V PCI adapter
8088 * A PCI9050 bug prevents reading LCR registers if
8089 * LCR base address bit 7 is set. Maintain shadow
8090 * value so we can write to LCR misc control reg.
8092 info
->misc_ctrl_value
= 0x087e4546;
8093 info
->hw_version
= 0;
8096 mgsl_add_device(info
);
8101 static void synclink_remove_one (struct pci_dev
*dev
)