2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
74 #define SYNCLINK_GENERIC_HDLC 0
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
82 #include <asm/uaccess.h>
84 static MGSL_PARAMS default_params
= {
85 MGSL_MODE_HDLC
, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE
/* unsigned char parity; */
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
108 #define BUFFERLISTSIZE 4096
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
113 u16 next
; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr
; /* lower 16 bits of buffer addr */
115 u8 buf_base
; /* upper 8 bits of buffer addr */
117 u16 length
; /* length of buffer */
118 u8 status
; /* status of buffer */
120 } SCADESC
, *PSCADESC
;
122 typedef struct _SCADESC_EX
124 /* device driver bookkeeping section */
125 char *virt_addr
; /* virtual address of data buffer */
126 u16 phys_entry
; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX
, *PSCADESC_EX
;
129 /* The queue of BH actions to be performed */
132 #define BH_TRANSMIT 2
135 #define IO_PIN_SHUTDOWN_LIMIT 100
137 struct _input_signal_events
{
149 * Device instance data structure
151 typedef struct _synclinkmp_info
{
152 void *if_ptr
; /* General purpose pointer (used by SPPP) */
154 struct tty_port port
;
156 unsigned short close_delay
;
157 unsigned short closing_wait
; /* time to wait before closing */
159 struct mgsl_icount icount
;
162 int x_char
; /* xon/xoff character */
163 u16 read_status_mask1
; /* break detection (SR1 indications) */
164 u16 read_status_mask2
; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1
; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2
; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf
;
172 wait_queue_head_t status_event_wait_q
;
173 wait_queue_head_t event_wait_q
;
174 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info
*next_device
; /* device list link */
176 struct timer_list status_timer
; /* input signal status check timer */
178 spinlock_t lock
; /* spinlock for synchronizing with ISR */
179 struct work_struct task
; /* task structure for scheduling bh */
181 u32 max_frame_size
; /* as set by device config */
185 bool bh_running
; /* Protection from multiple */
189 int dcd_chkcount
; /* check counts to prevent */
190 int cts_chkcount
; /* too many IRQs if a signal */
191 int dsr_chkcount
; /* is floating */
194 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys
;
197 unsigned int rx_buf_count
; /* count of total allocated Rx buffers */
198 SCADESC
*rx_buf_list
; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex
[SCAMAXDESC
]; /* list of receive buffer entries */
200 unsigned int current_rx_buf
;
202 unsigned int tx_buf_count
; /* count of total allocated Tx buffers */
203 SCADESC
*tx_buf_list
; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex
[SCAMAXDESC
]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf
;
207 unsigned char *tmp_rx_buf
;
208 unsigned int tmp_rx_buf_count
;
217 unsigned char ie0_value
;
218 unsigned char ie1_value
;
219 unsigned char ie2_value
;
220 unsigned char ctrlreg_value
;
221 unsigned char old_signals
;
223 char device_name
[25]; /* device instance name */
229 struct _synclinkmp_info
*port_array
[SCA_MAX_PORTS
];
231 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
233 unsigned int irq_level
; /* interrupt level */
234 unsigned long irq_flags
;
235 bool irq_requested
; /* true if IRQ requested */
237 MGSL_PARAMS params
; /* communications parameters */
239 unsigned char serial_signals
; /* current serial signal states */
241 bool irq_occurred
; /* for diagnostics use */
242 unsigned int init_error
; /* Initialization startup error */
245 unsigned char* memory_base
; /* shared memory address (PCI only) */
246 u32 phys_memory_base
;
247 int shared_mem_requested
;
249 unsigned char* sca_base
; /* HD64570 SCA Memory address */
252 bool sca_base_requested
;
254 unsigned char* lcr_base
; /* local config registers (PCI only) */
257 int lcr_mem_requested
;
259 unsigned char* statctrl_base
; /* status/control register memory */
260 u32 phys_statctrl_base
;
262 bool sca_statctrl_requested
;
265 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
266 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
267 bool drop_rts_on_tx_done
;
269 struct _input_signal_events input_signal_events
;
271 /* SPPP/Cisco HDLC device parts */
275 #if SYNCLINK_GENERIC_HDLC
276 struct net_device
*netdev
;
281 #define MGSL_MAGIC 0x5401
284 * define serial signal status change macros
286 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
287 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
288 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
289 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
291 /* Common Register macros */
310 /* MSCI Register macros */
340 /* Timer Register Macros */
350 /* DMA Controller Register macros */
381 /* combine with timer or DMA register address */
389 /* SCA Command Codes */
392 #define TXENABLE 0x02
393 #define TXDISABLE 0x03
394 #define TXCRCINIT 0x04
395 #define TXCRCEXCL 0x05
399 #define TXBUFCLR 0x09
401 #define RXENABLE 0x12
402 #define RXDISABLE 0x13
403 #define RXCRCINIT 0x14
404 #define RXREJECT 0x15
405 #define SEARCHMP 0x16
406 #define RXCRCEXCL 0x17
407 #define RXCRCCALC 0x18
411 /* DMA command codes */
413 #define FEICLEAR 0x02
447 * Global linked list of SyncLink devices
449 static SLMP_INFO
*synclinkmp_device_list
= NULL
;
450 static int synclinkmp_adapter_count
= -1;
451 static int synclinkmp_device_count
= 0;
454 * Set this param to non-zero to load eax with the
455 * .text section address and breakpoint on module load.
456 * This is useful for use with gdb and add-symbol-file command.
458 static bool break_on_load
= 0;
461 * Driver major number, defaults to zero to get auto
462 * assigned major number. May be forced as module parameter.
464 static int ttymajor
= 0;
467 * Array of user specified options for ISA adapters.
469 static int debug_level
= 0;
470 static int maxframe
[MAX_DEVICES
] = {0,};
472 module_param(break_on_load
, bool, 0);
473 module_param(ttymajor
, int, 0);
474 module_param(debug_level
, int, 0);
475 module_param_array(maxframe
, int, NULL
, 0);
477 static char *driver_name
= "SyncLink MultiPort driver";
478 static char *driver_version
= "$Revision: 4.38 $";
480 static int synclinkmp_init_one(struct pci_dev
*dev
,const struct pci_device_id
*ent
);
481 static void synclinkmp_remove_one(struct pci_dev
*dev
);
483 static struct pci_device_id synclinkmp_pci_tbl
[] = {
484 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_SCA
, PCI_ANY_ID
, PCI_ANY_ID
, },
485 { 0, }, /* terminate list */
487 MODULE_DEVICE_TABLE(pci
, synclinkmp_pci_tbl
);
489 MODULE_LICENSE("GPL");
491 static struct pci_driver synclinkmp_pci_driver
= {
492 .name
= "synclinkmp",
493 .id_table
= synclinkmp_pci_tbl
,
494 .probe
= synclinkmp_init_one
,
495 .remove
= __devexit_p(synclinkmp_remove_one
),
499 static struct tty_driver
*serial_driver
;
501 /* number of characters left in xmit buffer before we ask for more */
502 #define WAKEUP_CHARS 256
507 static int open(struct tty_struct
*tty
, struct file
* filp
);
508 static void close(struct tty_struct
*tty
, struct file
* filp
);
509 static void hangup(struct tty_struct
*tty
);
510 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
);
512 static int write(struct tty_struct
*tty
, const unsigned char *buf
, int count
);
513 static int put_char(struct tty_struct
*tty
, unsigned char ch
);
514 static void send_xchar(struct tty_struct
*tty
, char ch
);
515 static void wait_until_sent(struct tty_struct
*tty
, int timeout
);
516 static int write_room(struct tty_struct
*tty
);
517 static void flush_chars(struct tty_struct
*tty
);
518 static void flush_buffer(struct tty_struct
*tty
);
519 static void tx_hold(struct tty_struct
*tty
);
520 static void tx_release(struct tty_struct
*tty
);
522 static int ioctl(struct tty_struct
*tty
, unsigned int cmd
, unsigned long arg
);
523 static int chars_in_buffer(struct tty_struct
*tty
);
524 static void throttle(struct tty_struct
* tty
);
525 static void unthrottle(struct tty_struct
* tty
);
526 static int set_break(struct tty_struct
*tty
, int break_state
);
528 #if SYNCLINK_GENERIC_HDLC
529 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
530 static void hdlcdev_tx_done(SLMP_INFO
*info
);
531 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
);
532 static int hdlcdev_init(SLMP_INFO
*info
);
533 static void hdlcdev_exit(SLMP_INFO
*info
);
538 static int get_stats(SLMP_INFO
*info
, struct mgsl_icount __user
*user_icount
);
539 static int get_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
540 static int set_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
541 static int get_txidle(SLMP_INFO
*info
, int __user
*idle_mode
);
542 static int set_txidle(SLMP_INFO
*info
, int idle_mode
);
543 static int tx_enable(SLMP_INFO
*info
, int enable
);
544 static int tx_abort(SLMP_INFO
*info
);
545 static int rx_enable(SLMP_INFO
*info
, int enable
);
546 static int modem_input_wait(SLMP_INFO
*info
,int arg
);
547 static int wait_mgsl_event(SLMP_INFO
*info
, int __user
*mask_ptr
);
548 static int tiocmget(struct tty_struct
*tty
);
549 static int tiocmset(struct tty_struct
*tty
,
550 unsigned int set
, unsigned int clear
);
551 static int set_break(struct tty_struct
*tty
, int break_state
);
553 static void add_device(SLMP_INFO
*info
);
554 static void device_init(int adapter_num
, struct pci_dev
*pdev
);
555 static int claim_resources(SLMP_INFO
*info
);
556 static void release_resources(SLMP_INFO
*info
);
558 static int startup(SLMP_INFO
*info
);
559 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,SLMP_INFO
*info
);
560 static int carrier_raised(struct tty_port
*port
);
561 static void shutdown(SLMP_INFO
*info
);
562 static void program_hw(SLMP_INFO
*info
);
563 static void change_params(SLMP_INFO
*info
);
565 static bool init_adapter(SLMP_INFO
*info
);
566 static bool register_test(SLMP_INFO
*info
);
567 static bool irq_test(SLMP_INFO
*info
);
568 static bool loopback_test(SLMP_INFO
*info
);
569 static int adapter_test(SLMP_INFO
*info
);
570 static bool memory_test(SLMP_INFO
*info
);
572 static void reset_adapter(SLMP_INFO
*info
);
573 static void reset_port(SLMP_INFO
*info
);
574 static void async_mode(SLMP_INFO
*info
);
575 static void hdlc_mode(SLMP_INFO
*info
);
577 static void rx_stop(SLMP_INFO
*info
);
578 static void rx_start(SLMP_INFO
*info
);
579 static void rx_reset_buffers(SLMP_INFO
*info
);
580 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
);
581 static bool rx_get_frame(SLMP_INFO
*info
);
583 static void tx_start(SLMP_INFO
*info
);
584 static void tx_stop(SLMP_INFO
*info
);
585 static void tx_load_fifo(SLMP_INFO
*info
);
586 static void tx_set_idle(SLMP_INFO
*info
);
587 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
);
589 static void get_signals(SLMP_INFO
*info
);
590 static void set_signals(SLMP_INFO
*info
);
591 static void enable_loopback(SLMP_INFO
*info
, int enable
);
592 static void set_rate(SLMP_INFO
*info
, u32 data_rate
);
594 static int bh_action(SLMP_INFO
*info
);
595 static void bh_handler(struct work_struct
*work
);
596 static void bh_receive(SLMP_INFO
*info
);
597 static void bh_transmit(SLMP_INFO
*info
);
598 static void bh_status(SLMP_INFO
*info
);
599 static void isr_timer(SLMP_INFO
*info
);
600 static void isr_rxint(SLMP_INFO
*info
);
601 static void isr_rxrdy(SLMP_INFO
*info
);
602 static void isr_txint(SLMP_INFO
*info
);
603 static void isr_txrdy(SLMP_INFO
*info
);
604 static void isr_rxdmaok(SLMP_INFO
*info
);
605 static void isr_rxdmaerror(SLMP_INFO
*info
);
606 static void isr_txdmaok(SLMP_INFO
*info
);
607 static void isr_txdmaerror(SLMP_INFO
*info
);
608 static void isr_io_pin(SLMP_INFO
*info
, u16 status
);
610 static int alloc_dma_bufs(SLMP_INFO
*info
);
611 static void free_dma_bufs(SLMP_INFO
*info
);
612 static int alloc_buf_list(SLMP_INFO
*info
);
613 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*list
, SCADESC_EX
*list_ex
,int count
);
614 static int alloc_tmp_rx_buf(SLMP_INFO
*info
);
615 static void free_tmp_rx_buf(SLMP_INFO
*info
);
617 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
);
618 static void trace_block(SLMP_INFO
*info
, const char* data
, int count
, int xmit
);
619 static void tx_timeout(unsigned long context
);
620 static void status_timeout(unsigned long context
);
622 static unsigned char read_reg(SLMP_INFO
*info
, unsigned char addr
);
623 static void write_reg(SLMP_INFO
*info
, unsigned char addr
, unsigned char val
);
624 static u16
read_reg16(SLMP_INFO
*info
, unsigned char addr
);
625 static void write_reg16(SLMP_INFO
*info
, unsigned char addr
, u16 val
);
626 static unsigned char read_status_reg(SLMP_INFO
* info
);
627 static void write_control_reg(SLMP_INFO
* info
);
630 static unsigned char rx_active_fifo_level
= 16; // rx request FIFO activation level in bytes
631 static unsigned char tx_active_fifo_level
= 16; // tx request FIFO activation level in bytes
632 static unsigned char tx_negate_fifo_level
= 32; // tx request FIFO negation level in bytes
634 static u32 misc_ctrl_value
= 0x007e4040;
635 static u32 lcr1_brdr_value
= 0x00800028;
637 static u32 read_ahead_count
= 8;
639 /* DPCR, DMA Priority Control
641 * 07..05 Not used, must be 0
642 * 04 BRC, bus release condition: 0=all transfers complete
643 * 1=release after 1 xfer on all channels
644 * 03 CCC, channel change condition: 0=every cycle
645 * 1=after each channel completes all xfers
646 * 02..00 PR<2..0>, priority 100=round robin
650 static unsigned char dma_priority
= 0x04;
652 // Number of bytes that can be written to shared RAM
653 // in a single write operation
654 static u32 sca_pci_load_interval
= 64;
657 * 1st function defined in .text section. Calling this function in
658 * init_module() followed by a breakpoint allows a remote debugger
659 * (gdb) to get the .text address for the add-symbol-file command.
660 * This allows remote debugging of dynamically loadable modules.
662 static void* synclinkmp_get_text_ptr(void);
663 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr
;}
665 static inline int sanity_check(SLMP_INFO
*info
,
666 char *name
, const char *routine
)
669 static const char *badmagic
=
670 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
671 static const char *badinfo
=
672 "Warning: null synclinkmp_struct for (%s) in %s\n";
675 printk(badinfo
, name
, routine
);
678 if (info
->magic
!= MGSL_MAGIC
) {
679 printk(badmagic
, name
, routine
);
690 * line discipline callback wrappers
692 * The wrappers maintain line discipline references
693 * while calling into the line discipline.
695 * ldisc_receive_buf - pass receive data to line discipline
698 static void ldisc_receive_buf(struct tty_struct
*tty
,
699 const __u8
*data
, char *flags
, int count
)
701 struct tty_ldisc
*ld
;
704 ld
= tty_ldisc_ref(tty
);
706 if (ld
->ops
->receive_buf
)
707 ld
->ops
->receive_buf(tty
, data
, flags
, count
);
714 static int install(struct tty_driver
*driver
, struct tty_struct
*tty
)
717 int line
= tty
->index
;
719 if (line
>= synclinkmp_device_count
) {
720 printk("%s(%d): open with invalid line #%d.\n",
721 __FILE__
,__LINE__
,line
);
725 info
= synclinkmp_device_list
;
726 while (info
&& info
->line
!= line
)
727 info
= info
->next_device
;
728 if (sanity_check(info
, tty
->name
, "open"))
730 if (info
->init_error
) {
731 printk("%s(%d):%s device is not allocated, init error=%d\n",
732 __FILE__
, __LINE__
, info
->device_name
,
737 tty
->driver_data
= info
;
739 return tty_port_install(&info
->port
, driver
, tty
);
742 /* Called when a port is opened. Init and enable port.
744 static int open(struct tty_struct
*tty
, struct file
*filp
)
746 SLMP_INFO
*info
= tty
->driver_data
;
750 info
->port
.tty
= tty
;
752 if (debug_level
>= DEBUG_LEVEL_INFO
)
753 printk("%s(%d):%s open(), old ref count = %d\n",
754 __FILE__
,__LINE__
,tty
->driver
->name
, info
->port
.count
);
756 /* If port is closing, signal caller to try again */
757 if (tty_hung_up_p(filp
) || info
->port
.flags
& ASYNC_CLOSING
){
758 if (info
->port
.flags
& ASYNC_CLOSING
)
759 interruptible_sleep_on(&info
->port
.close_wait
);
760 retval
= ((info
->port
.flags
& ASYNC_HUP_NOTIFY
) ?
761 -EAGAIN
: -ERESTARTSYS
);
765 info
->port
.tty
->low_latency
= (info
->port
.flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
767 spin_lock_irqsave(&info
->netlock
, flags
);
768 if (info
->netcount
) {
770 spin_unlock_irqrestore(&info
->netlock
, flags
);
774 spin_unlock_irqrestore(&info
->netlock
, flags
);
776 if (info
->port
.count
== 1) {
777 /* 1st open on this device, init hardware */
778 retval
= startup(info
);
783 retval
= block_til_ready(tty
, filp
, info
);
785 if (debug_level
>= DEBUG_LEVEL_INFO
)
786 printk("%s(%d):%s block_til_ready() returned %d\n",
787 __FILE__
,__LINE__
, info
->device_name
, retval
);
791 if (debug_level
>= DEBUG_LEVEL_INFO
)
792 printk("%s(%d):%s open() success\n",
793 __FILE__
,__LINE__
, info
->device_name
);
799 info
->port
.tty
= NULL
; /* tty layer will release tty struct */
807 /* Called when port is closed. Wait for remaining data to be
808 * sent. Disable port and free resources.
810 static void close(struct tty_struct
*tty
, struct file
*filp
)
812 SLMP_INFO
* info
= tty
->driver_data
;
814 if (sanity_check(info
, tty
->name
, "close"))
817 if (debug_level
>= DEBUG_LEVEL_INFO
)
818 printk("%s(%d):%s close() entry, count=%d\n",
819 __FILE__
,__LINE__
, info
->device_name
, info
->port
.count
);
821 if (tty_port_close_start(&info
->port
, tty
, filp
) == 0)
824 mutex_lock(&info
->port
.mutex
);
825 if (info
->port
.flags
& ASYNC_INITIALIZED
)
826 wait_until_sent(tty
, info
->timeout
);
829 tty_ldisc_flush(tty
);
831 mutex_unlock(&info
->port
.mutex
);
833 tty_port_close_end(&info
->port
, tty
);
834 info
->port
.tty
= NULL
;
836 if (debug_level
>= DEBUG_LEVEL_INFO
)
837 printk("%s(%d):%s close() exit, count=%d\n", __FILE__
,__LINE__
,
838 tty
->driver
->name
, info
->port
.count
);
841 /* Called by tty_hangup() when a hangup is signaled.
842 * This is the same as closing all open descriptors for the port.
844 static void hangup(struct tty_struct
*tty
)
846 SLMP_INFO
*info
= tty
->driver_data
;
849 if (debug_level
>= DEBUG_LEVEL_INFO
)
850 printk("%s(%d):%s hangup()\n",
851 __FILE__
,__LINE__
, info
->device_name
);
853 if (sanity_check(info
, tty
->name
, "hangup"))
856 mutex_lock(&info
->port
.mutex
);
860 spin_lock_irqsave(&info
->port
.lock
, flags
);
861 info
->port
.count
= 0;
862 info
->port
.flags
&= ~ASYNC_NORMAL_ACTIVE
;
863 info
->port
.tty
= NULL
;
864 spin_unlock_irqrestore(&info
->port
.lock
, flags
);
865 mutex_unlock(&info
->port
.mutex
);
867 wake_up_interruptible(&info
->port
.open_wait
);
870 /* Set new termios settings
872 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
874 SLMP_INFO
*info
= tty
->driver_data
;
877 if (debug_level
>= DEBUG_LEVEL_INFO
)
878 printk("%s(%d):%s set_termios()\n", __FILE__
,__LINE__
,
883 /* Handle transition to B0 status */
884 if (old_termios
->c_cflag
& CBAUD
&&
885 !(tty
->termios
.c_cflag
& CBAUD
)) {
886 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
887 spin_lock_irqsave(&info
->lock
,flags
);
889 spin_unlock_irqrestore(&info
->lock
,flags
);
892 /* Handle transition away from B0 status */
893 if (!(old_termios
->c_cflag
& CBAUD
) &&
894 tty
->termios
.c_cflag
& CBAUD
) {
895 info
->serial_signals
|= SerialSignal_DTR
;
896 if (!(tty
->termios
.c_cflag
& CRTSCTS
) ||
897 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
898 info
->serial_signals
|= SerialSignal_RTS
;
900 spin_lock_irqsave(&info
->lock
,flags
);
902 spin_unlock_irqrestore(&info
->lock
,flags
);
905 /* Handle turning off CRTSCTS */
906 if (old_termios
->c_cflag
& CRTSCTS
&&
907 !(tty
->termios
.c_cflag
& CRTSCTS
)) {
913 /* Send a block of data
917 * tty pointer to tty information structure
918 * buf pointer to buffer containing send data
919 * count size of send data in bytes
921 * Return Value: number of characters written
923 static int write(struct tty_struct
*tty
,
924 const unsigned char *buf
, int count
)
927 SLMP_INFO
*info
= tty
->driver_data
;
930 if (debug_level
>= DEBUG_LEVEL_INFO
)
931 printk("%s(%d):%s write() count=%d\n",
932 __FILE__
,__LINE__
,info
->device_name
,count
);
934 if (sanity_check(info
, tty
->name
, "write"))
940 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
941 if (count
> info
->max_frame_size
) {
947 if (info
->tx_count
) {
948 /* send accumulated data from send_char() calls */
949 /* as frame and wait before accepting more data. */
950 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
953 ret
= info
->tx_count
= count
;
954 tx_load_dma_buffer(info
, buf
, count
);
959 c
= min_t(int, count
,
960 min(info
->max_frame_size
- info
->tx_count
- 1,
961 info
->max_frame_size
- info
->tx_put
));
965 memcpy(info
->tx_buf
+ info
->tx_put
, buf
, c
);
967 spin_lock_irqsave(&info
->lock
,flags
);
969 if (info
->tx_put
>= info
->max_frame_size
)
970 info
->tx_put
-= info
->max_frame_size
;
972 spin_unlock_irqrestore(&info
->lock
,flags
);
979 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
981 ret
= info
->tx_count
= 0;
984 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
987 if (info
->tx_count
&& !tty
->stopped
&& !tty
->hw_stopped
) {
988 spin_lock_irqsave(&info
->lock
,flags
);
989 if (!info
->tx_active
)
991 spin_unlock_irqrestore(&info
->lock
,flags
);
995 if (debug_level
>= DEBUG_LEVEL_INFO
)
996 printk( "%s(%d):%s write() returning=%d\n",
997 __FILE__
,__LINE__
,info
->device_name
,ret
);
1001 /* Add a character to the transmit buffer.
1003 static int put_char(struct tty_struct
*tty
, unsigned char ch
)
1005 SLMP_INFO
*info
= tty
->driver_data
;
1006 unsigned long flags
;
1009 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
1010 printk( "%s(%d):%s put_char(%d)\n",
1011 __FILE__
,__LINE__
,info
->device_name
,ch
);
1014 if (sanity_check(info
, tty
->name
, "put_char"))
1020 spin_lock_irqsave(&info
->lock
,flags
);
1022 if ( (info
->params
.mode
!= MGSL_MODE_HDLC
) ||
1023 !info
->tx_active
) {
1025 if (info
->tx_count
< info
->max_frame_size
- 1) {
1026 info
->tx_buf
[info
->tx_put
++] = ch
;
1027 if (info
->tx_put
>= info
->max_frame_size
)
1028 info
->tx_put
-= info
->max_frame_size
;
1034 spin_unlock_irqrestore(&info
->lock
,flags
);
1038 /* Send a high-priority XON/XOFF character
1040 static void send_xchar(struct tty_struct
*tty
, char ch
)
1042 SLMP_INFO
*info
= tty
->driver_data
;
1043 unsigned long flags
;
1045 if (debug_level
>= DEBUG_LEVEL_INFO
)
1046 printk("%s(%d):%s send_xchar(%d)\n",
1047 __FILE__
,__LINE__
, info
->device_name
, ch
);
1049 if (sanity_check(info
, tty
->name
, "send_xchar"))
1054 /* Make sure transmit interrupts are on */
1055 spin_lock_irqsave(&info
->lock
,flags
);
1056 if (!info
->tx_enabled
)
1058 spin_unlock_irqrestore(&info
->lock
,flags
);
1062 /* Wait until the transmitter is empty.
1064 static void wait_until_sent(struct tty_struct
*tty
, int timeout
)
1066 SLMP_INFO
* info
= tty
->driver_data
;
1067 unsigned long orig_jiffies
, char_time
;
1072 if (debug_level
>= DEBUG_LEVEL_INFO
)
1073 printk("%s(%d):%s wait_until_sent() entry\n",
1074 __FILE__
,__LINE__
, info
->device_name
);
1076 if (sanity_check(info
, tty
->name
, "wait_until_sent"))
1079 if (!test_bit(ASYNCB_INITIALIZED
, &info
->port
.flags
))
1082 orig_jiffies
= jiffies
;
1084 /* Set check interval to 1/5 of estimated time to
1085 * send a character, and make it at least 1. The check
1086 * interval should also be less than the timeout.
1087 * Note: use tight timings here to satisfy the NIST-PCTS.
1090 if ( info
->params
.data_rate
) {
1091 char_time
= info
->timeout
/(32 * 5);
1098 char_time
= min_t(unsigned long, char_time
, timeout
);
1100 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
1101 while (info
->tx_active
) {
1102 msleep_interruptible(jiffies_to_msecs(char_time
));
1103 if (signal_pending(current
))
1105 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1110 * TODO: determine if there is something similar to USC16C32
1111 * TXSTATUS_ALL_SENT status
1113 while ( info
->tx_active
&& info
->tx_enabled
) {
1114 msleep_interruptible(jiffies_to_msecs(char_time
));
1115 if (signal_pending(current
))
1117 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1123 if (debug_level
>= DEBUG_LEVEL_INFO
)
1124 printk("%s(%d):%s wait_until_sent() exit\n",
1125 __FILE__
,__LINE__
, info
->device_name
);
1128 /* Return the count of free bytes in transmit buffer
1130 static int write_room(struct tty_struct
*tty
)
1132 SLMP_INFO
*info
= tty
->driver_data
;
1135 if (sanity_check(info
, tty
->name
, "write_room"))
1138 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1139 ret
= (info
->tx_active
) ? 0 : HDLC_MAX_FRAME_SIZE
;
1141 ret
= info
->max_frame_size
- info
->tx_count
- 1;
1146 if (debug_level
>= DEBUG_LEVEL_INFO
)
1147 printk("%s(%d):%s write_room()=%d\n",
1148 __FILE__
, __LINE__
, info
->device_name
, ret
);
1153 /* enable transmitter and send remaining buffered characters
1155 static void flush_chars(struct tty_struct
*tty
)
1157 SLMP_INFO
*info
= tty
->driver_data
;
1158 unsigned long flags
;
1160 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1161 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1162 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
1164 if (sanity_check(info
, tty
->name
, "flush_chars"))
1167 if (info
->tx_count
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
1171 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1172 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1173 __FILE__
,__LINE__
,info
->device_name
);
1175 spin_lock_irqsave(&info
->lock
,flags
);
1177 if (!info
->tx_active
) {
1178 if ( (info
->params
.mode
== MGSL_MODE_HDLC
) &&
1180 /* operating in synchronous (frame oriented) mode */
1181 /* copy data from circular tx_buf to */
1182 /* transmit DMA buffer. */
1183 tx_load_dma_buffer(info
,
1184 info
->tx_buf
,info
->tx_count
);
1189 spin_unlock_irqrestore(&info
->lock
,flags
);
1192 /* Discard all data in the send buffer
1194 static void flush_buffer(struct tty_struct
*tty
)
1196 SLMP_INFO
*info
= tty
->driver_data
;
1197 unsigned long flags
;
1199 if (debug_level
>= DEBUG_LEVEL_INFO
)
1200 printk("%s(%d):%s flush_buffer() entry\n",
1201 __FILE__
,__LINE__
, info
->device_name
);
1203 if (sanity_check(info
, tty
->name
, "flush_buffer"))
1206 spin_lock_irqsave(&info
->lock
,flags
);
1207 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
1208 del_timer(&info
->tx_timer
);
1209 spin_unlock_irqrestore(&info
->lock
,flags
);
1214 /* throttle (stop) transmitter
1216 static void tx_hold(struct tty_struct
*tty
)
1218 SLMP_INFO
*info
= tty
->driver_data
;
1219 unsigned long flags
;
1221 if (sanity_check(info
, tty
->name
, "tx_hold"))
1224 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1225 printk("%s(%d):%s tx_hold()\n",
1226 __FILE__
,__LINE__
,info
->device_name
);
1228 spin_lock_irqsave(&info
->lock
,flags
);
1229 if (info
->tx_enabled
)
1231 spin_unlock_irqrestore(&info
->lock
,flags
);
1234 /* release (start) transmitter
1236 static void tx_release(struct tty_struct
*tty
)
1238 SLMP_INFO
*info
= tty
->driver_data
;
1239 unsigned long flags
;
1241 if (sanity_check(info
, tty
->name
, "tx_release"))
1244 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1245 printk("%s(%d):%s tx_release()\n",
1246 __FILE__
,__LINE__
,info
->device_name
);
1248 spin_lock_irqsave(&info
->lock
,flags
);
1249 if (!info
->tx_enabled
)
1251 spin_unlock_irqrestore(&info
->lock
,flags
);
1254 /* Service an IOCTL request
1258 * tty pointer to tty instance data
1259 * cmd IOCTL command code
1260 * arg command argument/context
1262 * Return Value: 0 if success, otherwise error code
1264 static int ioctl(struct tty_struct
*tty
,
1265 unsigned int cmd
, unsigned long arg
)
1267 SLMP_INFO
*info
= tty
->driver_data
;
1268 void __user
*argp
= (void __user
*)arg
;
1270 if (debug_level
>= DEBUG_LEVEL_INFO
)
1271 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__
,__LINE__
,
1272 info
->device_name
, cmd
);
1274 if (sanity_check(info
, tty
->name
, "ioctl"))
1277 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
1278 (cmd
!= TIOCMIWAIT
)) {
1279 if (tty
->flags
& (1 << TTY_IO_ERROR
))
1284 case MGSL_IOCGPARAMS
:
1285 return get_params(info
, argp
);
1286 case MGSL_IOCSPARAMS
:
1287 return set_params(info
, argp
);
1288 case MGSL_IOCGTXIDLE
:
1289 return get_txidle(info
, argp
);
1290 case MGSL_IOCSTXIDLE
:
1291 return set_txidle(info
, (int)arg
);
1292 case MGSL_IOCTXENABLE
:
1293 return tx_enable(info
, (int)arg
);
1294 case MGSL_IOCRXENABLE
:
1295 return rx_enable(info
, (int)arg
);
1296 case MGSL_IOCTXABORT
:
1297 return tx_abort(info
);
1298 case MGSL_IOCGSTATS
:
1299 return get_stats(info
, argp
);
1300 case MGSL_IOCWAITEVENT
:
1301 return wait_mgsl_event(info
, argp
);
1302 case MGSL_IOCLOOPTXDONE
:
1303 return 0; // TODO: Not supported, need to document
1304 /* Wait for modem input (DCD,RI,DSR,CTS) change
1305 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1308 return modem_input_wait(info
,(int)arg
);
1311 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1312 * Return: write counters to the user passed counter struct
1313 * NB: both 1->0 and 0->1 transitions are counted except for
1314 * RI where only 0->1 is counted.
1317 return -ENOIOCTLCMD
;
1322 static int get_icount(struct tty_struct
*tty
,
1323 struct serial_icounter_struct
*icount
)
1325 SLMP_INFO
*info
= tty
->driver_data
;
1326 struct mgsl_icount cnow
; /* kernel counter temps */
1327 unsigned long flags
;
1329 spin_lock_irqsave(&info
->lock
,flags
);
1330 cnow
= info
->icount
;
1331 spin_unlock_irqrestore(&info
->lock
,flags
);
1333 icount
->cts
= cnow
.cts
;
1334 icount
->dsr
= cnow
.dsr
;
1335 icount
->rng
= cnow
.rng
;
1336 icount
->dcd
= cnow
.dcd
;
1337 icount
->rx
= cnow
.rx
;
1338 icount
->tx
= cnow
.tx
;
1339 icount
->frame
= cnow
.frame
;
1340 icount
->overrun
= cnow
.overrun
;
1341 icount
->parity
= cnow
.parity
;
1342 icount
->brk
= cnow
.brk
;
1343 icount
->buf_overrun
= cnow
.buf_overrun
;
1349 * /proc fs routines....
1352 static inline void line_info(struct seq_file
*m
, SLMP_INFO
*info
)
1355 unsigned long flags
;
1357 seq_printf(m
, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1358 "\tIRQ=%d MaxFrameSize=%u\n",
1360 info
->phys_sca_base
,
1361 info
->phys_memory_base
,
1362 info
->phys_statctrl_base
,
1363 info
->phys_lcr_base
,
1365 info
->max_frame_size
);
1367 /* output current serial signal states */
1368 spin_lock_irqsave(&info
->lock
,flags
);
1370 spin_unlock_irqrestore(&info
->lock
,flags
);
1374 if (info
->serial_signals
& SerialSignal_RTS
)
1375 strcat(stat_buf
, "|RTS");
1376 if (info
->serial_signals
& SerialSignal_CTS
)
1377 strcat(stat_buf
, "|CTS");
1378 if (info
->serial_signals
& SerialSignal_DTR
)
1379 strcat(stat_buf
, "|DTR");
1380 if (info
->serial_signals
& SerialSignal_DSR
)
1381 strcat(stat_buf
, "|DSR");
1382 if (info
->serial_signals
& SerialSignal_DCD
)
1383 strcat(stat_buf
, "|CD");
1384 if (info
->serial_signals
& SerialSignal_RI
)
1385 strcat(stat_buf
, "|RI");
1387 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1388 seq_printf(m
, "\tHDLC txok:%d rxok:%d",
1389 info
->icount
.txok
, info
->icount
.rxok
);
1390 if (info
->icount
.txunder
)
1391 seq_printf(m
, " txunder:%d", info
->icount
.txunder
);
1392 if (info
->icount
.txabort
)
1393 seq_printf(m
, " txabort:%d", info
->icount
.txabort
);
1394 if (info
->icount
.rxshort
)
1395 seq_printf(m
, " rxshort:%d", info
->icount
.rxshort
);
1396 if (info
->icount
.rxlong
)
1397 seq_printf(m
, " rxlong:%d", info
->icount
.rxlong
);
1398 if (info
->icount
.rxover
)
1399 seq_printf(m
, " rxover:%d", info
->icount
.rxover
);
1400 if (info
->icount
.rxcrc
)
1401 seq_printf(m
, " rxlong:%d", info
->icount
.rxcrc
);
1403 seq_printf(m
, "\tASYNC tx:%d rx:%d",
1404 info
->icount
.tx
, info
->icount
.rx
);
1405 if (info
->icount
.frame
)
1406 seq_printf(m
, " fe:%d", info
->icount
.frame
);
1407 if (info
->icount
.parity
)
1408 seq_printf(m
, " pe:%d", info
->icount
.parity
);
1409 if (info
->icount
.brk
)
1410 seq_printf(m
, " brk:%d", info
->icount
.brk
);
1411 if (info
->icount
.overrun
)
1412 seq_printf(m
, " oe:%d", info
->icount
.overrun
);
1415 /* Append serial signal status to end */
1416 seq_printf(m
, " %s\n", stat_buf
+1);
1418 seq_printf(m
, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1419 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
1423 /* Called to print information about devices
1425 static int synclinkmp_proc_show(struct seq_file
*m
, void *v
)
1429 seq_printf(m
, "synclinkmp driver:%s\n", driver_version
);
1431 info
= synclinkmp_device_list
;
1434 info
= info
->next_device
;
1439 static int synclinkmp_proc_open(struct inode
*inode
, struct file
*file
)
1441 return single_open(file
, synclinkmp_proc_show
, NULL
);
1444 static const struct file_operations synclinkmp_proc_fops
= {
1445 .owner
= THIS_MODULE
,
1446 .open
= synclinkmp_proc_open
,
1448 .llseek
= seq_lseek
,
1449 .release
= single_release
,
1452 /* Return the count of bytes in transmit buffer
1454 static int chars_in_buffer(struct tty_struct
*tty
)
1456 SLMP_INFO
*info
= tty
->driver_data
;
1458 if (sanity_check(info
, tty
->name
, "chars_in_buffer"))
1461 if (debug_level
>= DEBUG_LEVEL_INFO
)
1462 printk("%s(%d):%s chars_in_buffer()=%d\n",
1463 __FILE__
, __LINE__
, info
->device_name
, info
->tx_count
);
1465 return info
->tx_count
;
1468 /* Signal remote device to throttle send data (our receive data)
1470 static void throttle(struct tty_struct
* tty
)
1472 SLMP_INFO
*info
= tty
->driver_data
;
1473 unsigned long flags
;
1475 if (debug_level
>= DEBUG_LEVEL_INFO
)
1476 printk("%s(%d):%s throttle() entry\n",
1477 __FILE__
,__LINE__
, info
->device_name
);
1479 if (sanity_check(info
, tty
->name
, "throttle"))
1483 send_xchar(tty
, STOP_CHAR(tty
));
1485 if (tty
->termios
.c_cflag
& CRTSCTS
) {
1486 spin_lock_irqsave(&info
->lock
,flags
);
1487 info
->serial_signals
&= ~SerialSignal_RTS
;
1489 spin_unlock_irqrestore(&info
->lock
,flags
);
1493 /* Signal remote device to stop throttling send data (our receive data)
1495 static void unthrottle(struct tty_struct
* tty
)
1497 SLMP_INFO
*info
= tty
->driver_data
;
1498 unsigned long flags
;
1500 if (debug_level
>= DEBUG_LEVEL_INFO
)
1501 printk("%s(%d):%s unthrottle() entry\n",
1502 __FILE__
,__LINE__
, info
->device_name
);
1504 if (sanity_check(info
, tty
->name
, "unthrottle"))
1511 send_xchar(tty
, START_CHAR(tty
));
1514 if (tty
->termios
.c_cflag
& CRTSCTS
) {
1515 spin_lock_irqsave(&info
->lock
,flags
);
1516 info
->serial_signals
|= SerialSignal_RTS
;
1518 spin_unlock_irqrestore(&info
->lock
,flags
);
1522 /* set or clear transmit break condition
1523 * break_state -1=set break condition, 0=clear
1525 static int set_break(struct tty_struct
*tty
, int break_state
)
1527 unsigned char RegValue
;
1528 SLMP_INFO
* info
= tty
->driver_data
;
1529 unsigned long flags
;
1531 if (debug_level
>= DEBUG_LEVEL_INFO
)
1532 printk("%s(%d):%s set_break(%d)\n",
1533 __FILE__
,__LINE__
, info
->device_name
, break_state
);
1535 if (sanity_check(info
, tty
->name
, "set_break"))
1538 spin_lock_irqsave(&info
->lock
,flags
);
1539 RegValue
= read_reg(info
, CTL
);
1540 if (break_state
== -1)
1544 write_reg(info
, CTL
, RegValue
);
1545 spin_unlock_irqrestore(&info
->lock
,flags
);
1549 #if SYNCLINK_GENERIC_HDLC
1552 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1553 * set encoding and frame check sequence (FCS) options
1555 * dev pointer to network device structure
1556 * encoding serial encoding setting
1557 * parity FCS setting
1559 * returns 0 if success, otherwise error code
1561 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
1562 unsigned short parity
)
1564 SLMP_INFO
*info
= dev_to_port(dev
);
1565 unsigned char new_encoding
;
1566 unsigned short new_crctype
;
1568 /* return error if TTY interface open */
1569 if (info
->port
.count
)
1574 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
1575 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
1576 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
1577 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
1578 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
1579 default: return -EINVAL
;
1584 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
1585 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
1586 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
1587 default: return -EINVAL
;
1590 info
->params
.encoding
= new_encoding
;
1591 info
->params
.crc_type
= new_crctype
;
1593 /* if network interface up, reprogram hardware */
1601 * called by generic HDLC layer to send frame
1603 * skb socket buffer containing HDLC frame
1604 * dev pointer to network device structure
1606 static netdev_tx_t
hdlcdev_xmit(struct sk_buff
*skb
,
1607 struct net_device
*dev
)
1609 SLMP_INFO
*info
= dev_to_port(dev
);
1610 unsigned long flags
;
1612 if (debug_level
>= DEBUG_LEVEL_INFO
)
1613 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
1615 /* stop sending until this frame completes */
1616 netif_stop_queue(dev
);
1618 /* copy data to device buffers */
1619 info
->tx_count
= skb
->len
;
1620 tx_load_dma_buffer(info
, skb
->data
, skb
->len
);
1622 /* update network statistics */
1623 dev
->stats
.tx_packets
++;
1624 dev
->stats
.tx_bytes
+= skb
->len
;
1626 /* done with socket buffer, so free it */
1629 /* save start time for transmit timeout detection */
1630 dev
->trans_start
= jiffies
;
1632 /* start hardware transmitter if necessary */
1633 spin_lock_irqsave(&info
->lock
,flags
);
1634 if (!info
->tx_active
)
1636 spin_unlock_irqrestore(&info
->lock
,flags
);
1638 return NETDEV_TX_OK
;
1642 * called by network layer when interface enabled
1643 * claim resources and initialize hardware
1645 * dev pointer to network device structure
1647 * returns 0 if success, otherwise error code
1649 static int hdlcdev_open(struct net_device
*dev
)
1651 SLMP_INFO
*info
= dev_to_port(dev
);
1653 unsigned long flags
;
1655 if (debug_level
>= DEBUG_LEVEL_INFO
)
1656 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
1658 /* generic HDLC layer open processing */
1659 if ((rc
= hdlc_open(dev
)))
1662 /* arbitrate between network and tty opens */
1663 spin_lock_irqsave(&info
->netlock
, flags
);
1664 if (info
->port
.count
!= 0 || info
->netcount
!= 0) {
1665 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
1666 spin_unlock_irqrestore(&info
->netlock
, flags
);
1670 spin_unlock_irqrestore(&info
->netlock
, flags
);
1672 /* claim resources and init adapter */
1673 if ((rc
= startup(info
)) != 0) {
1674 spin_lock_irqsave(&info
->netlock
, flags
);
1676 spin_unlock_irqrestore(&info
->netlock
, flags
);
1680 /* assert DTR and RTS, apply hardware settings */
1681 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1684 /* enable network layer transmit */
1685 dev
->trans_start
= jiffies
;
1686 netif_start_queue(dev
);
1688 /* inform generic HDLC layer of current DCD status */
1689 spin_lock_irqsave(&info
->lock
, flags
);
1691 spin_unlock_irqrestore(&info
->lock
, flags
);
1692 if (info
->serial_signals
& SerialSignal_DCD
)
1693 netif_carrier_on(dev
);
1695 netif_carrier_off(dev
);
1700 * called by network layer when interface is disabled
1701 * shutdown hardware and release resources
1703 * dev pointer to network device structure
1705 * returns 0 if success, otherwise error code
1707 static int hdlcdev_close(struct net_device
*dev
)
1709 SLMP_INFO
*info
= dev_to_port(dev
);
1710 unsigned long flags
;
1712 if (debug_level
>= DEBUG_LEVEL_INFO
)
1713 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
1715 netif_stop_queue(dev
);
1717 /* shutdown adapter and release resources */
1722 spin_lock_irqsave(&info
->netlock
, flags
);
1724 spin_unlock_irqrestore(&info
->netlock
, flags
);
1730 * called by network layer to process IOCTL call to network device
1732 * dev pointer to network device structure
1733 * ifr pointer to network interface request structure
1734 * cmd IOCTL command code
1736 * returns 0 if success, otherwise error code
1738 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1740 const size_t size
= sizeof(sync_serial_settings
);
1741 sync_serial_settings new_line
;
1742 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
1743 SLMP_INFO
*info
= dev_to_port(dev
);
1746 if (debug_level
>= DEBUG_LEVEL_INFO
)
1747 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
1749 /* return error if TTY interface open */
1750 if (info
->port
.count
)
1753 if (cmd
!= SIOCWANDEV
)
1754 return hdlc_ioctl(dev
, ifr
, cmd
);
1756 switch(ifr
->ifr_settings
.type
) {
1757 case IF_GET_IFACE
: /* return current sync_serial_settings */
1759 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
1760 if (ifr
->ifr_settings
.size
< size
) {
1761 ifr
->ifr_settings
.size
= size
; /* data size wanted */
1765 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1766 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1767 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1768 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1771 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
1772 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
1773 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
1774 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
1775 default: new_line
.clock_type
= CLOCK_DEFAULT
;
1778 new_line
.clock_rate
= info
->params
.clock_speed
;
1779 new_line
.loopback
= info
->params
.loopback
? 1:0;
1781 if (copy_to_user(line
, &new_line
, size
))
1785 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
1787 if(!capable(CAP_NET_ADMIN
))
1789 if (copy_from_user(&new_line
, line
, size
))
1792 switch (new_line
.clock_type
)
1794 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
1795 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
1796 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
1797 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
1798 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
1799 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1800 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1801 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1802 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
1803 default: return -EINVAL
;
1806 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
1809 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1810 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1811 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1812 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1813 info
->params
.flags
|= flags
;
1815 info
->params
.loopback
= new_line
.loopback
;
1817 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
1818 info
->params
.clock_speed
= new_line
.clock_rate
;
1820 info
->params
.clock_speed
= 0;
1822 /* if network interface up, reprogram hardware */
1828 return hdlc_ioctl(dev
, ifr
, cmd
);
1833 * called by network layer when transmit timeout is detected
1835 * dev pointer to network device structure
1837 static void hdlcdev_tx_timeout(struct net_device
*dev
)
1839 SLMP_INFO
*info
= dev_to_port(dev
);
1840 unsigned long flags
;
1842 if (debug_level
>= DEBUG_LEVEL_INFO
)
1843 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
1845 dev
->stats
.tx_errors
++;
1846 dev
->stats
.tx_aborted_errors
++;
1848 spin_lock_irqsave(&info
->lock
,flags
);
1850 spin_unlock_irqrestore(&info
->lock
,flags
);
1852 netif_wake_queue(dev
);
1856 * called by device driver when transmit completes
1857 * reenable network layer transmit if stopped
1859 * info pointer to device instance information
1861 static void hdlcdev_tx_done(SLMP_INFO
*info
)
1863 if (netif_queue_stopped(info
->netdev
))
1864 netif_wake_queue(info
->netdev
);
1868 * called by device driver when frame received
1869 * pass frame to network layer
1871 * info pointer to device instance information
1872 * buf pointer to buffer contianing frame data
1873 * size count of data bytes in buf
1875 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
)
1877 struct sk_buff
*skb
= dev_alloc_skb(size
);
1878 struct net_device
*dev
= info
->netdev
;
1880 if (debug_level
>= DEBUG_LEVEL_INFO
)
1881 printk("hdlcdev_rx(%s)\n",dev
->name
);
1884 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n",
1886 dev
->stats
.rx_dropped
++;
1890 memcpy(skb_put(skb
, size
), buf
, size
);
1892 skb
->protocol
= hdlc_type_trans(skb
, dev
);
1894 dev
->stats
.rx_packets
++;
1895 dev
->stats
.rx_bytes
+= size
;
1900 static const struct net_device_ops hdlcdev_ops
= {
1901 .ndo_open
= hdlcdev_open
,
1902 .ndo_stop
= hdlcdev_close
,
1903 .ndo_change_mtu
= hdlc_change_mtu
,
1904 .ndo_start_xmit
= hdlc_start_xmit
,
1905 .ndo_do_ioctl
= hdlcdev_ioctl
,
1906 .ndo_tx_timeout
= hdlcdev_tx_timeout
,
1910 * called by device driver when adding device instance
1911 * do generic HDLC initialization
1913 * info pointer to device instance information
1915 * returns 0 if success, otherwise error code
1917 static int hdlcdev_init(SLMP_INFO
*info
)
1920 struct net_device
*dev
;
1923 /* allocate and initialize network and HDLC layer objects */
1925 if (!(dev
= alloc_hdlcdev(info
))) {
1926 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
1930 /* for network layer reporting purposes only */
1931 dev
->mem_start
= info
->phys_sca_base
;
1932 dev
->mem_end
= info
->phys_sca_base
+ SCA_BASE_SIZE
- 1;
1933 dev
->irq
= info
->irq_level
;
1935 /* network layer callbacks and settings */
1936 dev
->netdev_ops
= &hdlcdev_ops
;
1937 dev
->watchdog_timeo
= 10 * HZ
;
1938 dev
->tx_queue_len
= 50;
1940 /* generic HDLC layer callbacks and settings */
1941 hdlc
= dev_to_hdlc(dev
);
1942 hdlc
->attach
= hdlcdev_attach
;
1943 hdlc
->xmit
= hdlcdev_xmit
;
1945 /* register objects with HDLC layer */
1946 if ((rc
= register_hdlc_device(dev
))) {
1947 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
1957 * called by device driver when removing device instance
1958 * do generic HDLC cleanup
1960 * info pointer to device instance information
1962 static void hdlcdev_exit(SLMP_INFO
*info
)
1964 unregister_hdlc_device(info
->netdev
);
1965 free_netdev(info
->netdev
);
1966 info
->netdev
= NULL
;
1969 #endif /* CONFIG_HDLC */
1972 /* Return next bottom half action to perform.
1973 * Return Value: BH action code or 0 if nothing to do.
1975 static int bh_action(SLMP_INFO
*info
)
1977 unsigned long flags
;
1980 spin_lock_irqsave(&info
->lock
,flags
);
1982 if (info
->pending_bh
& BH_RECEIVE
) {
1983 info
->pending_bh
&= ~BH_RECEIVE
;
1985 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1986 info
->pending_bh
&= ~BH_TRANSMIT
;
1988 } else if (info
->pending_bh
& BH_STATUS
) {
1989 info
->pending_bh
&= ~BH_STATUS
;
1994 /* Mark BH routine as complete */
1995 info
->bh_running
= false;
1996 info
->bh_requested
= false;
1999 spin_unlock_irqrestore(&info
->lock
,flags
);
2004 /* Perform bottom half processing of work items queued by ISR.
2006 static void bh_handler(struct work_struct
*work
)
2008 SLMP_INFO
*info
= container_of(work
, SLMP_INFO
, task
);
2014 if ( debug_level
>= DEBUG_LEVEL_BH
)
2015 printk( "%s(%d):%s bh_handler() entry\n",
2016 __FILE__
,__LINE__
,info
->device_name
);
2018 info
->bh_running
= true;
2020 while((action
= bh_action(info
)) != 0) {
2022 /* Process work item */
2023 if ( debug_level
>= DEBUG_LEVEL_BH
)
2024 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2025 __FILE__
,__LINE__
,info
->device_name
, action
);
2039 /* unknown work item ID */
2040 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2041 __FILE__
,__LINE__
,info
->device_name
,action
);
2046 if ( debug_level
>= DEBUG_LEVEL_BH
)
2047 printk( "%s(%d):%s bh_handler() exit\n",
2048 __FILE__
,__LINE__
,info
->device_name
);
2051 static void bh_receive(SLMP_INFO
*info
)
2053 if ( debug_level
>= DEBUG_LEVEL_BH
)
2054 printk( "%s(%d):%s bh_receive()\n",
2055 __FILE__
,__LINE__
,info
->device_name
);
2057 while( rx_get_frame(info
) );
2060 static void bh_transmit(SLMP_INFO
*info
)
2062 struct tty_struct
*tty
= info
->port
.tty
;
2064 if ( debug_level
>= DEBUG_LEVEL_BH
)
2065 printk( "%s(%d):%s bh_transmit() entry\n",
2066 __FILE__
,__LINE__
,info
->device_name
);
2072 static void bh_status(SLMP_INFO
*info
)
2074 if ( debug_level
>= DEBUG_LEVEL_BH
)
2075 printk( "%s(%d):%s bh_status() entry\n",
2076 __FILE__
,__LINE__
,info
->device_name
);
2078 info
->ri_chkcount
= 0;
2079 info
->dsr_chkcount
= 0;
2080 info
->dcd_chkcount
= 0;
2081 info
->cts_chkcount
= 0;
2084 static void isr_timer(SLMP_INFO
* info
)
2086 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
2088 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2089 write_reg(info
, IER2
, 0);
2091 /* TMCS, Timer Control/Status Register
2093 * 07 CMF, Compare match flag (read only) 1=match
2094 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2095 * 05 Reserved, must be 0
2096 * 04 TME, Timer Enable
2097 * 03..00 Reserved, must be 0
2101 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0);
2103 info
->irq_occurred
= true;
2105 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2106 printk("%s(%d):%s isr_timer()\n",
2107 __FILE__
,__LINE__
,info
->device_name
);
2110 static void isr_rxint(SLMP_INFO
* info
)
2112 struct tty_struct
*tty
= info
->port
.tty
;
2113 struct mgsl_icount
*icount
= &info
->icount
;
2114 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (FLGD
+ IDLD
+ CDCD
+ BRKD
);
2115 unsigned char status2
= read_reg(info
, SR2
) & info
->ie2_value
& OVRN
;
2117 /* clear status bits */
2119 write_reg(info
, SR1
, status
);
2122 write_reg(info
, SR2
, status2
);
2124 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2125 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2126 __FILE__
,__LINE__
,info
->device_name
,status
,status2
);
2128 if (info
->params
.mode
== MGSL_MODE_ASYNC
) {
2129 if (status
& BRKD
) {
2132 /* process break detection if tty control
2133 * is not set to ignore it
2136 if (!(status
& info
->ignore_status_mask1
)) {
2137 if (info
->read_status_mask1
& BRKD
) {
2138 tty_insert_flip_char(tty
, 0, TTY_BREAK
);
2139 if (info
->port
.flags
& ASYNC_SAK
)
2147 if (status
& (FLGD
|IDLD
)) {
2149 info
->icount
.exithunt
++;
2150 else if (status
& IDLD
)
2151 info
->icount
.rxidle
++;
2152 wake_up_interruptible(&info
->event_wait_q
);
2156 if (status
& CDCD
) {
2157 /* simulate a common modem status change interrupt
2160 get_signals( info
);
2162 MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
));
2167 * handle async rx data interrupts
2169 static void isr_rxrdy(SLMP_INFO
* info
)
2172 unsigned char DataByte
;
2173 struct tty_struct
*tty
= info
->port
.tty
;
2174 struct mgsl_icount
*icount
= &info
->icount
;
2176 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2177 printk("%s(%d):%s isr_rxrdy\n",
2178 __FILE__
,__LINE__
,info
->device_name
);
2180 while((status
= read_reg(info
,CST0
)) & BIT0
)
2184 DataByte
= read_reg(info
,TRB
);
2188 if ( status
& (PE
+ FRME
+ OVRN
) ) {
2189 printk("%s(%d):%s rxerr=%04X\n",
2190 __FILE__
,__LINE__
,info
->device_name
,status
);
2192 /* update error statistics */
2195 else if (status
& FRME
)
2197 else if (status
& OVRN
)
2200 /* discard char if tty control flags say so */
2201 if (status
& info
->ignore_status_mask2
)
2204 status
&= info
->read_status_mask2
;
2209 else if (status
& FRME
)
2211 if (status
& OVRN
) {
2212 /* Overrun is special, since it's
2213 * reported immediately, and doesn't
2214 * affect the current character
2219 } /* end of if (error) */
2222 tty_insert_flip_char(tty
, DataByte
, flag
);
2224 tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
2228 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
2229 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2230 __FILE__
,__LINE__
,info
->device_name
,
2231 icount
->rx
,icount
->brk
,icount
->parity
,
2232 icount
->frame
,icount
->overrun
);
2236 tty_flip_buffer_push(tty
);
2239 static void isr_txeom(SLMP_INFO
* info
, unsigned char status
)
2241 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2242 printk("%s(%d):%s isr_txeom status=%02x\n",
2243 __FILE__
,__LINE__
,info
->device_name
,status
);
2245 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2246 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2247 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2249 if (status
& UDRN
) {
2250 write_reg(info
, CMD
, TXRESET
);
2251 write_reg(info
, CMD
, TXENABLE
);
2253 write_reg(info
, CMD
, TXBUFCLR
);
2255 /* disable and clear tx interrupts */
2256 info
->ie0_value
&= ~TXRDYE
;
2257 info
->ie1_value
&= ~(IDLE
+ UDRN
);
2258 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2259 write_reg(info
, SR1
, (unsigned char)(UDRN
+ IDLE
));
2261 if ( info
->tx_active
) {
2262 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2264 info
->icount
.txunder
++;
2265 else if (status
& IDLE
)
2266 info
->icount
.txok
++;
2269 info
->tx_active
= false;
2270 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2272 del_timer(&info
->tx_timer
);
2274 if (info
->params
.mode
!= MGSL_MODE_ASYNC
&& info
->drop_rts_on_tx_done
) {
2275 info
->serial_signals
&= ~SerialSignal_RTS
;
2276 info
->drop_rts_on_tx_done
= false;
2280 #if SYNCLINK_GENERIC_HDLC
2282 hdlcdev_tx_done(info
);
2286 if (info
->port
.tty
&& (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
)) {
2290 info
->pending_bh
|= BH_TRANSMIT
;
2297 * handle tx status interrupts
2299 static void isr_txint(SLMP_INFO
* info
)
2301 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (UDRN
+ IDLE
+ CCTS
);
2303 /* clear status bits */
2304 write_reg(info
, SR1
, status
);
2306 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2307 printk("%s(%d):%s isr_txint status=%02x\n",
2308 __FILE__
,__LINE__
,info
->device_name
,status
);
2310 if (status
& (UDRN
+ IDLE
))
2311 isr_txeom(info
, status
);
2313 if (status
& CCTS
) {
2314 /* simulate a common modem status change interrupt
2317 get_signals( info
);
2319 MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
));
2325 * handle async tx data interrupts
2327 static void isr_txrdy(SLMP_INFO
* info
)
2329 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2330 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2331 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
2333 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2334 /* disable TXRDY IRQ, enable IDLE IRQ */
2335 info
->ie0_value
&= ~TXRDYE
;
2336 info
->ie1_value
|= IDLE
;
2337 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2341 if (info
->port
.tty
&& (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
)) {
2346 if ( info
->tx_count
)
2347 tx_load_fifo( info
);
2349 info
->tx_active
= false;
2350 info
->ie0_value
&= ~TXRDYE
;
2351 write_reg(info
, IE0
, info
->ie0_value
);
2354 if (info
->tx_count
< WAKEUP_CHARS
)
2355 info
->pending_bh
|= BH_TRANSMIT
;
2358 static void isr_rxdmaok(SLMP_INFO
* info
)
2360 /* BIT7 = EOT (end of transfer)
2361 * BIT6 = EOM (end of message/frame)
2363 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0xc0;
2365 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2366 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2368 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2369 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2370 __FILE__
,__LINE__
,info
->device_name
,status
);
2372 info
->pending_bh
|= BH_RECEIVE
;
2375 static void isr_rxdmaerror(SLMP_INFO
* info
)
2377 /* BIT5 = BOF (buffer overflow)
2378 * BIT4 = COF (counter overflow)
2380 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0x30;
2382 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2383 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2385 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2386 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2387 __FILE__
,__LINE__
,info
->device_name
,status
);
2389 info
->rx_overflow
= true;
2390 info
->pending_bh
|= BH_RECEIVE
;
2393 static void isr_txdmaok(SLMP_INFO
* info
)
2395 unsigned char status_reg1
= read_reg(info
, SR1
);
2397 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2398 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2399 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2401 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2402 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2403 __FILE__
,__LINE__
,info
->device_name
,status_reg1
);
2405 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2406 write_reg16(info
, TRC0
, 0);
2407 info
->ie0_value
|= TXRDYE
;
2408 write_reg(info
, IE0
, info
->ie0_value
);
2411 static void isr_txdmaerror(SLMP_INFO
* info
)
2413 /* BIT5 = BOF (buffer overflow)
2414 * BIT4 = COF (counter overflow)
2416 unsigned char status
= read_reg(info
,TXDMA
+ DSR
) & 0x30;
2418 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2419 write_reg(info
, TXDMA
+ DSR
, (unsigned char)(status
| 1));
2421 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2422 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2423 __FILE__
,__LINE__
,info
->device_name
,status
);
2426 /* handle input serial signal changes
2428 static void isr_io_pin( SLMP_INFO
*info
, u16 status
)
2430 struct mgsl_icount
*icount
;
2432 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2433 printk("%s(%d):isr_io_pin status=%04X\n",
2434 __FILE__
,__LINE__
,status
);
2436 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
2437 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
2438 icount
= &info
->icount
;
2439 /* update input line counters */
2440 if (status
& MISCSTATUS_RI_LATCHED
) {
2442 if ( status
& SerialSignal_RI
)
2443 info
->input_signal_events
.ri_up
++;
2445 info
->input_signal_events
.ri_down
++;
2447 if (status
& MISCSTATUS_DSR_LATCHED
) {
2449 if ( status
& SerialSignal_DSR
)
2450 info
->input_signal_events
.dsr_up
++;
2452 info
->input_signal_events
.dsr_down
++;
2454 if (status
& MISCSTATUS_DCD_LATCHED
) {
2455 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2456 info
->ie1_value
&= ~CDCD
;
2457 write_reg(info
, IE1
, info
->ie1_value
);
2460 if (status
& SerialSignal_DCD
) {
2461 info
->input_signal_events
.dcd_up
++;
2463 info
->input_signal_events
.dcd_down
++;
2464 #if SYNCLINK_GENERIC_HDLC
2465 if (info
->netcount
) {
2466 if (status
& SerialSignal_DCD
)
2467 netif_carrier_on(info
->netdev
);
2469 netif_carrier_off(info
->netdev
);
2473 if (status
& MISCSTATUS_CTS_LATCHED
)
2475 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2476 info
->ie1_value
&= ~CCTS
;
2477 write_reg(info
, IE1
, info
->ie1_value
);
2480 if ( status
& SerialSignal_CTS
)
2481 info
->input_signal_events
.cts_up
++;
2483 info
->input_signal_events
.cts_down
++;
2485 wake_up_interruptible(&info
->status_event_wait_q
);
2486 wake_up_interruptible(&info
->event_wait_q
);
2488 if ( (info
->port
.flags
& ASYNC_CHECK_CD
) &&
2489 (status
& MISCSTATUS_DCD_LATCHED
) ) {
2490 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2491 printk("%s CD now %s...", info
->device_name
,
2492 (status
& SerialSignal_DCD
) ? "on" : "off");
2493 if (status
& SerialSignal_DCD
)
2494 wake_up_interruptible(&info
->port
.open_wait
);
2496 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2497 printk("doing serial hangup...");
2499 tty_hangup(info
->port
.tty
);
2503 if (tty_port_cts_enabled(&info
->port
) &&
2504 (status
& MISCSTATUS_CTS_LATCHED
) ) {
2505 if ( info
->port
.tty
) {
2506 if (info
->port
.tty
->hw_stopped
) {
2507 if (status
& SerialSignal_CTS
) {
2508 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2509 printk("CTS tx start...");
2510 info
->port
.tty
->hw_stopped
= 0;
2512 info
->pending_bh
|= BH_TRANSMIT
;
2516 if (!(status
& SerialSignal_CTS
)) {
2517 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2518 printk("CTS tx stop...");
2519 info
->port
.tty
->hw_stopped
= 1;
2527 info
->pending_bh
|= BH_STATUS
;
2530 /* Interrupt service routine entry point.
2533 * irq interrupt number that caused interrupt
2534 * dev_id device ID supplied during interrupt registration
2535 * regs interrupted processor context
2537 static irqreturn_t
synclinkmp_interrupt(int dummy
, void *dev_id
)
2539 SLMP_INFO
*info
= dev_id
;
2540 unsigned char status
, status0
, status1
=0;
2541 unsigned char dmastatus
, dmastatus0
, dmastatus1
=0;
2542 unsigned char timerstatus0
, timerstatus1
=0;
2543 unsigned char shift
;
2547 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2548 printk(KERN_DEBUG
"%s(%d): synclinkmp_interrupt(%d)entry.\n",
2549 __FILE__
, __LINE__
, info
->irq_level
);
2551 spin_lock(&info
->lock
);
2555 /* get status for SCA0 (ports 0-1) */
2556 tmp
= read_reg16(info
, ISR0
); /* get ISR0 and ISR1 in one read */
2557 status0
= (unsigned char)tmp
;
2558 dmastatus0
= (unsigned char)(tmp
>>8);
2559 timerstatus0
= read_reg(info
, ISR2
);
2561 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2562 printk(KERN_DEBUG
"%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2563 __FILE__
, __LINE__
, info
->device_name
,
2564 status0
, dmastatus0
, timerstatus0
);
2566 if (info
->port_count
== 4) {
2567 /* get status for SCA1 (ports 2-3) */
2568 tmp
= read_reg16(info
->port_array
[2], ISR0
);
2569 status1
= (unsigned char)tmp
;
2570 dmastatus1
= (unsigned char)(tmp
>>8);
2571 timerstatus1
= read_reg(info
->port_array
[2], ISR2
);
2573 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2574 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2575 __FILE__
,__LINE__
,info
->device_name
,
2576 status1
,dmastatus1
,timerstatus1
);
2579 if (!status0
&& !dmastatus0
&& !timerstatus0
&&
2580 !status1
&& !dmastatus1
&& !timerstatus1
)
2583 for(i
=0; i
< info
->port_count
; i
++) {
2584 if (info
->port_array
[i
] == NULL
)
2588 dmastatus
= dmastatus0
;
2591 dmastatus
= dmastatus1
;
2594 shift
= i
& 1 ? 4 :0;
2596 if (status
& BIT0
<< shift
)
2597 isr_rxrdy(info
->port_array
[i
]);
2598 if (status
& BIT1
<< shift
)
2599 isr_txrdy(info
->port_array
[i
]);
2600 if (status
& BIT2
<< shift
)
2601 isr_rxint(info
->port_array
[i
]);
2602 if (status
& BIT3
<< shift
)
2603 isr_txint(info
->port_array
[i
]);
2605 if (dmastatus
& BIT0
<< shift
)
2606 isr_rxdmaerror(info
->port_array
[i
]);
2607 if (dmastatus
& BIT1
<< shift
)
2608 isr_rxdmaok(info
->port_array
[i
]);
2609 if (dmastatus
& BIT2
<< shift
)
2610 isr_txdmaerror(info
->port_array
[i
]);
2611 if (dmastatus
& BIT3
<< shift
)
2612 isr_txdmaok(info
->port_array
[i
]);
2615 if (timerstatus0
& (BIT5
| BIT4
))
2616 isr_timer(info
->port_array
[0]);
2617 if (timerstatus0
& (BIT7
| BIT6
))
2618 isr_timer(info
->port_array
[1]);
2619 if (timerstatus1
& (BIT5
| BIT4
))
2620 isr_timer(info
->port_array
[2]);
2621 if (timerstatus1
& (BIT7
| BIT6
))
2622 isr_timer(info
->port_array
[3]);
2625 for(i
=0; i
< info
->port_count
; i
++) {
2626 SLMP_INFO
* port
= info
->port_array
[i
];
2628 /* Request bottom half processing if there's something
2629 * for it to do and the bh is not already running.
2631 * Note: startup adapter diags require interrupts.
2632 * do not request bottom half processing if the
2633 * device is not open in a normal mode.
2635 if ( port
&& (port
->port
.count
|| port
->netcount
) &&
2636 port
->pending_bh
&& !port
->bh_running
&&
2637 !port
->bh_requested
) {
2638 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2639 printk("%s(%d):%s queueing bh task.\n",
2640 __FILE__
,__LINE__
,port
->device_name
);
2641 schedule_work(&port
->task
);
2642 port
->bh_requested
= true;
2646 spin_unlock(&info
->lock
);
2648 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2649 printk(KERN_DEBUG
"%s(%d):synclinkmp_interrupt(%d)exit.\n",
2650 __FILE__
, __LINE__
, info
->irq_level
);
2654 /* Initialize and start device.
2656 static int startup(SLMP_INFO
* info
)
2658 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2659 printk("%s(%d):%s tx_releaseup()\n",__FILE__
,__LINE__
,info
->device_name
);
2661 if (info
->port
.flags
& ASYNC_INITIALIZED
)
2664 if (!info
->tx_buf
) {
2665 info
->tx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
2666 if (!info
->tx_buf
) {
2667 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
2668 __FILE__
,__LINE__
,info
->device_name
);
2673 info
->pending_bh
= 0;
2675 memset(&info
->icount
, 0, sizeof(info
->icount
));
2677 /* program hardware for current parameters */
2680 change_params(info
);
2682 mod_timer(&info
->status_timer
, jiffies
+ msecs_to_jiffies(10));
2685 clear_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
2687 info
->port
.flags
|= ASYNC_INITIALIZED
;
2692 /* Called by close() and hangup() to shutdown hardware
2694 static void shutdown(SLMP_INFO
* info
)
2696 unsigned long flags
;
2698 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
2701 if (debug_level
>= DEBUG_LEVEL_INFO
)
2702 printk("%s(%d):%s synclinkmp_shutdown()\n",
2703 __FILE__
,__LINE__
, info
->device_name
);
2705 /* clear status wait queue because status changes */
2706 /* can't happen after shutting down the hardware */
2707 wake_up_interruptible(&info
->status_event_wait_q
);
2708 wake_up_interruptible(&info
->event_wait_q
);
2710 del_timer(&info
->tx_timer
);
2711 del_timer(&info
->status_timer
);
2713 kfree(info
->tx_buf
);
2714 info
->tx_buf
= NULL
;
2716 spin_lock_irqsave(&info
->lock
,flags
);
2720 if (!info
->port
.tty
|| info
->port
.tty
->termios
.c_cflag
& HUPCL
) {
2721 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
2725 spin_unlock_irqrestore(&info
->lock
,flags
);
2728 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
2730 info
->port
.flags
&= ~ASYNC_INITIALIZED
;
2733 static void program_hw(SLMP_INFO
*info
)
2735 unsigned long flags
;
2737 spin_lock_irqsave(&info
->lock
,flags
);
2742 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2744 if (info
->params
.mode
== MGSL_MODE_HDLC
|| info
->netcount
)
2751 info
->dcd_chkcount
= 0;
2752 info
->cts_chkcount
= 0;
2753 info
->ri_chkcount
= 0;
2754 info
->dsr_chkcount
= 0;
2756 info
->ie1_value
|= (CDCD
|CCTS
);
2757 write_reg(info
, IE1
, info
->ie1_value
);
2761 if (info
->netcount
|| (info
->port
.tty
&& info
->port
.tty
->termios
.c_cflag
& CREAD
) )
2764 spin_unlock_irqrestore(&info
->lock
,flags
);
2767 /* Reconfigure adapter based on new parameters
2769 static void change_params(SLMP_INFO
*info
)
2774 if (!info
->port
.tty
)
2777 if (debug_level
>= DEBUG_LEVEL_INFO
)
2778 printk("%s(%d):%s change_params()\n",
2779 __FILE__
,__LINE__
, info
->device_name
);
2781 cflag
= info
->port
.tty
->termios
.c_cflag
;
2783 /* if B0 rate (hangup) specified then negate DTR and RTS */
2784 /* otherwise assert DTR and RTS */
2786 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
2788 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
2790 /* byte size and parity */
2792 switch (cflag
& CSIZE
) {
2793 case CS5
: info
->params
.data_bits
= 5; break;
2794 case CS6
: info
->params
.data_bits
= 6; break;
2795 case CS7
: info
->params
.data_bits
= 7; break;
2796 case CS8
: info
->params
.data_bits
= 8; break;
2797 /* Never happens, but GCC is too dumb to figure it out */
2798 default: info
->params
.data_bits
= 7; break;
2802 info
->params
.stop_bits
= 2;
2804 info
->params
.stop_bits
= 1;
2806 info
->params
.parity
= ASYNC_PARITY_NONE
;
2807 if (cflag
& PARENB
) {
2809 info
->params
.parity
= ASYNC_PARITY_ODD
;
2811 info
->params
.parity
= ASYNC_PARITY_EVEN
;
2814 info
->params
.parity
= ASYNC_PARITY_SPACE
;
2818 /* calculate number of jiffies to transmit a full
2819 * FIFO (32 bytes) at specified data rate
2821 bits_per_char
= info
->params
.data_bits
+
2822 info
->params
.stop_bits
+ 1;
2824 /* if port data rate is set to 460800 or less then
2825 * allow tty settings to override, otherwise keep the
2826 * current data rate.
2828 if (info
->params
.data_rate
<= 460800) {
2829 info
->params
.data_rate
= tty_get_baud_rate(info
->port
.tty
);
2832 if ( info
->params
.data_rate
) {
2833 info
->timeout
= (32*HZ
*bits_per_char
) /
2834 info
->params
.data_rate
;
2836 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2838 if (cflag
& CRTSCTS
)
2839 info
->port
.flags
|= ASYNC_CTS_FLOW
;
2841 info
->port
.flags
&= ~ASYNC_CTS_FLOW
;
2844 info
->port
.flags
&= ~ASYNC_CHECK_CD
;
2846 info
->port
.flags
|= ASYNC_CHECK_CD
;
2848 /* process tty input control flags */
2850 info
->read_status_mask2
= OVRN
;
2851 if (I_INPCK(info
->port
.tty
))
2852 info
->read_status_mask2
|= PE
| FRME
;
2853 if (I_BRKINT(info
->port
.tty
) || I_PARMRK(info
->port
.tty
))
2854 info
->read_status_mask1
|= BRKD
;
2855 if (I_IGNPAR(info
->port
.tty
))
2856 info
->ignore_status_mask2
|= PE
| FRME
;
2857 if (I_IGNBRK(info
->port
.tty
)) {
2858 info
->ignore_status_mask1
|= BRKD
;
2859 /* If ignoring parity and break indicators, ignore
2860 * overruns too. (For real raw support).
2862 if (I_IGNPAR(info
->port
.tty
))
2863 info
->ignore_status_mask2
|= OVRN
;
2869 static int get_stats(SLMP_INFO
* info
, struct mgsl_icount __user
*user_icount
)
2873 if (debug_level
>= DEBUG_LEVEL_INFO
)
2874 printk("%s(%d):%s get_params()\n",
2875 __FILE__
,__LINE__
, info
->device_name
);
2878 memset(&info
->icount
, 0, sizeof(info
->icount
));
2880 mutex_lock(&info
->port
.mutex
);
2881 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2882 mutex_unlock(&info
->port
.mutex
);
2890 static int get_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*user_params
)
2893 if (debug_level
>= DEBUG_LEVEL_INFO
)
2894 printk("%s(%d):%s get_params()\n",
2895 __FILE__
,__LINE__
, info
->device_name
);
2897 mutex_lock(&info
->port
.mutex
);
2898 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2899 mutex_unlock(&info
->port
.mutex
);
2901 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2902 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2903 __FILE__
,__LINE__
,info
->device_name
);
2910 static int set_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*new_params
)
2912 unsigned long flags
;
2913 MGSL_PARAMS tmp_params
;
2916 if (debug_level
>= DEBUG_LEVEL_INFO
)
2917 printk("%s(%d):%s set_params\n",
2918 __FILE__
,__LINE__
,info
->device_name
);
2919 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2921 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2922 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2923 __FILE__
,__LINE__
,info
->device_name
);
2927 mutex_lock(&info
->port
.mutex
);
2928 spin_lock_irqsave(&info
->lock
,flags
);
2929 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2930 spin_unlock_irqrestore(&info
->lock
,flags
);
2932 change_params(info
);
2933 mutex_unlock(&info
->port
.mutex
);
2938 static int get_txidle(SLMP_INFO
* info
, int __user
*idle_mode
)
2942 if (debug_level
>= DEBUG_LEVEL_INFO
)
2943 printk("%s(%d):%s get_txidle()=%d\n",
2944 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2946 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2948 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2949 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2950 __FILE__
,__LINE__
,info
->device_name
);
2957 static int set_txidle(SLMP_INFO
* info
, int idle_mode
)
2959 unsigned long flags
;
2961 if (debug_level
>= DEBUG_LEVEL_INFO
)
2962 printk("%s(%d):%s set_txidle(%d)\n",
2963 __FILE__
,__LINE__
,info
->device_name
, idle_mode
);
2965 spin_lock_irqsave(&info
->lock
,flags
);
2966 info
->idle_mode
= idle_mode
;
2967 tx_set_idle( info
);
2968 spin_unlock_irqrestore(&info
->lock
,flags
);
2972 static int tx_enable(SLMP_INFO
* info
, int enable
)
2974 unsigned long flags
;
2976 if (debug_level
>= DEBUG_LEVEL_INFO
)
2977 printk("%s(%d):%s tx_enable(%d)\n",
2978 __FILE__
,__LINE__
,info
->device_name
, enable
);
2980 spin_lock_irqsave(&info
->lock
,flags
);
2982 if ( !info
->tx_enabled
) {
2986 if ( info
->tx_enabled
)
2989 spin_unlock_irqrestore(&info
->lock
,flags
);
2993 /* abort send HDLC frame
2995 static int tx_abort(SLMP_INFO
* info
)
2997 unsigned long flags
;
2999 if (debug_level
>= DEBUG_LEVEL_INFO
)
3000 printk("%s(%d):%s tx_abort()\n",
3001 __FILE__
,__LINE__
,info
->device_name
);
3003 spin_lock_irqsave(&info
->lock
,flags
);
3004 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
3005 info
->ie1_value
&= ~UDRN
;
3006 info
->ie1_value
|= IDLE
;
3007 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
3008 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
3010 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
3011 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
3013 write_reg(info
, CMD
, TXABORT
);
3015 spin_unlock_irqrestore(&info
->lock
,flags
);
3019 static int rx_enable(SLMP_INFO
* info
, int enable
)
3021 unsigned long flags
;
3023 if (debug_level
>= DEBUG_LEVEL_INFO
)
3024 printk("%s(%d):%s rx_enable(%d)\n",
3025 __FILE__
,__LINE__
,info
->device_name
,enable
);
3027 spin_lock_irqsave(&info
->lock
,flags
);
3029 if ( !info
->rx_enabled
)
3032 if ( info
->rx_enabled
)
3035 spin_unlock_irqrestore(&info
->lock
,flags
);
3039 /* wait for specified event to occur
3041 static int wait_mgsl_event(SLMP_INFO
* info
, int __user
*mask_ptr
)
3043 unsigned long flags
;
3046 struct mgsl_icount cprev
, cnow
;
3049 struct _input_signal_events oldsigs
, newsigs
;
3050 DECLARE_WAITQUEUE(wait
, current
);
3052 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
3057 if (debug_level
>= DEBUG_LEVEL_INFO
)
3058 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3059 __FILE__
,__LINE__
,info
->device_name
,mask
);
3061 spin_lock_irqsave(&info
->lock
,flags
);
3063 /* return immediately if state matches requested events */
3065 s
= info
->serial_signals
;
3068 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
3069 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
3070 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
3071 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
3073 spin_unlock_irqrestore(&info
->lock
,flags
);
3077 /* save current irq counts */
3078 cprev
= info
->icount
;
3079 oldsigs
= info
->input_signal_events
;
3081 /* enable hunt and idle irqs if needed */
3082 if (mask
& (MgslEvent_ExitHuntMode
+MgslEvent_IdleReceived
)) {
3083 unsigned char oldval
= info
->ie1_value
;
3084 unsigned char newval
= oldval
+
3085 (mask
& MgslEvent_ExitHuntMode
? FLGD
:0) +
3086 (mask
& MgslEvent_IdleReceived
? IDLD
:0);
3087 if ( oldval
!= newval
) {
3088 info
->ie1_value
= newval
;
3089 write_reg(info
, IE1
, info
->ie1_value
);
3093 set_current_state(TASK_INTERRUPTIBLE
);
3094 add_wait_queue(&info
->event_wait_q
, &wait
);
3096 spin_unlock_irqrestore(&info
->lock
,flags
);
3100 if (signal_pending(current
)) {
3105 /* get current irq counts */
3106 spin_lock_irqsave(&info
->lock
,flags
);
3107 cnow
= info
->icount
;
3108 newsigs
= info
->input_signal_events
;
3109 set_current_state(TASK_INTERRUPTIBLE
);
3110 spin_unlock_irqrestore(&info
->lock
,flags
);
3112 /* if no change, wait aborted for some reason */
3113 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
3114 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
3115 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
3116 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
3117 newsigs
.cts_up
== oldsigs
.cts_up
&&
3118 newsigs
.cts_down
== oldsigs
.cts_down
&&
3119 newsigs
.ri_up
== oldsigs
.ri_up
&&
3120 newsigs
.ri_down
== oldsigs
.ri_down
&&
3121 cnow
.exithunt
== cprev
.exithunt
&&
3122 cnow
.rxidle
== cprev
.rxidle
) {
3128 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
3129 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
3130 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
3131 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
3132 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
3133 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
3134 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
3135 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
3136 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
3137 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
3145 remove_wait_queue(&info
->event_wait_q
, &wait
);
3146 set_current_state(TASK_RUNNING
);
3149 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
3150 spin_lock_irqsave(&info
->lock
,flags
);
3151 if (!waitqueue_active(&info
->event_wait_q
)) {
3152 /* disable enable exit hunt mode/idle rcvd IRQs */
3153 info
->ie1_value
&= ~(FLGD
|IDLD
);
3154 write_reg(info
, IE1
, info
->ie1_value
);
3156 spin_unlock_irqrestore(&info
->lock
,flags
);
3160 PUT_USER(rc
, events
, mask_ptr
);
3165 static int modem_input_wait(SLMP_INFO
*info
,int arg
)
3167 unsigned long flags
;
3169 struct mgsl_icount cprev
, cnow
;
3170 DECLARE_WAITQUEUE(wait
, current
);
3172 /* save current irq counts */
3173 spin_lock_irqsave(&info
->lock
,flags
);
3174 cprev
= info
->icount
;
3175 add_wait_queue(&info
->status_event_wait_q
, &wait
);
3176 set_current_state(TASK_INTERRUPTIBLE
);
3177 spin_unlock_irqrestore(&info
->lock
,flags
);
3181 if (signal_pending(current
)) {
3186 /* get new irq counts */
3187 spin_lock_irqsave(&info
->lock
,flags
);
3188 cnow
= info
->icount
;
3189 set_current_state(TASK_INTERRUPTIBLE
);
3190 spin_unlock_irqrestore(&info
->lock
,flags
);
3192 /* if no change, wait aborted for some reason */
3193 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
3194 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
3199 /* check for change in caller specified modem input */
3200 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
3201 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
3202 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
3203 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
3210 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
3211 set_current_state(TASK_RUNNING
);
3215 /* return the state of the serial control and status signals
3217 static int tiocmget(struct tty_struct
*tty
)
3219 SLMP_INFO
*info
= tty
->driver_data
;
3220 unsigned int result
;
3221 unsigned long flags
;
3223 spin_lock_irqsave(&info
->lock
,flags
);
3225 spin_unlock_irqrestore(&info
->lock
,flags
);
3227 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
3228 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
3229 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
3230 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
3231 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
3232 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
3234 if (debug_level
>= DEBUG_LEVEL_INFO
)
3235 printk("%s(%d):%s tiocmget() value=%08X\n",
3236 __FILE__
,__LINE__
, info
->device_name
, result
);
3240 /* set modem control signals (DTR/RTS)
3242 static int tiocmset(struct tty_struct
*tty
,
3243 unsigned int set
, unsigned int clear
)
3245 SLMP_INFO
*info
= tty
->driver_data
;
3246 unsigned long flags
;
3248 if (debug_level
>= DEBUG_LEVEL_INFO
)
3249 printk("%s(%d):%s tiocmset(%x,%x)\n",
3250 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
3252 if (set
& TIOCM_RTS
)
3253 info
->serial_signals
|= SerialSignal_RTS
;
3254 if (set
& TIOCM_DTR
)
3255 info
->serial_signals
|= SerialSignal_DTR
;
3256 if (clear
& TIOCM_RTS
)
3257 info
->serial_signals
&= ~SerialSignal_RTS
;
3258 if (clear
& TIOCM_DTR
)
3259 info
->serial_signals
&= ~SerialSignal_DTR
;
3261 spin_lock_irqsave(&info
->lock
,flags
);
3263 spin_unlock_irqrestore(&info
->lock
,flags
);
3268 static int carrier_raised(struct tty_port
*port
)
3270 SLMP_INFO
*info
= container_of(port
, SLMP_INFO
, port
);
3271 unsigned long flags
;
3273 spin_lock_irqsave(&info
->lock
,flags
);
3275 spin_unlock_irqrestore(&info
->lock
,flags
);
3277 return (info
->serial_signals
& SerialSignal_DCD
) ? 1 : 0;
3280 static void dtr_rts(struct tty_port
*port
, int on
)
3282 SLMP_INFO
*info
= container_of(port
, SLMP_INFO
, port
);
3283 unsigned long flags
;
3285 spin_lock_irqsave(&info
->lock
,flags
);
3287 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3289 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3291 spin_unlock_irqrestore(&info
->lock
,flags
);
3294 /* Block the current process until the specified port is ready to open.
3296 static int block_til_ready(struct tty_struct
*tty
, struct file
*filp
,
3299 DECLARE_WAITQUEUE(wait
, current
);
3301 bool do_clocal
= false;
3302 bool extra_count
= false;
3303 unsigned long flags
;
3305 struct tty_port
*port
= &info
->port
;
3307 if (debug_level
>= DEBUG_LEVEL_INFO
)
3308 printk("%s(%d):%s block_til_ready()\n",
3309 __FILE__
,__LINE__
, tty
->driver
->name
);
3311 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3312 /* nonblock mode is set or port is not enabled */
3313 /* just verify that callout device is not active */
3314 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3318 if (tty
->termios
.c_cflag
& CLOCAL
)
3321 /* Wait for carrier detect and the line to become
3322 * free (i.e., not in use by the callout). While we are in
3323 * this loop, port->count is dropped by one, so that
3324 * close() knows when to free things. We restore it upon
3325 * exit, either normal or abnormal.
3329 add_wait_queue(&port
->open_wait
, &wait
);
3331 if (debug_level
>= DEBUG_LEVEL_INFO
)
3332 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3333 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3335 spin_lock_irqsave(&info
->lock
, flags
);
3336 if (!tty_hung_up_p(filp
)) {
3340 spin_unlock_irqrestore(&info
->lock
, flags
);
3341 port
->blocked_open
++;
3344 if (tty
->termios
.c_cflag
& CBAUD
)
3345 tty_port_raise_dtr_rts(port
);
3347 set_current_state(TASK_INTERRUPTIBLE
);
3349 if (tty_hung_up_p(filp
) || !(port
->flags
& ASYNC_INITIALIZED
)){
3350 retval
= (port
->flags
& ASYNC_HUP_NOTIFY
) ?
3351 -EAGAIN
: -ERESTARTSYS
;
3355 cd
= tty_port_carrier_raised(port
);
3357 if (!(port
->flags
& ASYNC_CLOSING
) && (do_clocal
|| cd
))
3360 if (signal_pending(current
)) {
3361 retval
= -ERESTARTSYS
;
3365 if (debug_level
>= DEBUG_LEVEL_INFO
)
3366 printk("%s(%d):%s block_til_ready() count=%d\n",
3367 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3374 set_current_state(TASK_RUNNING
);
3375 remove_wait_queue(&port
->open_wait
, &wait
);
3379 port
->blocked_open
--;
3381 if (debug_level
>= DEBUG_LEVEL_INFO
)
3382 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3383 __FILE__
,__LINE__
, tty
->driver
->name
, port
->count
);
3386 port
->flags
|= ASYNC_NORMAL_ACTIVE
;
3391 static int alloc_dma_bufs(SLMP_INFO
*info
)
3393 unsigned short BuffersPerFrame
;
3394 unsigned short BufferCount
;
3396 // Force allocation to start at 64K boundary for each port.
3397 // This is necessary because *all* buffer descriptors for a port
3398 // *must* be in the same 64K block. All descriptors on a port
3399 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3400 // into the CBP register.
3401 info
->port_array
[0]->last_mem_alloc
= (SCA_MEM_SIZE
/4) * info
->port_num
;
3403 /* Calculate the number of DMA buffers necessary to hold the */
3404 /* largest allowable frame size. Note: If the max frame size is */
3405 /* not an even multiple of the DMA buffer size then we need to */
3406 /* round the buffer count per frame up one. */
3408 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/SCABUFSIZE
);
3409 if ( info
->max_frame_size
% SCABUFSIZE
)
3412 /* calculate total number of data buffers (SCABUFSIZE) possible
3413 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3414 * for the descriptor list (BUFFERLISTSIZE).
3416 BufferCount
= (SCA_MEM_SIZE
/4 - BUFFERLISTSIZE
)/SCABUFSIZE
;
3418 /* limit number of buffers to maximum amount of descriptors */
3419 if (BufferCount
> BUFFERLISTSIZE
/sizeof(SCADESC
))
3420 BufferCount
= BUFFERLISTSIZE
/sizeof(SCADESC
);
3422 /* use enough buffers to transmit one max size frame */
3423 info
->tx_buf_count
= BuffersPerFrame
+ 1;
3425 /* never use more than half the available buffers for transmit */
3426 if (info
->tx_buf_count
> (BufferCount
/2))
3427 info
->tx_buf_count
= BufferCount
/2;
3429 if (info
->tx_buf_count
> SCAMAXDESC
)
3430 info
->tx_buf_count
= SCAMAXDESC
;
3432 /* use remaining buffers for receive */
3433 info
->rx_buf_count
= BufferCount
- info
->tx_buf_count
;
3435 if (info
->rx_buf_count
> SCAMAXDESC
)
3436 info
->rx_buf_count
= SCAMAXDESC
;
3438 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3439 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3440 __FILE__
,__LINE__
, info
->device_name
,
3441 info
->tx_buf_count
,info
->rx_buf_count
);
3443 if ( alloc_buf_list( info
) < 0 ||
3444 alloc_frame_bufs(info
,
3446 info
->rx_buf_list_ex
,
3447 info
->rx_buf_count
) < 0 ||
3448 alloc_frame_bufs(info
,
3450 info
->tx_buf_list_ex
,
3451 info
->tx_buf_count
) < 0 ||
3452 alloc_tmp_rx_buf(info
) < 0 ) {
3453 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3454 __FILE__
,__LINE__
, info
->device_name
);
3458 rx_reset_buffers( info
);
3463 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3465 static int alloc_buf_list(SLMP_INFO
*info
)
3469 /* build list in adapter shared memory */
3470 info
->buffer_list
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3471 info
->buffer_list_phys
= info
->port_array
[0]->last_mem_alloc
;
3472 info
->port_array
[0]->last_mem_alloc
+= BUFFERLISTSIZE
;
3474 memset(info
->buffer_list
, 0, BUFFERLISTSIZE
);
3476 /* Save virtual address pointers to the receive and */
3477 /* transmit buffer lists. (Receive 1st). These pointers will */
3478 /* be used by the processor to access the lists. */
3479 info
->rx_buf_list
= (SCADESC
*)info
->buffer_list
;
3481 info
->tx_buf_list
= (SCADESC
*)info
->buffer_list
;
3482 info
->tx_buf_list
+= info
->rx_buf_count
;
3484 /* Build links for circular buffer entry lists (tx and rx)
3486 * Note: links are physical addresses read by the SCA device
3487 * to determine the next buffer entry to use.
3490 for ( i
= 0; i
< info
->rx_buf_count
; i
++ ) {
3491 /* calculate and store physical address of this buffer entry */
3492 info
->rx_buf_list_ex
[i
].phys_entry
=
3493 info
->buffer_list_phys
+ (i
* sizeof(SCABUFSIZE
));
3495 /* calculate and store physical address of */
3496 /* next entry in cirular list of entries */
3497 info
->rx_buf_list
[i
].next
= info
->buffer_list_phys
;
3498 if ( i
< info
->rx_buf_count
- 1 )
3499 info
->rx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3501 info
->rx_buf_list
[i
].length
= SCABUFSIZE
;
3504 for ( i
= 0; i
< info
->tx_buf_count
; i
++ ) {
3505 /* calculate and store physical address of this buffer entry */
3506 info
->tx_buf_list_ex
[i
].phys_entry
= info
->buffer_list_phys
+
3507 ((info
->rx_buf_count
+ i
) * sizeof(SCADESC
));
3509 /* calculate and store physical address of */
3510 /* next entry in cirular list of entries */
3512 info
->tx_buf_list
[i
].next
= info
->buffer_list_phys
+
3513 info
->rx_buf_count
* sizeof(SCADESC
);
3515 if ( i
< info
->tx_buf_count
- 1 )
3516 info
->tx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3522 /* Allocate the frame DMA buffers used by the specified buffer list.
3524 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*buf_list
,SCADESC_EX
*buf_list_ex
,int count
)
3527 unsigned long phys_addr
;
3529 for ( i
= 0; i
< count
; i
++ ) {
3530 buf_list_ex
[i
].virt_addr
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3531 phys_addr
= info
->port_array
[0]->last_mem_alloc
;
3532 info
->port_array
[0]->last_mem_alloc
+= SCABUFSIZE
;
3534 buf_list
[i
].buf_ptr
= (unsigned short)phys_addr
;
3535 buf_list
[i
].buf_base
= (unsigned char)(phys_addr
>> 16);
3541 static void free_dma_bufs(SLMP_INFO
*info
)
3543 info
->buffer_list
= NULL
;
3544 info
->rx_buf_list
= NULL
;
3545 info
->tx_buf_list
= NULL
;
3548 /* allocate buffer large enough to hold max_frame_size.
3549 * This buffer is used to pass an assembled frame to the line discipline.
3551 static int alloc_tmp_rx_buf(SLMP_INFO
*info
)
3553 info
->tmp_rx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3554 if (info
->tmp_rx_buf
== NULL
)
3559 static void free_tmp_rx_buf(SLMP_INFO
*info
)
3561 kfree(info
->tmp_rx_buf
);
3562 info
->tmp_rx_buf
= NULL
;
3565 static int claim_resources(SLMP_INFO
*info
)
3567 if (request_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
,"synclinkmp") == NULL
) {
3568 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3569 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3570 info
->init_error
= DiagStatus_AddressConflict
;
3574 info
->shared_mem_requested
= true;
3576 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclinkmp") == NULL
) {
3577 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3578 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3579 info
->init_error
= DiagStatus_AddressConflict
;
3583 info
->lcr_mem_requested
= true;
3585 if (request_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
,"synclinkmp") == NULL
) {
3586 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3587 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3588 info
->init_error
= DiagStatus_AddressConflict
;
3592 info
->sca_base_requested
= true;
3594 if (request_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
,"synclinkmp") == NULL
) {
3595 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3596 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3597 info
->init_error
= DiagStatus_AddressConflict
;
3601 info
->sca_statctrl_requested
= true;
3603 info
->memory_base
= ioremap_nocache(info
->phys_memory_base
,
3605 if (!info
->memory_base
) {
3606 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3607 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3608 info
->init_error
= DiagStatus_CantAssignPciResources
;
3612 info
->lcr_base
= ioremap_nocache(info
->phys_lcr_base
, PAGE_SIZE
);
3613 if (!info
->lcr_base
) {
3614 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3615 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3616 info
->init_error
= DiagStatus_CantAssignPciResources
;
3619 info
->lcr_base
+= info
->lcr_offset
;
3621 info
->sca_base
= ioremap_nocache(info
->phys_sca_base
, PAGE_SIZE
);
3622 if (!info
->sca_base
) {
3623 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3624 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3625 info
->init_error
= DiagStatus_CantAssignPciResources
;
3628 info
->sca_base
+= info
->sca_offset
;
3630 info
->statctrl_base
= ioremap_nocache(info
->phys_statctrl_base
,
3632 if (!info
->statctrl_base
) {
3633 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3634 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3635 info
->init_error
= DiagStatus_CantAssignPciResources
;
3638 info
->statctrl_base
+= info
->statctrl_offset
;
3640 if ( !memory_test(info
) ) {
3641 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3642 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3643 info
->init_error
= DiagStatus_MemoryError
;
3650 release_resources( info
);
3654 static void release_resources(SLMP_INFO
*info
)
3656 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3657 printk( "%s(%d):%s release_resources() entry\n",
3658 __FILE__
,__LINE__
,info
->device_name
);
3660 if ( info
->irq_requested
) {
3661 free_irq(info
->irq_level
, info
);
3662 info
->irq_requested
= false;
3665 if ( info
->shared_mem_requested
) {
3666 release_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
);
3667 info
->shared_mem_requested
= false;
3669 if ( info
->lcr_mem_requested
) {
3670 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
3671 info
->lcr_mem_requested
= false;
3673 if ( info
->sca_base_requested
) {
3674 release_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
);
3675 info
->sca_base_requested
= false;
3677 if ( info
->sca_statctrl_requested
) {
3678 release_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
);
3679 info
->sca_statctrl_requested
= false;
3682 if (info
->memory_base
){
3683 iounmap(info
->memory_base
);
3684 info
->memory_base
= NULL
;
3687 if (info
->sca_base
) {
3688 iounmap(info
->sca_base
- info
->sca_offset
);
3689 info
->sca_base
=NULL
;
3692 if (info
->statctrl_base
) {
3693 iounmap(info
->statctrl_base
- info
->statctrl_offset
);
3694 info
->statctrl_base
=NULL
;
3697 if (info
->lcr_base
){
3698 iounmap(info
->lcr_base
- info
->lcr_offset
);
3699 info
->lcr_base
= NULL
;
3702 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3703 printk( "%s(%d):%s release_resources() exit\n",
3704 __FILE__
,__LINE__
,info
->device_name
);
3707 /* Add the specified device instance data structure to the
3708 * global linked list of devices and increment the device count.
3710 static void add_device(SLMP_INFO
*info
)
3712 info
->next_device
= NULL
;
3713 info
->line
= synclinkmp_device_count
;
3714 sprintf(info
->device_name
,"ttySLM%dp%d",info
->adapter_num
,info
->port_num
);
3716 if (info
->line
< MAX_DEVICES
) {
3717 if (maxframe
[info
->line
])
3718 info
->max_frame_size
= maxframe
[info
->line
];
3721 synclinkmp_device_count
++;
3723 if ( !synclinkmp_device_list
)
3724 synclinkmp_device_list
= info
;
3726 SLMP_INFO
*current_dev
= synclinkmp_device_list
;
3727 while( current_dev
->next_device
)
3728 current_dev
= current_dev
->next_device
;
3729 current_dev
->next_device
= info
;
3732 if ( info
->max_frame_size
< 4096 )
3733 info
->max_frame_size
= 4096;
3734 else if ( info
->max_frame_size
> 65535 )
3735 info
->max_frame_size
= 65535;
3737 printk( "SyncLink MultiPort %s: "
3738 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3740 info
->phys_sca_base
,
3741 info
->phys_memory_base
,
3742 info
->phys_statctrl_base
,
3743 info
->phys_lcr_base
,
3745 info
->max_frame_size
);
3747 #if SYNCLINK_GENERIC_HDLC
3752 static const struct tty_port_operations port_ops
= {
3753 .carrier_raised
= carrier_raised
,
3757 /* Allocate and initialize a device instance structure
3759 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3761 static SLMP_INFO
*alloc_dev(int adapter_num
, int port_num
, struct pci_dev
*pdev
)
3765 info
= kzalloc(sizeof(SLMP_INFO
),
3769 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3770 __FILE__
,__LINE__
, adapter_num
, port_num
);
3772 tty_port_init(&info
->port
);
3773 info
->port
.ops
= &port_ops
;
3774 info
->magic
= MGSL_MAGIC
;
3775 INIT_WORK(&info
->task
, bh_handler
);
3776 info
->max_frame_size
= 4096;
3777 info
->port
.close_delay
= 5*HZ
/10;
3778 info
->port
.closing_wait
= 30*HZ
;
3779 init_waitqueue_head(&info
->status_event_wait_q
);
3780 init_waitqueue_head(&info
->event_wait_q
);
3781 spin_lock_init(&info
->netlock
);
3782 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
3783 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
3784 info
->adapter_num
= adapter_num
;
3785 info
->port_num
= port_num
;
3787 /* Copy configuration info to device instance data */
3788 info
->irq_level
= pdev
->irq
;
3789 info
->phys_lcr_base
= pci_resource_start(pdev
,0);
3790 info
->phys_sca_base
= pci_resource_start(pdev
,2);
3791 info
->phys_memory_base
= pci_resource_start(pdev
,3);
3792 info
->phys_statctrl_base
= pci_resource_start(pdev
,4);
3794 /* Because veremap only works on page boundaries we must map
3795 * a larger area than is actually implemented for the LCR
3796 * memory range. We map a full page starting at the page boundary.
3798 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
3799 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
3801 info
->sca_offset
= info
->phys_sca_base
& (PAGE_SIZE
-1);
3802 info
->phys_sca_base
&= ~(PAGE_SIZE
-1);
3804 info
->statctrl_offset
= info
->phys_statctrl_base
& (PAGE_SIZE
-1);
3805 info
->phys_statctrl_base
&= ~(PAGE_SIZE
-1);
3807 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
3808 info
->irq_flags
= IRQF_SHARED
;
3810 setup_timer(&info
->tx_timer
, tx_timeout
, (unsigned long)info
);
3811 setup_timer(&info
->status_timer
, status_timeout
,
3812 (unsigned long)info
);
3814 /* Store the PCI9050 misc control register value because a flaw
3815 * in the PCI9050 prevents LCR registers from being read if
3816 * BIOS assigns an LCR base address with bit 7 set.
3818 * Only the misc control register is accessed for which only
3819 * write access is needed, so set an initial value and change
3820 * bits to the device instance data as we write the value
3821 * to the actual misc control register.
3823 info
->misc_ctrl_value
= 0x087e4546;
3825 /* initial port state is unknown - if startup errors
3826 * occur, init_error will be set to indicate the
3827 * problem. Once the port is fully initialized,
3828 * this value will be set to 0 to indicate the
3829 * port is available.
3831 info
->init_error
= -1;
3837 static void device_init(int adapter_num
, struct pci_dev
*pdev
)
3839 SLMP_INFO
*port_array
[SCA_MAX_PORTS
];
3842 /* allocate device instances for up to SCA_MAX_PORTS devices */
3843 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3844 port_array
[port
] = alloc_dev(adapter_num
,port
,pdev
);
3845 if( port_array
[port
] == NULL
) {
3846 for ( --port
; port
>= 0; --port
)
3847 kfree(port_array
[port
]);
3852 /* give copy of port_array to all ports and add to device list */
3853 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3854 memcpy(port_array
[port
]->port_array
,port_array
,sizeof(port_array
));
3855 add_device( port_array
[port
] );
3856 spin_lock_init(&port_array
[port
]->lock
);
3859 /* Allocate and claim adapter resources */
3860 if ( !claim_resources(port_array
[0]) ) {
3862 alloc_dma_bufs(port_array
[0]);
3864 /* copy resource information from first port to others */
3865 for ( port
= 1; port
< SCA_MAX_PORTS
; ++port
) {
3866 port_array
[port
]->lock
= port_array
[0]->lock
;
3867 port_array
[port
]->irq_level
= port_array
[0]->irq_level
;
3868 port_array
[port
]->memory_base
= port_array
[0]->memory_base
;
3869 port_array
[port
]->sca_base
= port_array
[0]->sca_base
;
3870 port_array
[port
]->statctrl_base
= port_array
[0]->statctrl_base
;
3871 port_array
[port
]->lcr_base
= port_array
[0]->lcr_base
;
3872 alloc_dma_bufs(port_array
[port
]);
3875 if ( request_irq(port_array
[0]->irq_level
,
3876 synclinkmp_interrupt
,
3877 port_array
[0]->irq_flags
,
3878 port_array
[0]->device_name
,
3879 port_array
[0]) < 0 ) {
3880 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3882 port_array
[0]->device_name
,
3883 port_array
[0]->irq_level
);
3886 port_array
[0]->irq_requested
= true;
3887 adapter_test(port_array
[0]);
3892 static const struct tty_operations ops
= {
3897 .put_char
= put_char
,
3898 .flush_chars
= flush_chars
,
3899 .write_room
= write_room
,
3900 .chars_in_buffer
= chars_in_buffer
,
3901 .flush_buffer
= flush_buffer
,
3903 .throttle
= throttle
,
3904 .unthrottle
= unthrottle
,
3905 .send_xchar
= send_xchar
,
3906 .break_ctl
= set_break
,
3907 .wait_until_sent
= wait_until_sent
,
3908 .set_termios
= set_termios
,
3910 .start
= tx_release
,
3912 .tiocmget
= tiocmget
,
3913 .tiocmset
= tiocmset
,
3914 .get_icount
= get_icount
,
3915 .proc_fops
= &synclinkmp_proc_fops
,
3919 static void synclinkmp_cleanup(void)
3925 printk("Unloading %s %s\n", driver_name
, driver_version
);
3927 if (serial_driver
) {
3928 if ((rc
= tty_unregister_driver(serial_driver
)))
3929 printk("%s(%d) failed to unregister tty driver err=%d\n",
3930 __FILE__
,__LINE__
,rc
);
3931 put_tty_driver(serial_driver
);
3935 info
= synclinkmp_device_list
;
3938 info
= info
->next_device
;
3941 /* release devices */
3942 info
= synclinkmp_device_list
;
3944 #if SYNCLINK_GENERIC_HDLC
3947 free_dma_bufs(info
);
3948 free_tmp_rx_buf(info
);
3949 if ( info
->port_num
== 0 ) {
3951 write_reg(info
, LPR
, 1); /* set low power mode */
3952 release_resources(info
);
3955 info
= info
->next_device
;
3959 pci_unregister_driver(&synclinkmp_pci_driver
);
3962 /* Driver initialization entry point.
3965 static int __init
synclinkmp_init(void)
3969 if (break_on_load
) {
3970 synclinkmp_get_text_ptr();
3974 printk("%s %s\n", driver_name
, driver_version
);
3976 if ((rc
= pci_register_driver(&synclinkmp_pci_driver
)) < 0) {
3977 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
3981 serial_driver
= alloc_tty_driver(128);
3982 if (!serial_driver
) {
3987 /* Initialize the tty_driver structure */
3989 serial_driver
->driver_name
= "synclinkmp";
3990 serial_driver
->name
= "ttySLM";
3991 serial_driver
->major
= ttymajor
;
3992 serial_driver
->minor_start
= 64;
3993 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
3994 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
3995 serial_driver
->init_termios
= tty_std_termios
;
3996 serial_driver
->init_termios
.c_cflag
=
3997 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
3998 serial_driver
->init_termios
.c_ispeed
= 9600;
3999 serial_driver
->init_termios
.c_ospeed
= 9600;
4000 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4001 tty_set_operations(serial_driver
, &ops
);
4002 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4003 printk("%s(%d):Couldn't register serial driver\n",
4005 put_tty_driver(serial_driver
);
4006 serial_driver
= NULL
;
4010 printk("%s %s, tty major#%d\n",
4011 driver_name
, driver_version
,
4012 serial_driver
->major
);
4017 synclinkmp_cleanup();
4021 static void __exit
synclinkmp_exit(void)
4023 synclinkmp_cleanup();
4026 module_init(synclinkmp_init
);
4027 module_exit(synclinkmp_exit
);
4029 /* Set the port for internal loopback mode.
4030 * The TxCLK and RxCLK signals are generated from the BRG and
4031 * the TxD is looped back to the RxD internally.
4033 static void enable_loopback(SLMP_INFO
*info
, int enable
)
4036 /* MD2 (Mode Register 2)
4037 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4039 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) | (BIT1
+ BIT0
)));
4041 /* degate external TxC clock source */
4042 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4043 write_control_reg(info
);
4045 /* RXS/TXS (Rx/Tx clock source)
4046 * 07 Reserved, must be 0
4047 * 06..04 Clock Source, 100=BRG
4048 * 03..00 Clock Divisor, 0000=1
4050 write_reg(info
, RXS
, 0x40);
4051 write_reg(info
, TXS
, 0x40);
4054 /* MD2 (Mode Register 2)
4055 * 01..00 CNCT<1..0> Channel connection, 0=normal
4057 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) & ~(BIT1
+ BIT0
)));
4059 /* RXS/TXS (Rx/Tx clock source)
4060 * 07 Reserved, must be 0
4061 * 06..04 Clock Source, 000=RxC/TxC Pin
4062 * 03..00 Clock Divisor, 0000=1
4064 write_reg(info
, RXS
, 0x00);
4065 write_reg(info
, TXS
, 0x00);
4068 /* set LinkSpeed if available, otherwise default to 2Mbps */
4069 if (info
->params
.clock_speed
)
4070 set_rate(info
, info
->params
.clock_speed
);
4072 set_rate(info
, 3686400);
4075 /* Set the baud rate register to the desired speed
4077 * data_rate data rate of clock in bits per second
4078 * A data rate of 0 disables the AUX clock.
4080 static void set_rate( SLMP_INFO
*info
, u32 data_rate
)
4083 unsigned char BRValue
;
4086 /* fBRG = fCLK/(TMC * 2^BR)
4088 if (data_rate
!= 0) {
4089 Divisor
= 14745600/data_rate
;
4096 if (TMCValue
!= 1 && TMCValue
!= 2) {
4097 /* BRValue of 0 provides 50/50 duty cycle *only* when
4098 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4105 /* while TMCValue is too big for TMC register, divide
4106 * by 2 and increment BR exponent.
4108 for(; TMCValue
> 256 && BRValue
< 10; BRValue
++)
4111 write_reg(info
, TXS
,
4112 (unsigned char)((read_reg(info
, TXS
) & 0xf0) | BRValue
));
4113 write_reg(info
, RXS
,
4114 (unsigned char)((read_reg(info
, RXS
) & 0xf0) | BRValue
));
4115 write_reg(info
, TMC
, (unsigned char)TMCValue
);
4118 write_reg(info
, TXS
,0);
4119 write_reg(info
, RXS
,0);
4120 write_reg(info
, TMC
, 0);
4126 static void rx_stop(SLMP_INFO
*info
)
4128 if (debug_level
>= DEBUG_LEVEL_ISR
)
4129 printk("%s(%d):%s rx_stop()\n",
4130 __FILE__
,__LINE__
, info
->device_name
);
4132 write_reg(info
, CMD
, RXRESET
);
4134 info
->ie0_value
&= ~RXRDYE
;
4135 write_reg(info
, IE0
, info
->ie0_value
); /* disable Rx data interrupts */
4137 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4138 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4139 write_reg(info
, RXDMA
+ DIR, 0); /* disable Rx DMA interrupts */
4141 info
->rx_enabled
= false;
4142 info
->rx_overflow
= false;
4145 /* enable the receiver
4147 static void rx_start(SLMP_INFO
*info
)
4151 if (debug_level
>= DEBUG_LEVEL_ISR
)
4152 printk("%s(%d):%s rx_start()\n",
4153 __FILE__
,__LINE__
, info
->device_name
);
4155 write_reg(info
, CMD
, RXRESET
);
4157 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
4158 /* HDLC, disabe IRQ on rxdata */
4159 info
->ie0_value
&= ~RXRDYE
;
4160 write_reg(info
, IE0
, info
->ie0_value
);
4162 /* Reset all Rx DMA buffers and program rx dma */
4163 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4164 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4166 for (i
= 0; i
< info
->rx_buf_count
; i
++) {
4167 info
->rx_buf_list
[i
].status
= 0xff;
4169 // throttle to 4 shared memory writes at a time to prevent
4170 // hogging local bus (keep latency time for DMA requests low).
4172 read_status_reg(info
);
4174 info
->current_rx_buf
= 0;
4176 /* set current/1st descriptor address */
4177 write_reg16(info
, RXDMA
+ CDA
,
4178 info
->rx_buf_list_ex
[0].phys_entry
);
4180 /* set new last rx descriptor address */
4181 write_reg16(info
, RXDMA
+ EDA
,
4182 info
->rx_buf_list_ex
[info
->rx_buf_count
- 1].phys_entry
);
4184 /* set buffer length (shared by all rx dma data buffers) */
4185 write_reg16(info
, RXDMA
+ BFL
, SCABUFSIZE
);
4187 write_reg(info
, RXDMA
+ DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4188 write_reg(info
, RXDMA
+ DSR
, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4190 /* async, enable IRQ on rxdata */
4191 info
->ie0_value
|= RXRDYE
;
4192 write_reg(info
, IE0
, info
->ie0_value
);
4195 write_reg(info
, CMD
, RXENABLE
);
4197 info
->rx_overflow
= false;
4198 info
->rx_enabled
= true;
4201 /* Enable the transmitter and send a transmit frame if
4202 * one is loaded in the DMA buffers.
4204 static void tx_start(SLMP_INFO
*info
)
4206 if (debug_level
>= DEBUG_LEVEL_ISR
)
4207 printk("%s(%d):%s tx_start() tx_count=%d\n",
4208 __FILE__
,__LINE__
, info
->device_name
,info
->tx_count
);
4210 if (!info
->tx_enabled
) {
4211 write_reg(info
, CMD
, TXRESET
);
4212 write_reg(info
, CMD
, TXENABLE
);
4213 info
->tx_enabled
= true;
4216 if ( info
->tx_count
) {
4218 /* If auto RTS enabled and RTS is inactive, then assert */
4219 /* RTS and set a flag indicating that the driver should */
4220 /* negate RTS when the transmission completes. */
4222 info
->drop_rts_on_tx_done
= false;
4224 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
4226 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
4227 get_signals( info
);
4228 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
4229 info
->serial_signals
|= SerialSignal_RTS
;
4230 set_signals( info
);
4231 info
->drop_rts_on_tx_done
= true;
4235 write_reg16(info
, TRC0
,
4236 (unsigned short)(((tx_negate_fifo_level
-1)<<8) + tx_active_fifo_level
));
4238 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4239 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4241 /* set TX CDA (current descriptor address) */
4242 write_reg16(info
, TXDMA
+ CDA
,
4243 info
->tx_buf_list_ex
[0].phys_entry
);
4245 /* set TX EDA (last descriptor address) */
4246 write_reg16(info
, TXDMA
+ EDA
,
4247 info
->tx_buf_list_ex
[info
->last_tx_buf
].phys_entry
);
4249 /* enable underrun IRQ */
4250 info
->ie1_value
&= ~IDLE
;
4251 info
->ie1_value
|= UDRN
;
4252 write_reg(info
, IE1
, info
->ie1_value
);
4253 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
));
4255 write_reg(info
, TXDMA
+ DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4256 write_reg(info
, TXDMA
+ DSR
, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4258 mod_timer(&info
->tx_timer
, jiffies
+
4259 msecs_to_jiffies(5000));
4263 /* async, enable IRQ on txdata */
4264 info
->ie0_value
|= TXRDYE
;
4265 write_reg(info
, IE0
, info
->ie0_value
);
4268 info
->tx_active
= true;
4272 /* stop the transmitter and DMA
4274 static void tx_stop( SLMP_INFO
*info
)
4276 if (debug_level
>= DEBUG_LEVEL_ISR
)
4277 printk("%s(%d):%s tx_stop()\n",
4278 __FILE__
,__LINE__
, info
->device_name
);
4280 del_timer(&info
->tx_timer
);
4282 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4283 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4285 write_reg(info
, CMD
, TXRESET
);
4287 info
->ie1_value
&= ~(UDRN
+ IDLE
);
4288 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
4289 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
4291 info
->ie0_value
&= ~TXRDYE
;
4292 write_reg(info
, IE0
, info
->ie0_value
); /* disable tx data interrupts */
4294 info
->tx_enabled
= false;
4295 info
->tx_active
= false;
4298 /* Fill the transmit FIFO until the FIFO is full or
4299 * there is no more data to load.
4301 static void tx_load_fifo(SLMP_INFO
*info
)
4305 /* do nothing is now tx data available and no XON/XOFF pending */
4307 if ( !info
->tx_count
&& !info
->x_char
)
4310 /* load the Transmit FIFO until FIFOs full or all data sent */
4312 while( info
->tx_count
&& (read_reg(info
,SR0
) & BIT1
) ) {
4314 /* there is more space in the transmit FIFO and */
4315 /* there is more data in transmit buffer */
4317 if ( (info
->tx_count
> 1) && !info
->x_char
) {
4319 TwoBytes
[0] = info
->tx_buf
[info
->tx_get
++];
4320 if (info
->tx_get
>= info
->max_frame_size
)
4321 info
->tx_get
-= info
->max_frame_size
;
4322 TwoBytes
[1] = info
->tx_buf
[info
->tx_get
++];
4323 if (info
->tx_get
>= info
->max_frame_size
)
4324 info
->tx_get
-= info
->max_frame_size
;
4326 write_reg16(info
, TRB
, *((u16
*)TwoBytes
));
4328 info
->tx_count
-= 2;
4329 info
->icount
.tx
+= 2;
4331 /* only 1 byte left to transmit or 1 FIFO slot left */
4334 /* transmit pending high priority char */
4335 write_reg(info
, TRB
, info
->x_char
);
4338 write_reg(info
, TRB
, info
->tx_buf
[info
->tx_get
++]);
4339 if (info
->tx_get
>= info
->max_frame_size
)
4340 info
->tx_get
-= info
->max_frame_size
;
4348 /* Reset a port to a known state
4350 static void reset_port(SLMP_INFO
*info
)
4352 if (info
->sca_base
) {
4357 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
4360 /* disable all port interrupts */
4361 info
->ie0_value
= 0;
4362 info
->ie1_value
= 0;
4363 info
->ie2_value
= 0;
4364 write_reg(info
, IE0
, info
->ie0_value
);
4365 write_reg(info
, IE1
, info
->ie1_value
);
4366 write_reg(info
, IE2
, info
->ie2_value
);
4368 write_reg(info
, CMD
, CHRESET
);
4372 /* Reset all the ports to a known state.
4374 static void reset_adapter(SLMP_INFO
*info
)
4378 for ( i
=0; i
< SCA_MAX_PORTS
; ++i
) {
4379 if (info
->port_array
[i
])
4380 reset_port(info
->port_array
[i
]);
4384 /* Program port for asynchronous communications.
4386 static void async_mode(SLMP_INFO
*info
)
4389 unsigned char RegValue
;
4394 /* MD0, Mode Register 0
4396 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4397 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4398 * 03 Reserved, must be 0
4399 * 02 CRCCC, CRC Calculation, 0=disabled
4400 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4405 if (info
->params
.stop_bits
!= 1)
4407 write_reg(info
, MD0
, RegValue
);
4409 /* MD1, Mode Register 1
4411 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4412 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4413 * 03..02 RXCHR<1..0>, rx char size
4414 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4419 switch (info
->params
.data_bits
) {
4420 case 7: RegValue
|= BIT4
+ BIT2
; break;
4421 case 6: RegValue
|= BIT5
+ BIT3
; break;
4422 case 5: RegValue
|= BIT5
+ BIT4
+ BIT3
+ BIT2
; break;
4424 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
4426 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
4429 write_reg(info
, MD1
, RegValue
);
4431 /* MD2, Mode Register 2
4433 * 07..02 Reserved, must be 0
4434 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4439 if (info
->params
.loopback
)
4440 RegValue
|= (BIT1
+ BIT0
);
4441 write_reg(info
, MD2
, RegValue
);
4443 /* RXS, Receive clock source
4445 * 07 Reserved, must be 0
4446 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4447 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4450 write_reg(info
, RXS
, RegValue
);
4452 /* TXS, Transmit clock source
4454 * 07 Reserved, must be 0
4455 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4456 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4459 write_reg(info
, TXS
, RegValue
);
4463 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4465 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4466 write_control_reg(info
);
4470 /* RRC Receive Ready Control 0
4472 * 07..05 Reserved, must be 0
4473 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4475 write_reg(info
, RRC
, 0x00);
4477 /* TRC0 Transmit Ready Control 0
4479 * 07..05 Reserved, must be 0
4480 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4482 write_reg(info
, TRC0
, 0x10);
4484 /* TRC1 Transmit Ready Control 1
4486 * 07..05 Reserved, must be 0
4487 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4489 write_reg(info
, TRC1
, 0x1e);
4491 /* CTL, MSCI control register
4493 * 07..06 Reserved, set to 0
4494 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4495 * 04 IDLC, idle control, 0=mark 1=idle register
4496 * 03 BRK, break, 0=off 1 =on (async)
4497 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4498 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4499 * 00 RTS, RTS output control, 0=active 1=inactive
4504 if (!(info
->serial_signals
& SerialSignal_RTS
))
4506 write_reg(info
, CTL
, RegValue
);
4508 /* enable status interrupts */
4509 info
->ie0_value
|= TXINTE
+ RXINTE
;
4510 write_reg(info
, IE0
, info
->ie0_value
);
4512 /* enable break detect interrupt */
4513 info
->ie1_value
= BRKD
;
4514 write_reg(info
, IE1
, info
->ie1_value
);
4516 /* enable rx overrun interrupt */
4517 info
->ie2_value
= OVRN
;
4518 write_reg(info
, IE2
, info
->ie2_value
);
4520 set_rate( info
, info
->params
.data_rate
* 16 );
4523 /* Program the SCA for HDLC communications.
4525 static void hdlc_mode(SLMP_INFO
*info
)
4527 unsigned char RegValue
;
4530 // Can't use DPLL because SCA outputs recovered clock on RxC when
4531 // DPLL mode selected. This causes output contention with RxC receiver.
4532 // Use of DPLL would require external hardware to disable RxC receiver
4533 // when DPLL mode selected.
4534 info
->params
.flags
&= ~(HDLC_FLAG_TXC_DPLL
+ HDLC_FLAG_RXC_DPLL
);
4536 /* disable DMA interrupts */
4537 write_reg(info
, TXDMA
+ DIR, 0);
4538 write_reg(info
, RXDMA
+ DIR, 0);
4540 /* MD0, Mode Register 0
4542 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4543 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4544 * 03 Reserved, must be 0
4545 * 02 CRCCC, CRC Calculation, 1=enabled
4546 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4547 * 00 CRC0, CRC initial value, 1 = all 1s
4552 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
4554 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
4556 if (info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
4557 RegValue
|= BIT2
+ BIT1
;
4558 write_reg(info
, MD0
, RegValue
);
4560 /* MD1, Mode Register 1
4562 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4563 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4564 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4565 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4570 write_reg(info
, MD1
, RegValue
);
4572 /* MD2, Mode Register 2
4574 * 07 NRZFM, 0=NRZ, 1=FM
4575 * 06..05 CODE<1..0> Encoding, 00=NRZ
4576 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4577 * 02 Reserved, must be 0
4578 * 01..00 CNCT<1..0> Channel connection, 0=normal
4583 switch(info
->params
.encoding
) {
4584 case HDLC_ENCODING_NRZI
: RegValue
|= BIT5
; break;
4585 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT7
+ BIT5
; break; /* aka FM1 */
4586 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT7
+ BIT6
; break; /* aka FM0 */
4587 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT7
; break; /* aka Manchester */
4589 case HDLC_ENCODING_NRZB
: /* not supported */
4590 case HDLC_ENCODING_NRZI_MARK
: /* not supported */
4591 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: /* not supported */
4594 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4597 } else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4603 write_reg(info
, MD2
, RegValue
);
4606 /* RXS, Receive clock source
4608 * 07 Reserved, must be 0
4609 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4610 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4613 if (info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4615 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4616 RegValue
|= BIT6
+ BIT5
;
4617 write_reg(info
, RXS
, RegValue
);
4619 /* TXS, Transmit clock source
4621 * 07 Reserved, must be 0
4622 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4623 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4626 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4628 if (info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4629 RegValue
|= BIT6
+ BIT5
;
4630 write_reg(info
, TXS
, RegValue
);
4632 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4633 set_rate(info
, info
->params
.clock_speed
* DpllDivisor
);
4635 set_rate(info
, info
->params
.clock_speed
);
4637 /* GPDATA (General Purpose I/O Data Register)
4639 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4641 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4642 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4644 info
->port_array
[0]->ctrlreg_value
&= ~(BIT0
<< (info
->port_num
* 2));
4645 write_control_reg(info
);
4647 /* RRC Receive Ready Control 0
4649 * 07..05 Reserved, must be 0
4650 * 04..00 RRC<4..0> Rx FIFO trigger active
4652 write_reg(info
, RRC
, rx_active_fifo_level
);
4654 /* TRC0 Transmit Ready Control 0
4656 * 07..05 Reserved, must be 0
4657 * 04..00 TRC<4..0> Tx FIFO trigger active
4659 write_reg(info
, TRC0
, tx_active_fifo_level
);
4661 /* TRC1 Transmit Ready Control 1
4663 * 07..05 Reserved, must be 0
4664 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4666 write_reg(info
, TRC1
, (unsigned char)(tx_negate_fifo_level
- 1));
4668 /* DMR, DMA Mode Register
4670 * 07..05 Reserved, must be 0
4671 * 04 TMOD, Transfer Mode: 1=chained-block
4672 * 03 Reserved, must be 0
4673 * 02 NF, Number of Frames: 1=multi-frame
4674 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4675 * 00 Reserved, must be 0
4679 write_reg(info
, TXDMA
+ DMR
, 0x14);
4680 write_reg(info
, RXDMA
+ DMR
, 0x14);
4682 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4683 write_reg(info
, RXDMA
+ CPB
,
4684 (unsigned char)(info
->buffer_list_phys
>> 16));
4686 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4687 write_reg(info
, TXDMA
+ CPB
,
4688 (unsigned char)(info
->buffer_list_phys
>> 16));
4690 /* enable status interrupts. other code enables/disables
4691 * the individual sources for these two interrupt classes.
4693 info
->ie0_value
|= TXINTE
+ RXINTE
;
4694 write_reg(info
, IE0
, info
->ie0_value
);
4696 /* CTL, MSCI control register
4698 * 07..06 Reserved, set to 0
4699 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4700 * 04 IDLC, idle control, 0=mark 1=idle register
4701 * 03 BRK, break, 0=off 1 =on (async)
4702 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4703 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4704 * 00 RTS, RTS output control, 0=active 1=inactive
4709 if (!(info
->serial_signals
& SerialSignal_RTS
))
4711 write_reg(info
, CTL
, RegValue
);
4713 /* preamble not supported ! */
4719 set_rate(info
, info
->params
.clock_speed
);
4721 if (info
->params
.loopback
)
4722 enable_loopback(info
,1);
4725 /* Set the transmit HDLC idle mode
4727 static void tx_set_idle(SLMP_INFO
*info
)
4729 unsigned char RegValue
= 0xff;
4731 /* Map API idle mode to SCA register bits */
4732 switch(info
->idle_mode
) {
4733 case HDLC_TXIDLE_FLAGS
: RegValue
= 0x7e; break;
4734 case HDLC_TXIDLE_ALT_ZEROS_ONES
: RegValue
= 0xaa; break;
4735 case HDLC_TXIDLE_ZEROS
: RegValue
= 0x00; break;
4736 case HDLC_TXIDLE_ONES
: RegValue
= 0xff; break;
4737 case HDLC_TXIDLE_ALT_MARK_SPACE
: RegValue
= 0xaa; break;
4738 case HDLC_TXIDLE_SPACE
: RegValue
= 0x00; break;
4739 case HDLC_TXIDLE_MARK
: RegValue
= 0xff; break;
4742 write_reg(info
, IDL
, RegValue
);
4745 /* Query the adapter for the state of the V24 status (input) signals.
4747 static void get_signals(SLMP_INFO
*info
)
4749 u16 status
= read_reg(info
, SR3
);
4750 u16 gpstatus
= read_status_reg(info
);
4753 /* clear all serial signals except DTR and RTS */
4754 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
4756 /* set serial signal bits to reflect MISR */
4758 if (!(status
& BIT3
))
4759 info
->serial_signals
|= SerialSignal_CTS
;
4761 if ( !(status
& BIT2
))
4762 info
->serial_signals
|= SerialSignal_DCD
;
4764 testbit
= BIT1
<< (info
->port_num
* 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4765 if (!(gpstatus
& testbit
))
4766 info
->serial_signals
|= SerialSignal_RI
;
4768 testbit
= BIT0
<< (info
->port_num
* 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4769 if (!(gpstatus
& testbit
))
4770 info
->serial_signals
|= SerialSignal_DSR
;
4773 /* Set the state of DTR and RTS based on contents of
4774 * serial_signals member of device context.
4776 static void set_signals(SLMP_INFO
*info
)
4778 unsigned char RegValue
;
4781 RegValue
= read_reg(info
, CTL
);
4782 if (info
->serial_signals
& SerialSignal_RTS
)
4786 write_reg(info
, CTL
, RegValue
);
4788 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4789 EnableBit
= BIT1
<< (info
->port_num
*2);
4790 if (info
->serial_signals
& SerialSignal_DTR
)
4791 info
->port_array
[0]->ctrlreg_value
&= ~EnableBit
;
4793 info
->port_array
[0]->ctrlreg_value
|= EnableBit
;
4794 write_control_reg(info
);
4797 /*******************/
4798 /* DMA Buffer Code */
4799 /*******************/
4801 /* Set the count for all receive buffers to SCABUFSIZE
4802 * and set the current buffer to the first buffer. This effectively
4803 * makes all buffers free and discards any data in buffers.
4805 static void rx_reset_buffers(SLMP_INFO
*info
)
4807 rx_free_frame_buffers(info
, 0, info
->rx_buf_count
- 1);
4810 /* Free the buffers used by a received frame
4812 * info pointer to device instance data
4813 * first index of 1st receive buffer of frame
4814 * last index of last receive buffer of frame
4816 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
)
4821 /* reset current buffer for reuse */
4822 info
->rx_buf_list
[first
].status
= 0xff;
4824 if (first
== last
) {
4826 /* set new last rx descriptor address */
4827 write_reg16(info
, RXDMA
+ EDA
, info
->rx_buf_list_ex
[first
].phys_entry
);
4831 if (first
== info
->rx_buf_count
)
4835 /* set current buffer to next buffer after last buffer of frame */
4836 info
->current_rx_buf
= first
;
4839 /* Return a received frame from the receive DMA buffers.
4840 * Only frames received without errors are returned.
4842 * Return Value: true if frame returned, otherwise false
4844 static bool rx_get_frame(SLMP_INFO
*info
)
4846 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
4847 unsigned short status
;
4848 unsigned int framesize
= 0;
4849 bool ReturnCode
= false;
4850 unsigned long flags
;
4851 struct tty_struct
*tty
= info
->port
.tty
;
4852 unsigned char addr_field
= 0xff;
4854 SCADESC_EX
*desc_ex
;
4857 /* assume no frame returned, set zero length */
4862 * current_rx_buf points to the 1st buffer of the next available
4863 * receive frame. To find the last buffer of the frame look for
4864 * a non-zero status field in the buffer entries. (The status
4865 * field is set by the 16C32 after completing a receive frame.
4867 StartIndex
= EndIndex
= info
->current_rx_buf
;
4870 desc
= &info
->rx_buf_list
[EndIndex
];
4871 desc_ex
= &info
->rx_buf_list_ex
[EndIndex
];
4873 if (desc
->status
== 0xff)
4874 goto Cleanup
; /* current desc still in use, no frames available */
4876 if (framesize
== 0 && info
->params
.addr_filter
!= 0xff)
4877 addr_field
= desc_ex
->virt_addr
[0];
4879 framesize
+= desc
->length
;
4881 /* Status != 0 means last buffer of frame */
4886 if (EndIndex
== info
->rx_buf_count
)
4889 if (EndIndex
== info
->current_rx_buf
) {
4890 /* all buffers have been 'used' but none mark */
4891 /* the end of a frame. Reset buffers and receiver. */
4892 if ( info
->rx_enabled
){
4893 spin_lock_irqsave(&info
->lock
,flags
);
4895 spin_unlock_irqrestore(&info
->lock
,flags
);
4902 /* check status of receive frame */
4904 /* frame status is byte stored after frame data
4906 * 7 EOM (end of msg), 1 = last buffer of frame
4907 * 6 Short Frame, 1 = short frame
4908 * 5 Abort, 1 = frame aborted
4909 * 4 Residue, 1 = last byte is partial
4910 * 3 Overrun, 1 = overrun occurred during frame reception
4911 * 2 CRC, 1 = CRC error detected
4914 status
= desc
->status
;
4916 /* ignore CRC bit if not using CRC (bit is undefined) */
4917 /* Note:CRC is not save to data buffer */
4918 if (info
->params
.crc_type
== HDLC_CRC_NONE
)
4921 if (framesize
== 0 ||
4922 (addr_field
!= 0xff && addr_field
!= info
->params
.addr_filter
)) {
4923 /* discard 0 byte frames, this seems to occur sometime
4924 * when remote is idling flags.
4926 rx_free_frame_buffers(info
, StartIndex
, EndIndex
);
4933 if (status
& (BIT6
+BIT5
+BIT3
+BIT2
)) {
4934 /* received frame has errors,
4935 * update counts and mark frame size as 0
4938 info
->icount
.rxshort
++;
4939 else if (status
& BIT5
)
4940 info
->icount
.rxabort
++;
4941 else if (status
& BIT3
)
4942 info
->icount
.rxover
++;
4944 info
->icount
.rxcrc
++;
4947 #if SYNCLINK_GENERIC_HDLC
4949 info
->netdev
->stats
.rx_errors
++;
4950 info
->netdev
->stats
.rx_frame_errors
++;
4955 if ( debug_level
>= DEBUG_LEVEL_BH
)
4956 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4957 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
4959 if ( debug_level
>= DEBUG_LEVEL_DATA
)
4960 trace_block(info
,info
->rx_buf_list_ex
[StartIndex
].virt_addr
,
4961 min_t(unsigned int, framesize
, SCABUFSIZE
), 0);
4964 if (framesize
> info
->max_frame_size
)
4965 info
->icount
.rxlong
++;
4967 /* copy dma buffer(s) to contiguous intermediate buffer */
4968 int copy_count
= framesize
;
4969 int index
= StartIndex
;
4970 unsigned char *ptmp
= info
->tmp_rx_buf
;
4971 info
->tmp_rx_buf_count
= framesize
;
4973 info
->icount
.rxok
++;
4976 int partial_count
= min(copy_count
,SCABUFSIZE
);
4978 info
->rx_buf_list_ex
[index
].virt_addr
,
4980 ptmp
+= partial_count
;
4981 copy_count
-= partial_count
;
4983 if ( ++index
== info
->rx_buf_count
)
4987 #if SYNCLINK_GENERIC_HDLC
4989 hdlcdev_rx(info
,info
->tmp_rx_buf
,framesize
);
4992 ldisc_receive_buf(tty
,info
->tmp_rx_buf
,
4993 info
->flag_buf
, framesize
);
4996 /* Free the buffers used by this frame. */
4997 rx_free_frame_buffers( info
, StartIndex
, EndIndex
);
5002 if ( info
->rx_enabled
&& info
->rx_overflow
) {
5003 /* Receiver is enabled, but needs to restarted due to
5004 * rx buffer overflow. If buffers are empty, restart receiver.
5006 if (info
->rx_buf_list
[EndIndex
].status
== 0xff) {
5007 spin_lock_irqsave(&info
->lock
,flags
);
5009 spin_unlock_irqrestore(&info
->lock
,flags
);
5016 /* load the transmit DMA buffer with data
5018 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
)
5020 unsigned short copy_count
;
5023 SCADESC_EX
*desc_ex
;
5025 if ( debug_level
>= DEBUG_LEVEL_DATA
)
5026 trace_block(info
, buf
, min_t(unsigned int, count
, SCABUFSIZE
), 1);
5028 /* Copy source buffer to one or more DMA buffers, starting with
5029 * the first transmit dma buffer.
5033 copy_count
= min_t(unsigned int, count
, SCABUFSIZE
);
5035 desc
= &info
->tx_buf_list
[i
];
5036 desc_ex
= &info
->tx_buf_list_ex
[i
];
5038 load_pci_memory(info
, desc_ex
->virt_addr
,buf
,copy_count
);
5040 desc
->length
= copy_count
;
5044 count
-= copy_count
;
5050 if (i
>= info
->tx_buf_count
)
5054 info
->tx_buf_list
[i
].status
= 0x81; /* set EOM and EOT status */
5055 info
->last_tx_buf
= ++i
;
5058 static bool register_test(SLMP_INFO
*info
)
5060 static unsigned char testval
[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5061 static unsigned int count
= ARRAY_SIZE(testval
);
5064 unsigned long flags
;
5066 spin_lock_irqsave(&info
->lock
,flags
);
5069 /* assume failure */
5070 info
->init_error
= DiagStatus_AddressFailure
;
5072 /* Write bit patterns to various registers but do it out of */
5073 /* sync, then read back and verify values. */
5075 for (i
= 0 ; i
< count
; i
++) {
5076 write_reg(info
, TMC
, testval
[i
]);
5077 write_reg(info
, IDL
, testval
[(i
+1)%count
]);
5078 write_reg(info
, SA0
, testval
[(i
+2)%count
]);
5079 write_reg(info
, SA1
, testval
[(i
+3)%count
]);
5081 if ( (read_reg(info
, TMC
) != testval
[i
]) ||
5082 (read_reg(info
, IDL
) != testval
[(i
+1)%count
]) ||
5083 (read_reg(info
, SA0
) != testval
[(i
+2)%count
]) ||
5084 (read_reg(info
, SA1
) != testval
[(i
+3)%count
]) )
5092 spin_unlock_irqrestore(&info
->lock
,flags
);
5097 static bool irq_test(SLMP_INFO
*info
)
5099 unsigned long timeout
;
5100 unsigned long flags
;
5102 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
5104 spin_lock_irqsave(&info
->lock
,flags
);
5107 /* assume failure */
5108 info
->init_error
= DiagStatus_IrqFailure
;
5109 info
->irq_occurred
= false;
5111 /* setup timer0 on SCA0 to interrupt */
5113 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5114 write_reg(info
, IER2
, (unsigned char)((info
->port_num
& 1) ? BIT6
: BIT4
));
5116 write_reg(info
, (unsigned char)(timer
+ TEPR
), 0); /* timer expand prescale */
5117 write_reg16(info
, (unsigned char)(timer
+ TCONR
), 1); /* timer constant */
5120 /* TMCS, Timer Control/Status Register
5122 * 07 CMF, Compare match flag (read only) 1=match
5123 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5124 * 05 Reserved, must be 0
5125 * 04 TME, Timer Enable
5126 * 03..00 Reserved, must be 0
5130 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0x50);
5132 spin_unlock_irqrestore(&info
->lock
,flags
);
5135 while( timeout
-- && !info
->irq_occurred
) {
5136 msleep_interruptible(10);
5139 spin_lock_irqsave(&info
->lock
,flags
);
5141 spin_unlock_irqrestore(&info
->lock
,flags
);
5143 return info
->irq_occurred
;
5146 /* initialize individual SCA device (2 ports)
5148 static bool sca_init(SLMP_INFO
*info
)
5150 /* set wait controller to single mem partition (low), no wait states */
5151 write_reg(info
, PABR0
, 0); /* wait controller addr boundary 0 */
5152 write_reg(info
, PABR1
, 0); /* wait controller addr boundary 1 */
5153 write_reg(info
, WCRL
, 0); /* wait controller low range */
5154 write_reg(info
, WCRM
, 0); /* wait controller mid range */
5155 write_reg(info
, WCRH
, 0); /* wait controller high range */
5157 /* DPCR, DMA Priority Control
5159 * 07..05 Not used, must be 0
5160 * 04 BRC, bus release condition: 0=all transfers complete
5161 * 03 CCC, channel change condition: 0=every cycle
5162 * 02..00 PR<2..0>, priority 100=round robin
5166 write_reg(info
, DPCR
, dma_priority
);
5168 /* DMA Master Enable, BIT7: 1=enable all channels */
5169 write_reg(info
, DMER
, 0x80);
5171 /* enable all interrupt classes */
5172 write_reg(info
, IER0
, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5173 write_reg(info
, IER1
, 0xff); /* DMIB,DMIA (channels 0-3) */
5174 write_reg(info
, IER2
, 0xf0); /* TIRQ (timers 0-3) */
5176 /* ITCR, interrupt control register
5177 * 07 IPC, interrupt priority, 0=MSCI->DMA
5178 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5179 * 04 VOS, Vector Output, 0=unmodified vector
5180 * 03..00 Reserved, must be 0
5182 write_reg(info
, ITCR
, 0);
5187 /* initialize adapter hardware
5189 static bool init_adapter(SLMP_INFO
*info
)
5193 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5194 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5197 info
->misc_ctrl_value
|= BIT30
;
5198 *MiscCtrl
= info
->misc_ctrl_value
;
5201 * Force at least 170ns delay before clearing
5202 * reset bit. Each read from LCR takes at least
5203 * 30ns so 10 times for 300ns to be safe.
5206 readval
= *MiscCtrl
;
5208 info
->misc_ctrl_value
&= ~BIT30
;
5209 *MiscCtrl
= info
->misc_ctrl_value
;
5211 /* init control reg (all DTRs off, all clksel=input) */
5212 info
->ctrlreg_value
= 0xaa;
5213 write_control_reg(info
);
5216 volatile u32
*LCR1BRDR
= (u32
*)(info
->lcr_base
+ 0x2c);
5217 lcr1_brdr_value
&= ~(BIT5
+ BIT4
+ BIT3
);
5219 switch(read_ahead_count
)
5222 lcr1_brdr_value
|= BIT5
+ BIT4
+ BIT3
;
5225 lcr1_brdr_value
|= BIT5
+ BIT4
;
5228 lcr1_brdr_value
|= BIT5
+ BIT3
;
5231 lcr1_brdr_value
|= BIT5
;
5235 *LCR1BRDR
= lcr1_brdr_value
;
5236 *MiscCtrl
= misc_ctrl_value
;
5239 sca_init(info
->port_array
[0]);
5240 sca_init(info
->port_array
[2]);
5245 /* Loopback an HDLC frame to test the hardware
5246 * interrupt and DMA functions.
5248 static bool loopback_test(SLMP_INFO
*info
)
5250 #define TESTFRAMESIZE 20
5252 unsigned long timeout
;
5253 u16 count
= TESTFRAMESIZE
;
5254 unsigned char buf
[TESTFRAMESIZE
];
5256 unsigned long flags
;
5258 struct tty_struct
*oldtty
= info
->port
.tty
;
5259 u32 speed
= info
->params
.clock_speed
;
5261 info
->params
.clock_speed
= 3686400;
5262 info
->port
.tty
= NULL
;
5264 /* assume failure */
5265 info
->init_error
= DiagStatus_DmaFailure
;
5267 /* build and send transmit frame */
5268 for (count
= 0; count
< TESTFRAMESIZE
;++count
)
5269 buf
[count
] = (unsigned char)count
;
5271 memset(info
->tmp_rx_buf
,0,TESTFRAMESIZE
);
5273 /* program hardware for HDLC and enabled receiver */
5274 spin_lock_irqsave(&info
->lock
,flags
);
5276 enable_loopback(info
,1);
5278 info
->tx_count
= count
;
5279 tx_load_dma_buffer(info
,buf
,count
);
5281 spin_unlock_irqrestore(&info
->lock
,flags
);
5283 /* wait for receive complete */
5284 /* Set a timeout for waiting for interrupt. */
5285 for ( timeout
= 100; timeout
; --timeout
) {
5286 msleep_interruptible(10);
5288 if (rx_get_frame(info
)) {
5294 /* verify received frame length and contents */
5296 ( info
->tmp_rx_buf_count
!= count
||
5297 memcmp(buf
, info
->tmp_rx_buf
,count
))) {
5301 spin_lock_irqsave(&info
->lock
,flags
);
5302 reset_adapter(info
);
5303 spin_unlock_irqrestore(&info
->lock
,flags
);
5305 info
->params
.clock_speed
= speed
;
5306 info
->port
.tty
= oldtty
;
5311 /* Perform diagnostics on hardware
5313 static int adapter_test( SLMP_INFO
*info
)
5315 unsigned long flags
;
5316 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5317 printk( "%s(%d):Testing device %s\n",
5318 __FILE__
,__LINE__
,info
->device_name
);
5320 spin_lock_irqsave(&info
->lock
,flags
);
5322 spin_unlock_irqrestore(&info
->lock
,flags
);
5324 info
->port_array
[0]->port_count
= 0;
5326 if ( register_test(info
->port_array
[0]) &&
5327 register_test(info
->port_array
[1])) {
5329 info
->port_array
[0]->port_count
= 2;
5331 if ( register_test(info
->port_array
[2]) &&
5332 register_test(info
->port_array
[3]) )
5333 info
->port_array
[0]->port_count
+= 2;
5336 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5337 __FILE__
,__LINE__
,info
->device_name
, (unsigned long)(info
->phys_sca_base
));
5341 if ( !irq_test(info
->port_array
[0]) ||
5342 !irq_test(info
->port_array
[1]) ||
5343 (info
->port_count
== 4 && !irq_test(info
->port_array
[2])) ||
5344 (info
->port_count
== 4 && !irq_test(info
->port_array
[3]))) {
5345 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5346 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
5350 if (!loopback_test(info
->port_array
[0]) ||
5351 !loopback_test(info
->port_array
[1]) ||
5352 (info
->port_count
== 4 && !loopback_test(info
->port_array
[2])) ||
5353 (info
->port_count
== 4 && !loopback_test(info
->port_array
[3]))) {
5354 printk( "%s(%d):DMA test failure for device %s\n",
5355 __FILE__
,__LINE__
,info
->device_name
);
5359 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5360 printk( "%s(%d):device %s passed diagnostics\n",
5361 __FILE__
,__LINE__
,info
->device_name
);
5363 info
->port_array
[0]->init_error
= 0;
5364 info
->port_array
[1]->init_error
= 0;
5365 if ( info
->port_count
> 2 ) {
5366 info
->port_array
[2]->init_error
= 0;
5367 info
->port_array
[3]->init_error
= 0;
5373 /* Test the shared memory on a PCI adapter.
5375 static bool memory_test(SLMP_INFO
*info
)
5377 static unsigned long testval
[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5378 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5379 unsigned long count
= ARRAY_SIZE(testval
);
5381 unsigned long limit
= SCA_MEM_SIZE
/sizeof(unsigned long);
5382 unsigned long * addr
= (unsigned long *)info
->memory_base
;
5384 /* Test data lines with test pattern at one location. */
5386 for ( i
= 0 ; i
< count
; i
++ ) {
5388 if ( *addr
!= testval
[i
] )
5392 /* Test address lines with incrementing pattern over */
5393 /* entire address range. */
5395 for ( i
= 0 ; i
< limit
; i
++ ) {
5400 addr
= (unsigned long *)info
->memory_base
;
5402 for ( i
= 0 ; i
< limit
; i
++ ) {
5403 if ( *addr
!= i
* 4 )
5408 memset( info
->memory_base
, 0, SCA_MEM_SIZE
);
5412 /* Load data into PCI adapter shared memory.
5414 * The PCI9050 releases control of the local bus
5415 * after completing the current read or write operation.
5417 * While the PCI9050 write FIFO not empty, the
5418 * PCI9050 treats all of the writes as a single transaction
5419 * and does not release the bus. This causes DMA latency problems
5420 * at high speeds when copying large data blocks to the shared memory.
5422 * This function breaks a write into multiple transations by
5423 * interleaving a read which flushes the write FIFO and 'completes'
5424 * the write transation. This allows any pending DMA request to gain control
5425 * of the local bus in a timely fasion.
5427 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
)
5429 /* A load interval of 16 allows for 4 32-bit writes at */
5430 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5432 unsigned short interval
= count
/ sca_pci_load_interval
;
5435 for ( i
= 0 ; i
< interval
; i
++ )
5437 memcpy(dest
, src
, sca_pci_load_interval
);
5438 read_status_reg(info
);
5439 dest
+= sca_pci_load_interval
;
5440 src
+= sca_pci_load_interval
;
5443 memcpy(dest
, src
, count
% sca_pci_load_interval
);
5446 static void trace_block(SLMP_INFO
*info
,const char* data
, int count
, int xmit
)
5451 printk("%s tx data:\n",info
->device_name
);
5453 printk("%s rx data:\n",info
->device_name
);
5461 for(i
=0;i
<linecount
;i
++)
5462 printk("%02X ",(unsigned char)data
[i
]);
5465 for(i
=0;i
<linecount
;i
++) {
5466 if (data
[i
]>=040 && data
[i
]<=0176)
5467 printk("%c",data
[i
]);
5476 } /* end of trace_block() */
5478 /* called when HDLC frame times out
5479 * update stats and do tx completion processing
5481 static void tx_timeout(unsigned long context
)
5483 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5484 unsigned long flags
;
5486 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5487 printk( "%s(%d):%s tx_timeout()\n",
5488 __FILE__
,__LINE__
,info
->device_name
);
5489 if(info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
5490 info
->icount
.txtimeout
++;
5492 spin_lock_irqsave(&info
->lock
,flags
);
5493 info
->tx_active
= false;
5494 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
5496 spin_unlock_irqrestore(&info
->lock
,flags
);
5498 #if SYNCLINK_GENERIC_HDLC
5500 hdlcdev_tx_done(info
);
5506 /* called to periodically check the DSR/RI modem signal input status
5508 static void status_timeout(unsigned long context
)
5511 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5512 unsigned long flags
;
5513 unsigned char delta
;
5516 spin_lock_irqsave(&info
->lock
,flags
);
5518 spin_unlock_irqrestore(&info
->lock
,flags
);
5520 /* check for DSR/RI state change */
5522 delta
= info
->old_signals
^ info
->serial_signals
;
5523 info
->old_signals
= info
->serial_signals
;
5525 if (delta
& SerialSignal_DSR
)
5526 status
|= MISCSTATUS_DSR_LATCHED
|(info
->serial_signals
&SerialSignal_DSR
);
5528 if (delta
& SerialSignal_RI
)
5529 status
|= MISCSTATUS_RI_LATCHED
|(info
->serial_signals
&SerialSignal_RI
);
5531 if (delta
& SerialSignal_DCD
)
5532 status
|= MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
);
5534 if (delta
& SerialSignal_CTS
)
5535 status
|= MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
);
5538 isr_io_pin(info
,status
);
5540 mod_timer(&info
->status_timer
, jiffies
+ msecs_to_jiffies(10));
5544 /* Register Access Routines -
5545 * All registers are memory mapped
5547 #define CALC_REGADDR() \
5548 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5549 if (info->port_num > 1) \
5550 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5551 if ( info->port_num & 1) { \
5553 RegAddr += 0x40; /* DMA access */ \
5554 else if (Addr > 0x1f && Addr < 0x60) \
5555 RegAddr += 0x20; /* MSCI access */ \
5559 static unsigned char read_reg(SLMP_INFO
* info
, unsigned char Addr
)
5564 static void write_reg(SLMP_INFO
* info
, unsigned char Addr
, unsigned char Value
)
5570 static u16
read_reg16(SLMP_INFO
* info
, unsigned char Addr
)
5573 return *((u16
*)RegAddr
);
5576 static void write_reg16(SLMP_INFO
* info
, unsigned char Addr
, u16 Value
)
5579 *((u16
*)RegAddr
) = Value
;
5582 static unsigned char read_status_reg(SLMP_INFO
* info
)
5584 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5588 static void write_control_reg(SLMP_INFO
* info
)
5590 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5591 *RegAddr
= info
->port_array
[0]->ctrlreg_value
;
5595 static int __devinit
synclinkmp_init_one (struct pci_dev
*dev
,
5596 const struct pci_device_id
*ent
)
5598 if (pci_enable_device(dev
)) {
5599 printk("error enabling pci device %p\n", dev
);
5602 device_init( ++synclinkmp_adapter_count
, dev
);
5606 static void __devexit
synclinkmp_remove_one (struct pci_dev
*dev
)