2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
27 * - STALL_IN: non-empty bulk-in pipes cannot be halted
28 * if defined mass storage compliance succeeds but with warnings
32 * if undefined usbtest 13 fails
33 * - TRACE: enable function tracing (depends on DEBUG)
36 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
37 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
38 * - Normal & LPM support
41 * - OK: 0-12, 13 (STALL_IN defined) & 14
42 * - Not Supported: 15 & 16 (ISO)
45 * - Suspend & Remote Wakeup
47 #include <linux/delay.h>
48 #include <linux/device.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/phy/phy.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/idr.h>
54 #include <linux/interrupt.h>
56 #include <linux/kernel.h>
57 #include <linux/slab.h>
58 #include <linux/pm_runtime.h>
59 #include <linux/usb/ch9.h>
60 #include <linux/usb/gadget.h>
61 #include <linux/usb/otg.h>
62 #include <linux/usb/chipidea.h>
63 #include <linux/usb/of.h>
65 #include <linux/phy.h>
66 #include <linux/regulator/consumer.h>
76 /* Controller register map */
77 static const u8 ci_regs_nolpm
[] = {
78 [CAP_CAPLENGTH
] = 0x00U
,
79 [CAP_HCCPARAMS
] = 0x08U
,
80 [CAP_DCCPARAMS
] = 0x24U
,
81 [CAP_TESTMODE
] = 0x38U
,
85 [OP_DEVICEADDR
] = 0x14U
,
86 [OP_ENDPTLISTADDR
] = 0x18U
,
91 [OP_ENDPTSETUPSTAT
] = 0x6CU
,
92 [OP_ENDPTPRIME
] = 0x70U
,
93 [OP_ENDPTFLUSH
] = 0x74U
,
94 [OP_ENDPTSTAT
] = 0x78U
,
95 [OP_ENDPTCOMPLETE
] = 0x7CU
,
96 [OP_ENDPTCTRL
] = 0x80U
,
99 static const u8 ci_regs_lpm
[] = {
100 [CAP_CAPLENGTH
] = 0x00U
,
101 [CAP_HCCPARAMS
] = 0x08U
,
102 [CAP_DCCPARAMS
] = 0x24U
,
103 [CAP_TESTMODE
] = 0xFCU
,
106 [OP_USBINTR
] = 0x08U
,
107 [OP_DEVICEADDR
] = 0x14U
,
108 [OP_ENDPTLISTADDR
] = 0x18U
,
112 [OP_USBMODE
] = 0xC8U
,
113 [OP_ENDPTSETUPSTAT
] = 0xD8U
,
114 [OP_ENDPTPRIME
] = 0xDCU
,
115 [OP_ENDPTFLUSH
] = 0xE0U
,
116 [OP_ENDPTSTAT
] = 0xE4U
,
117 [OP_ENDPTCOMPLETE
] = 0xE8U
,
118 [OP_ENDPTCTRL
] = 0xECU
,
121 static int hw_alloc_regmap(struct ci_hdrc
*ci
, bool is_lpm
)
125 for (i
= 0; i
< OP_ENDPTCTRL
; i
++)
126 ci
->hw_bank
.regmap
[i
] =
127 (i
<= CAP_LAST
? ci
->hw_bank
.cap
: ci
->hw_bank
.op
) +
128 (is_lpm
? ci_regs_lpm
[i
] : ci_regs_nolpm
[i
]);
130 for (; i
<= OP_LAST
; i
++)
131 ci
->hw_bank
.regmap
[i
] = ci
->hw_bank
.op
+
132 4 * (i
- OP_ENDPTCTRL
) +
134 ? ci_regs_lpm
[OP_ENDPTCTRL
]
135 : ci_regs_nolpm
[OP_ENDPTCTRL
]);
140 static enum ci_revision
ci_get_revision(struct ci_hdrc
*ci
)
142 int ver
= hw_read_id_reg(ci
, ID_ID
, VERSION
) >> __ffs(VERSION
);
143 enum ci_revision rev
= CI_REVISION_UNKNOWN
;
146 rev
= hw_read_id_reg(ci
, ID_ID
, REVISION
)
148 rev
+= CI_REVISION_20
;
149 } else if (ver
== 0x0) {
150 rev
= CI_REVISION_1X
;
157 * hw_read_intr_enable: returns interrupt enable register
159 * @ci: the controller
161 * This function returns register data
163 u32
hw_read_intr_enable(struct ci_hdrc
*ci
)
165 return hw_read(ci
, OP_USBINTR
, ~0);
169 * hw_read_intr_status: returns interrupt status register
171 * @ci: the controller
173 * This function returns register data
175 u32
hw_read_intr_status(struct ci_hdrc
*ci
)
177 return hw_read(ci
, OP_USBSTS
, ~0);
181 * hw_port_test_set: writes port test mode (execute without interruption)
184 * This function returns an error code
186 int hw_port_test_set(struct ci_hdrc
*ci
, u8 mode
)
188 const u8 TEST_MODE_MAX
= 7;
190 if (mode
> TEST_MODE_MAX
)
193 hw_write(ci
, OP_PORTSC
, PORTSC_PTC
, mode
<< __ffs(PORTSC_PTC
));
198 * hw_port_test_get: reads port test mode value
200 * @ci: the controller
202 * This function returns port test mode value
204 u8
hw_port_test_get(struct ci_hdrc
*ci
)
206 return hw_read(ci
, OP_PORTSC
, PORTSC_PTC
) >> __ffs(PORTSC_PTC
);
209 static void hw_wait_phy_stable(void)
212 * The phy needs some delay to output the stable status from low
213 * power mode. And for OTGSC, the status inputs are debounced
214 * using a 1 ms time constant, so, delay 2ms for controller to get
215 * the stable status, like vbus and id when the phy leaves low power.
217 usleep_range(2000, 2500);
220 /* The PHY enters/leaves low power mode */
221 static void ci_hdrc_enter_lpm(struct ci_hdrc
*ci
, bool enable
)
223 enum ci_hw_regs reg
= ci
->hw_bank
.lpm
? OP_DEVLC
: OP_PORTSC
;
224 bool lpm
= !!(hw_read(ci
, reg
, PORTSC_PHCD(ci
->hw_bank
.lpm
)));
227 hw_write(ci
, reg
, PORTSC_PHCD(ci
->hw_bank
.lpm
),
228 PORTSC_PHCD(ci
->hw_bank
.lpm
));
229 else if (!enable
&& lpm
)
230 hw_write(ci
, reg
, PORTSC_PHCD(ci
->hw_bank
.lpm
),
234 static int hw_device_init(struct ci_hdrc
*ci
, void __iomem
*base
)
238 /* bank is a module variable */
239 ci
->hw_bank
.abs
= base
;
241 ci
->hw_bank
.cap
= ci
->hw_bank
.abs
;
242 ci
->hw_bank
.cap
+= ci
->platdata
->capoffset
;
243 ci
->hw_bank
.op
= ci
->hw_bank
.cap
+ (ioread32(ci
->hw_bank
.cap
) & 0xff);
245 hw_alloc_regmap(ci
, false);
246 reg
= hw_read(ci
, CAP_HCCPARAMS
, HCCPARAMS_LEN
) >>
247 __ffs(HCCPARAMS_LEN
);
248 ci
->hw_bank
.lpm
= reg
;
250 hw_alloc_regmap(ci
, !!reg
);
251 ci
->hw_bank
.size
= ci
->hw_bank
.op
- ci
->hw_bank
.abs
;
252 ci
->hw_bank
.size
+= OP_LAST
;
253 ci
->hw_bank
.size
/= sizeof(u32
);
255 reg
= hw_read(ci
, CAP_DCCPARAMS
, DCCPARAMS_DEN
) >>
256 __ffs(DCCPARAMS_DEN
);
257 ci
->hw_ep_max
= reg
* 2; /* cache hw ENDPT_MAX */
259 if (ci
->hw_ep_max
> ENDPT_MAX
)
262 ci_hdrc_enter_lpm(ci
, false);
264 /* Disable all interrupts bits */
265 hw_write(ci
, OP_USBINTR
, 0xffffffff, 0);
267 /* Clear all interrupts status bits*/
268 hw_write(ci
, OP_USBSTS
, 0xffffffff, 0xffffffff);
270 ci
->rev
= ci_get_revision(ci
);
273 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
274 ci
->rev
, ci
->hw_bank
.lpm
, ci
->hw_bank
.cap
, ci
->hw_bank
.op
);
276 /* setup lock mode ? */
278 /* ENDPTSETUPSTAT is '0' by default */
280 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
285 static void hw_phymode_configure(struct ci_hdrc
*ci
)
287 u32 portsc
, lpm
, sts
= 0;
289 switch (ci
->platdata
->phy_mode
) {
290 case USBPHY_INTERFACE_MODE_UTMI
:
291 portsc
= PORTSC_PTS(PTS_UTMI
);
292 lpm
= DEVLC_PTS(PTS_UTMI
);
294 case USBPHY_INTERFACE_MODE_UTMIW
:
295 portsc
= PORTSC_PTS(PTS_UTMI
) | PORTSC_PTW
;
296 lpm
= DEVLC_PTS(PTS_UTMI
) | DEVLC_PTW
;
298 case USBPHY_INTERFACE_MODE_ULPI
:
299 portsc
= PORTSC_PTS(PTS_ULPI
);
300 lpm
= DEVLC_PTS(PTS_ULPI
);
302 case USBPHY_INTERFACE_MODE_SERIAL
:
303 portsc
= PORTSC_PTS(PTS_SERIAL
);
304 lpm
= DEVLC_PTS(PTS_SERIAL
);
307 case USBPHY_INTERFACE_MODE_HSIC
:
308 portsc
= PORTSC_PTS(PTS_HSIC
);
309 lpm
= DEVLC_PTS(PTS_HSIC
);
315 if (ci
->hw_bank
.lpm
) {
316 hw_write(ci
, OP_DEVLC
, DEVLC_PTS(7) | DEVLC_PTW
, lpm
);
318 hw_write(ci
, OP_DEVLC
, DEVLC_STS
, DEVLC_STS
);
320 hw_write(ci
, OP_PORTSC
, PORTSC_PTS(7) | PORTSC_PTW
, portsc
);
322 hw_write(ci
, OP_PORTSC
, PORTSC_STS
, PORTSC_STS
);
327 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
329 * @ci: the controller
331 * This function returns an error code if the phy failed to init
333 static int _ci_usb_phy_init(struct ci_hdrc
*ci
)
338 ret
= phy_init(ci
->phy
);
342 ret
= phy_power_on(ci
->phy
);
348 ret
= usb_phy_init(ci
->usb_phy
);
355 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
357 * @ci: the controller
359 static void ci_usb_phy_exit(struct ci_hdrc
*ci
)
362 phy_power_off(ci
->phy
);
365 usb_phy_shutdown(ci
->usb_phy
);
370 * ci_usb_phy_init: initialize phy according to different phy type
371 * @ci: the controller
373 * This function returns an error code if usb_phy_init has failed
375 static int ci_usb_phy_init(struct ci_hdrc
*ci
)
379 switch (ci
->platdata
->phy_mode
) {
380 case USBPHY_INTERFACE_MODE_UTMI
:
381 case USBPHY_INTERFACE_MODE_UTMIW
:
382 case USBPHY_INTERFACE_MODE_HSIC
:
383 ret
= _ci_usb_phy_init(ci
);
385 hw_wait_phy_stable();
388 hw_phymode_configure(ci
);
390 case USBPHY_INTERFACE_MODE_ULPI
:
391 case USBPHY_INTERFACE_MODE_SERIAL
:
392 hw_phymode_configure(ci
);
393 ret
= _ci_usb_phy_init(ci
);
398 ret
= _ci_usb_phy_init(ci
);
400 hw_wait_phy_stable();
407 * hw_controller_reset: do controller reset
408 * @ci: the controller
410 * This function returns an error code
412 static int hw_controller_reset(struct ci_hdrc
*ci
)
416 hw_write(ci
, OP_USBCMD
, USBCMD_RST
, USBCMD_RST
);
417 while (hw_read(ci
, OP_USBCMD
, USBCMD_RST
)) {
427 * hw_device_reset: resets chip (execute without interruption)
428 * @ci: the controller
430 * This function returns an error code
432 int hw_device_reset(struct ci_hdrc
*ci
)
436 /* should flush & stop before reset */
437 hw_write(ci
, OP_ENDPTFLUSH
, ~0, ~0);
438 hw_write(ci
, OP_USBCMD
, USBCMD_RS
, 0);
440 ret
= hw_controller_reset(ci
);
442 dev_err(ci
->dev
, "error resetting controller, ret=%d\n", ret
);
446 if (ci
->platdata
->notify_event
)
447 ci
->platdata
->notify_event(ci
,
448 CI_HDRC_CONTROLLER_RESET_EVENT
);
450 if (ci
->platdata
->flags
& CI_HDRC_DISABLE_STREAMING
)
451 hw_write(ci
, OP_USBMODE
, USBMODE_CI_SDIS
, USBMODE_CI_SDIS
);
453 if (ci
->platdata
->flags
& CI_HDRC_FORCE_FULLSPEED
) {
455 hw_write(ci
, OP_DEVLC
, DEVLC_PFSC
, DEVLC_PFSC
);
457 hw_write(ci
, OP_PORTSC
, PORTSC_PFSC
, PORTSC_PFSC
);
460 /* USBMODE should be configured step by step */
461 hw_write(ci
, OP_USBMODE
, USBMODE_CM
, USBMODE_CM_IDLE
);
462 hw_write(ci
, OP_USBMODE
, USBMODE_CM
, USBMODE_CM_DC
);
464 hw_write(ci
, OP_USBMODE
, USBMODE_SLOM
, USBMODE_SLOM
);
466 if (hw_read(ci
, OP_USBMODE
, USBMODE_CM
) != USBMODE_CM_DC
) {
467 pr_err("cannot enter in %s device mode", ci_role(ci
)->name
);
468 pr_err("lpm = %i", ci
->hw_bank
.lpm
);
476 * hw_wait_reg: wait the register value
478 * Sometimes, it needs to wait register value before going on.
479 * Eg, when switch to device mode, the vbus value should be lower
480 * than OTGSC_BSV before connects to host.
482 * @ci: the controller
483 * @reg: register index
485 * @value: the bit value to wait
486 * @timeout_ms: timeout in millisecond
488 * This function returns an error code if timeout
490 int hw_wait_reg(struct ci_hdrc
*ci
, enum ci_hw_regs reg
, u32 mask
,
491 u32 value
, unsigned int timeout_ms
)
493 unsigned long elapse
= jiffies
+ msecs_to_jiffies(timeout_ms
);
495 while (hw_read(ci
, reg
, mask
) != value
) {
496 if (time_after(jiffies
, elapse
)) {
497 dev_err(ci
->dev
, "timeout waiting for %08x in %d\n",
507 static irqreturn_t
ci_irq(int irq
, void *data
)
509 struct ci_hdrc
*ci
= data
;
510 irqreturn_t ret
= IRQ_NONE
;
514 disable_irq_nosync(irq
);
515 ci
->wakeup_int
= true;
516 pm_runtime_get(ci
->dev
);
521 otgsc
= hw_read_otgsc(ci
, ~0);
522 if (ci_otg_is_fsm_mode(ci
)) {
523 ret
= ci_otg_fsm_irq(ci
);
524 if (ret
== IRQ_HANDLED
)
530 * Handle id change interrupt, it indicates device/host function
533 if (ci
->is_otg
&& (otgsc
& OTGSC_IDIE
) && (otgsc
& OTGSC_IDIS
)) {
535 /* Clear ID change irq status */
536 hw_write_otgsc(ci
, OTGSC_IDIS
, OTGSC_IDIS
);
537 ci_otg_queue_work(ci
);
542 * Handle vbus change interrupt, it indicates device connection
543 * and disconnection events.
545 if (ci
->is_otg
&& (otgsc
& OTGSC_BSVIE
) && (otgsc
& OTGSC_BSVIS
)) {
546 ci
->b_sess_valid_event
= true;
548 hw_write_otgsc(ci
, OTGSC_BSVIS
, OTGSC_BSVIS
);
549 ci_otg_queue_work(ci
);
553 /* Handle device/host interrupt */
554 if (ci
->role
!= CI_ROLE_END
)
555 ret
= ci_role(ci
)->irq(ci
);
560 static int ci_get_platdata(struct device
*dev
,
561 struct ci_hdrc_platform_data
*platdata
)
563 if (!platdata
->phy_mode
)
564 platdata
->phy_mode
= of_usb_get_phy_mode(dev
->of_node
);
566 if (!platdata
->dr_mode
)
567 platdata
->dr_mode
= of_usb_get_dr_mode(dev
->of_node
);
569 if (platdata
->dr_mode
== USB_DR_MODE_UNKNOWN
)
570 platdata
->dr_mode
= USB_DR_MODE_OTG
;
572 if (platdata
->dr_mode
!= USB_DR_MODE_PERIPHERAL
) {
573 /* Get the vbus regulator */
574 platdata
->reg_vbus
= devm_regulator_get(dev
, "vbus");
575 if (PTR_ERR(platdata
->reg_vbus
) == -EPROBE_DEFER
) {
576 return -EPROBE_DEFER
;
577 } else if (PTR_ERR(platdata
->reg_vbus
) == -ENODEV
) {
578 /* no vbus regulator is needed */
579 platdata
->reg_vbus
= NULL
;
580 } else if (IS_ERR(platdata
->reg_vbus
)) {
581 dev_err(dev
, "Getting regulator error: %ld\n",
582 PTR_ERR(platdata
->reg_vbus
));
583 return PTR_ERR(platdata
->reg_vbus
);
585 /* Get TPL support */
586 if (!platdata
->tpl_support
)
587 platdata
->tpl_support
=
588 of_usb_host_tpl_support(dev
->of_node
);
591 if (of_usb_get_maximum_speed(dev
->of_node
) == USB_SPEED_FULL
)
592 platdata
->flags
|= CI_HDRC_FORCE_FULLSPEED
;
597 static DEFINE_IDA(ci_ida
);
599 struct platform_device
*ci_hdrc_add_device(struct device
*dev
,
600 struct resource
*res
, int nres
,
601 struct ci_hdrc_platform_data
*platdata
)
603 struct platform_device
*pdev
;
606 ret
= ci_get_platdata(dev
, platdata
);
610 id
= ida_simple_get(&ci_ida
, 0, 0, GFP_KERNEL
);
614 pdev
= platform_device_alloc("ci_hdrc", id
);
620 pdev
->dev
.parent
= dev
;
621 pdev
->dev
.dma_mask
= dev
->dma_mask
;
622 pdev
->dev
.dma_parms
= dev
->dma_parms
;
623 dma_set_coherent_mask(&pdev
->dev
, dev
->coherent_dma_mask
);
625 ret
= platform_device_add_resources(pdev
, res
, nres
);
629 ret
= platform_device_add_data(pdev
, platdata
, sizeof(*platdata
));
633 ret
= platform_device_add(pdev
);
640 platform_device_put(pdev
);
642 ida_simple_remove(&ci_ida
, id
);
645 EXPORT_SYMBOL_GPL(ci_hdrc_add_device
);
647 void ci_hdrc_remove_device(struct platform_device
*pdev
)
650 platform_device_unregister(pdev
);
651 ida_simple_remove(&ci_ida
, id
);
653 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device
);
655 static inline void ci_role_destroy(struct ci_hdrc
*ci
)
657 ci_hdrc_gadget_destroy(ci
);
658 ci_hdrc_host_destroy(ci
);
660 ci_hdrc_otg_destroy(ci
);
663 static void ci_get_otg_capable(struct ci_hdrc
*ci
)
665 if (ci
->platdata
->flags
& CI_HDRC_DUAL_ROLE_NOT_OTG
)
668 ci
->is_otg
= (hw_read(ci
, CAP_DCCPARAMS
,
669 DCCPARAMS_DC
| DCCPARAMS_HC
)
670 == (DCCPARAMS_DC
| DCCPARAMS_HC
));
672 dev_dbg(ci
->dev
, "It is OTG capable controller\n");
673 /* Disable and clear all OTG irq */
674 hw_write_otgsc(ci
, OTGSC_INT_EN_BITS
| OTGSC_INT_STATUS_BITS
,
675 OTGSC_INT_STATUS_BITS
);
679 static int ci_hdrc_probe(struct platform_device
*pdev
)
681 struct device
*dev
= &pdev
->dev
;
683 struct resource
*res
;
686 enum usb_dr_mode dr_mode
;
688 if (!dev_get_platdata(dev
)) {
689 dev_err(dev
, "platform data missing\n");
693 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
694 base
= devm_ioremap_resource(dev
, res
);
696 return PTR_ERR(base
);
698 ci
= devm_kzalloc(dev
, sizeof(*ci
), GFP_KERNEL
);
703 ci
->platdata
= dev_get_platdata(dev
);
704 ci
->imx28_write_fix
= !!(ci
->platdata
->flags
&
705 CI_HDRC_IMX28_WRITE_FIX
);
706 ci
->supports_runtime_pm
= !!(ci
->platdata
->flags
&
707 CI_HDRC_SUPPORTS_RUNTIME_PM
);
709 ret
= hw_device_init(ci
, base
);
711 dev_err(dev
, "can't initialize hardware\n");
715 if (ci
->platdata
->phy
) {
716 ci
->phy
= ci
->platdata
->phy
;
717 } else if (ci
->platdata
->usb_phy
) {
718 ci
->usb_phy
= ci
->platdata
->usb_phy
;
720 ci
->phy
= devm_phy_get(dev
->parent
, "usb-phy");
721 ci
->usb_phy
= devm_usb_get_phy(dev
->parent
, USB_PHY_TYPE_USB2
);
723 /* if both generic PHY and USB PHY layers aren't enabled */
724 if (PTR_ERR(ci
->phy
) == -ENOSYS
&&
725 PTR_ERR(ci
->usb_phy
) == -ENXIO
)
728 if (IS_ERR(ci
->phy
) && IS_ERR(ci
->usb_phy
))
729 return -EPROBE_DEFER
;
733 else if (IS_ERR(ci
->usb_phy
))
737 ret
= ci_usb_phy_init(ci
);
739 dev_err(dev
, "unable to init phy: %d\n", ret
);
743 ci
->hw_bank
.phys
= res
->start
;
745 ci
->irq
= platform_get_irq(pdev
, 0);
747 dev_err(dev
, "missing IRQ\n");
752 ci_get_otg_capable(ci
);
754 dr_mode
= ci
->platdata
->dr_mode
;
755 /* initialize role(s) before the interrupt is requested */
756 if (dr_mode
== USB_DR_MODE_OTG
|| dr_mode
== USB_DR_MODE_HOST
) {
757 ret
= ci_hdrc_host_init(ci
);
759 dev_info(dev
, "doesn't support host\n");
762 if (dr_mode
== USB_DR_MODE_OTG
|| dr_mode
== USB_DR_MODE_PERIPHERAL
) {
763 ret
= ci_hdrc_gadget_init(ci
);
765 dev_info(dev
, "doesn't support gadget\n");
768 if (!ci
->roles
[CI_ROLE_HOST
] && !ci
->roles
[CI_ROLE_GADGET
]) {
769 dev_err(dev
, "no supported roles\n");
774 if (ci
->is_otg
&& ci
->roles
[CI_ROLE_GADGET
]) {
775 ret
= ci_hdrc_otg_init(ci
);
777 dev_err(dev
, "init otg fails, ret = %d\n", ret
);
782 if (ci
->roles
[CI_ROLE_HOST
] && ci
->roles
[CI_ROLE_GADGET
]) {
784 ci
->role
= ci_otg_role(ci
);
785 /* Enable ID change irq */
786 hw_write_otgsc(ci
, OTGSC_IDIE
, OTGSC_IDIE
);
789 * If the controller is not OTG capable, but support
790 * role switch, the defalt role is gadget, and the
791 * user can switch it through debugfs.
793 ci
->role
= CI_ROLE_GADGET
;
796 ci
->role
= ci
->roles
[CI_ROLE_HOST
]
801 if (!ci_otg_is_fsm_mode(ci
)) {
802 /* only update vbus status for peripheral */
803 if (ci
->role
== CI_ROLE_GADGET
)
804 ci_handle_vbus_change(ci
);
806 ret
= ci_role_start(ci
, ci
->role
);
808 dev_err(dev
, "can't start %s role\n",
814 platform_set_drvdata(pdev
, ci
);
815 ret
= devm_request_irq(dev
, ci
->irq
, ci_irq
, IRQF_SHARED
,
816 ci
->platdata
->name
, ci
);
820 if (ci
->supports_runtime_pm
) {
821 pm_runtime_set_active(&pdev
->dev
);
822 pm_runtime_enable(&pdev
->dev
);
823 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 2000);
824 pm_runtime_mark_last_busy(ci
->dev
);
825 pm_runtime_use_autosuspend(&pdev
->dev
);
828 if (ci_otg_is_fsm_mode(ci
))
829 ci_hdrc_otg_fsm_start(ci
);
831 device_set_wakeup_capable(&pdev
->dev
, true);
833 ret
= dbg_create_files(ci
);
845 static int ci_hdrc_remove(struct platform_device
*pdev
)
847 struct ci_hdrc
*ci
= platform_get_drvdata(pdev
);
849 if (ci
->supports_runtime_pm
) {
850 pm_runtime_get_sync(&pdev
->dev
);
851 pm_runtime_disable(&pdev
->dev
);
852 pm_runtime_put_noidle(&pdev
->dev
);
855 dbg_remove_files(ci
);
857 ci_hdrc_enter_lpm(ci
, true);
864 /* Prepare wakeup by SRP before suspend */
865 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc
*ci
)
867 if ((ci
->fsm
.otg
->state
== OTG_STATE_A_IDLE
) &&
868 !hw_read_otgsc(ci
, OTGSC_ID
)) {
869 hw_write(ci
, OP_PORTSC
, PORTSC_W1C_BITS
| PORTSC_PP
,
871 hw_write(ci
, OP_PORTSC
, PORTSC_W1C_BITS
| PORTSC_WKCN
,
876 /* Handle SRP when wakeup by data pulse */
877 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc
*ci
)
879 if ((ci
->fsm
.otg
->state
== OTG_STATE_A_IDLE
) &&
880 (ci
->fsm
.a_bus_drop
== 1) && (ci
->fsm
.a_bus_req
== 0)) {
881 if (!hw_read_otgsc(ci
, OTGSC_ID
)) {
882 ci
->fsm
.a_srp_det
= 1;
883 ci
->fsm
.a_bus_drop
= 0;
887 ci_otg_queue_work(ci
);
891 static void ci_controller_suspend(struct ci_hdrc
*ci
)
893 disable_irq(ci
->irq
);
894 ci_hdrc_enter_lpm(ci
, true);
895 usb_phy_set_suspend(ci
->usb_phy
, 1);
900 static int ci_controller_resume(struct device
*dev
)
902 struct ci_hdrc
*ci
= dev_get_drvdata(dev
);
904 dev_dbg(dev
, "at %s\n", __func__
);
911 ci_hdrc_enter_lpm(ci
, false);
913 usb_phy_set_suspend(ci
->usb_phy
, 0);
914 usb_phy_set_wakeup(ci
->usb_phy
, false);
915 hw_wait_phy_stable();
919 if (ci
->wakeup_int
) {
920 ci
->wakeup_int
= false;
921 pm_runtime_mark_last_busy(ci
->dev
);
922 pm_runtime_put_autosuspend(ci
->dev
);
924 if (ci_otg_is_fsm_mode(ci
))
925 ci_otg_fsm_wakeup_by_srp(ci
);
931 #ifdef CONFIG_PM_SLEEP
932 static int ci_suspend(struct device
*dev
)
934 struct ci_hdrc
*ci
= dev_get_drvdata(dev
);
937 flush_workqueue(ci
->wq
);
939 * Controller needs to be active during suspend, otherwise the core
940 * may run resume when the parent is at suspend if other driver's
941 * suspend fails, it occurs before parent's suspend has not started,
942 * but the core suspend has finished.
945 pm_runtime_resume(dev
);
952 if (device_may_wakeup(dev
)) {
953 if (ci_otg_is_fsm_mode(ci
))
954 ci_otg_fsm_suspend_for_srp(ci
);
956 usb_phy_set_wakeup(ci
->usb_phy
, true);
957 enable_irq_wake(ci
->irq
);
960 ci_controller_suspend(ci
);
965 static int ci_resume(struct device
*dev
)
967 struct ci_hdrc
*ci
= dev_get_drvdata(dev
);
970 if (device_may_wakeup(dev
))
971 disable_irq_wake(ci
->irq
);
973 ret
= ci_controller_resume(dev
);
977 if (ci
->supports_runtime_pm
) {
978 pm_runtime_disable(dev
);
979 pm_runtime_set_active(dev
);
980 pm_runtime_enable(dev
);
985 #endif /* CONFIG_PM_SLEEP */
987 static int ci_runtime_suspend(struct device
*dev
)
989 struct ci_hdrc
*ci
= dev_get_drvdata(dev
);
991 dev_dbg(dev
, "at %s\n", __func__
);
998 if (ci_otg_is_fsm_mode(ci
))
999 ci_otg_fsm_suspend_for_srp(ci
);
1001 usb_phy_set_wakeup(ci
->usb_phy
, true);
1002 ci_controller_suspend(ci
);
1007 static int ci_runtime_resume(struct device
*dev
)
1009 return ci_controller_resume(dev
);
1012 #endif /* CONFIG_PM */
1013 static const struct dev_pm_ops ci_pm_ops
= {
1014 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend
, ci_resume
)
1015 SET_RUNTIME_PM_OPS(ci_runtime_suspend
, ci_runtime_resume
, NULL
)
1018 static struct platform_driver ci_hdrc_driver
= {
1019 .probe
= ci_hdrc_probe
,
1020 .remove
= ci_hdrc_remove
,
1027 module_platform_driver(ci_hdrc_driver
);
1029 MODULE_ALIAS("platform:ci_hdrc");
1030 MODULE_LICENSE("GPL v2");
1031 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1032 MODULE_DESCRIPTION("ChipIdea HDRC Driver");