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407151465645b3216c7b0d22755763d9744084e7
[deliverable/linux.git] / drivers / usb / dwc3 / core.c
1 /**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/io.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
38
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
43
44 #include "platform_data.h"
45 #include "core.h"
46 #include "gadget.h"
47 #include "io.h"
48
49 #include "debug.h"
50
51 /* -------------------------------------------------------------------------- */
52
53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
54 {
55 u32 reg;
56
57 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
58 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
59 reg |= DWC3_GCTL_PRTCAPDIR(mode);
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
61 }
62
63 /**
64 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
65 * @dwc: pointer to our context structure
66 */
67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
68 {
69 u32 reg;
70 int ret;
71
72 /* Before Resetting PHY, put Core in Reset */
73 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
74 reg |= DWC3_GCTL_CORESOFTRESET;
75 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
76
77 /* Assert USB3 PHY reset */
78 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
79 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
80 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
81
82 /* Assert USB2 PHY reset */
83 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
84 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
85 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
86
87 usb_phy_init(dwc->usb2_phy);
88 usb_phy_init(dwc->usb3_phy);
89 ret = phy_init(dwc->usb2_generic_phy);
90 if (ret < 0)
91 return ret;
92
93 ret = phy_init(dwc->usb3_generic_phy);
94 if (ret < 0) {
95 phy_exit(dwc->usb2_generic_phy);
96 return ret;
97 }
98 mdelay(100);
99
100 /* Clear USB3 PHY reset */
101 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
102 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
103 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
104
105 /* Clear USB2 PHY reset */
106 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
107 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
108 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
109
110 mdelay(100);
111
112 /* After PHYs are stable we can take Core out of reset state */
113 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
114 reg &= ~DWC3_GCTL_CORESOFTRESET;
115 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
116
117 return 0;
118 }
119
120 /**
121 * dwc3_soft_reset - Issue soft reset
122 * @dwc: Pointer to our controller context structure
123 */
124 static int dwc3_soft_reset(struct dwc3 *dwc)
125 {
126 unsigned long timeout;
127 u32 reg;
128
129 timeout = jiffies + msecs_to_jiffies(500);
130 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
131 do {
132 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
133 if (!(reg & DWC3_DCTL_CSFTRST))
134 break;
135
136 if (time_after(jiffies, timeout)) {
137 dev_err(dwc->dev, "Reset Timed Out\n");
138 return -ETIMEDOUT;
139 }
140
141 cpu_relax();
142 } while (true);
143
144 return 0;
145 }
146
147 /*
148 * dwc3_frame_length_adjustment - Adjusts frame length if required
149 * @dwc3: Pointer to our controller context structure
150 * @fladj: Value of GFLADJ_30MHZ to adjust frame length
151 */
152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
153 {
154 u32 reg;
155 u32 dft;
156
157 if (dwc->revision < DWC3_REVISION_250A)
158 return;
159
160 if (fladj == 0)
161 return;
162
163 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
164 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
165 if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
166 "request value same as default, ignoring\n")) {
167 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
168 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
169 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
170 }
171 }
172
173 /**
174 * dwc3_free_one_event_buffer - Frees one event buffer
175 * @dwc: Pointer to our controller context structure
176 * @evt: Pointer to event buffer to be freed
177 */
178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
179 struct dwc3_event_buffer *evt)
180 {
181 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
182 }
183
184 /**
185 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
186 * @dwc: Pointer to our controller context structure
187 * @length: size of the event buffer
188 *
189 * Returns a pointer to the allocated event buffer structure on success
190 * otherwise ERR_PTR(errno).
191 */
192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
193 unsigned length)
194 {
195 struct dwc3_event_buffer *evt;
196
197 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
198 if (!evt)
199 return ERR_PTR(-ENOMEM);
200
201 evt->dwc = dwc;
202 evt->length = length;
203 evt->buf = dma_alloc_coherent(dwc->dev, length,
204 &evt->dma, GFP_KERNEL);
205 if (!evt->buf)
206 return ERR_PTR(-ENOMEM);
207
208 return evt;
209 }
210
211 /**
212 * dwc3_free_event_buffers - frees all allocated event buffers
213 * @dwc: Pointer to our controller context structure
214 */
215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
216 {
217 struct dwc3_event_buffer *evt;
218 int i;
219
220 for (i = 0; i < dwc->num_event_buffers; i++) {
221 evt = dwc->ev_buffs[i];
222 if (evt)
223 dwc3_free_one_event_buffer(dwc, evt);
224 }
225 }
226
227 /**
228 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
229 * @dwc: pointer to our controller context structure
230 * @length: size of event buffer
231 *
232 * Returns 0 on success otherwise negative errno. In the error case, dwc
233 * may contain some buffers allocated but not all which were requested.
234 */
235 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
236 {
237 int num;
238 int i;
239
240 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
241 dwc->num_event_buffers = num;
242
243 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
244 GFP_KERNEL);
245 if (!dwc->ev_buffs)
246 return -ENOMEM;
247
248 for (i = 0; i < num; i++) {
249 struct dwc3_event_buffer *evt;
250
251 evt = dwc3_alloc_one_event_buffer(dwc, length);
252 if (IS_ERR(evt)) {
253 dev_err(dwc->dev, "can't allocate event buffer\n");
254 return PTR_ERR(evt);
255 }
256 dwc->ev_buffs[i] = evt;
257 }
258
259 return 0;
260 }
261
262 /**
263 * dwc3_event_buffers_setup - setup our allocated event buffers
264 * @dwc: pointer to our controller context structure
265 *
266 * Returns 0 on success otherwise negative errno.
267 */
268 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
269 {
270 struct dwc3_event_buffer *evt;
271 int n;
272
273 for (n = 0; n < dwc->num_event_buffers; n++) {
274 evt = dwc->ev_buffs[n];
275 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
276 evt->buf, (unsigned long long) evt->dma,
277 evt->length);
278
279 evt->lpos = 0;
280
281 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
282 lower_32_bits(evt->dma));
283 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
284 upper_32_bits(evt->dma));
285 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
286 DWC3_GEVNTSIZ_SIZE(evt->length));
287 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
288 }
289
290 return 0;
291 }
292
293 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
294 {
295 struct dwc3_event_buffer *evt;
296 int n;
297
298 for (n = 0; n < dwc->num_event_buffers; n++) {
299 evt = dwc->ev_buffs[n];
300
301 evt->lpos = 0;
302
303 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
304 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
305 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
306 | DWC3_GEVNTSIZ_SIZE(0));
307 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
308 }
309 }
310
311 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
312 {
313 if (!dwc->has_hibernation)
314 return 0;
315
316 if (!dwc->nr_scratch)
317 return 0;
318
319 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
320 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
321 if (!dwc->scratchbuf)
322 return -ENOMEM;
323
324 return 0;
325 }
326
327 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
328 {
329 dma_addr_t scratch_addr;
330 u32 param;
331 int ret;
332
333 if (!dwc->has_hibernation)
334 return 0;
335
336 if (!dwc->nr_scratch)
337 return 0;
338
339 /* should never fall here */
340 if (!WARN_ON(dwc->scratchbuf))
341 return 0;
342
343 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
344 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
345 DMA_BIDIRECTIONAL);
346 if (dma_mapping_error(dwc->dev, scratch_addr)) {
347 dev_err(dwc->dev, "failed to map scratch buffer\n");
348 ret = -EFAULT;
349 goto err0;
350 }
351
352 dwc->scratch_addr = scratch_addr;
353
354 param = lower_32_bits(scratch_addr);
355
356 ret = dwc3_send_gadget_generic_command(dwc,
357 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
358 if (ret < 0)
359 goto err1;
360
361 param = upper_32_bits(scratch_addr);
362
363 ret = dwc3_send_gadget_generic_command(dwc,
364 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
365 if (ret < 0)
366 goto err1;
367
368 return 0;
369
370 err1:
371 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
372 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
373
374 err0:
375 return ret;
376 }
377
378 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
379 {
380 if (!dwc->has_hibernation)
381 return;
382
383 if (!dwc->nr_scratch)
384 return;
385
386 /* should never fall here */
387 if (!WARN_ON(dwc->scratchbuf))
388 return;
389
390 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
391 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
392 kfree(dwc->scratchbuf);
393 }
394
395 static void dwc3_core_num_eps(struct dwc3 *dwc)
396 {
397 struct dwc3_hwparams *parms = &dwc->hwparams;
398
399 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
400 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
401
402 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
403 dwc->num_in_eps, dwc->num_out_eps);
404 }
405
406 static void dwc3_cache_hwparams(struct dwc3 *dwc)
407 {
408 struct dwc3_hwparams *parms = &dwc->hwparams;
409
410 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
411 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
412 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
413 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
414 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
415 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
416 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
417 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
418 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
419 }
420
421 /**
422 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
423 * @dwc: Pointer to our controller context structure
424 *
425 * Returns 0 on success. The USB PHY interfaces are configured but not
426 * initialized. The PHY interfaces and the PHYs get initialized together with
427 * the core in dwc3_core_init.
428 */
429 static int dwc3_phy_setup(struct dwc3 *dwc)
430 {
431 u32 reg;
432 int ret;
433
434 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
435
436 /*
437 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
438 * to '0' during coreConsultant configuration. So default value
439 * will be '0' when the core is reset. Application needs to set it
440 * to '1' after the core initialization is completed.
441 */
442 if (dwc->revision > DWC3_REVISION_194A)
443 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
444
445 if (dwc->u2ss_inp3_quirk)
446 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
447
448 if (dwc->req_p1p2p3_quirk)
449 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
450
451 if (dwc->del_p1p2p3_quirk)
452 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
453
454 if (dwc->del_phy_power_chg_quirk)
455 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
456
457 if (dwc->lfps_filter_quirk)
458 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
459
460 if (dwc->rx_detect_poll_quirk)
461 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
462
463 if (dwc->tx_de_emphasis_quirk)
464 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
465
466 if (dwc->dis_u3_susphy_quirk)
467 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
468
469 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
470
471 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
472
473 /* Select the HS PHY interface */
474 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
475 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
476 if (dwc->hsphy_interface &&
477 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
478 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
479 break;
480 } else if (dwc->hsphy_interface &&
481 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
482 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
483 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
484 } else {
485 /* Relying on default value. */
486 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
487 break;
488 }
489 /* FALLTHROUGH */
490 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
491 /* Making sure the interface and PHY are operational */
492 ret = dwc3_soft_reset(dwc);
493 if (ret)
494 return ret;
495
496 udelay(1);
497
498 ret = dwc3_ulpi_init(dwc);
499 if (ret)
500 return ret;
501 /* FALLTHROUGH */
502 default:
503 break;
504 }
505
506 /*
507 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
508 * '0' during coreConsultant configuration. So default value will
509 * be '0' when the core is reset. Application needs to set it to
510 * '1' after the core initialization is completed.
511 */
512 if (dwc->revision > DWC3_REVISION_194A)
513 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
514
515 if (dwc->dis_u2_susphy_quirk)
516 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
517
518 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
519
520 return 0;
521 }
522
523 /**
524 * dwc3_core_init - Low-level initialization of DWC3 Core
525 * @dwc: Pointer to our controller context structure
526 *
527 * Returns 0 on success otherwise negative errno.
528 */
529 static int dwc3_core_init(struct dwc3 *dwc)
530 {
531 u32 hwparams4 = dwc->hwparams.hwparams4;
532 u32 reg;
533 int ret;
534
535 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
536 /* This should read as U3 followed by revision number */
537 if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
538 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
539 ret = -ENODEV;
540 goto err0;
541 }
542 dwc->revision = reg;
543
544 /*
545 * Write Linux Version Code to our GUID register so it's easy to figure
546 * out which kernel version a bug was found.
547 */
548 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
549
550 /* Handle USB2.0-only core configuration */
551 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
552 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
553 if (dwc->maximum_speed == USB_SPEED_SUPER)
554 dwc->maximum_speed = USB_SPEED_HIGH;
555 }
556
557 /* issue device SoftReset too */
558 ret = dwc3_soft_reset(dwc);
559 if (ret)
560 goto err0;
561
562 ret = dwc3_core_soft_reset(dwc);
563 if (ret)
564 goto err0;
565
566 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
567 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
568
569 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
570 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
571 /**
572 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
573 * issue which would cause xHCI compliance tests to fail.
574 *
575 * Because of that we cannot enable clock gating on such
576 * configurations.
577 *
578 * Refers to:
579 *
580 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
581 * SOF/ITP Mode Used
582 */
583 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
584 dwc->dr_mode == USB_DR_MODE_OTG) &&
585 (dwc->revision >= DWC3_REVISION_210A &&
586 dwc->revision <= DWC3_REVISION_250A))
587 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
588 else
589 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
590 break;
591 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
592 /* enable hibernation here */
593 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
594
595 /*
596 * REVISIT Enabling this bit so that host-mode hibernation
597 * will work. Device-mode hibernation is not yet implemented.
598 */
599 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
600 break;
601 default:
602 dev_dbg(dwc->dev, "No power optimization available\n");
603 }
604
605 /* check if current dwc3 is on simulation board */
606 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
607 dev_dbg(dwc->dev, "it is on FPGA board\n");
608 dwc->is_fpga = true;
609 }
610
611 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
612 "disable_scramble cannot be used on non-FPGA builds\n");
613
614 if (dwc->disable_scramble_quirk && dwc->is_fpga)
615 reg |= DWC3_GCTL_DISSCRAMBLE;
616 else
617 reg &= ~DWC3_GCTL_DISSCRAMBLE;
618
619 if (dwc->u2exit_lfps_quirk)
620 reg |= DWC3_GCTL_U2EXIT_LFPS;
621
622 /*
623 * WORKAROUND: DWC3 revisions <1.90a have a bug
624 * where the device can fail to connect at SuperSpeed
625 * and falls back to high-speed mode which causes
626 * the device to enter a Connect/Disconnect loop
627 */
628 if (dwc->revision < DWC3_REVISION_190A)
629 reg |= DWC3_GCTL_U2RSTECN;
630
631 dwc3_core_num_eps(dwc);
632
633 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
634
635 ret = dwc3_alloc_scratch_buffers(dwc);
636 if (ret)
637 goto err1;
638
639 ret = dwc3_setup_scratch_buffers(dwc);
640 if (ret)
641 goto err2;
642
643 return 0;
644
645 err2:
646 dwc3_free_scratch_buffers(dwc);
647
648 err1:
649 usb_phy_shutdown(dwc->usb2_phy);
650 usb_phy_shutdown(dwc->usb3_phy);
651 phy_exit(dwc->usb2_generic_phy);
652 phy_exit(dwc->usb3_generic_phy);
653
654 err0:
655 return ret;
656 }
657
658 static void dwc3_core_exit(struct dwc3 *dwc)
659 {
660 dwc3_free_scratch_buffers(dwc);
661 usb_phy_shutdown(dwc->usb2_phy);
662 usb_phy_shutdown(dwc->usb3_phy);
663 phy_exit(dwc->usb2_generic_phy);
664 phy_exit(dwc->usb3_generic_phy);
665 }
666
667 static int dwc3_core_get_phy(struct dwc3 *dwc)
668 {
669 struct device *dev = dwc->dev;
670 struct device_node *node = dev->of_node;
671 int ret;
672
673 if (node) {
674 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
675 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
676 } else {
677 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
678 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
679 }
680
681 if (IS_ERR(dwc->usb2_phy)) {
682 ret = PTR_ERR(dwc->usb2_phy);
683 if (ret == -ENXIO || ret == -ENODEV) {
684 dwc->usb2_phy = NULL;
685 } else if (ret == -EPROBE_DEFER) {
686 return ret;
687 } else {
688 dev_err(dev, "no usb2 phy configured\n");
689 return ret;
690 }
691 }
692
693 if (IS_ERR(dwc->usb3_phy)) {
694 ret = PTR_ERR(dwc->usb3_phy);
695 if (ret == -ENXIO || ret == -ENODEV) {
696 dwc->usb3_phy = NULL;
697 } else if (ret == -EPROBE_DEFER) {
698 return ret;
699 } else {
700 dev_err(dev, "no usb3 phy configured\n");
701 return ret;
702 }
703 }
704
705 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
706 if (IS_ERR(dwc->usb2_generic_phy)) {
707 ret = PTR_ERR(dwc->usb2_generic_phy);
708 if (ret == -ENOSYS || ret == -ENODEV) {
709 dwc->usb2_generic_phy = NULL;
710 } else if (ret == -EPROBE_DEFER) {
711 return ret;
712 } else {
713 dev_err(dev, "no usb2 phy configured\n");
714 return ret;
715 }
716 }
717
718 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
719 if (IS_ERR(dwc->usb3_generic_phy)) {
720 ret = PTR_ERR(dwc->usb3_generic_phy);
721 if (ret == -ENOSYS || ret == -ENODEV) {
722 dwc->usb3_generic_phy = NULL;
723 } else if (ret == -EPROBE_DEFER) {
724 return ret;
725 } else {
726 dev_err(dev, "no usb3 phy configured\n");
727 return ret;
728 }
729 }
730
731 return 0;
732 }
733
734 static int dwc3_core_init_mode(struct dwc3 *dwc)
735 {
736 struct device *dev = dwc->dev;
737 int ret;
738
739 switch (dwc->dr_mode) {
740 case USB_DR_MODE_PERIPHERAL:
741 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
742 ret = dwc3_gadget_init(dwc);
743 if (ret) {
744 dev_err(dev, "failed to initialize gadget\n");
745 return ret;
746 }
747 break;
748 case USB_DR_MODE_HOST:
749 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
750 ret = dwc3_host_init(dwc);
751 if (ret) {
752 dev_err(dev, "failed to initialize host\n");
753 return ret;
754 }
755 break;
756 case USB_DR_MODE_OTG:
757 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
758 ret = dwc3_host_init(dwc);
759 if (ret) {
760 dev_err(dev, "failed to initialize host\n");
761 return ret;
762 }
763
764 ret = dwc3_gadget_init(dwc);
765 if (ret) {
766 dev_err(dev, "failed to initialize gadget\n");
767 return ret;
768 }
769 break;
770 default:
771 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
772 return -EINVAL;
773 }
774
775 return 0;
776 }
777
778 static void dwc3_core_exit_mode(struct dwc3 *dwc)
779 {
780 switch (dwc->dr_mode) {
781 case USB_DR_MODE_PERIPHERAL:
782 dwc3_gadget_exit(dwc);
783 break;
784 case USB_DR_MODE_HOST:
785 dwc3_host_exit(dwc);
786 break;
787 case USB_DR_MODE_OTG:
788 dwc3_host_exit(dwc);
789 dwc3_gadget_exit(dwc);
790 break;
791 default:
792 /* do nothing */
793 break;
794 }
795 }
796
797 #define DWC3_ALIGN_MASK (16 - 1)
798
799 static int dwc3_probe(struct platform_device *pdev)
800 {
801 struct device *dev = &pdev->dev;
802 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
803 struct device_node *node = dev->of_node;
804 struct resource *res;
805 struct dwc3 *dwc;
806 u8 lpm_nyet_threshold;
807 u8 tx_de_emphasis;
808 u8 hird_threshold;
809 u32 fladj = 0;
810
811 int ret;
812
813 void __iomem *regs;
814 void *mem;
815
816 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
817 if (!mem)
818 return -ENOMEM;
819
820 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
821 dwc->mem = mem;
822 dwc->dev = dev;
823
824 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
825 if (!res) {
826 dev_err(dev, "missing IRQ\n");
827 return -ENODEV;
828 }
829 dwc->xhci_resources[1].start = res->start;
830 dwc->xhci_resources[1].end = res->end;
831 dwc->xhci_resources[1].flags = res->flags;
832 dwc->xhci_resources[1].name = res->name;
833
834 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
835 if (!res) {
836 dev_err(dev, "missing memory resource\n");
837 return -ENODEV;
838 }
839
840 dwc->xhci_resources[0].start = res->start;
841 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
842 DWC3_XHCI_REGS_END;
843 dwc->xhci_resources[0].flags = res->flags;
844 dwc->xhci_resources[0].name = res->name;
845
846 res->start += DWC3_GLOBALS_REGS_START;
847
848 /*
849 * Request memory region but exclude xHCI regs,
850 * since it will be requested by the xhci-plat driver.
851 */
852 regs = devm_ioremap_resource(dev, res);
853 if (IS_ERR(regs)) {
854 ret = PTR_ERR(regs);
855 goto err0;
856 }
857
858 dwc->regs = regs;
859 dwc->regs_size = resource_size(res);
860
861 /* default to highest possible threshold */
862 lpm_nyet_threshold = 0xff;
863
864 /* default to -3.5dB de-emphasis */
865 tx_de_emphasis = 1;
866
867 /*
868 * default to assert utmi_sleep_n and use maximum allowed HIRD
869 * threshold value of 0b1100
870 */
871 hird_threshold = 12;
872
873 dwc->maximum_speed = usb_get_maximum_speed(dev);
874 dwc->dr_mode = usb_get_dr_mode(dev);
875
876 if (node) {
877 dwc->has_lpm_erratum = of_property_read_bool(node,
878 "snps,has-lpm-erratum");
879 of_property_read_u8(node, "snps,lpm-nyet-threshold",
880 &lpm_nyet_threshold);
881 dwc->is_utmi_l1_suspend = of_property_read_bool(node,
882 "snps,is-utmi-l1-suspend");
883 of_property_read_u8(node, "snps,hird-threshold",
884 &hird_threshold);
885 dwc->usb3_lpm_capable = of_property_read_bool(node,
886 "snps,usb3_lpm_capable");
887
888 dwc->needs_fifo_resize = of_property_read_bool(node,
889 "tx-fifo-resize");
890
891 dwc->disable_scramble_quirk = of_property_read_bool(node,
892 "snps,disable_scramble_quirk");
893 dwc->u2exit_lfps_quirk = of_property_read_bool(node,
894 "snps,u2exit_lfps_quirk");
895 dwc->u2ss_inp3_quirk = of_property_read_bool(node,
896 "snps,u2ss_inp3_quirk");
897 dwc->req_p1p2p3_quirk = of_property_read_bool(node,
898 "snps,req_p1p2p3_quirk");
899 dwc->del_p1p2p3_quirk = of_property_read_bool(node,
900 "snps,del_p1p2p3_quirk");
901 dwc->del_phy_power_chg_quirk = of_property_read_bool(node,
902 "snps,del_phy_power_chg_quirk");
903 dwc->lfps_filter_quirk = of_property_read_bool(node,
904 "snps,lfps_filter_quirk");
905 dwc->rx_detect_poll_quirk = of_property_read_bool(node,
906 "snps,rx_detect_poll_quirk");
907 dwc->dis_u3_susphy_quirk = of_property_read_bool(node,
908 "snps,dis_u3_susphy_quirk");
909 dwc->dis_u2_susphy_quirk = of_property_read_bool(node,
910 "snps,dis_u2_susphy_quirk");
911
912 dwc->tx_de_emphasis_quirk = of_property_read_bool(node,
913 "snps,tx_de_emphasis_quirk");
914 of_property_read_u8(node, "snps,tx_de_emphasis",
915 &tx_de_emphasis);
916 of_property_read_string(node, "snps,hsphy_interface",
917 &dwc->hsphy_interface);
918 of_property_read_u32(node,
919 "snps,quirk-frame-length-adjustment",
920 &fladj);
921 } else if (pdata) {
922 dwc->maximum_speed = pdata->maximum_speed;
923 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
924 if (pdata->lpm_nyet_threshold)
925 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
926 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
927 if (pdata->hird_threshold)
928 hird_threshold = pdata->hird_threshold;
929
930 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
931 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
932 dwc->dr_mode = pdata->dr_mode;
933
934 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
935 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
936 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
937 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
938 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
939 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
940 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
941 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
942 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
943 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
944
945 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
946 if (pdata->tx_de_emphasis)
947 tx_de_emphasis = pdata->tx_de_emphasis;
948
949 dwc->hsphy_interface = pdata->hsphy_interface;
950 fladj = pdata->fladj_value;
951 }
952
953 /* default to superspeed if no maximum_speed passed */
954 if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
955 dwc->maximum_speed = USB_SPEED_SUPER;
956
957 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
958 dwc->tx_de_emphasis = tx_de_emphasis;
959
960 dwc->hird_threshold = hird_threshold
961 | (dwc->is_utmi_l1_suspend << 4);
962
963 platform_set_drvdata(pdev, dwc);
964 dwc3_cache_hwparams(dwc);
965
966 ret = dwc3_phy_setup(dwc);
967 if (ret)
968 goto err0;
969
970 ret = dwc3_core_get_phy(dwc);
971 if (ret)
972 goto err0;
973
974 spin_lock_init(&dwc->lock);
975
976 if (!dev->dma_mask) {
977 dev->dma_mask = dev->parent->dma_mask;
978 dev->dma_parms = dev->parent->dma_parms;
979 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
980 }
981
982 pm_runtime_enable(dev);
983 pm_runtime_get_sync(dev);
984 pm_runtime_forbid(dev);
985
986 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
987 if (ret) {
988 dev_err(dwc->dev, "failed to allocate event buffers\n");
989 ret = -ENOMEM;
990 goto err1;
991 }
992
993 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
994 dwc->dr_mode = USB_DR_MODE_HOST;
995 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
996 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
997
998 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
999 dwc->dr_mode = USB_DR_MODE_OTG;
1000
1001 ret = dwc3_core_init(dwc);
1002 if (ret) {
1003 dev_err(dev, "failed to initialize core\n");
1004 goto err1;
1005 }
1006
1007 /* Adjust Frame Length */
1008 dwc3_frame_length_adjustment(dwc, fladj);
1009
1010 usb_phy_set_suspend(dwc->usb2_phy, 0);
1011 usb_phy_set_suspend(dwc->usb3_phy, 0);
1012 ret = phy_power_on(dwc->usb2_generic_phy);
1013 if (ret < 0)
1014 goto err2;
1015
1016 ret = phy_power_on(dwc->usb3_generic_phy);
1017 if (ret < 0)
1018 goto err3;
1019
1020 ret = dwc3_event_buffers_setup(dwc);
1021 if (ret) {
1022 dev_err(dwc->dev, "failed to setup event buffers\n");
1023 goto err4;
1024 }
1025
1026 ret = dwc3_core_init_mode(dwc);
1027 if (ret)
1028 goto err5;
1029
1030 ret = dwc3_debugfs_init(dwc);
1031 if (ret) {
1032 dev_err(dev, "failed to initialize debugfs\n");
1033 goto err6;
1034 }
1035
1036 pm_runtime_allow(dev);
1037
1038 return 0;
1039
1040 err6:
1041 dwc3_core_exit_mode(dwc);
1042
1043 err5:
1044 dwc3_event_buffers_cleanup(dwc);
1045
1046 err4:
1047 phy_power_off(dwc->usb3_generic_phy);
1048
1049 err3:
1050 phy_power_off(dwc->usb2_generic_phy);
1051
1052 err2:
1053 usb_phy_set_suspend(dwc->usb2_phy, 1);
1054 usb_phy_set_suspend(dwc->usb3_phy, 1);
1055 dwc3_core_exit(dwc);
1056
1057 err1:
1058 dwc3_free_event_buffers(dwc);
1059 dwc3_ulpi_exit(dwc);
1060
1061 err0:
1062 /*
1063 * restore res->start back to its original value so that, in case the
1064 * probe is deferred, we don't end up getting error in request the
1065 * memory region the next time probe is called.
1066 */
1067 res->start -= DWC3_GLOBALS_REGS_START;
1068
1069 return ret;
1070 }
1071
1072 static int dwc3_remove(struct platform_device *pdev)
1073 {
1074 struct dwc3 *dwc = platform_get_drvdata(pdev);
1075 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1076
1077 /*
1078 * restore res->start back to its original value so that, in case the
1079 * probe is deferred, we don't end up getting error in request the
1080 * memory region the next time probe is called.
1081 */
1082 res->start -= DWC3_GLOBALS_REGS_START;
1083
1084 dwc3_debugfs_exit(dwc);
1085 dwc3_core_exit_mode(dwc);
1086 dwc3_event_buffers_cleanup(dwc);
1087 dwc3_free_event_buffers(dwc);
1088
1089 usb_phy_set_suspend(dwc->usb2_phy, 1);
1090 usb_phy_set_suspend(dwc->usb3_phy, 1);
1091 phy_power_off(dwc->usb2_generic_phy);
1092 phy_power_off(dwc->usb3_generic_phy);
1093
1094 dwc3_core_exit(dwc);
1095 dwc3_ulpi_exit(dwc);
1096
1097 pm_runtime_put_sync(&pdev->dev);
1098 pm_runtime_disable(&pdev->dev);
1099
1100 return 0;
1101 }
1102
1103 #ifdef CONFIG_PM_SLEEP
1104 static int dwc3_suspend(struct device *dev)
1105 {
1106 struct dwc3 *dwc = dev_get_drvdata(dev);
1107 unsigned long flags;
1108
1109 spin_lock_irqsave(&dwc->lock, flags);
1110
1111 switch (dwc->dr_mode) {
1112 case USB_DR_MODE_PERIPHERAL:
1113 case USB_DR_MODE_OTG:
1114 dwc3_gadget_suspend(dwc);
1115 /* FALLTHROUGH */
1116 case USB_DR_MODE_HOST:
1117 default:
1118 dwc3_event_buffers_cleanup(dwc);
1119 break;
1120 }
1121
1122 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1123 spin_unlock_irqrestore(&dwc->lock, flags);
1124
1125 usb_phy_shutdown(dwc->usb3_phy);
1126 usb_phy_shutdown(dwc->usb2_phy);
1127 phy_exit(dwc->usb2_generic_phy);
1128 phy_exit(dwc->usb3_generic_phy);
1129
1130 pinctrl_pm_select_sleep_state(dev);
1131
1132 return 0;
1133 }
1134
1135 static int dwc3_resume(struct device *dev)
1136 {
1137 struct dwc3 *dwc = dev_get_drvdata(dev);
1138 unsigned long flags;
1139 int ret;
1140
1141 pinctrl_pm_select_default_state(dev);
1142
1143 usb_phy_init(dwc->usb3_phy);
1144 usb_phy_init(dwc->usb2_phy);
1145 ret = phy_init(dwc->usb2_generic_phy);
1146 if (ret < 0)
1147 return ret;
1148
1149 ret = phy_init(dwc->usb3_generic_phy);
1150 if (ret < 0)
1151 goto err_usb2phy_init;
1152
1153 spin_lock_irqsave(&dwc->lock, flags);
1154
1155 dwc3_event_buffers_setup(dwc);
1156 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1157
1158 switch (dwc->dr_mode) {
1159 case USB_DR_MODE_PERIPHERAL:
1160 case USB_DR_MODE_OTG:
1161 dwc3_gadget_resume(dwc);
1162 /* FALLTHROUGH */
1163 case USB_DR_MODE_HOST:
1164 default:
1165 /* do nothing */
1166 break;
1167 }
1168
1169 spin_unlock_irqrestore(&dwc->lock, flags);
1170
1171 pm_runtime_disable(dev);
1172 pm_runtime_set_active(dev);
1173 pm_runtime_enable(dev);
1174
1175 return 0;
1176
1177 err_usb2phy_init:
1178 phy_exit(dwc->usb2_generic_phy);
1179
1180 return ret;
1181 }
1182
1183 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1184 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1185 };
1186
1187 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
1188 #else
1189 #define DWC3_PM_OPS NULL
1190 #endif
1191
1192 #ifdef CONFIG_OF
1193 static const struct of_device_id of_dwc3_match[] = {
1194 {
1195 .compatible = "snps,dwc3"
1196 },
1197 {
1198 .compatible = "synopsys,dwc3"
1199 },
1200 { },
1201 };
1202 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1203 #endif
1204
1205 #ifdef CONFIG_ACPI
1206
1207 #define ACPI_ID_INTEL_BSW "808622B7"
1208
1209 static const struct acpi_device_id dwc3_acpi_match[] = {
1210 { ACPI_ID_INTEL_BSW, 0 },
1211 { },
1212 };
1213 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1214 #endif
1215
1216 static struct platform_driver dwc3_driver = {
1217 .probe = dwc3_probe,
1218 .remove = dwc3_remove,
1219 .driver = {
1220 .name = "dwc3",
1221 .of_match_table = of_match_ptr(of_dwc3_match),
1222 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1223 .pm = DWC3_PM_OPS,
1224 },
1225 };
1226
1227 module_platform_driver(dwc3_driver);
1228
1229 MODULE_ALIAS("platform:dwc3");
1230 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1231 MODULE_LICENSE("GPL v2");
1232 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux kernel - Deliverables
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