2 * core.c - DesignWare USB3 DRD Controller Core file
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
46 #include <linux/ioport.h>
48 #include <linux/list.h>
49 #include <linux/delay.h>
50 #include <linux/dma-mapping.h>
53 #include <linux/usb/otg.h>
54 #include <linux/usb/ch9.h>
55 #include <linux/usb/gadget.h>
63 static char *maximum_speed
= "super";
64 module_param(maximum_speed
, charp
, 0);
65 MODULE_PARM_DESC(maximum_speed
, "Maximum supported speed.");
67 /* -------------------------------------------------------------------------- */
69 void dwc3_set_mode(struct dwc3
*dwc
, u32 mode
)
73 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
74 reg
&= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG
));
75 reg
|= DWC3_GCTL_PRTCAPDIR(mode
);
76 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
80 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
81 * @dwc: pointer to our context structure
83 static void dwc3_core_soft_reset(struct dwc3
*dwc
)
87 /* Before Resetting PHY, put Core in Reset */
88 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
89 reg
|= DWC3_GCTL_CORESOFTRESET
;
90 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
92 /* Assert USB3 PHY reset */
93 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
94 reg
|= DWC3_GUSB3PIPECTL_PHYSOFTRST
;
95 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
97 /* Assert USB2 PHY reset */
98 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
99 reg
|= DWC3_GUSB2PHYCFG_PHYSOFTRST
;
100 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
102 usb_phy_init(dwc
->usb2_phy
);
103 usb_phy_init(dwc
->usb3_phy
);
106 /* Clear USB3 PHY reset */
107 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB3PIPECTL(0));
108 reg
&= ~DWC3_GUSB3PIPECTL_PHYSOFTRST
;
109 dwc3_writel(dwc
->regs
, DWC3_GUSB3PIPECTL(0), reg
);
111 /* Clear USB2 PHY reset */
112 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
113 reg
&= ~DWC3_GUSB2PHYCFG_PHYSOFTRST
;
114 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
118 /* After PHYs are stable we can take Core out of reset state */
119 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
120 reg
&= ~DWC3_GCTL_CORESOFTRESET
;
121 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
125 * dwc3_free_one_event_buffer - Frees one event buffer
126 * @dwc: Pointer to our controller context structure
127 * @evt: Pointer to event buffer to be freed
129 static void dwc3_free_one_event_buffer(struct dwc3
*dwc
,
130 struct dwc3_event_buffer
*evt
)
132 dma_free_coherent(dwc
->dev
, evt
->length
, evt
->buf
, evt
->dma
);
136 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
137 * @dwc: Pointer to our controller context structure
138 * @length: size of the event buffer
140 * Returns a pointer to the allocated event buffer structure on success
141 * otherwise ERR_PTR(errno).
143 static struct dwc3_event_buffer
*__devinit
144 dwc3_alloc_one_event_buffer(struct dwc3
*dwc
, unsigned length
)
146 struct dwc3_event_buffer
*evt
;
148 evt
= devm_kzalloc(dwc
->dev
, sizeof(*evt
), GFP_KERNEL
);
150 return ERR_PTR(-ENOMEM
);
153 evt
->length
= length
;
154 evt
->buf
= dma_alloc_coherent(dwc
->dev
, length
,
155 &evt
->dma
, GFP_KERNEL
);
157 return ERR_PTR(-ENOMEM
);
163 * dwc3_free_event_buffers - frees all allocated event buffers
164 * @dwc: Pointer to our controller context structure
166 static void dwc3_free_event_buffers(struct dwc3
*dwc
)
168 struct dwc3_event_buffer
*evt
;
171 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
172 evt
= dwc
->ev_buffs
[i
];
174 dwc3_free_one_event_buffer(dwc
, evt
);
179 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
180 * @dwc: pointer to our controller context structure
181 * @length: size of event buffer
183 * Returns 0 on success otherwise negative errno. In the error case, dwc
184 * may contain some buffers allocated but not all which were requested.
186 static int __devinit
dwc3_alloc_event_buffers(struct dwc3
*dwc
, unsigned length
)
191 num
= DWC3_NUM_INT(dwc
->hwparams
.hwparams1
);
192 dwc
->num_event_buffers
= num
;
194 dwc
->ev_buffs
= devm_kzalloc(dwc
->dev
, sizeof(*dwc
->ev_buffs
) * num
,
196 if (!dwc
->ev_buffs
) {
197 dev_err(dwc
->dev
, "can't allocate event buffers array\n");
201 for (i
= 0; i
< num
; i
++) {
202 struct dwc3_event_buffer
*evt
;
204 evt
= dwc3_alloc_one_event_buffer(dwc
, length
);
206 dev_err(dwc
->dev
, "can't allocate event buffer\n");
209 dwc
->ev_buffs
[i
] = evt
;
216 * dwc3_event_buffers_setup - setup our allocated event buffers
217 * @dwc: pointer to our controller context structure
219 * Returns 0 on success otherwise negative errno.
221 static int dwc3_event_buffers_setup(struct dwc3
*dwc
)
223 struct dwc3_event_buffer
*evt
;
226 for (n
= 0; n
< dwc
->num_event_buffers
; n
++) {
227 evt
= dwc
->ev_buffs
[n
];
228 dev_dbg(dwc
->dev
, "Event buf %p dma %08llx length %d\n",
229 evt
->buf
, (unsigned long long) evt
->dma
,
234 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRLO(n
),
235 lower_32_bits(evt
->dma
));
236 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRHI(n
),
237 upper_32_bits(evt
->dma
));
238 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(n
),
239 evt
->length
& 0xffff);
240 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(n
), 0);
246 static void dwc3_event_buffers_cleanup(struct dwc3
*dwc
)
248 struct dwc3_event_buffer
*evt
;
251 for (n
= 0; n
< dwc
->num_event_buffers
; n
++) {
252 evt
= dwc
->ev_buffs
[n
];
256 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRLO(n
), 0);
257 dwc3_writel(dwc
->regs
, DWC3_GEVNTADRHI(n
), 0);
258 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(n
), 0);
259 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(n
), 0);
263 static void __devinit
dwc3_cache_hwparams(struct dwc3
*dwc
)
265 struct dwc3_hwparams
*parms
= &dwc
->hwparams
;
267 parms
->hwparams0
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS0
);
268 parms
->hwparams1
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS1
);
269 parms
->hwparams2
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS2
);
270 parms
->hwparams3
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS3
);
271 parms
->hwparams4
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS4
);
272 parms
->hwparams5
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS5
);
273 parms
->hwparams6
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS6
);
274 parms
->hwparams7
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS7
);
275 parms
->hwparams8
= dwc3_readl(dwc
->regs
, DWC3_GHWPARAMS8
);
279 * dwc3_core_init - Low-level initialization of DWC3 Core
280 * @dwc: Pointer to our controller context structure
282 * Returns 0 on success otherwise negative errno.
284 static int __devinit
dwc3_core_init(struct dwc3
*dwc
)
286 unsigned long timeout
;
290 reg
= dwc3_readl(dwc
->regs
, DWC3_GSNPSID
);
291 /* This should read as U3 followed by revision number */
292 if ((reg
& DWC3_GSNPSID_MASK
) != 0x55330000) {
293 dev_err(dwc
->dev
, "this is not a DesignWare USB3 DRD Core\n");
299 /* issue device SoftReset too */
300 timeout
= jiffies
+ msecs_to_jiffies(500);
301 dwc3_writel(dwc
->regs
, DWC3_DCTL
, DWC3_DCTL_CSFTRST
);
303 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
304 if (!(reg
& DWC3_DCTL_CSFTRST
))
307 if (time_after(jiffies
, timeout
)) {
308 dev_err(dwc
->dev
, "Reset Timed Out\n");
316 dwc3_core_soft_reset(dwc
);
318 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
319 reg
&= ~DWC3_GCTL_SCALEDOWN_MASK
;
320 reg
&= ~DWC3_GCTL_DISSCRAMBLE
;
322 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
)) {
323 case DWC3_GHWPARAMS1_EN_PWROPT_CLK
:
324 reg
&= ~DWC3_GCTL_DSBLCLKGTNG
;
327 dev_dbg(dwc
->dev
, "No power optimization available\n");
331 * WORKAROUND: DWC3 revisions <1.90a have a bug
332 * where the device can fail to connect at SuperSpeed
333 * and falls back to high-speed mode which causes
334 * the device to enter a Connect/Disconnect loop
336 if (dwc
->revision
< DWC3_REVISION_190A
)
337 reg
|= DWC3_GCTL_U2RSTECN
;
339 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
341 ret
= dwc3_event_buffers_setup(dwc
);
343 dev_err(dwc
->dev
, "failed to setup event buffers\n");
353 static void dwc3_core_exit(struct dwc3
*dwc
)
355 dwc3_event_buffers_cleanup(dwc
);
357 usb_phy_shutdown(dwc
->usb2_phy
);
358 usb_phy_shutdown(dwc
->usb3_phy
);
361 #define DWC3_ALIGN_MASK (16 - 1)
363 static int __devinit
dwc3_probe(struct platform_device
*pdev
)
365 struct device_node
*node
= pdev
->dev
.of_node
;
366 struct resource
*res
;
368 struct device
*dev
= &pdev
->dev
;
377 mem
= devm_kzalloc(dev
, sizeof(*dwc
) + DWC3_ALIGN_MASK
, GFP_KERNEL
);
379 dev_err(dev
, "not enough memory\n");
382 dwc
= PTR_ALIGN(mem
, DWC3_ALIGN_MASK
+ 1);
385 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
387 dev_err(dev
, "missing IRQ\n");
390 dwc
->xhci_resources
[1].start
= res
->start
;
391 dwc
->xhci_resources
[1].end
= res
->end
;
392 dwc
->xhci_resources
[1].flags
= res
->flags
;
393 dwc
->xhci_resources
[1].name
= res
->name
;
395 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
397 dev_err(dev
, "missing memory resource\n");
400 dwc
->xhci_resources
[0].start
= res
->start
;
401 dwc
->xhci_resources
[0].end
= dwc
->xhci_resources
[0].start
+
403 dwc
->xhci_resources
[0].flags
= res
->flags
;
404 dwc
->xhci_resources
[0].name
= res
->name
;
407 * Request memory region but exclude xHCI regs,
408 * since it will be requested by the xhci-plat driver.
410 res
= devm_request_mem_region(dev
, res
->start
+ DWC3_GLOBALS_REGS_START
,
411 resource_size(res
) - DWC3_GLOBALS_REGS_START
,
414 dev_err(dev
, "can't request mem region\n");
418 regs
= devm_ioremap_nocache(dev
, res
->start
, resource_size(res
));
420 dev_err(dev
, "ioremap failed\n");
424 dwc
->usb2_phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB2
);
425 if (IS_ERR_OR_NULL(dwc
->usb2_phy
)) {
426 dev_err(dev
, "no usb2 phy configured\n");
427 return -EPROBE_DEFER
;
430 dwc
->usb3_phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB3
);
431 if (IS_ERR_OR_NULL(dwc
->usb3_phy
)) {
432 dev_err(dev
, "no usb3 phy configured\n");
433 return -EPROBE_DEFER
;
436 spin_lock_init(&dwc
->lock
);
437 platform_set_drvdata(pdev
, dwc
);
440 dwc
->regs_size
= resource_size(res
);
443 if (!strncmp("super", maximum_speed
, 5))
444 dwc
->maximum_speed
= DWC3_DCFG_SUPERSPEED
;
445 else if (!strncmp("high", maximum_speed
, 4))
446 dwc
->maximum_speed
= DWC3_DCFG_HIGHSPEED
;
447 else if (!strncmp("full", maximum_speed
, 4))
448 dwc
->maximum_speed
= DWC3_DCFG_FULLSPEED1
;
449 else if (!strncmp("low", maximum_speed
, 3))
450 dwc
->maximum_speed
= DWC3_DCFG_LOWSPEED
;
452 dwc
->maximum_speed
= DWC3_DCFG_SUPERSPEED
;
454 if (of_get_property(node
, "tx-fifo-resize", NULL
))
455 dwc
->needs_fifo_resize
= true;
457 pm_runtime_enable(dev
);
458 pm_runtime_get_sync(dev
);
459 pm_runtime_forbid(dev
);
461 dwc3_cache_hwparams(dwc
);
463 ret
= dwc3_alloc_event_buffers(dwc
, DWC3_EVENT_BUFFERS_SIZE
);
465 dev_err(dwc
->dev
, "failed to allocate event buffers\n");
470 ret
= dwc3_core_init(dwc
);
472 dev_err(dev
, "failed to initialize core\n");
476 mode
= DWC3_MODE(dwc
->hwparams
.hwparams0
);
479 case DWC3_MODE_DEVICE
:
480 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_DEVICE
);
481 ret
= dwc3_gadget_init(dwc
);
483 dev_err(dev
, "failed to initialize gadget\n");
488 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_HOST
);
489 ret
= dwc3_host_init(dwc
);
491 dev_err(dev
, "failed to initialize host\n");
496 dwc3_set_mode(dwc
, DWC3_GCTL_PRTCAP_OTG
);
497 ret
= dwc3_host_init(dwc
);
499 dev_err(dev
, "failed to initialize host\n");
503 ret
= dwc3_gadget_init(dwc
);
505 dev_err(dev
, "failed to initialize gadget\n");
510 dev_err(dev
, "Unsupported mode of operation %d\n", mode
);
515 ret
= dwc3_debugfs_init(dwc
);
517 dev_err(dev
, "failed to initialize debugfs\n");
521 pm_runtime_allow(dev
);
527 case DWC3_MODE_DEVICE
:
528 dwc3_gadget_exit(dwc
);
535 dwc3_gadget_exit(dwc
);
546 dwc3_free_event_buffers(dwc
);
551 static int __devexit
dwc3_remove(struct platform_device
*pdev
)
553 struct dwc3
*dwc
= platform_get_drvdata(pdev
);
554 struct resource
*res
;
556 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
558 pm_runtime_put(&pdev
->dev
);
559 pm_runtime_disable(&pdev
->dev
);
561 dwc3_debugfs_exit(dwc
);
564 case DWC3_MODE_DEVICE
:
565 dwc3_gadget_exit(dwc
);
572 dwc3_gadget_exit(dwc
);
584 static struct platform_driver dwc3_driver
= {
586 .remove
= dwc3_remove
,
592 module_platform_driver(dwc3_driver
);
594 MODULE_ALIAS("platform:dwc3");
595 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
596 MODULE_LICENSE("Dual BSD/GPL");
597 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");