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Merge branch 'for-linus-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/mason...
[deliverable/linux.git] / drivers / usb / dwc3 / core.c
1 /**
2 * core.c - DesignWare USB3 DRD Controller Core file
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/version.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/io.h>
32 #include <linux/list.h>
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of.h>
36 #include <linux/acpi.h>
37 #include <linux/pinctrl/consumer.h>
38
39 #include <linux/usb/ch9.h>
40 #include <linux/usb/gadget.h>
41 #include <linux/usb/of.h>
42 #include <linux/usb/otg.h>
43
44 #include "platform_data.h"
45 #include "core.h"
46 #include "gadget.h"
47 #include "io.h"
48
49 #include "debug.h"
50
51 /* -------------------------------------------------------------------------- */
52
53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
54 {
55 u32 reg;
56
57 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
58 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
59 reg |= DWC3_GCTL_PRTCAPDIR(mode);
60 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
61 }
62
63 /**
64 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
65 * @dwc: pointer to our context structure
66 */
67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
68 {
69 u32 reg;
70 int ret;
71
72 /* Before Resetting PHY, put Core in Reset */
73 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
74 reg |= DWC3_GCTL_CORESOFTRESET;
75 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
76
77 /* Assert USB3 PHY reset */
78 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
79 reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
80 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
81
82 /* Assert USB2 PHY reset */
83 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
84 reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
85 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
86
87 usb_phy_init(dwc->usb2_phy);
88 usb_phy_init(dwc->usb3_phy);
89 ret = phy_init(dwc->usb2_generic_phy);
90 if (ret < 0)
91 return ret;
92
93 ret = phy_init(dwc->usb3_generic_phy);
94 if (ret < 0) {
95 phy_exit(dwc->usb2_generic_phy);
96 return ret;
97 }
98 mdelay(100);
99
100 /* Clear USB3 PHY reset */
101 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
102 reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
103 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
104
105 /* Clear USB2 PHY reset */
106 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
107 reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
108 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
109
110 mdelay(100);
111
112 /* After PHYs are stable we can take Core out of reset state */
113 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
114 reg &= ~DWC3_GCTL_CORESOFTRESET;
115 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
116
117 return 0;
118 }
119
120 /**
121 * dwc3_soft_reset - Issue soft reset
122 * @dwc: Pointer to our controller context structure
123 */
124 static int dwc3_soft_reset(struct dwc3 *dwc)
125 {
126 unsigned long timeout;
127 u32 reg;
128
129 timeout = jiffies + msecs_to_jiffies(500);
130 dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
131 do {
132 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
133 if (!(reg & DWC3_DCTL_CSFTRST))
134 break;
135
136 if (time_after(jiffies, timeout)) {
137 dev_err(dwc->dev, "Reset Timed Out\n");
138 return -ETIMEDOUT;
139 }
140
141 cpu_relax();
142 } while (true);
143
144 return 0;
145 }
146
147 /*
148 * dwc3_frame_length_adjustment - Adjusts frame length if required
149 * @dwc3: Pointer to our controller context structure
150 * @fladj: Value of GFLADJ_30MHZ to adjust frame length
151 */
152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
153 {
154 u32 reg;
155 u32 dft;
156
157 if (dwc->revision < DWC3_REVISION_250A)
158 return;
159
160 if (fladj == 0)
161 return;
162
163 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
164 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
165 if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
166 "request value same as default, ignoring\n")) {
167 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
168 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
169 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
170 }
171 }
172
173 /**
174 * dwc3_free_one_event_buffer - Frees one event buffer
175 * @dwc: Pointer to our controller context structure
176 * @evt: Pointer to event buffer to be freed
177 */
178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
179 struct dwc3_event_buffer *evt)
180 {
181 dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
182 }
183
184 /**
185 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
186 * @dwc: Pointer to our controller context structure
187 * @length: size of the event buffer
188 *
189 * Returns a pointer to the allocated event buffer structure on success
190 * otherwise ERR_PTR(errno).
191 */
192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
193 unsigned length)
194 {
195 struct dwc3_event_buffer *evt;
196
197 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
198 if (!evt)
199 return ERR_PTR(-ENOMEM);
200
201 evt->dwc = dwc;
202 evt->length = length;
203 evt->buf = dma_alloc_coherent(dwc->dev, length,
204 &evt->dma, GFP_KERNEL);
205 if (!evt->buf)
206 return ERR_PTR(-ENOMEM);
207
208 return evt;
209 }
210
211 /**
212 * dwc3_free_event_buffers - frees all allocated event buffers
213 * @dwc: Pointer to our controller context structure
214 */
215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
216 {
217 struct dwc3_event_buffer *evt;
218 int i;
219
220 for (i = 0; i < dwc->num_event_buffers; i++) {
221 evt = dwc->ev_buffs[i];
222 if (evt)
223 dwc3_free_one_event_buffer(dwc, evt);
224 }
225 }
226
227 /**
228 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
229 * @dwc: pointer to our controller context structure
230 * @length: size of event buffer
231 *
232 * Returns 0 on success otherwise negative errno. In the error case, dwc
233 * may contain some buffers allocated but not all which were requested.
234 */
235 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
236 {
237 int num;
238 int i;
239
240 num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
241 dwc->num_event_buffers = num;
242
243 dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
244 GFP_KERNEL);
245 if (!dwc->ev_buffs)
246 return -ENOMEM;
247
248 for (i = 0; i < num; i++) {
249 struct dwc3_event_buffer *evt;
250
251 evt = dwc3_alloc_one_event_buffer(dwc, length);
252 if (IS_ERR(evt)) {
253 dev_err(dwc->dev, "can't allocate event buffer\n");
254 return PTR_ERR(evt);
255 }
256 dwc->ev_buffs[i] = evt;
257 }
258
259 return 0;
260 }
261
262 /**
263 * dwc3_event_buffers_setup - setup our allocated event buffers
264 * @dwc: pointer to our controller context structure
265 *
266 * Returns 0 on success otherwise negative errno.
267 */
268 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
269 {
270 struct dwc3_event_buffer *evt;
271 int n;
272
273 for (n = 0; n < dwc->num_event_buffers; n++) {
274 evt = dwc->ev_buffs[n];
275 dwc3_trace(trace_dwc3_core,
276 "Event buf %p dma %08llx length %d\n",
277 evt->buf, (unsigned long long) evt->dma,
278 evt->length);
279
280 evt->lpos = 0;
281
282 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
283 lower_32_bits(evt->dma));
284 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
285 upper_32_bits(evt->dma));
286 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
287 DWC3_GEVNTSIZ_SIZE(evt->length));
288 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
289 }
290
291 return 0;
292 }
293
294 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
295 {
296 struct dwc3_event_buffer *evt;
297 int n;
298
299 for (n = 0; n < dwc->num_event_buffers; n++) {
300 evt = dwc->ev_buffs[n];
301
302 evt->lpos = 0;
303
304 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
305 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
306 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
307 | DWC3_GEVNTSIZ_SIZE(0));
308 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
309 }
310 }
311
312 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
313 {
314 if (!dwc->has_hibernation)
315 return 0;
316
317 if (!dwc->nr_scratch)
318 return 0;
319
320 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
321 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
322 if (!dwc->scratchbuf)
323 return -ENOMEM;
324
325 return 0;
326 }
327
328 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
329 {
330 dma_addr_t scratch_addr;
331 u32 param;
332 int ret;
333
334 if (!dwc->has_hibernation)
335 return 0;
336
337 if (!dwc->nr_scratch)
338 return 0;
339
340 /* should never fall here */
341 if (!WARN_ON(dwc->scratchbuf))
342 return 0;
343
344 scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
345 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
346 DMA_BIDIRECTIONAL);
347 if (dma_mapping_error(dwc->dev, scratch_addr)) {
348 dev_err(dwc->dev, "failed to map scratch buffer\n");
349 ret = -EFAULT;
350 goto err0;
351 }
352
353 dwc->scratch_addr = scratch_addr;
354
355 param = lower_32_bits(scratch_addr);
356
357 ret = dwc3_send_gadget_generic_command(dwc,
358 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
359 if (ret < 0)
360 goto err1;
361
362 param = upper_32_bits(scratch_addr);
363
364 ret = dwc3_send_gadget_generic_command(dwc,
365 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
366 if (ret < 0)
367 goto err1;
368
369 return 0;
370
371 err1:
372 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
373 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
374
375 err0:
376 return ret;
377 }
378
379 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
380 {
381 if (!dwc->has_hibernation)
382 return;
383
384 if (!dwc->nr_scratch)
385 return;
386
387 /* should never fall here */
388 if (!WARN_ON(dwc->scratchbuf))
389 return;
390
391 dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
392 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
393 kfree(dwc->scratchbuf);
394 }
395
396 static void dwc3_core_num_eps(struct dwc3 *dwc)
397 {
398 struct dwc3_hwparams *parms = &dwc->hwparams;
399
400 dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
401 dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
402
403 dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
404 dwc->num_in_eps, dwc->num_out_eps);
405 }
406
407 static void dwc3_cache_hwparams(struct dwc3 *dwc)
408 {
409 struct dwc3_hwparams *parms = &dwc->hwparams;
410
411 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
412 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
413 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
414 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
415 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
416 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
417 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
418 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
419 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
420 }
421
422 /**
423 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
424 * @dwc: Pointer to our controller context structure
425 *
426 * Returns 0 on success. The USB PHY interfaces are configured but not
427 * initialized. The PHY interfaces and the PHYs get initialized together with
428 * the core in dwc3_core_init.
429 */
430 static int dwc3_phy_setup(struct dwc3 *dwc)
431 {
432 u32 reg;
433 int ret;
434
435 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
436
437 /*
438 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
439 * to '0' during coreConsultant configuration. So default value
440 * will be '0' when the core is reset. Application needs to set it
441 * to '1' after the core initialization is completed.
442 */
443 if (dwc->revision > DWC3_REVISION_194A)
444 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
445
446 if (dwc->u2ss_inp3_quirk)
447 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
448
449 if (dwc->req_p1p2p3_quirk)
450 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
451
452 if (dwc->del_p1p2p3_quirk)
453 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
454
455 if (dwc->del_phy_power_chg_quirk)
456 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
457
458 if (dwc->lfps_filter_quirk)
459 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
460
461 if (dwc->rx_detect_poll_quirk)
462 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
463
464 if (dwc->tx_de_emphasis_quirk)
465 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
466
467 if (dwc->dis_u3_susphy_quirk)
468 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
469
470 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
471
472 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
473
474 /* Select the HS PHY interface */
475 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
476 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
477 if (dwc->hsphy_interface &&
478 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
479 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
480 break;
481 } else if (dwc->hsphy_interface &&
482 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
483 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
484 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
485 } else {
486 /* Relying on default value. */
487 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
488 break;
489 }
490 /* FALLTHROUGH */
491 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
492 /* Making sure the interface and PHY are operational */
493 ret = dwc3_soft_reset(dwc);
494 if (ret)
495 return ret;
496
497 udelay(1);
498
499 ret = dwc3_ulpi_init(dwc);
500 if (ret)
501 return ret;
502 /* FALLTHROUGH */
503 default:
504 break;
505 }
506
507 /*
508 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
509 * '0' during coreConsultant configuration. So default value will
510 * be '0' when the core is reset. Application needs to set it to
511 * '1' after the core initialization is completed.
512 */
513 if (dwc->revision > DWC3_REVISION_194A)
514 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
515
516 if (dwc->dis_u2_susphy_quirk)
517 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
518
519 if (dwc->dis_enblslpm_quirk)
520 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
521
522 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
523
524 return 0;
525 }
526
527 /**
528 * dwc3_core_init - Low-level initialization of DWC3 Core
529 * @dwc: Pointer to our controller context structure
530 *
531 * Returns 0 on success otherwise negative errno.
532 */
533 static int dwc3_core_init(struct dwc3 *dwc)
534 {
535 u32 hwparams4 = dwc->hwparams.hwparams4;
536 u32 reg;
537 int ret;
538
539 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
540 /* This should read as U3 followed by revision number */
541 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
542 /* Detected DWC_usb3 IP */
543 dwc->revision = reg;
544 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
545 /* Detected DWC_usb31 IP */
546 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
547 dwc->revision |= DWC3_REVISION_IS_DWC31;
548 } else {
549 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
550 ret = -ENODEV;
551 goto err0;
552 }
553
554 /*
555 * Write Linux Version Code to our GUID register so it's easy to figure
556 * out which kernel version a bug was found.
557 */
558 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
559
560 /* Handle USB2.0-only core configuration */
561 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
562 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
563 if (dwc->maximum_speed == USB_SPEED_SUPER)
564 dwc->maximum_speed = USB_SPEED_HIGH;
565 }
566
567 /* issue device SoftReset too */
568 ret = dwc3_soft_reset(dwc);
569 if (ret)
570 goto err0;
571
572 ret = dwc3_core_soft_reset(dwc);
573 if (ret)
574 goto err0;
575
576 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
577 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
578
579 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
580 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
581 /**
582 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
583 * issue which would cause xHCI compliance tests to fail.
584 *
585 * Because of that we cannot enable clock gating on such
586 * configurations.
587 *
588 * Refers to:
589 *
590 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
591 * SOF/ITP Mode Used
592 */
593 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
594 dwc->dr_mode == USB_DR_MODE_OTG) &&
595 (dwc->revision >= DWC3_REVISION_210A &&
596 dwc->revision <= DWC3_REVISION_250A))
597 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
598 else
599 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
600 break;
601 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
602 /* enable hibernation here */
603 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
604
605 /*
606 * REVISIT Enabling this bit so that host-mode hibernation
607 * will work. Device-mode hibernation is not yet implemented.
608 */
609 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
610 break;
611 default:
612 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
613 }
614
615 /* check if current dwc3 is on simulation board */
616 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
617 dwc3_trace(trace_dwc3_core,
618 "running on FPGA platform\n");
619 dwc->is_fpga = true;
620 }
621
622 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
623 "disable_scramble cannot be used on non-FPGA builds\n");
624
625 if (dwc->disable_scramble_quirk && dwc->is_fpga)
626 reg |= DWC3_GCTL_DISSCRAMBLE;
627 else
628 reg &= ~DWC3_GCTL_DISSCRAMBLE;
629
630 if (dwc->u2exit_lfps_quirk)
631 reg |= DWC3_GCTL_U2EXIT_LFPS;
632
633 /*
634 * WORKAROUND: DWC3 revisions <1.90a have a bug
635 * where the device can fail to connect at SuperSpeed
636 * and falls back to high-speed mode which causes
637 * the device to enter a Connect/Disconnect loop
638 */
639 if (dwc->revision < DWC3_REVISION_190A)
640 reg |= DWC3_GCTL_U2RSTECN;
641
642 dwc3_core_num_eps(dwc);
643
644 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
645
646 ret = dwc3_alloc_scratch_buffers(dwc);
647 if (ret)
648 goto err1;
649
650 ret = dwc3_setup_scratch_buffers(dwc);
651 if (ret)
652 goto err2;
653
654 return 0;
655
656 err2:
657 dwc3_free_scratch_buffers(dwc);
658
659 err1:
660 usb_phy_shutdown(dwc->usb2_phy);
661 usb_phy_shutdown(dwc->usb3_phy);
662 phy_exit(dwc->usb2_generic_phy);
663 phy_exit(dwc->usb3_generic_phy);
664
665 err0:
666 return ret;
667 }
668
669 static void dwc3_core_exit(struct dwc3 *dwc)
670 {
671 dwc3_free_scratch_buffers(dwc);
672 usb_phy_shutdown(dwc->usb2_phy);
673 usb_phy_shutdown(dwc->usb3_phy);
674 phy_exit(dwc->usb2_generic_phy);
675 phy_exit(dwc->usb3_generic_phy);
676 }
677
678 static int dwc3_core_get_phy(struct dwc3 *dwc)
679 {
680 struct device *dev = dwc->dev;
681 struct device_node *node = dev->of_node;
682 int ret;
683
684 if (node) {
685 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
686 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
687 } else {
688 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
689 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
690 }
691
692 if (IS_ERR(dwc->usb2_phy)) {
693 ret = PTR_ERR(dwc->usb2_phy);
694 if (ret == -ENXIO || ret == -ENODEV) {
695 dwc->usb2_phy = NULL;
696 } else if (ret == -EPROBE_DEFER) {
697 return ret;
698 } else {
699 dev_err(dev, "no usb2 phy configured\n");
700 return ret;
701 }
702 }
703
704 if (IS_ERR(dwc->usb3_phy)) {
705 ret = PTR_ERR(dwc->usb3_phy);
706 if (ret == -ENXIO || ret == -ENODEV) {
707 dwc->usb3_phy = NULL;
708 } else if (ret == -EPROBE_DEFER) {
709 return ret;
710 } else {
711 dev_err(dev, "no usb3 phy configured\n");
712 return ret;
713 }
714 }
715
716 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
717 if (IS_ERR(dwc->usb2_generic_phy)) {
718 ret = PTR_ERR(dwc->usb2_generic_phy);
719 if (ret == -ENOSYS || ret == -ENODEV) {
720 dwc->usb2_generic_phy = NULL;
721 } else if (ret == -EPROBE_DEFER) {
722 return ret;
723 } else {
724 dev_err(dev, "no usb2 phy configured\n");
725 return ret;
726 }
727 }
728
729 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
730 if (IS_ERR(dwc->usb3_generic_phy)) {
731 ret = PTR_ERR(dwc->usb3_generic_phy);
732 if (ret == -ENOSYS || ret == -ENODEV) {
733 dwc->usb3_generic_phy = NULL;
734 } else if (ret == -EPROBE_DEFER) {
735 return ret;
736 } else {
737 dev_err(dev, "no usb3 phy configured\n");
738 return ret;
739 }
740 }
741
742 return 0;
743 }
744
745 static int dwc3_core_init_mode(struct dwc3 *dwc)
746 {
747 struct device *dev = dwc->dev;
748 int ret;
749
750 switch (dwc->dr_mode) {
751 case USB_DR_MODE_PERIPHERAL:
752 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
753 ret = dwc3_gadget_init(dwc);
754 if (ret) {
755 dev_err(dev, "failed to initialize gadget\n");
756 return ret;
757 }
758 break;
759 case USB_DR_MODE_HOST:
760 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
761 ret = dwc3_host_init(dwc);
762 if (ret) {
763 dev_err(dev, "failed to initialize host\n");
764 return ret;
765 }
766 break;
767 case USB_DR_MODE_OTG:
768 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
769 ret = dwc3_host_init(dwc);
770 if (ret) {
771 dev_err(dev, "failed to initialize host\n");
772 return ret;
773 }
774
775 ret = dwc3_gadget_init(dwc);
776 if (ret) {
777 dev_err(dev, "failed to initialize gadget\n");
778 return ret;
779 }
780 break;
781 default:
782 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
783 return -EINVAL;
784 }
785
786 return 0;
787 }
788
789 static void dwc3_core_exit_mode(struct dwc3 *dwc)
790 {
791 switch (dwc->dr_mode) {
792 case USB_DR_MODE_PERIPHERAL:
793 dwc3_gadget_exit(dwc);
794 break;
795 case USB_DR_MODE_HOST:
796 dwc3_host_exit(dwc);
797 break;
798 case USB_DR_MODE_OTG:
799 dwc3_host_exit(dwc);
800 dwc3_gadget_exit(dwc);
801 break;
802 default:
803 /* do nothing */
804 break;
805 }
806 }
807
808 #define DWC3_ALIGN_MASK (16 - 1)
809
810 static int dwc3_probe(struct platform_device *pdev)
811 {
812 struct device *dev = &pdev->dev;
813 struct dwc3_platform_data *pdata = dev_get_platdata(dev);
814 struct resource *res;
815 struct dwc3 *dwc;
816 u8 lpm_nyet_threshold;
817 u8 tx_de_emphasis;
818 u8 hird_threshold;
819 u32 fladj = 0;
820
821 int ret;
822
823 void __iomem *regs;
824 void *mem;
825
826 mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
827 if (!mem)
828 return -ENOMEM;
829
830 dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
831 dwc->mem = mem;
832 dwc->dev = dev;
833
834 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
835 if (!res) {
836 dev_err(dev, "missing IRQ\n");
837 return -ENODEV;
838 }
839 dwc->xhci_resources[1].start = res->start;
840 dwc->xhci_resources[1].end = res->end;
841 dwc->xhci_resources[1].flags = res->flags;
842 dwc->xhci_resources[1].name = res->name;
843
844 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
845 if (!res) {
846 dev_err(dev, "missing memory resource\n");
847 return -ENODEV;
848 }
849
850 dwc->xhci_resources[0].start = res->start;
851 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
852 DWC3_XHCI_REGS_END;
853 dwc->xhci_resources[0].flags = res->flags;
854 dwc->xhci_resources[0].name = res->name;
855
856 res->start += DWC3_GLOBALS_REGS_START;
857
858 /*
859 * Request memory region but exclude xHCI regs,
860 * since it will be requested by the xhci-plat driver.
861 */
862 regs = devm_ioremap_resource(dev, res);
863 if (IS_ERR(regs)) {
864 ret = PTR_ERR(regs);
865 goto err0;
866 }
867
868 dwc->regs = regs;
869 dwc->regs_size = resource_size(res);
870
871 /* default to highest possible threshold */
872 lpm_nyet_threshold = 0xff;
873
874 /* default to -3.5dB de-emphasis */
875 tx_de_emphasis = 1;
876
877 /*
878 * default to assert utmi_sleep_n and use maximum allowed HIRD
879 * threshold value of 0b1100
880 */
881 hird_threshold = 12;
882
883 dwc->maximum_speed = usb_get_maximum_speed(dev);
884 dwc->dr_mode = usb_get_dr_mode(dev);
885
886 dwc->has_lpm_erratum = device_property_read_bool(dev,
887 "snps,has-lpm-erratum");
888 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
889 &lpm_nyet_threshold);
890 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
891 "snps,is-utmi-l1-suspend");
892 device_property_read_u8(dev, "snps,hird-threshold",
893 &hird_threshold);
894 dwc->usb3_lpm_capable = device_property_read_bool(dev,
895 "snps,usb3_lpm_capable");
896
897 dwc->needs_fifo_resize = device_property_read_bool(dev,
898 "tx-fifo-resize");
899
900 dwc->disable_scramble_quirk = device_property_read_bool(dev,
901 "snps,disable_scramble_quirk");
902 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
903 "snps,u2exit_lfps_quirk");
904 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
905 "snps,u2ss_inp3_quirk");
906 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
907 "snps,req_p1p2p3_quirk");
908 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
909 "snps,del_p1p2p3_quirk");
910 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
911 "snps,del_phy_power_chg_quirk");
912 dwc->lfps_filter_quirk = device_property_read_bool(dev,
913 "snps,lfps_filter_quirk");
914 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
915 "snps,rx_detect_poll_quirk");
916 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
917 "snps,dis_u3_susphy_quirk");
918 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
919 "snps,dis_u2_susphy_quirk");
920 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
921 "snps,dis_enblslpm_quirk");
922
923 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
924 "snps,tx_de_emphasis_quirk");
925 device_property_read_u8(dev, "snps,tx_de_emphasis",
926 &tx_de_emphasis);
927 device_property_read_string(dev, "snps,hsphy_interface",
928 &dwc->hsphy_interface);
929 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
930 &fladj);
931
932 if (pdata) {
933 dwc->maximum_speed = pdata->maximum_speed;
934 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
935 if (pdata->lpm_nyet_threshold)
936 lpm_nyet_threshold = pdata->lpm_nyet_threshold;
937 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
938 if (pdata->hird_threshold)
939 hird_threshold = pdata->hird_threshold;
940
941 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
942 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
943 dwc->dr_mode = pdata->dr_mode;
944
945 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
946 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
947 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
948 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
949 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
950 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
951 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
952 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
953 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
954 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
955 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
956
957 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
958 if (pdata->tx_de_emphasis)
959 tx_de_emphasis = pdata->tx_de_emphasis;
960
961 dwc->hsphy_interface = pdata->hsphy_interface;
962 fladj = pdata->fladj_value;
963 }
964
965 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
966 dwc->tx_de_emphasis = tx_de_emphasis;
967
968 dwc->hird_threshold = hird_threshold
969 | (dwc->is_utmi_l1_suspend << 4);
970
971 platform_set_drvdata(pdev, dwc);
972 dwc3_cache_hwparams(dwc);
973
974 ret = dwc3_phy_setup(dwc);
975 if (ret)
976 goto err0;
977
978 ret = dwc3_core_get_phy(dwc);
979 if (ret)
980 goto err0;
981
982 spin_lock_init(&dwc->lock);
983
984 if (!dev->dma_mask) {
985 dev->dma_mask = dev->parent->dma_mask;
986 dev->dma_parms = dev->parent->dma_parms;
987 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
988 }
989
990 pm_runtime_enable(dev);
991 pm_runtime_get_sync(dev);
992 pm_runtime_forbid(dev);
993
994 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
995 if (ret) {
996 dev_err(dwc->dev, "failed to allocate event buffers\n");
997 ret = -ENOMEM;
998 goto err1;
999 }
1000
1001 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1002 dwc->dr_mode = USB_DR_MODE_HOST;
1003 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1004 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1005
1006 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1007 dwc->dr_mode = USB_DR_MODE_OTG;
1008
1009 ret = dwc3_core_init(dwc);
1010 if (ret) {
1011 dev_err(dev, "failed to initialize core\n");
1012 goto err1;
1013 }
1014
1015 /* Check the maximum_speed parameter */
1016 switch (dwc->maximum_speed) {
1017 case USB_SPEED_LOW:
1018 case USB_SPEED_FULL:
1019 case USB_SPEED_HIGH:
1020 case USB_SPEED_SUPER:
1021 case USB_SPEED_SUPER_PLUS:
1022 break;
1023 default:
1024 dev_err(dev, "invalid maximum_speed parameter %d\n",
1025 dwc->maximum_speed);
1026 /* fall through */
1027 case USB_SPEED_UNKNOWN:
1028 /* default to superspeed */
1029 dwc->maximum_speed = USB_SPEED_SUPER;
1030
1031 /*
1032 * default to superspeed plus if we are capable.
1033 */
1034 if (dwc3_is_usb31(dwc) &&
1035 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1036 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1037 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1038
1039 break;
1040 }
1041
1042 /* Adjust Frame Length */
1043 dwc3_frame_length_adjustment(dwc, fladj);
1044
1045 usb_phy_set_suspend(dwc->usb2_phy, 0);
1046 usb_phy_set_suspend(dwc->usb3_phy, 0);
1047 ret = phy_power_on(dwc->usb2_generic_phy);
1048 if (ret < 0)
1049 goto err2;
1050
1051 ret = phy_power_on(dwc->usb3_generic_phy);
1052 if (ret < 0)
1053 goto err3;
1054
1055 ret = dwc3_event_buffers_setup(dwc);
1056 if (ret) {
1057 dev_err(dwc->dev, "failed to setup event buffers\n");
1058 goto err4;
1059 }
1060
1061 ret = dwc3_core_init_mode(dwc);
1062 if (ret)
1063 goto err5;
1064
1065 ret = dwc3_debugfs_init(dwc);
1066 if (ret) {
1067 dev_err(dev, "failed to initialize debugfs\n");
1068 goto err6;
1069 }
1070
1071 pm_runtime_allow(dev);
1072
1073 return 0;
1074
1075 err6:
1076 dwc3_core_exit_mode(dwc);
1077
1078 err5:
1079 dwc3_event_buffers_cleanup(dwc);
1080
1081 err4:
1082 phy_power_off(dwc->usb3_generic_phy);
1083
1084 err3:
1085 phy_power_off(dwc->usb2_generic_phy);
1086
1087 err2:
1088 usb_phy_set_suspend(dwc->usb2_phy, 1);
1089 usb_phy_set_suspend(dwc->usb3_phy, 1);
1090 dwc3_core_exit(dwc);
1091
1092 err1:
1093 dwc3_free_event_buffers(dwc);
1094 dwc3_ulpi_exit(dwc);
1095
1096 err0:
1097 /*
1098 * restore res->start back to its original value so that, in case the
1099 * probe is deferred, we don't end up getting error in request the
1100 * memory region the next time probe is called.
1101 */
1102 res->start -= DWC3_GLOBALS_REGS_START;
1103
1104 return ret;
1105 }
1106
1107 static int dwc3_remove(struct platform_device *pdev)
1108 {
1109 struct dwc3 *dwc = platform_get_drvdata(pdev);
1110 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1111
1112 /*
1113 * restore res->start back to its original value so that, in case the
1114 * probe is deferred, we don't end up getting error in request the
1115 * memory region the next time probe is called.
1116 */
1117 res->start -= DWC3_GLOBALS_REGS_START;
1118
1119 dwc3_debugfs_exit(dwc);
1120 dwc3_core_exit_mode(dwc);
1121 dwc3_event_buffers_cleanup(dwc);
1122 dwc3_free_event_buffers(dwc);
1123
1124 usb_phy_set_suspend(dwc->usb2_phy, 1);
1125 usb_phy_set_suspend(dwc->usb3_phy, 1);
1126 phy_power_off(dwc->usb2_generic_phy);
1127 phy_power_off(dwc->usb3_generic_phy);
1128
1129 dwc3_core_exit(dwc);
1130 dwc3_ulpi_exit(dwc);
1131
1132 pm_runtime_put_sync(&pdev->dev);
1133 pm_runtime_disable(&pdev->dev);
1134
1135 return 0;
1136 }
1137
1138 #ifdef CONFIG_PM_SLEEP
1139 static int dwc3_suspend(struct device *dev)
1140 {
1141 struct dwc3 *dwc = dev_get_drvdata(dev);
1142 unsigned long flags;
1143
1144 spin_lock_irqsave(&dwc->lock, flags);
1145
1146 switch (dwc->dr_mode) {
1147 case USB_DR_MODE_PERIPHERAL:
1148 case USB_DR_MODE_OTG:
1149 dwc3_gadget_suspend(dwc);
1150 /* FALLTHROUGH */
1151 case USB_DR_MODE_HOST:
1152 default:
1153 dwc3_event_buffers_cleanup(dwc);
1154 break;
1155 }
1156
1157 dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1158 spin_unlock_irqrestore(&dwc->lock, flags);
1159
1160 usb_phy_shutdown(dwc->usb3_phy);
1161 usb_phy_shutdown(dwc->usb2_phy);
1162 phy_exit(dwc->usb2_generic_phy);
1163 phy_exit(dwc->usb3_generic_phy);
1164
1165 pinctrl_pm_select_sleep_state(dev);
1166
1167 return 0;
1168 }
1169
1170 static int dwc3_resume(struct device *dev)
1171 {
1172 struct dwc3 *dwc = dev_get_drvdata(dev);
1173 unsigned long flags;
1174 int ret;
1175
1176 pinctrl_pm_select_default_state(dev);
1177
1178 usb_phy_init(dwc->usb3_phy);
1179 usb_phy_init(dwc->usb2_phy);
1180 ret = phy_init(dwc->usb2_generic_phy);
1181 if (ret < 0)
1182 return ret;
1183
1184 ret = phy_init(dwc->usb3_generic_phy);
1185 if (ret < 0)
1186 goto err_usb2phy_init;
1187
1188 spin_lock_irqsave(&dwc->lock, flags);
1189
1190 dwc3_event_buffers_setup(dwc);
1191 dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1192
1193 switch (dwc->dr_mode) {
1194 case USB_DR_MODE_PERIPHERAL:
1195 case USB_DR_MODE_OTG:
1196 dwc3_gadget_resume(dwc);
1197 /* FALLTHROUGH */
1198 case USB_DR_MODE_HOST:
1199 default:
1200 /* do nothing */
1201 break;
1202 }
1203
1204 spin_unlock_irqrestore(&dwc->lock, flags);
1205
1206 pm_runtime_disable(dev);
1207 pm_runtime_set_active(dev);
1208 pm_runtime_enable(dev);
1209
1210 return 0;
1211
1212 err_usb2phy_init:
1213 phy_exit(dwc->usb2_generic_phy);
1214
1215 return ret;
1216 }
1217
1218 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1219 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1220 };
1221
1222 #define DWC3_PM_OPS &(dwc3_dev_pm_ops)
1223 #else
1224 #define DWC3_PM_OPS NULL
1225 #endif
1226
1227 #ifdef CONFIG_OF
1228 static const struct of_device_id of_dwc3_match[] = {
1229 {
1230 .compatible = "snps,dwc3"
1231 },
1232 {
1233 .compatible = "synopsys,dwc3"
1234 },
1235 { },
1236 };
1237 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1238 #endif
1239
1240 #ifdef CONFIG_ACPI
1241
1242 #define ACPI_ID_INTEL_BSW "808622B7"
1243
1244 static const struct acpi_device_id dwc3_acpi_match[] = {
1245 { ACPI_ID_INTEL_BSW, 0 },
1246 { },
1247 };
1248 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1249 #endif
1250
1251 static struct platform_driver dwc3_driver = {
1252 .probe = dwc3_probe,
1253 .remove = dwc3_remove,
1254 .driver = {
1255 .name = "dwc3",
1256 .of_match_table = of_match_ptr(of_dwc3_match),
1257 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1258 .pm = DWC3_PM_OPS,
1259 },
1260 };
1261
1262 module_platform_driver(dwc3_driver);
1263
1264 MODULE_ALIAS("platform:dwc3");
1265 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1266 MODULE_LICENSE("GPL v2");
1267 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Linux kernel - Deliverables
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