2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
39 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
40 struct dwc3_ep
*dep
, struct dwc3_request
*req
);
42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state
)
51 case EP0_STATUS_PHASE
:
52 return "Status Phase";
58 static int dwc3_ep0_start_trans(struct dwc3
*dwc
, u8 epnum
, dma_addr_t buf_dma
,
59 u32 len
, u32 type
, bool chain
)
61 struct dwc3_gadget_ep_cmd_params params
;
67 dep
= dwc
->eps
[epnum
];
68 if (dep
->flags
& DWC3_EP_BUSY
) {
69 dwc3_trace(trace_dwc3_ep0
, "%s still busy", dep
->name
);
73 trb
= &dwc
->ep0_trb
[dep
->free_slot
];
78 trb
->bpl
= lower_32_bits(buf_dma
);
79 trb
->bph
= upper_32_bits(buf_dma
);
83 trb
->ctrl
|= (DWC3_TRB_CTRL_HWO
84 | DWC3_TRB_CTRL_ISP_IMI
);
87 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
89 trb
->ctrl
|= (DWC3_TRB_CTRL_IOC
95 memset(¶ms
, 0, sizeof(params
));
96 params
.param0
= upper_32_bits(dwc
->ep0_trb_addr
);
97 params
.param1
= lower_32_bits(dwc
->ep0_trb_addr
);
99 trace_dwc3_prepare_trb(dep
, trb
);
101 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
102 DWC3_DEPCMD_STARTTRANSFER
, ¶ms
);
104 dwc3_trace(trace_dwc3_ep0
, "%s STARTTRANSFER failed",
109 dep
->flags
|= DWC3_EP_BUSY
;
110 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dwc
,
113 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep
*dep
,
119 struct dwc3_request
*req
)
121 struct dwc3
*dwc
= dep
->dwc
;
123 req
->request
.actual
= 0;
124 req
->request
.status
= -EINPROGRESS
;
125 req
->epnum
= dep
->number
;
127 list_add_tail(&req
->list
, &dep
->request_list
);
130 * Gadget driver might not be quick enough to queue a request
131 * before we get a Transfer Not Ready event on this endpoint.
133 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
134 * flag is set, it's telling us that as soon as Gadget queues the
135 * required request, we should kick the transfer here because the
136 * IRQ we were waiting for is long gone.
138 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
141 direction
= !!(dep
->flags
& DWC3_EP0_DIR_IN
);
143 if (dwc
->ep0state
!= EP0_DATA_PHASE
) {
144 dev_WARN(dwc
->dev
, "Unexpected pending request\n");
148 __dwc3_ep0_do_control_data(dwc
, dwc
->eps
[direction
], req
);
150 dep
->flags
&= ~(DWC3_EP_PENDING_REQUEST
|
157 * In case gadget driver asked us to delay the STATUS phase,
160 if (dwc
->delayed_status
) {
163 direction
= !dwc
->ep0_expect_in
;
164 dwc
->delayed_status
= false;
165 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_CONFIGURED
);
167 if (dwc
->ep0state
== EP0_STATUS_PHASE
)
168 __dwc3_ep0_do_control_status(dwc
, dwc
->eps
[direction
]);
170 dwc3_trace(trace_dwc3_ep0
,
171 "too early for delayed status");
177 * Unfortunately we have uncovered a limitation wrt the Data Phase.
179 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
180 * come before issueing Start Transfer command, but if we do, we will
181 * miss situations where the host starts another SETUP phase instead of
182 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
183 * Layer Compliance Suite.
185 * The problem surfaces due to the fact that in case of back-to-back
186 * SETUP packets there will be no XferNotReady(DATA) generated and we
187 * will be stuck waiting for XferNotReady(DATA) forever.
189 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
190 * it tells us to start Data Phase right away. It also mentions that if
191 * we receive a SETUP phase instead of the DATA phase, core will issue
192 * XferComplete for the DATA phase, before actually initiating it in
193 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
194 * can only be used to print some debugging logs, as the core expects
195 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
196 * just so it completes right away, without transferring anything and,
197 * only then, we can go back to the SETUP phase.
199 * Because of this scenario, SNPS decided to change the programming
200 * model of control transfers and support on-demand transfers only for
201 * the STATUS phase. To fix the issue we have now, we will always wait
202 * for gadget driver to queue the DATA phase's struct usb_request, then
203 * start it right away.
205 * If we're actually in a 2-stage transfer, we will wait for
206 * XferNotReady(STATUS).
208 if (dwc
->three_stage_setup
) {
211 direction
= dwc
->ep0_expect_in
;
212 dwc
->ep0state
= EP0_DATA_PHASE
;
214 __dwc3_ep0_do_control_data(dwc
, dwc
->eps
[direction
], req
);
216 dep
->flags
&= ~DWC3_EP0_DIR_IN
;
222 int dwc3_gadget_ep0_queue(struct usb_ep
*ep
, struct usb_request
*request
,
225 struct dwc3_request
*req
= to_dwc3_request(request
);
226 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
227 struct dwc3
*dwc
= dep
->dwc
;
233 spin_lock_irqsave(&dwc
->lock
, flags
);
234 if (!dep
->endpoint
.desc
) {
235 dwc3_trace(trace_dwc3_ep0
,
236 "trying to queue request %p to disabled %s",
242 /* we share one TRB for ep0/1 */
243 if (!list_empty(&dep
->request_list
)) {
248 dwc3_trace(trace_dwc3_ep0
,
249 "queueing request %p to %s length %d state '%s'",
250 request
, dep
->name
, request
->length
,
251 dwc3_ep0_state_string(dwc
->ep0state
));
253 ret
= __dwc3_gadget_ep0_queue(dep
, req
);
256 spin_unlock_irqrestore(&dwc
->lock
, flags
);
261 static void dwc3_ep0_stall_and_restart(struct dwc3
*dwc
)
265 /* reinitialize physical ep1 */
267 dep
->flags
= DWC3_EP_ENABLED
;
269 /* stall is always issued on EP0 */
271 __dwc3_gadget_ep_set_halt(dep
, 1, false);
272 dep
->flags
= DWC3_EP_ENABLED
;
273 dwc
->delayed_status
= false;
275 if (!list_empty(&dep
->request_list
)) {
276 struct dwc3_request
*req
;
278 req
= next_request(&dep
->request_list
);
279 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
282 dwc
->ep0state
= EP0_SETUP_PHASE
;
283 dwc3_ep0_out_start(dwc
);
286 int __dwc3_gadget_ep0_set_halt(struct usb_ep
*ep
, int value
)
288 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
289 struct dwc3
*dwc
= dep
->dwc
;
291 dwc3_ep0_stall_and_restart(dwc
);
296 int dwc3_gadget_ep0_set_halt(struct usb_ep
*ep
, int value
)
298 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
299 struct dwc3
*dwc
= dep
->dwc
;
303 spin_lock_irqsave(&dwc
->lock
, flags
);
304 ret
= __dwc3_gadget_ep0_set_halt(ep
, value
);
305 spin_unlock_irqrestore(&dwc
->lock
, flags
);
310 void dwc3_ep0_out_start(struct dwc3
*dwc
)
314 ret
= dwc3_ep0_start_trans(dwc
, 0, dwc
->ctrl_req_addr
, 8,
315 DWC3_TRBCTL_CONTROL_SETUP
, false);
319 static struct dwc3_ep
*dwc3_wIndex_to_dep(struct dwc3
*dwc
, __le16 wIndex_le
)
322 u32 windex
= le16_to_cpu(wIndex_le
);
325 epnum
= (windex
& USB_ENDPOINT_NUMBER_MASK
) << 1;
326 if ((windex
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
)
329 dep
= dwc
->eps
[epnum
];
330 if (dep
->flags
& DWC3_EP_ENABLED
)
336 static void dwc3_ep0_status_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
342 static int dwc3_ep0_handle_status(struct dwc3
*dwc
,
343 struct usb_ctrlrequest
*ctrl
)
349 __le16
*response_pkt
;
351 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
353 case USB_RECIP_DEVICE
:
355 * LTM will be set once we know how to set this in HW.
357 usb_status
|= dwc
->gadget
.is_selfpowered
;
359 if ((dwc
->speed
== DWC3_DSTS_SUPERSPEED
) ||
360 (dwc
->speed
== DWC3_DSTS_SUPERSPEED_PLUS
)) {
361 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
362 if (reg
& DWC3_DCTL_INITU1ENA
)
363 usb_status
|= 1 << USB_DEV_STAT_U1_ENABLED
;
364 if (reg
& DWC3_DCTL_INITU2ENA
)
365 usb_status
|= 1 << USB_DEV_STAT_U2_ENABLED
;
370 case USB_RECIP_INTERFACE
:
372 * Function Remote Wake Capable D0
373 * Function Remote Wakeup D1
377 case USB_RECIP_ENDPOINT
:
378 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
382 if (dep
->flags
& DWC3_EP_STALL
)
383 usb_status
= 1 << USB_ENDPOINT_HALT
;
389 response_pkt
= (__le16
*) dwc
->setup_buf
;
390 *response_pkt
= cpu_to_le16(usb_status
);
393 dwc
->ep0_usb_req
.dep
= dep
;
394 dwc
->ep0_usb_req
.request
.length
= sizeof(*response_pkt
);
395 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
396 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_status_cmpl
;
398 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
401 static int dwc3_ep0_handle_feature(struct dwc3
*dwc
,
402 struct usb_ctrlrequest
*ctrl
, int set
)
410 enum usb_device_state state
;
412 wValue
= le16_to_cpu(ctrl
->wValue
);
413 wIndex
= le16_to_cpu(ctrl
->wIndex
);
414 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
415 state
= dwc
->gadget
.state
;
418 case USB_RECIP_DEVICE
:
421 case USB_DEVICE_REMOTE_WAKEUP
:
424 * 9.4.1 says only only for SS, in AddressState only for
425 * default control pipe
427 case USB_DEVICE_U1_ENABLE
:
428 if (state
!= USB_STATE_CONFIGURED
)
430 if ((dwc
->speed
!= DWC3_DSTS_SUPERSPEED
) &&
431 (dwc
->speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
434 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
436 reg
|= DWC3_DCTL_INITU1ENA
;
438 reg
&= ~DWC3_DCTL_INITU1ENA
;
439 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
442 case USB_DEVICE_U2_ENABLE
:
443 if (state
!= USB_STATE_CONFIGURED
)
445 if ((dwc
->speed
!= DWC3_DSTS_SUPERSPEED
) &&
446 (dwc
->speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
449 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
451 reg
|= DWC3_DCTL_INITU2ENA
;
453 reg
&= ~DWC3_DCTL_INITU2ENA
;
454 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
457 case USB_DEVICE_LTM_ENABLE
:
460 case USB_DEVICE_TEST_MODE
:
461 if ((wIndex
& 0xff) != 0)
466 dwc
->test_mode_nr
= wIndex
>> 8;
467 dwc
->test_mode
= true;
474 case USB_RECIP_INTERFACE
:
476 case USB_INTRF_FUNC_SUSPEND
:
477 if (wIndex
& USB_INTRF_FUNC_SUSPEND_LP
)
478 /* XXX enable Low power suspend */
480 if (wIndex
& USB_INTRF_FUNC_SUSPEND_RW
)
481 /* XXX enable remote wakeup */
489 case USB_RECIP_ENDPOINT
:
491 case USB_ENDPOINT_HALT
:
492 dep
= dwc3_wIndex_to_dep(dwc
, wIndex
);
495 if (set
== 0 && (dep
->flags
& DWC3_EP_WEDGE
))
497 ret
= __dwc3_gadget_ep_set_halt(dep
, set
, true);
513 static int dwc3_ep0_set_address(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
515 enum usb_device_state state
= dwc
->gadget
.state
;
519 addr
= le16_to_cpu(ctrl
->wValue
);
521 dwc3_trace(trace_dwc3_ep0
, "invalid device address %d", addr
);
525 if (state
== USB_STATE_CONFIGURED
) {
526 dwc3_trace(trace_dwc3_ep0
,
527 "trying to set address when configured");
531 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
532 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
533 reg
|= DWC3_DCFG_DEVADDR(addr
);
534 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
537 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_ADDRESS
);
539 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_DEFAULT
);
544 static int dwc3_ep0_delegate_req(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
548 spin_unlock(&dwc
->lock
);
549 ret
= dwc
->gadget_driver
->setup(&dwc
->gadget
, ctrl
);
550 spin_lock(&dwc
->lock
);
554 static int dwc3_ep0_set_config(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
556 enum usb_device_state state
= dwc
->gadget
.state
;
561 cfg
= le16_to_cpu(ctrl
->wValue
);
564 case USB_STATE_DEFAULT
:
567 case USB_STATE_ADDRESS
:
568 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
569 /* if the cfg matches and the cfg is non zero */
570 if (cfg
&& (!ret
|| (ret
== USB_GADGET_DELAYED_STATUS
))) {
573 * only change state if set_config has already
574 * been processed. If gadget driver returns
575 * USB_GADGET_DELAYED_STATUS, we will wait
576 * to change the state on the next usb_ep_queue()
579 usb_gadget_set_state(&dwc
->gadget
,
580 USB_STATE_CONFIGURED
);
583 * Enable transition to U1/U2 state when
584 * nothing is pending from application.
586 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
587 reg
|= (DWC3_DCTL_ACCEPTU1ENA
| DWC3_DCTL_ACCEPTU2ENA
);
588 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
590 dwc
->resize_fifos
= true;
591 dwc3_trace(trace_dwc3_ep0
, "resize FIFOs flag SET");
595 case USB_STATE_CONFIGURED
:
596 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
598 usb_gadget_set_state(&dwc
->gadget
,
607 static void dwc3_ep0_set_sel_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
609 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
610 struct dwc3
*dwc
= dep
->dwc
;
624 memcpy(&timing
, req
->buf
, sizeof(timing
));
626 dwc
->u1sel
= timing
.u1sel
;
627 dwc
->u1pel
= timing
.u1pel
;
628 dwc
->u2sel
= le16_to_cpu(timing
.u2sel
);
629 dwc
->u2pel
= le16_to_cpu(timing
.u2pel
);
631 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
632 if (reg
& DWC3_DCTL_INITU2ENA
)
634 if (reg
& DWC3_DCTL_INITU1ENA
)
638 * According to Synopsys Databook, if parameter is
639 * greater than 125, a value of zero should be
640 * programmed in the register.
645 /* now that we have the time, issue DGCMD Set Sel */
646 ret
= dwc3_send_gadget_generic_command(dwc
,
647 DWC3_DGCMD_SET_PERIODIC_PAR
, param
);
651 static int dwc3_ep0_set_sel(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
654 enum usb_device_state state
= dwc
->gadget
.state
;
658 if (state
== USB_STATE_DEFAULT
)
661 wValue
= le16_to_cpu(ctrl
->wValue
);
662 wLength
= le16_to_cpu(ctrl
->wLength
);
665 dev_err(dwc
->dev
, "Set SEL should be 6 bytes, got %d\n",
671 * To handle Set SEL we need to receive 6 bytes from Host. So let's
672 * queue a usb_request for 6 bytes.
674 * Remember, though, this controller can't handle non-wMaxPacketSize
675 * aligned transfers on the OUT direction, so we queue a request for
676 * wMaxPacketSize instead.
679 dwc
->ep0_usb_req
.dep
= dep
;
680 dwc
->ep0_usb_req
.request
.length
= dep
->endpoint
.maxpacket
;
681 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
682 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_set_sel_cmpl
;
684 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
687 static int dwc3_ep0_set_isoch_delay(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
693 wValue
= le16_to_cpu(ctrl
->wValue
);
694 wLength
= le16_to_cpu(ctrl
->wLength
);
695 wIndex
= le16_to_cpu(ctrl
->wIndex
);
697 if (wIndex
|| wLength
)
701 * REVISIT It's unclear from Databook what to do with this
702 * value. For now, just cache it.
704 dwc
->isoch_delay
= wValue
;
709 static int dwc3_ep0_std_request(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
713 switch (ctrl
->bRequest
) {
714 case USB_REQ_GET_STATUS
:
715 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_GET_STATUS");
716 ret
= dwc3_ep0_handle_status(dwc
, ctrl
);
718 case USB_REQ_CLEAR_FEATURE
:
719 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_CLEAR_FEATURE");
720 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 0);
722 case USB_REQ_SET_FEATURE
:
723 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_FEATURE");
724 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 1);
726 case USB_REQ_SET_ADDRESS
:
727 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_ADDRESS");
728 ret
= dwc3_ep0_set_address(dwc
, ctrl
);
730 case USB_REQ_SET_CONFIGURATION
:
731 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_CONFIGURATION");
732 ret
= dwc3_ep0_set_config(dwc
, ctrl
);
734 case USB_REQ_SET_SEL
:
735 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_SEL");
736 ret
= dwc3_ep0_set_sel(dwc
, ctrl
);
738 case USB_REQ_SET_ISOCH_DELAY
:
739 dwc3_trace(trace_dwc3_ep0
, "USB_REQ_SET_ISOCH_DELAY");
740 ret
= dwc3_ep0_set_isoch_delay(dwc
, ctrl
);
743 dwc3_trace(trace_dwc3_ep0
, "Forwarding to gadget driver");
744 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
751 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
752 const struct dwc3_event_depevt
*event
)
754 struct usb_ctrlrequest
*ctrl
= dwc
->ctrl_req
;
758 if (!dwc
->gadget_driver
)
761 trace_dwc3_ctrl_req(ctrl
);
763 len
= le16_to_cpu(ctrl
->wLength
);
765 dwc
->three_stage_setup
= false;
766 dwc
->ep0_expect_in
= false;
767 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
769 dwc
->three_stage_setup
= true;
770 dwc
->ep0_expect_in
= !!(ctrl
->bRequestType
& USB_DIR_IN
);
771 dwc
->ep0_next_event
= DWC3_EP0_NRDY_DATA
;
774 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
)
775 ret
= dwc3_ep0_std_request(dwc
, ctrl
);
777 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
779 if (ret
== USB_GADGET_DELAYED_STATUS
)
780 dwc
->delayed_status
= true;
784 dwc3_ep0_stall_and_restart(dwc
);
787 static void dwc3_ep0_complete_data(struct dwc3
*dwc
,
788 const struct dwc3_event_depevt
*event
)
790 struct dwc3_request
*r
= NULL
;
791 struct usb_request
*ur
;
792 struct dwc3_trb
*trb
;
794 unsigned transfer_size
= 0;
796 unsigned remaining_ur_length
;
803 epnum
= event
->endpoint_number
;
806 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
810 trace_dwc3_complete_trb(ep0
, trb
);
812 r
= next_request(&ep0
->request_list
);
816 status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
817 if (status
== DWC3_TRBSTS_SETUP_PENDING
) {
818 dwc
->setup_packet_pending
= true;
820 dwc3_trace(trace_dwc3_ep0
, "Setup Pending received");
823 dwc3_gadget_giveback(ep0
, r
, -ECONNRESET
);
830 remaining_ur_length
= ur
->length
;
832 length
= trb
->size
& DWC3_TRB_SIZE_MASK
;
834 maxp
= ep0
->endpoint
.maxpacket
;
836 if (dwc
->ep0_bounced
) {
838 * Handle the first TRB before handling the bounce buffer if
839 * the request length is greater than the bounce buffer size
841 if (ur
->length
> DWC3_EP0_BOUNCE_SIZE
) {
842 transfer_size
= ALIGN(ur
->length
- maxp
, maxp
);
843 transferred
= transfer_size
- length
;
844 buf
= (u8
*)buf
+ transferred
;
845 ur
->actual
+= transferred
;
846 remaining_ur_length
-= transferred
;
849 length
= trb
->size
& DWC3_TRB_SIZE_MASK
;
854 transfer_size
= roundup((ur
->length
- transfer_size
),
857 transferred
= min_t(u32
, remaining_ur_length
,
858 transfer_size
- length
);
859 memcpy(buf
, dwc
->ep0_bounce
, transferred
);
861 transferred
= ur
->length
- length
;
864 ur
->actual
+= transferred
;
866 if ((epnum
& 1) && ur
->actual
< ur
->length
) {
867 /* for some reason we did not get everything out */
869 dwc3_ep0_stall_and_restart(dwc
);
871 dwc3_gadget_giveback(ep0
, r
, 0);
873 if (IS_ALIGNED(ur
->length
, ep0
->endpoint
.maxpacket
) &&
874 ur
->length
&& ur
->zero
) {
877 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
879 ret
= dwc3_ep0_start_trans(dwc
, epnum
,
880 dwc
->ctrl_req_addr
, 0,
881 DWC3_TRBCTL_CONTROL_DATA
, false);
887 static void dwc3_ep0_complete_status(struct dwc3
*dwc
,
888 const struct dwc3_event_depevt
*event
)
890 struct dwc3_request
*r
;
892 struct dwc3_trb
*trb
;
898 trace_dwc3_complete_trb(dep
, trb
);
900 if (!list_empty(&dep
->request_list
)) {
901 r
= next_request(&dep
->request_list
);
903 dwc3_gadget_giveback(dep
, r
, 0);
906 if (dwc
->test_mode
) {
909 ret
= dwc3_gadget_set_test_mode(dwc
, dwc
->test_mode_nr
);
911 dwc3_trace(trace_dwc3_ep0
, "Invalid Test #%d",
913 dwc3_ep0_stall_and_restart(dwc
);
918 status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
919 if (status
== DWC3_TRBSTS_SETUP_PENDING
) {
920 dwc
->setup_packet_pending
= true;
921 dwc3_trace(trace_dwc3_ep0
, "Setup Pending received");
924 dwc
->ep0state
= EP0_SETUP_PHASE
;
925 dwc3_ep0_out_start(dwc
);
928 static void dwc3_ep0_xfer_complete(struct dwc3
*dwc
,
929 const struct dwc3_event_depevt
*event
)
931 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
933 dep
->flags
&= ~DWC3_EP_BUSY
;
934 dep
->resource_index
= 0;
935 dwc
->setup_packet_pending
= false;
937 switch (dwc
->ep0state
) {
938 case EP0_SETUP_PHASE
:
939 dwc3_trace(trace_dwc3_ep0
, "Setup Phase");
940 dwc3_ep0_inspect_setup(dwc
, event
);
944 dwc3_trace(trace_dwc3_ep0
, "Data Phase");
945 dwc3_ep0_complete_data(dwc
, event
);
948 case EP0_STATUS_PHASE
:
949 dwc3_trace(trace_dwc3_ep0
, "Status Phase");
950 dwc3_ep0_complete_status(dwc
, event
);
953 WARN(true, "UNKNOWN ep0state %d\n", dwc
->ep0state
);
957 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
958 struct dwc3_ep
*dep
, struct dwc3_request
*req
)
962 req
->direction
= !!dep
->number
;
964 if (req
->request
.length
== 0) {
965 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
966 dwc
->ctrl_req_addr
, 0,
967 DWC3_TRBCTL_CONTROL_DATA
, false);
968 } else if (!IS_ALIGNED(req
->request
.length
, dep
->endpoint
.maxpacket
)
969 && (dep
->number
== 0)) {
970 u32 transfer_size
= 0;
973 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
976 dwc3_trace(trace_dwc3_ep0
, "failed to map request\n");
980 maxpacket
= dep
->endpoint
.maxpacket
;
982 if (req
->request
.length
> DWC3_EP0_BOUNCE_SIZE
) {
983 transfer_size
= ALIGN(req
->request
.length
- maxpacket
,
985 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
988 DWC3_TRBCTL_CONTROL_DATA
,
992 transfer_size
= roundup((req
->request
.length
- transfer_size
),
995 dwc
->ep0_bounced
= true;
997 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
,
998 dwc
->ep0_bounce_addr
, transfer_size
,
999 DWC3_TRBCTL_CONTROL_DATA
, false);
1001 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1004 dwc3_trace(trace_dwc3_ep0
, "failed to map request\n");
1008 ret
= dwc3_ep0_start_trans(dwc
, dep
->number
, req
->request
.dma
,
1009 req
->request
.length
, DWC3_TRBCTL_CONTROL_DATA
,
1016 static int dwc3_ep0_start_control_status(struct dwc3_ep
*dep
)
1018 struct dwc3
*dwc
= dep
->dwc
;
1021 type
= dwc
->three_stage_setup
? DWC3_TRBCTL_CONTROL_STATUS3
1022 : DWC3_TRBCTL_CONTROL_STATUS2
;
1024 return dwc3_ep0_start_trans(dwc
, dep
->number
,
1025 dwc
->ctrl_req_addr
, 0, type
, false);
1028 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1030 if (dwc
->resize_fifos
) {
1031 dwc3_trace(trace_dwc3_ep0
, "Resizing FIFOs");
1032 dwc3_gadget_resize_tx_fifos(dwc
);
1033 dwc
->resize_fifos
= 0;
1036 WARN_ON(dwc3_ep0_start_control_status(dep
));
1039 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
,
1040 const struct dwc3_event_depevt
*event
)
1042 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
1044 __dwc3_ep0_do_control_status(dwc
, dep
);
1047 static void dwc3_ep0_end_control_data(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1049 struct dwc3_gadget_ep_cmd_params params
;
1053 if (!dep
->resource_index
)
1056 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
1057 cmd
|= DWC3_DEPCMD_CMDIOC
;
1058 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
1059 memset(¶ms
, 0, sizeof(params
));
1060 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
1062 dep
->resource_index
= 0;
1065 static void dwc3_ep0_xfernotready(struct dwc3
*dwc
,
1066 const struct dwc3_event_depevt
*event
)
1068 switch (event
->status
) {
1069 case DEPEVT_STATUS_CONTROL_DATA
:
1070 dwc3_trace(trace_dwc3_ep0
, "Control Data");
1073 * We already have a DATA transfer in the controller's cache,
1074 * if we receive a XferNotReady(DATA) we will ignore it, unless
1075 * it's for the wrong direction.
1077 * In that case, we must issue END_TRANSFER command to the Data
1078 * Phase we already have started and issue SetStall on the
1081 if (dwc
->ep0_expect_in
!= event
->endpoint_number
) {
1082 struct dwc3_ep
*dep
= dwc
->eps
[dwc
->ep0_expect_in
];
1084 dwc3_trace(trace_dwc3_ep0
,
1085 "Wrong direction for Data phase");
1086 dwc3_ep0_end_control_data(dwc
, dep
);
1087 dwc3_ep0_stall_and_restart(dwc
);
1093 case DEPEVT_STATUS_CONTROL_STATUS
:
1094 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_STATUS
)
1097 dwc3_trace(trace_dwc3_ep0
, "Control Status");
1099 dwc
->ep0state
= EP0_STATUS_PHASE
;
1101 if (dwc
->delayed_status
) {
1102 WARN_ON_ONCE(event
->endpoint_number
!= 1);
1103 dwc3_trace(trace_dwc3_ep0
, "Delayed Status");
1107 dwc3_ep0_do_control_status(dwc
, event
);
1111 void dwc3_ep0_interrupt(struct dwc3
*dwc
,
1112 const struct dwc3_event_depevt
*event
)
1114 u8 epnum
= event
->endpoint_number
;
1116 dwc3_trace(trace_dwc3_ep0
, "%s while ep%d%s in state '%s'",
1117 dwc3_ep_event_string(event
->endpoint_event
),
1118 epnum
>> 1, (epnum
& 1) ? "in" : "out",
1119 dwc3_ep0_state_string(dwc
->ep0state
));
1121 switch (event
->endpoint_event
) {
1122 case DWC3_DEPEVT_XFERCOMPLETE
:
1123 dwc3_ep0_xfer_complete(dwc
, event
);
1126 case DWC3_DEPEVT_XFERNOTREADY
:
1127 dwc3_ep0_xfernotready(dwc
, event
);
1130 case DWC3_DEPEVT_XFERINPROGRESS
:
1131 case DWC3_DEPEVT_RXTXFIFOEVT
:
1132 case DWC3_DEPEVT_STREAMEVT
:
1133 case DWC3_DEPEVT_EPCMDCMPLT
: