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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/nab/target...
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
1 /**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
46 #include <linux/io.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
49
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
52
53 #include "core.h"
54 #include "gadget.h"
55 #include "io.h"
56
57 /**
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
61 *
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
64 * is passed
65 */
66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
67 {
68 u32 reg;
69
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
72
73 switch (mode) {
74 case TEST_J:
75 case TEST_K:
76 case TEST_SE0_NAK:
77 case TEST_PACKET:
78 case TEST_FORCE_EN:
79 reg |= mode << 1;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
86
87 return 0;
88 }
89
90 /**
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
94 *
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
97 */
98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99 {
100 int retries = 10000;
101 u32 reg;
102
103 /*
104 * Wait until device controller is ready. Only applies to 1.94a and
105 * later RTL.
106 */
107 if (dwc->revision >= DWC3_REVISION_194A) {
108 while (--retries) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
111 udelay(5);
112 else
113 break;
114 }
115
116 if (retries <= 0)
117 return -ETIMEDOUT;
118 }
119
120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
122
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
126
127 /*
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
130 */
131 if (dwc->revision >= DWC3_REVISION_194A)
132 return 0;
133
134 /* wait for a change in DSTS */
135 retries = 10000;
136 while (--retries) {
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
138
139 if (DWC3_DSTS_USBLNKST(reg) == state)
140 return 0;
141
142 udelay(5);
143 }
144
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
146
147 return -ETIMEDOUT;
148 }
149
150 /**
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
153 *
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
157 *
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
162 *
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
165 *
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
168 *
169 * Unfortunately, due to many variables that's not always the case.
170 */
171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
172 {
173 int last_fifo_depth = 0;
174 int ram1_depth;
175 int fifo_size;
176 int mdwidth;
177 int num;
178
179 if (!dwc->needs_fifo_resize)
180 return 0;
181
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
184
185 /* MDWIDTH is represented in bits, we need it in bytes */
186 mdwidth >>= 3;
187
188 /*
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
192 * FIFO space
193 */
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
197 int mult = 1;
198 int tmp;
199
200 if (!(dep->number & 1))
201 continue;
202
203 if (!(dep->flags & DWC3_EP_ENABLED))
204 continue;
205
206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
208 mult = 3;
209
210 /*
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
214 * accordingly.
215 *
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
219 * packets
220 */
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
222 tmp += mdwidth;
223
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
225
226 fifo_size |= (last_fifo_depth << 16);
227
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
230
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
232 fifo_size);
233
234 last_fifo_depth += (fifo_size & 0xffff);
235 }
236
237 return 0;
238 }
239
240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
241 int status)
242 {
243 struct dwc3 *dwc = dep->dwc;
244
245 if (req->queued) {
246 if (req->request.num_mapped_sgs)
247 dep->busy_slot += req->request.num_mapped_sgs;
248 else
249 dep->busy_slot++;
250
251 /*
252 * Skip LINK TRB. We can't use req->trb and check for
253 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
254 * completed (not the LINK TRB).
255 */
256 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
258 dep->busy_slot++;
259 }
260 list_del(&req->list);
261 req->trb = NULL;
262
263 if (req->request.status == -EINPROGRESS)
264 req->request.status = status;
265
266 usb_gadget_unmap_request(&dwc->gadget, &req->request,
267 req->direction);
268
269 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
270 req, dep->name, req->request.actual,
271 req->request.length, status);
272
273 spin_unlock(&dwc->lock);
274 req->request.complete(&dep->endpoint, &req->request);
275 spin_lock(&dwc->lock);
276 }
277
278 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
279 {
280 switch (cmd) {
281 case DWC3_DEPCMD_DEPSTARTCFG:
282 return "Start New Configuration";
283 case DWC3_DEPCMD_ENDTRANSFER:
284 return "End Transfer";
285 case DWC3_DEPCMD_UPDATETRANSFER:
286 return "Update Transfer";
287 case DWC3_DEPCMD_STARTTRANSFER:
288 return "Start Transfer";
289 case DWC3_DEPCMD_CLEARSTALL:
290 return "Clear Stall";
291 case DWC3_DEPCMD_SETSTALL:
292 return "Set Stall";
293 case DWC3_DEPCMD_GETEPSTATE:
294 return "Get Endpoint State";
295 case DWC3_DEPCMD_SETTRANSFRESOURCE:
296 return "Set Endpoint Transfer Resource";
297 case DWC3_DEPCMD_SETEPCONFIG:
298 return "Set Endpoint Configuration";
299 default:
300 return "UNKNOWN command";
301 }
302 }
303
304 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
305 {
306 u32 timeout = 500;
307 u32 reg;
308
309 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
310 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
311
312 do {
313 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
314 if (!(reg & DWC3_DGCMD_CMDACT)) {
315 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
316 DWC3_DGCMD_STATUS(reg));
317 return 0;
318 }
319
320 /*
321 * We can't sleep here, because it's also called from
322 * interrupt context.
323 */
324 timeout--;
325 if (!timeout)
326 return -ETIMEDOUT;
327 udelay(1);
328 } while (1);
329 }
330
331 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
332 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
333 {
334 struct dwc3_ep *dep = dwc->eps[ep];
335 u32 timeout = 500;
336 u32 reg;
337
338 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
339 dep->name,
340 dwc3_gadget_ep_cmd_string(cmd), params->param0,
341 params->param1, params->param2);
342
343 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
344 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
345 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
346
347 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
348 do {
349 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
350 if (!(reg & DWC3_DEPCMD_CMDACT)) {
351 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
352 DWC3_DEPCMD_STATUS(reg));
353 return 0;
354 }
355
356 /*
357 * We can't sleep here, because it is also called from
358 * interrupt context.
359 */
360 timeout--;
361 if (!timeout)
362 return -ETIMEDOUT;
363
364 udelay(1);
365 } while (1);
366 }
367
368 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
369 struct dwc3_trb *trb)
370 {
371 u32 offset = (char *) trb - (char *) dep->trb_pool;
372
373 return dep->trb_pool_dma + offset;
374 }
375
376 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
377 {
378 struct dwc3 *dwc = dep->dwc;
379
380 if (dep->trb_pool)
381 return 0;
382
383 if (dep->number == 0 || dep->number == 1)
384 return 0;
385
386 dep->trb_pool = dma_alloc_coherent(dwc->dev,
387 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
388 &dep->trb_pool_dma, GFP_KERNEL);
389 if (!dep->trb_pool) {
390 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
391 dep->name);
392 return -ENOMEM;
393 }
394
395 return 0;
396 }
397
398 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
399 {
400 struct dwc3 *dwc = dep->dwc;
401
402 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
403 dep->trb_pool, dep->trb_pool_dma);
404
405 dep->trb_pool = NULL;
406 dep->trb_pool_dma = 0;
407 }
408
409 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
410 {
411 struct dwc3_gadget_ep_cmd_params params;
412 u32 cmd;
413
414 memset(&params, 0x00, sizeof(params));
415
416 if (dep->number != 1) {
417 cmd = DWC3_DEPCMD_DEPSTARTCFG;
418 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
419 if (dep->number > 1) {
420 if (dwc->start_config_issued)
421 return 0;
422 dwc->start_config_issued = true;
423 cmd |= DWC3_DEPCMD_PARAM(2);
424 }
425
426 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
427 }
428
429 return 0;
430 }
431
432 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
433 const struct usb_endpoint_descriptor *desc,
434 const struct usb_ss_ep_comp_descriptor *comp_desc)
435 {
436 struct dwc3_gadget_ep_cmd_params params;
437
438 memset(&params, 0x00, sizeof(params));
439
440 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
441 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
442 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst - 1);
443
444 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
445 | DWC3_DEPCFG_XFER_NOT_READY_EN;
446
447 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
448 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
449 | DWC3_DEPCFG_STREAM_EVENT_EN;
450 dep->stream_capable = true;
451 }
452
453 if (usb_endpoint_xfer_isoc(desc))
454 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
455
456 /*
457 * We are doing 1:1 mapping for endpoints, meaning
458 * Physical Endpoints 2 maps to Logical Endpoint 2 and
459 * so on. We consider the direction bit as part of the physical
460 * endpoint number. So USB endpoint 0x81 is 0x03.
461 */
462 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
463
464 /*
465 * We must use the lower 16 TX FIFOs even though
466 * HW might have more
467 */
468 if (dep->direction)
469 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
470
471 if (desc->bInterval) {
472 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
473 dep->interval = 1 << (desc->bInterval - 1);
474 }
475
476 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
477 DWC3_DEPCMD_SETEPCONFIG, &params);
478 }
479
480 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
481 {
482 struct dwc3_gadget_ep_cmd_params params;
483
484 memset(&params, 0x00, sizeof(params));
485
486 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
487
488 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
489 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
490 }
491
492 /**
493 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
494 * @dep: endpoint to be initialized
495 * @desc: USB Endpoint Descriptor
496 *
497 * Caller should take care of locking
498 */
499 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
500 const struct usb_endpoint_descriptor *desc,
501 const struct usb_ss_ep_comp_descriptor *comp_desc)
502 {
503 struct dwc3 *dwc = dep->dwc;
504 u32 reg;
505 int ret = -ENOMEM;
506
507 if (!(dep->flags & DWC3_EP_ENABLED)) {
508 ret = dwc3_gadget_start_config(dwc, dep);
509 if (ret)
510 return ret;
511 }
512
513 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
514 if (ret)
515 return ret;
516
517 if (!(dep->flags & DWC3_EP_ENABLED)) {
518 struct dwc3_trb *trb_st_hw;
519 struct dwc3_trb *trb_link;
520
521 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
522 if (ret)
523 return ret;
524
525 dep->endpoint.desc = desc;
526 dep->comp_desc = comp_desc;
527 dep->type = usb_endpoint_type(desc);
528 dep->flags |= DWC3_EP_ENABLED;
529
530 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
531 reg |= DWC3_DALEPENA_EP(dep->number);
532 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
533
534 if (!usb_endpoint_xfer_isoc(desc))
535 return 0;
536
537 memset(&trb_link, 0, sizeof(trb_link));
538
539 /* Link TRB for ISOC. The HWO bit is never reset */
540 trb_st_hw = &dep->trb_pool[0];
541
542 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
543
544 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
545 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
546 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
547 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
548 }
549
550 return 0;
551 }
552
553 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
554 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
555 {
556 struct dwc3_request *req;
557
558 if (!list_empty(&dep->req_queued)) {
559 dwc3_stop_active_transfer(dwc, dep->number);
560
561 /*
562 * NOTICE: We are violating what the Databook says about the
563 * EndTransfer command. Ideally we would _always_ wait for the
564 * EndTransfer Command Completion IRQ, but that's causing too
565 * much trouble synchronizing between us and gadget driver.
566 *
567 * We have discussed this with the IP Provider and it was
568 * suggested to giveback all requests here, but give HW some
569 * extra time to synchronize with the interconnect. We're using
570 * an arbitraty 100us delay for that.
571 *
572 * Note also that a similar handling was tested by Synopsys
573 * (thanks a lot Paul) and nothing bad has come out of it.
574 * In short, what we're doing is:
575 *
576 * - Issue EndTransfer WITH CMDIOC bit set
577 * - Wait 100us
578 * - giveback all requests to gadget driver
579 */
580 udelay(100);
581
582 while (!list_empty(&dep->req_queued)) {
583 req = next_request(&dep->req_queued);
584
585 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
586 }
587 }
588
589 while (!list_empty(&dep->request_list)) {
590 req = next_request(&dep->request_list);
591
592 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
593 }
594 }
595
596 /**
597 * __dwc3_gadget_ep_disable - Disables a HW endpoint
598 * @dep: the endpoint to disable
599 *
600 * This function also removes requests which are currently processed ny the
601 * hardware and those which are not yet scheduled.
602 * Caller should take care of locking.
603 */
604 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
605 {
606 struct dwc3 *dwc = dep->dwc;
607 u32 reg;
608
609 dwc3_remove_requests(dwc, dep);
610
611 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
612 reg &= ~DWC3_DALEPENA_EP(dep->number);
613 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
614
615 dep->stream_capable = false;
616 dep->endpoint.desc = NULL;
617 dep->comp_desc = NULL;
618 dep->type = 0;
619 dep->flags = 0;
620
621 return 0;
622 }
623
624 /* -------------------------------------------------------------------------- */
625
626 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
627 const struct usb_endpoint_descriptor *desc)
628 {
629 return -EINVAL;
630 }
631
632 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
633 {
634 return -EINVAL;
635 }
636
637 /* -------------------------------------------------------------------------- */
638
639 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
640 const struct usb_endpoint_descriptor *desc)
641 {
642 struct dwc3_ep *dep;
643 struct dwc3 *dwc;
644 unsigned long flags;
645 int ret;
646
647 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
648 pr_debug("dwc3: invalid parameters\n");
649 return -EINVAL;
650 }
651
652 if (!desc->wMaxPacketSize) {
653 pr_debug("dwc3: missing wMaxPacketSize\n");
654 return -EINVAL;
655 }
656
657 dep = to_dwc3_ep(ep);
658 dwc = dep->dwc;
659
660 switch (usb_endpoint_type(desc)) {
661 case USB_ENDPOINT_XFER_CONTROL:
662 strlcat(dep->name, "-control", sizeof(dep->name));
663 break;
664 case USB_ENDPOINT_XFER_ISOC:
665 strlcat(dep->name, "-isoc", sizeof(dep->name));
666 break;
667 case USB_ENDPOINT_XFER_BULK:
668 strlcat(dep->name, "-bulk", sizeof(dep->name));
669 break;
670 case USB_ENDPOINT_XFER_INT:
671 strlcat(dep->name, "-int", sizeof(dep->name));
672 break;
673 default:
674 dev_err(dwc->dev, "invalid endpoint transfer type\n");
675 }
676
677 if (dep->flags & DWC3_EP_ENABLED) {
678 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
679 dep->name);
680 return 0;
681 }
682
683 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
684
685 spin_lock_irqsave(&dwc->lock, flags);
686 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
687 spin_unlock_irqrestore(&dwc->lock, flags);
688
689 return ret;
690 }
691
692 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
693 {
694 struct dwc3_ep *dep;
695 struct dwc3 *dwc;
696 unsigned long flags;
697 int ret;
698
699 if (!ep) {
700 pr_debug("dwc3: invalid parameters\n");
701 return -EINVAL;
702 }
703
704 dep = to_dwc3_ep(ep);
705 dwc = dep->dwc;
706
707 if (!(dep->flags & DWC3_EP_ENABLED)) {
708 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
709 dep->name);
710 return 0;
711 }
712
713 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
714 dep->number >> 1,
715 (dep->number & 1) ? "in" : "out");
716
717 spin_lock_irqsave(&dwc->lock, flags);
718 ret = __dwc3_gadget_ep_disable(dep);
719 spin_unlock_irqrestore(&dwc->lock, flags);
720
721 return ret;
722 }
723
724 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
725 gfp_t gfp_flags)
726 {
727 struct dwc3_request *req;
728 struct dwc3_ep *dep = to_dwc3_ep(ep);
729 struct dwc3 *dwc = dep->dwc;
730
731 req = kzalloc(sizeof(*req), gfp_flags);
732 if (!req) {
733 dev_err(dwc->dev, "not enough memory\n");
734 return NULL;
735 }
736
737 req->epnum = dep->number;
738 req->dep = dep;
739
740 return &req->request;
741 }
742
743 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
744 struct usb_request *request)
745 {
746 struct dwc3_request *req = to_dwc3_request(request);
747
748 kfree(req);
749 }
750
751 /**
752 * dwc3_prepare_one_trb - setup one TRB from one request
753 * @dep: endpoint for which this request is prepared
754 * @req: dwc3_request pointer
755 */
756 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
757 struct dwc3_request *req, dma_addr_t dma,
758 unsigned length, unsigned last, unsigned chain)
759 {
760 struct dwc3 *dwc = dep->dwc;
761 struct dwc3_trb *trb;
762
763 unsigned int cur_slot;
764
765 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
766 dep->name, req, (unsigned long long) dma,
767 length, last ? " last" : "",
768 chain ? " chain" : "");
769
770 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
771 cur_slot = dep->free_slot;
772 dep->free_slot++;
773
774 /* Skip the LINK-TRB on ISOC */
775 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
776 usb_endpoint_xfer_isoc(dep->endpoint.desc))
777 return;
778
779 if (!req->trb) {
780 dwc3_gadget_move_request_queued(req);
781 req->trb = trb;
782 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
783 }
784
785 trb->size = DWC3_TRB_SIZE_LENGTH(length);
786 trb->bpl = lower_32_bits(dma);
787 trb->bph = upper_32_bits(dma);
788
789 switch (usb_endpoint_type(dep->endpoint.desc)) {
790 case USB_ENDPOINT_XFER_CONTROL:
791 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
792 break;
793
794 case USB_ENDPOINT_XFER_ISOC:
795 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
796
797 if (!req->request.no_interrupt)
798 trb->ctrl |= DWC3_TRB_CTRL_IOC;
799 break;
800
801 case USB_ENDPOINT_XFER_BULK:
802 case USB_ENDPOINT_XFER_INT:
803 trb->ctrl = DWC3_TRBCTL_NORMAL;
804 break;
805 default:
806 /*
807 * This is only possible with faulty memory because we
808 * checked it already :)
809 */
810 BUG();
811 }
812
813 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
814 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
815 trb->ctrl |= DWC3_TRB_CTRL_CSP;
816 } else {
817 if (chain)
818 trb->ctrl |= DWC3_TRB_CTRL_CHN;
819
820 if (last)
821 trb->ctrl |= DWC3_TRB_CTRL_LST;
822 }
823
824 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
825 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
826
827 trb->ctrl |= DWC3_TRB_CTRL_HWO;
828 }
829
830 /*
831 * dwc3_prepare_trbs - setup TRBs from requests
832 * @dep: endpoint for which requests are being prepared
833 * @starting: true if the endpoint is idle and no requests are queued.
834 *
835 * The function goes through the requests list and sets up TRBs for the
836 * transfers. The function returns once there are no more TRBs available or
837 * it runs out of requests.
838 */
839 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
840 {
841 struct dwc3_request *req, *n;
842 u32 trbs_left;
843 u32 max;
844 unsigned int last_one = 0;
845
846 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
847
848 /* the first request must not be queued */
849 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
850
851 /* Can't wrap around on a non-isoc EP since there's no link TRB */
852 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
853 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
854 if (trbs_left > max)
855 trbs_left = max;
856 }
857
858 /*
859 * If busy & slot are equal than it is either full or empty. If we are
860 * starting to process requests then we are empty. Otherwise we are
861 * full and don't do anything
862 */
863 if (!trbs_left) {
864 if (!starting)
865 return;
866 trbs_left = DWC3_TRB_NUM;
867 /*
868 * In case we start from scratch, we queue the ISOC requests
869 * starting from slot 1. This is done because we use ring
870 * buffer and have no LST bit to stop us. Instead, we place
871 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
872 * after the first request so we start at slot 1 and have
873 * 7 requests proceed before we hit the first IOC.
874 * Other transfer types don't use the ring buffer and are
875 * processed from the first TRB until the last one. Since we
876 * don't wrap around we have to start at the beginning.
877 */
878 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
879 dep->busy_slot = 1;
880 dep->free_slot = 1;
881 } else {
882 dep->busy_slot = 0;
883 dep->free_slot = 0;
884 }
885 }
886
887 /* The last TRB is a link TRB, not used for xfer */
888 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
889 return;
890
891 list_for_each_entry_safe(req, n, &dep->request_list, list) {
892 unsigned length;
893 dma_addr_t dma;
894
895 if (req->request.num_mapped_sgs > 0) {
896 struct usb_request *request = &req->request;
897 struct scatterlist *sg = request->sg;
898 struct scatterlist *s;
899 int i;
900
901 for_each_sg(sg, s, request->num_mapped_sgs, i) {
902 unsigned chain = true;
903
904 length = sg_dma_len(s);
905 dma = sg_dma_address(s);
906
907 if (i == (request->num_mapped_sgs - 1) ||
908 sg_is_last(s)) {
909 last_one = true;
910 chain = false;
911 }
912
913 trbs_left--;
914 if (!trbs_left)
915 last_one = true;
916
917 if (last_one)
918 chain = false;
919
920 dwc3_prepare_one_trb(dep, req, dma, length,
921 last_one, chain);
922
923 if (last_one)
924 break;
925 }
926 } else {
927 dma = req->request.dma;
928 length = req->request.length;
929 trbs_left--;
930
931 if (!trbs_left)
932 last_one = 1;
933
934 /* Is this the last request? */
935 if (list_is_last(&req->list, &dep->request_list))
936 last_one = 1;
937
938 dwc3_prepare_one_trb(dep, req, dma, length,
939 last_one, false);
940
941 if (last_one)
942 break;
943 }
944 }
945 }
946
947 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
948 int start_new)
949 {
950 struct dwc3_gadget_ep_cmd_params params;
951 struct dwc3_request *req;
952 struct dwc3 *dwc = dep->dwc;
953 int ret;
954 u32 cmd;
955
956 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
957 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
958 return -EBUSY;
959 }
960 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
961
962 /*
963 * If we are getting here after a short-out-packet we don't enqueue any
964 * new requests as we try to set the IOC bit only on the last request.
965 */
966 if (start_new) {
967 if (list_empty(&dep->req_queued))
968 dwc3_prepare_trbs(dep, start_new);
969
970 /* req points to the first request which will be sent */
971 req = next_request(&dep->req_queued);
972 } else {
973 dwc3_prepare_trbs(dep, start_new);
974
975 /*
976 * req points to the first request where HWO changed from 0 to 1
977 */
978 req = next_request(&dep->req_queued);
979 }
980 if (!req) {
981 dep->flags |= DWC3_EP_PENDING_REQUEST;
982 return 0;
983 }
984
985 memset(&params, 0, sizeof(params));
986 params.param0 = upper_32_bits(req->trb_dma);
987 params.param1 = lower_32_bits(req->trb_dma);
988
989 if (start_new)
990 cmd = DWC3_DEPCMD_STARTTRANSFER;
991 else
992 cmd = DWC3_DEPCMD_UPDATETRANSFER;
993
994 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
995 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
996 if (ret < 0) {
997 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
998
999 /*
1000 * FIXME we need to iterate over the list of requests
1001 * here and stop, unmap, free and del each of the linked
1002 * requests instead of what we do now.
1003 */
1004 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1005 req->direction);
1006 list_del(&req->list);
1007 return ret;
1008 }
1009
1010 dep->flags |= DWC3_EP_BUSY;
1011
1012 if (start_new) {
1013 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1014 dep->number);
1015 WARN_ON_ONCE(!dep->resource_index);
1016 }
1017
1018 return 0;
1019 }
1020
1021 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1022 struct dwc3_ep *dep, u32 cur_uf)
1023 {
1024 u32 uf;
1025
1026 if (list_empty(&dep->request_list)) {
1027 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1028 dep->name);
1029 return;
1030 }
1031
1032 /* 4 micro frames in the future */
1033 uf = cur_uf + dep->interval * 4;
1034
1035 __dwc3_gadget_kick_transfer(dep, uf, 1);
1036 }
1037
1038 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1039 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1040 {
1041 u32 cur_uf, mask;
1042
1043 mask = ~(dep->interval - 1);
1044 cur_uf = event->parameters & mask;
1045
1046 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1047 }
1048
1049 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1050 {
1051 struct dwc3 *dwc = dep->dwc;
1052 int ret;
1053
1054 req->request.actual = 0;
1055 req->request.status = -EINPROGRESS;
1056 req->direction = dep->direction;
1057 req->epnum = dep->number;
1058
1059 /*
1060 * We only add to our list of requests now and
1061 * start consuming the list once we get XferNotReady
1062 * IRQ.
1063 *
1064 * That way, we avoid doing anything that we don't need
1065 * to do now and defer it until the point we receive a
1066 * particular token from the Host side.
1067 *
1068 * This will also avoid Host cancelling URBs due to too
1069 * many NAKs.
1070 */
1071 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1072 dep->direction);
1073 if (ret)
1074 return ret;
1075
1076 list_add_tail(&req->list, &dep->request_list);
1077
1078 /*
1079 * There are a few special cases:
1080 *
1081 * 1. XferNotReady with empty list of requests. We need to kick the
1082 * transfer here in that situation, otherwise we will be NAKing
1083 * forever. If we get XferNotReady before gadget driver has a
1084 * chance to queue a request, we will ACK the IRQ but won't be
1085 * able to receive the data until the next request is queued.
1086 * The following code is handling exactly that.
1087 *
1088 */
1089 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1090 int ret;
1091
1092 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1093 if (ret && ret != -EBUSY) {
1094 struct dwc3 *dwc = dep->dwc;
1095
1096 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1097 dep->name);
1098 }
1099 }
1100
1101 /*
1102 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1103 * kick the transfer here after queuing a request, otherwise the
1104 * core may not see the modified TRB(s).
1105 */
1106 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1107 (dep->flags & DWC3_EP_BUSY)) {
1108 WARN_ON_ONCE(!dep->resource_index);
1109 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1110 false);
1111 if (ret && ret != -EBUSY) {
1112 struct dwc3 *dwc = dep->dwc;
1113
1114 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1115 dep->name);
1116 }
1117 }
1118
1119 /*
1120 * 3. Missed ISOC Handling. We need to start isoc transfer on the saved
1121 * uframe number.
1122 */
1123 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1124 (dep->flags & DWC3_EP_MISSED_ISOC)) {
1125 __dwc3_gadget_start_isoc(dwc, dep, dep->current_uf);
1126 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1127 }
1128
1129 return 0;
1130 }
1131
1132 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1133 gfp_t gfp_flags)
1134 {
1135 struct dwc3_request *req = to_dwc3_request(request);
1136 struct dwc3_ep *dep = to_dwc3_ep(ep);
1137 struct dwc3 *dwc = dep->dwc;
1138
1139 unsigned long flags;
1140
1141 int ret;
1142
1143 if (!dep->endpoint.desc) {
1144 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1145 request, ep->name);
1146 return -ESHUTDOWN;
1147 }
1148
1149 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1150 request, ep->name, request->length);
1151
1152 spin_lock_irqsave(&dwc->lock, flags);
1153 ret = __dwc3_gadget_ep_queue(dep, req);
1154 spin_unlock_irqrestore(&dwc->lock, flags);
1155
1156 return ret;
1157 }
1158
1159 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1160 struct usb_request *request)
1161 {
1162 struct dwc3_request *req = to_dwc3_request(request);
1163 struct dwc3_request *r = NULL;
1164
1165 struct dwc3_ep *dep = to_dwc3_ep(ep);
1166 struct dwc3 *dwc = dep->dwc;
1167
1168 unsigned long flags;
1169 int ret = 0;
1170
1171 spin_lock_irqsave(&dwc->lock, flags);
1172
1173 list_for_each_entry(r, &dep->request_list, list) {
1174 if (r == req)
1175 break;
1176 }
1177
1178 if (r != req) {
1179 list_for_each_entry(r, &dep->req_queued, list) {
1180 if (r == req)
1181 break;
1182 }
1183 if (r == req) {
1184 /* wait until it is processed */
1185 dwc3_stop_active_transfer(dwc, dep->number);
1186 goto out1;
1187 }
1188 dev_err(dwc->dev, "request %p was not queued to %s\n",
1189 request, ep->name);
1190 ret = -EINVAL;
1191 goto out0;
1192 }
1193
1194 out1:
1195 /* giveback the request */
1196 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1197
1198 out0:
1199 spin_unlock_irqrestore(&dwc->lock, flags);
1200
1201 return ret;
1202 }
1203
1204 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1205 {
1206 struct dwc3_gadget_ep_cmd_params params;
1207 struct dwc3 *dwc = dep->dwc;
1208 int ret;
1209
1210 memset(&params, 0x00, sizeof(params));
1211
1212 if (value) {
1213 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1214 DWC3_DEPCMD_SETSTALL, &params);
1215 if (ret)
1216 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1217 value ? "set" : "clear",
1218 dep->name);
1219 else
1220 dep->flags |= DWC3_EP_STALL;
1221 } else {
1222 if (dep->flags & DWC3_EP_WEDGE)
1223 return 0;
1224
1225 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1226 DWC3_DEPCMD_CLEARSTALL, &params);
1227 if (ret)
1228 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1229 value ? "set" : "clear",
1230 dep->name);
1231 else
1232 dep->flags &= ~DWC3_EP_STALL;
1233 }
1234
1235 return ret;
1236 }
1237
1238 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1239 {
1240 struct dwc3_ep *dep = to_dwc3_ep(ep);
1241 struct dwc3 *dwc = dep->dwc;
1242
1243 unsigned long flags;
1244
1245 int ret;
1246
1247 spin_lock_irqsave(&dwc->lock, flags);
1248
1249 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1250 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1251 ret = -EINVAL;
1252 goto out;
1253 }
1254
1255 ret = __dwc3_gadget_ep_set_halt(dep, value);
1256 out:
1257 spin_unlock_irqrestore(&dwc->lock, flags);
1258
1259 return ret;
1260 }
1261
1262 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1263 {
1264 struct dwc3_ep *dep = to_dwc3_ep(ep);
1265 struct dwc3 *dwc = dep->dwc;
1266 unsigned long flags;
1267
1268 spin_lock_irqsave(&dwc->lock, flags);
1269 dep->flags |= DWC3_EP_WEDGE;
1270 spin_unlock_irqrestore(&dwc->lock, flags);
1271
1272 if (dep->number == 0 || dep->number == 1)
1273 return dwc3_gadget_ep0_set_halt(ep, 1);
1274 else
1275 return dwc3_gadget_ep_set_halt(ep, 1);
1276 }
1277
1278 /* -------------------------------------------------------------------------- */
1279
1280 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1281 .bLength = USB_DT_ENDPOINT_SIZE,
1282 .bDescriptorType = USB_DT_ENDPOINT,
1283 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1284 };
1285
1286 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1287 .enable = dwc3_gadget_ep0_enable,
1288 .disable = dwc3_gadget_ep0_disable,
1289 .alloc_request = dwc3_gadget_ep_alloc_request,
1290 .free_request = dwc3_gadget_ep_free_request,
1291 .queue = dwc3_gadget_ep0_queue,
1292 .dequeue = dwc3_gadget_ep_dequeue,
1293 .set_halt = dwc3_gadget_ep0_set_halt,
1294 .set_wedge = dwc3_gadget_ep_set_wedge,
1295 };
1296
1297 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1298 .enable = dwc3_gadget_ep_enable,
1299 .disable = dwc3_gadget_ep_disable,
1300 .alloc_request = dwc3_gadget_ep_alloc_request,
1301 .free_request = dwc3_gadget_ep_free_request,
1302 .queue = dwc3_gadget_ep_queue,
1303 .dequeue = dwc3_gadget_ep_dequeue,
1304 .set_halt = dwc3_gadget_ep_set_halt,
1305 .set_wedge = dwc3_gadget_ep_set_wedge,
1306 };
1307
1308 /* -------------------------------------------------------------------------- */
1309
1310 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1311 {
1312 struct dwc3 *dwc = gadget_to_dwc(g);
1313 u32 reg;
1314
1315 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1316 return DWC3_DSTS_SOFFN(reg);
1317 }
1318
1319 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1320 {
1321 struct dwc3 *dwc = gadget_to_dwc(g);
1322
1323 unsigned long timeout;
1324 unsigned long flags;
1325
1326 u32 reg;
1327
1328 int ret = 0;
1329
1330 u8 link_state;
1331 u8 speed;
1332
1333 spin_lock_irqsave(&dwc->lock, flags);
1334
1335 /*
1336 * According to the Databook Remote wakeup request should
1337 * be issued only when the device is in early suspend state.
1338 *
1339 * We can check that via USB Link State bits in DSTS register.
1340 */
1341 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1342
1343 speed = reg & DWC3_DSTS_CONNECTSPD;
1344 if (speed == DWC3_DSTS_SUPERSPEED) {
1345 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1346 ret = -EINVAL;
1347 goto out;
1348 }
1349
1350 link_state = DWC3_DSTS_USBLNKST(reg);
1351
1352 switch (link_state) {
1353 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1354 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1355 break;
1356 default:
1357 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1358 link_state);
1359 ret = -EINVAL;
1360 goto out;
1361 }
1362
1363 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1364 if (ret < 0) {
1365 dev_err(dwc->dev, "failed to put link in Recovery\n");
1366 goto out;
1367 }
1368
1369 /* Recent versions do this automatically */
1370 if (dwc->revision < DWC3_REVISION_194A) {
1371 /* write zeroes to Link Change Request */
1372 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1373 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1374 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1375 }
1376
1377 /* poll until Link State changes to ON */
1378 timeout = jiffies + msecs_to_jiffies(100);
1379
1380 while (!time_after(jiffies, timeout)) {
1381 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1382
1383 /* in HS, means ON */
1384 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1385 break;
1386 }
1387
1388 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1389 dev_err(dwc->dev, "failed to send remote wakeup\n");
1390 ret = -EINVAL;
1391 }
1392
1393 out:
1394 spin_unlock_irqrestore(&dwc->lock, flags);
1395
1396 return ret;
1397 }
1398
1399 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1400 int is_selfpowered)
1401 {
1402 struct dwc3 *dwc = gadget_to_dwc(g);
1403 unsigned long flags;
1404
1405 spin_lock_irqsave(&dwc->lock, flags);
1406 dwc->is_selfpowered = !!is_selfpowered;
1407 spin_unlock_irqrestore(&dwc->lock, flags);
1408
1409 return 0;
1410 }
1411
1412 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1413 {
1414 u32 reg;
1415 u32 timeout = 500;
1416
1417 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1418 if (is_on) {
1419 if (dwc->revision <= DWC3_REVISION_187A) {
1420 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1421 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1422 }
1423
1424 if (dwc->revision >= DWC3_REVISION_194A)
1425 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1426 reg |= DWC3_DCTL_RUN_STOP;
1427 } else {
1428 reg &= ~DWC3_DCTL_RUN_STOP;
1429 }
1430
1431 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1432
1433 do {
1434 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1435 if (is_on) {
1436 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1437 break;
1438 } else {
1439 if (reg & DWC3_DSTS_DEVCTRLHLT)
1440 break;
1441 }
1442 timeout--;
1443 if (!timeout)
1444 return -ETIMEDOUT;
1445 udelay(1);
1446 } while (1);
1447
1448 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1449 dwc->gadget_driver
1450 ? dwc->gadget_driver->function : "no-function",
1451 is_on ? "connect" : "disconnect");
1452
1453 return 0;
1454 }
1455
1456 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1457 {
1458 struct dwc3 *dwc = gadget_to_dwc(g);
1459 unsigned long flags;
1460 int ret;
1461
1462 is_on = !!is_on;
1463
1464 spin_lock_irqsave(&dwc->lock, flags);
1465 ret = dwc3_gadget_run_stop(dwc, is_on);
1466 spin_unlock_irqrestore(&dwc->lock, flags);
1467
1468 return ret;
1469 }
1470
1471 static int dwc3_gadget_start(struct usb_gadget *g,
1472 struct usb_gadget_driver *driver)
1473 {
1474 struct dwc3 *dwc = gadget_to_dwc(g);
1475 struct dwc3_ep *dep;
1476 unsigned long flags;
1477 int ret = 0;
1478 u32 reg;
1479
1480 spin_lock_irqsave(&dwc->lock, flags);
1481
1482 if (dwc->gadget_driver) {
1483 dev_err(dwc->dev, "%s is already bound to %s\n",
1484 dwc->gadget.name,
1485 dwc->gadget_driver->driver.name);
1486 ret = -EBUSY;
1487 goto err0;
1488 }
1489
1490 dwc->gadget_driver = driver;
1491 dwc->gadget.dev.driver = &driver->driver;
1492
1493 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1494 reg &= ~(DWC3_DCFG_SPEED_MASK);
1495
1496 /**
1497 * WORKAROUND: DWC3 revision < 2.20a have an issue
1498 * which would cause metastability state on Run/Stop
1499 * bit if we try to force the IP to USB2-only mode.
1500 *
1501 * Because of that, we cannot configure the IP to any
1502 * speed other than the SuperSpeed
1503 *
1504 * Refers to:
1505 *
1506 * STAR#9000525659: Clock Domain Crossing on DCTL in
1507 * USB 2.0 Mode
1508 */
1509 if (dwc->revision < DWC3_REVISION_220A)
1510 reg |= DWC3_DCFG_SUPERSPEED;
1511 else
1512 reg |= dwc->maximum_speed;
1513 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1514
1515 dwc->start_config_issued = false;
1516
1517 /* Start with SuperSpeed Default */
1518 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1519
1520 dep = dwc->eps[0];
1521 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1522 if (ret) {
1523 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1524 goto err0;
1525 }
1526
1527 dep = dwc->eps[1];
1528 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1529 if (ret) {
1530 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1531 goto err1;
1532 }
1533
1534 /* begin to receive SETUP packets */
1535 dwc->ep0state = EP0_SETUP_PHASE;
1536 dwc3_ep0_out_start(dwc);
1537
1538 spin_unlock_irqrestore(&dwc->lock, flags);
1539
1540 return 0;
1541
1542 err1:
1543 __dwc3_gadget_ep_disable(dwc->eps[0]);
1544
1545 err0:
1546 spin_unlock_irqrestore(&dwc->lock, flags);
1547
1548 return ret;
1549 }
1550
1551 static int dwc3_gadget_stop(struct usb_gadget *g,
1552 struct usb_gadget_driver *driver)
1553 {
1554 struct dwc3 *dwc = gadget_to_dwc(g);
1555 unsigned long flags;
1556
1557 spin_lock_irqsave(&dwc->lock, flags);
1558
1559 __dwc3_gadget_ep_disable(dwc->eps[0]);
1560 __dwc3_gadget_ep_disable(dwc->eps[1]);
1561
1562 dwc->gadget_driver = NULL;
1563 dwc->gadget.dev.driver = NULL;
1564
1565 spin_unlock_irqrestore(&dwc->lock, flags);
1566
1567 return 0;
1568 }
1569
1570 static const struct usb_gadget_ops dwc3_gadget_ops = {
1571 .get_frame = dwc3_gadget_get_frame,
1572 .wakeup = dwc3_gadget_wakeup,
1573 .set_selfpowered = dwc3_gadget_set_selfpowered,
1574 .pullup = dwc3_gadget_pullup,
1575 .udc_start = dwc3_gadget_start,
1576 .udc_stop = dwc3_gadget_stop,
1577 };
1578
1579 /* -------------------------------------------------------------------------- */
1580
1581 static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1582 {
1583 struct dwc3_ep *dep;
1584 u8 epnum;
1585
1586 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1587
1588 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1589 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1590 if (!dep) {
1591 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1592 epnum);
1593 return -ENOMEM;
1594 }
1595
1596 dep->dwc = dwc;
1597 dep->number = epnum;
1598 dwc->eps[epnum] = dep;
1599
1600 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1601 (epnum & 1) ? "in" : "out");
1602 dep->endpoint.name = dep->name;
1603 dep->direction = (epnum & 1);
1604
1605 if (epnum == 0 || epnum == 1) {
1606 dep->endpoint.maxpacket = 512;
1607 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1608 if (!epnum)
1609 dwc->gadget.ep0 = &dep->endpoint;
1610 } else {
1611 int ret;
1612
1613 dep->endpoint.maxpacket = 1024;
1614 dep->endpoint.max_streams = 15;
1615 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1616 list_add_tail(&dep->endpoint.ep_list,
1617 &dwc->gadget.ep_list);
1618
1619 ret = dwc3_alloc_trb_pool(dep);
1620 if (ret)
1621 return ret;
1622 }
1623
1624 INIT_LIST_HEAD(&dep->request_list);
1625 INIT_LIST_HEAD(&dep->req_queued);
1626 }
1627
1628 return 0;
1629 }
1630
1631 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1632 {
1633 struct dwc3_ep *dep;
1634 u8 epnum;
1635
1636 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1637 dep = dwc->eps[epnum];
1638 dwc3_free_trb_pool(dep);
1639
1640 if (epnum != 0 && epnum != 1)
1641 list_del(&dep->endpoint.ep_list);
1642
1643 kfree(dep);
1644 }
1645 }
1646
1647 static void dwc3_gadget_release(struct device *dev)
1648 {
1649 dev_dbg(dev, "%s\n", __func__);
1650 }
1651
1652 /* -------------------------------------------------------------------------- */
1653 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1654 const struct dwc3_event_depevt *event, int status)
1655 {
1656 struct dwc3_request *req;
1657 struct dwc3_trb *trb;
1658 unsigned int count;
1659 unsigned int s_pkt = 0;
1660 unsigned int trb_status;
1661
1662 do {
1663 req = next_request(&dep->req_queued);
1664 if (!req) {
1665 WARN_ON_ONCE(1);
1666 return 1;
1667 }
1668
1669 trb = req->trb;
1670
1671 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1672 /*
1673 * We continue despite the error. There is not much we
1674 * can do. If we don't clean it up we loop forever. If
1675 * we skip the TRB then it gets overwritten after a
1676 * while since we use them in a ring buffer. A BUG()
1677 * would help. Lets hope that if this occurs, someone
1678 * fixes the root cause instead of looking away :)
1679 */
1680 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1681 dep->name, req->trb);
1682 count = trb->size & DWC3_TRB_SIZE_MASK;
1683
1684 if (dep->direction) {
1685 if (count) {
1686 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1687 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1688 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1689 dep->name);
1690 dep->current_uf = event->parameters &
1691 ~(dep->interval - 1);
1692 dep->flags |= DWC3_EP_MISSED_ISOC;
1693 } else {
1694 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1695 dep->name);
1696 status = -ECONNRESET;
1697 }
1698 }
1699 } else {
1700 if (count && (event->status & DEPEVT_STATUS_SHORT))
1701 s_pkt = 1;
1702 }
1703
1704 /*
1705 * We assume here we will always receive the entire data block
1706 * which we should receive. Meaning, if we program RX to
1707 * receive 4K but we receive only 2K, we assume that's all we
1708 * should receive and we simply bounce the request back to the
1709 * gadget driver for further processing.
1710 */
1711 req->request.actual += req->request.length - count;
1712 dwc3_gadget_giveback(dep, req, status);
1713 if (s_pkt)
1714 break;
1715 if ((event->status & DEPEVT_STATUS_LST) &&
1716 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1717 DWC3_TRB_CTRL_HWO)))
1718 break;
1719 if ((event->status & DEPEVT_STATUS_IOC) &&
1720 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1721 break;
1722 } while (1);
1723
1724 if ((event->status & DEPEVT_STATUS_IOC) &&
1725 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1726 return 0;
1727 return 1;
1728 }
1729
1730 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1731 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1732 int start_new)
1733 {
1734 unsigned status = 0;
1735 int clean_busy;
1736
1737 if (event->status & DEPEVT_STATUS_BUSERR)
1738 status = -ECONNRESET;
1739
1740 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1741 if (clean_busy)
1742 dep->flags &= ~DWC3_EP_BUSY;
1743
1744 /*
1745 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1746 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1747 */
1748 if (dwc->revision < DWC3_REVISION_183A) {
1749 u32 reg;
1750 int i;
1751
1752 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1753 struct dwc3_ep *dep = dwc->eps[i];
1754
1755 if (!(dep->flags & DWC3_EP_ENABLED))
1756 continue;
1757
1758 if (!list_empty(&dep->req_queued))
1759 return;
1760 }
1761
1762 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1763 reg |= dwc->u1u2;
1764 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1765
1766 dwc->u1u2 = 0;
1767 }
1768 }
1769
1770 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1771 const struct dwc3_event_depevt *event)
1772 {
1773 struct dwc3_ep *dep;
1774 u8 epnum = event->endpoint_number;
1775
1776 dep = dwc->eps[epnum];
1777
1778 if (!(dep->flags & DWC3_EP_ENABLED))
1779 return;
1780
1781 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1782 dwc3_ep_event_string(event->endpoint_event));
1783
1784 if (epnum == 0 || epnum == 1) {
1785 dwc3_ep0_interrupt(dwc, event);
1786 return;
1787 }
1788
1789 switch (event->endpoint_event) {
1790 case DWC3_DEPEVT_XFERCOMPLETE:
1791 dep->resource_index = 0;
1792
1793 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1794 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1795 dep->name);
1796 return;
1797 }
1798
1799 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1800 break;
1801 case DWC3_DEPEVT_XFERINPROGRESS:
1802 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1803 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1804 dep->name);
1805 return;
1806 }
1807
1808 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1809 break;
1810 case DWC3_DEPEVT_XFERNOTREADY:
1811 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1812 dwc3_gadget_start_isoc(dwc, dep, event);
1813 } else {
1814 int ret;
1815
1816 dev_vdbg(dwc->dev, "%s: reason %s\n",
1817 dep->name, event->status &
1818 DEPEVT_STATUS_TRANSFER_ACTIVE
1819 ? "Transfer Active"
1820 : "Transfer Not Active");
1821
1822 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1823 if (!ret || ret == -EBUSY)
1824 return;
1825
1826 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1827 dep->name);
1828 }
1829
1830 break;
1831 case DWC3_DEPEVT_STREAMEVT:
1832 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1833 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1834 dep->name);
1835 return;
1836 }
1837
1838 switch (event->status) {
1839 case DEPEVT_STREAMEVT_FOUND:
1840 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1841 event->parameters);
1842
1843 break;
1844 case DEPEVT_STREAMEVT_NOTFOUND:
1845 /* FALLTHROUGH */
1846 default:
1847 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1848 }
1849 break;
1850 case DWC3_DEPEVT_RXTXFIFOEVT:
1851 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1852 break;
1853 case DWC3_DEPEVT_EPCMDCMPLT:
1854 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1855 break;
1856 }
1857 }
1858
1859 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1860 {
1861 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1862 spin_unlock(&dwc->lock);
1863 dwc->gadget_driver->disconnect(&dwc->gadget);
1864 spin_lock(&dwc->lock);
1865 }
1866 }
1867
1868 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1869 {
1870 struct dwc3_ep *dep;
1871 struct dwc3_gadget_ep_cmd_params params;
1872 u32 cmd;
1873 int ret;
1874
1875 dep = dwc->eps[epnum];
1876
1877 if (!dep->resource_index)
1878 return;
1879
1880 cmd = DWC3_DEPCMD_ENDTRANSFER;
1881 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1882 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1883 memset(&params, 0, sizeof(params));
1884 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1885 WARN_ON_ONCE(ret);
1886 dep->resource_index = 0;
1887 }
1888
1889 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1890 {
1891 u32 epnum;
1892
1893 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1894 struct dwc3_ep *dep;
1895
1896 dep = dwc->eps[epnum];
1897 if (!(dep->flags & DWC3_EP_ENABLED))
1898 continue;
1899
1900 dwc3_remove_requests(dwc, dep);
1901 }
1902 }
1903
1904 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1905 {
1906 u32 epnum;
1907
1908 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1909 struct dwc3_ep *dep;
1910 struct dwc3_gadget_ep_cmd_params params;
1911 int ret;
1912
1913 dep = dwc->eps[epnum];
1914
1915 if (!(dep->flags & DWC3_EP_STALL))
1916 continue;
1917
1918 dep->flags &= ~DWC3_EP_STALL;
1919
1920 memset(&params, 0, sizeof(params));
1921 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1922 DWC3_DEPCMD_CLEARSTALL, &params);
1923 WARN_ON_ONCE(ret);
1924 }
1925 }
1926
1927 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1928 {
1929 int reg;
1930
1931 dev_vdbg(dwc->dev, "%s\n", __func__);
1932
1933 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1934 reg &= ~DWC3_DCTL_INITU1ENA;
1935 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1936
1937 reg &= ~DWC3_DCTL_INITU2ENA;
1938 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1939
1940 dwc3_disconnect_gadget(dwc);
1941 dwc->start_config_issued = false;
1942
1943 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1944 dwc->setup_packet_pending = false;
1945 }
1946
1947 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
1948 {
1949 u32 reg;
1950
1951 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1952
1953 if (suspend)
1954 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1955 else
1956 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1957
1958 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1959 }
1960
1961 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
1962 {
1963 u32 reg;
1964
1965 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1966
1967 if (suspend)
1968 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1969 else
1970 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1971
1972 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1973 }
1974
1975 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1976 {
1977 u32 reg;
1978
1979 dev_vdbg(dwc->dev, "%s\n", __func__);
1980
1981 /*
1982 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1983 * would cause a missing Disconnect Event if there's a
1984 * pending Setup Packet in the FIFO.
1985 *
1986 * There's no suggested workaround on the official Bug
1987 * report, which states that "unless the driver/application
1988 * is doing any special handling of a disconnect event,
1989 * there is no functional issue".
1990 *
1991 * Unfortunately, it turns out that we _do_ some special
1992 * handling of a disconnect event, namely complete all
1993 * pending transfers, notify gadget driver of the
1994 * disconnection, and so on.
1995 *
1996 * Our suggested workaround is to follow the Disconnect
1997 * Event steps here, instead, based on a setup_packet_pending
1998 * flag. Such flag gets set whenever we have a XferNotReady
1999 * event on EP0 and gets cleared on XferComplete for the
2000 * same endpoint.
2001 *
2002 * Refers to:
2003 *
2004 * STAR#9000466709: RTL: Device : Disconnect event not
2005 * generated if setup packet pending in FIFO
2006 */
2007 if (dwc->revision < DWC3_REVISION_188A) {
2008 if (dwc->setup_packet_pending)
2009 dwc3_gadget_disconnect_interrupt(dwc);
2010 }
2011
2012 /* after reset -> Default State */
2013 dwc->dev_state = DWC3_DEFAULT_STATE;
2014
2015 /* Recent versions support automatic phy suspend and don't need this */
2016 if (dwc->revision < DWC3_REVISION_194A) {
2017 /* Resume PHYs */
2018 dwc3_gadget_usb2_phy_suspend(dwc, false);
2019 dwc3_gadget_usb3_phy_suspend(dwc, false);
2020 }
2021
2022 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2023 dwc3_disconnect_gadget(dwc);
2024
2025 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2026 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2027 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2028 dwc->test_mode = false;
2029
2030 dwc3_stop_active_transfers(dwc);
2031 dwc3_clear_stall_all_ep(dwc);
2032 dwc->start_config_issued = false;
2033
2034 /* Reset device address to zero */
2035 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2036 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2037 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2038 }
2039
2040 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2041 {
2042 u32 reg;
2043 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2044
2045 /*
2046 * We change the clock only at SS but I dunno why I would want to do
2047 * this. Maybe it becomes part of the power saving plan.
2048 */
2049
2050 if (speed != DWC3_DSTS_SUPERSPEED)
2051 return;
2052
2053 /*
2054 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2055 * each time on Connect Done.
2056 */
2057 if (!usb30_clock)
2058 return;
2059
2060 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2061 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2062 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2063 }
2064
2065 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2066 {
2067 switch (speed) {
2068 case USB_SPEED_SUPER:
2069 dwc3_gadget_usb2_phy_suspend(dwc, true);
2070 break;
2071 case USB_SPEED_HIGH:
2072 case USB_SPEED_FULL:
2073 case USB_SPEED_LOW:
2074 dwc3_gadget_usb3_phy_suspend(dwc, true);
2075 break;
2076 }
2077 }
2078
2079 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2080 {
2081 struct dwc3_gadget_ep_cmd_params params;
2082 struct dwc3_ep *dep;
2083 int ret;
2084 u32 reg;
2085 u8 speed;
2086
2087 dev_vdbg(dwc->dev, "%s\n", __func__);
2088
2089 memset(&params, 0x00, sizeof(params));
2090
2091 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2092 speed = reg & DWC3_DSTS_CONNECTSPD;
2093 dwc->speed = speed;
2094
2095 dwc3_update_ram_clk_sel(dwc, speed);
2096
2097 switch (speed) {
2098 case DWC3_DCFG_SUPERSPEED:
2099 /*
2100 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2101 * would cause a missing USB3 Reset event.
2102 *
2103 * In such situations, we should force a USB3 Reset
2104 * event by calling our dwc3_gadget_reset_interrupt()
2105 * routine.
2106 *
2107 * Refers to:
2108 *
2109 * STAR#9000483510: RTL: SS : USB3 reset event may
2110 * not be generated always when the link enters poll
2111 */
2112 if (dwc->revision < DWC3_REVISION_190A)
2113 dwc3_gadget_reset_interrupt(dwc);
2114
2115 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2116 dwc->gadget.ep0->maxpacket = 512;
2117 dwc->gadget.speed = USB_SPEED_SUPER;
2118 break;
2119 case DWC3_DCFG_HIGHSPEED:
2120 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2121 dwc->gadget.ep0->maxpacket = 64;
2122 dwc->gadget.speed = USB_SPEED_HIGH;
2123 break;
2124 case DWC3_DCFG_FULLSPEED2:
2125 case DWC3_DCFG_FULLSPEED1:
2126 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2127 dwc->gadget.ep0->maxpacket = 64;
2128 dwc->gadget.speed = USB_SPEED_FULL;
2129 break;
2130 case DWC3_DCFG_LOWSPEED:
2131 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2132 dwc->gadget.ep0->maxpacket = 8;
2133 dwc->gadget.speed = USB_SPEED_LOW;
2134 break;
2135 }
2136
2137 /* Recent versions support automatic phy suspend and don't need this */
2138 if (dwc->revision < DWC3_REVISION_194A) {
2139 /* Suspend unneeded PHY */
2140 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2141 }
2142
2143 dep = dwc->eps[0];
2144 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2145 if (ret) {
2146 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2147 return;
2148 }
2149
2150 dep = dwc->eps[1];
2151 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2152 if (ret) {
2153 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2154 return;
2155 }
2156
2157 /*
2158 * Configure PHY via GUSB3PIPECTLn if required.
2159 *
2160 * Update GTXFIFOSIZn
2161 *
2162 * In both cases reset values should be sufficient.
2163 */
2164 }
2165
2166 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2167 {
2168 dev_vdbg(dwc->dev, "%s\n", __func__);
2169
2170 /*
2171 * TODO take core out of low power mode when that's
2172 * implemented.
2173 */
2174
2175 dwc->gadget_driver->resume(&dwc->gadget);
2176 }
2177
2178 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2179 unsigned int evtinfo)
2180 {
2181 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2182
2183 /*
2184 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2185 * on the link partner, the USB session might do multiple entry/exit
2186 * of low power states before a transfer takes place.
2187 *
2188 * Due to this problem, we might experience lower throughput. The
2189 * suggested workaround is to disable DCTL[12:9] bits if we're
2190 * transitioning from U1/U2 to U0 and enable those bits again
2191 * after a transfer completes and there are no pending transfers
2192 * on any of the enabled endpoints.
2193 *
2194 * This is the first half of that workaround.
2195 *
2196 * Refers to:
2197 *
2198 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2199 * core send LGO_Ux entering U0
2200 */
2201 if (dwc->revision < DWC3_REVISION_183A) {
2202 if (next == DWC3_LINK_STATE_U0) {
2203 u32 u1u2;
2204 u32 reg;
2205
2206 switch (dwc->link_state) {
2207 case DWC3_LINK_STATE_U1:
2208 case DWC3_LINK_STATE_U2:
2209 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2210 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2211 | DWC3_DCTL_ACCEPTU2ENA
2212 | DWC3_DCTL_INITU1ENA
2213 | DWC3_DCTL_ACCEPTU1ENA);
2214
2215 if (!dwc->u1u2)
2216 dwc->u1u2 = reg & u1u2;
2217
2218 reg &= ~u1u2;
2219
2220 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2221 break;
2222 default:
2223 /* do nothing */
2224 break;
2225 }
2226 }
2227 }
2228
2229 dwc->link_state = next;
2230
2231 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2232 }
2233
2234 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2235 const struct dwc3_event_devt *event)
2236 {
2237 switch (event->type) {
2238 case DWC3_DEVICE_EVENT_DISCONNECT:
2239 dwc3_gadget_disconnect_interrupt(dwc);
2240 break;
2241 case DWC3_DEVICE_EVENT_RESET:
2242 dwc3_gadget_reset_interrupt(dwc);
2243 break;
2244 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2245 dwc3_gadget_conndone_interrupt(dwc);
2246 break;
2247 case DWC3_DEVICE_EVENT_WAKEUP:
2248 dwc3_gadget_wakeup_interrupt(dwc);
2249 break;
2250 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2251 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2252 break;
2253 case DWC3_DEVICE_EVENT_EOPF:
2254 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2255 break;
2256 case DWC3_DEVICE_EVENT_SOF:
2257 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2258 break;
2259 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2260 dev_vdbg(dwc->dev, "Erratic Error\n");
2261 break;
2262 case DWC3_DEVICE_EVENT_CMD_CMPL:
2263 dev_vdbg(dwc->dev, "Command Complete\n");
2264 break;
2265 case DWC3_DEVICE_EVENT_OVERFLOW:
2266 dev_vdbg(dwc->dev, "Overflow\n");
2267 break;
2268 default:
2269 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2270 }
2271 }
2272
2273 static void dwc3_process_event_entry(struct dwc3 *dwc,
2274 const union dwc3_event *event)
2275 {
2276 /* Endpoint IRQ, handle it and return early */
2277 if (event->type.is_devspec == 0) {
2278 /* depevt */
2279 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2280 }
2281
2282 switch (event->type.type) {
2283 case DWC3_EVENT_TYPE_DEV:
2284 dwc3_gadget_interrupt(dwc, &event->devt);
2285 break;
2286 /* REVISIT what to do with Carkit and I2C events ? */
2287 default:
2288 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2289 }
2290 }
2291
2292 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2293 {
2294 struct dwc3_event_buffer *evt;
2295 int left;
2296 u32 count;
2297
2298 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2299 count &= DWC3_GEVNTCOUNT_MASK;
2300 if (!count)
2301 return IRQ_NONE;
2302
2303 evt = dwc->ev_buffs[buf];
2304 left = count;
2305
2306 while (left > 0) {
2307 union dwc3_event event;
2308
2309 event.raw = *(u32 *) (evt->buf + evt->lpos);
2310
2311 dwc3_process_event_entry(dwc, &event);
2312 /*
2313 * XXX we wrap around correctly to the next entry as almost all
2314 * entries are 4 bytes in size. There is one entry which has 12
2315 * bytes which is a regular entry followed by 8 bytes data. ATM
2316 * I don't know how things are organized if were get next to the
2317 * a boundary so I worry about that once we try to handle that.
2318 */
2319 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2320 left -= 4;
2321
2322 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2323 }
2324
2325 return IRQ_HANDLED;
2326 }
2327
2328 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2329 {
2330 struct dwc3 *dwc = _dwc;
2331 int i;
2332 irqreturn_t ret = IRQ_NONE;
2333
2334 spin_lock(&dwc->lock);
2335
2336 for (i = 0; i < dwc->num_event_buffers; i++) {
2337 irqreturn_t status;
2338
2339 status = dwc3_process_event_buf(dwc, i);
2340 if (status == IRQ_HANDLED)
2341 ret = status;
2342 }
2343
2344 spin_unlock(&dwc->lock);
2345
2346 return ret;
2347 }
2348
2349 /**
2350 * dwc3_gadget_init - Initializes gadget related registers
2351 * @dwc: pointer to our controller context structure
2352 *
2353 * Returns 0 on success otherwise negative errno.
2354 */
2355 int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2356 {
2357 u32 reg;
2358 int ret;
2359 int irq;
2360
2361 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2362 &dwc->ctrl_req_addr, GFP_KERNEL);
2363 if (!dwc->ctrl_req) {
2364 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2365 ret = -ENOMEM;
2366 goto err0;
2367 }
2368
2369 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2370 &dwc->ep0_trb_addr, GFP_KERNEL);
2371 if (!dwc->ep0_trb) {
2372 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2373 ret = -ENOMEM;
2374 goto err1;
2375 }
2376
2377 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2378 if (!dwc->setup_buf) {
2379 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2380 ret = -ENOMEM;
2381 goto err2;
2382 }
2383
2384 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2385 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2386 GFP_KERNEL);
2387 if (!dwc->ep0_bounce) {
2388 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2389 ret = -ENOMEM;
2390 goto err3;
2391 }
2392
2393 dev_set_name(&dwc->gadget.dev, "gadget");
2394
2395 dwc->gadget.ops = &dwc3_gadget_ops;
2396 dwc->gadget.max_speed = USB_SPEED_SUPER;
2397 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2398 dwc->gadget.dev.parent = dwc->dev;
2399 dwc->gadget.sg_supported = true;
2400
2401 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2402
2403 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2404 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2405 dwc->gadget.dev.release = dwc3_gadget_release;
2406 dwc->gadget.name = "dwc3-gadget";
2407
2408 /*
2409 * REVISIT: Here we should clear all pending IRQs to be
2410 * sure we're starting from a well known location.
2411 */
2412
2413 ret = dwc3_gadget_init_endpoints(dwc);
2414 if (ret)
2415 goto err4;
2416
2417 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2418
2419 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2420 "dwc3", dwc);
2421 if (ret) {
2422 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2423 irq, ret);
2424 goto err5;
2425 }
2426
2427 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2428 reg |= DWC3_DCFG_LPM_CAP;
2429 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2430
2431 /* Enable all but Start and End of Frame IRQs */
2432 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2433 DWC3_DEVTEN_EVNTOVERFLOWEN |
2434 DWC3_DEVTEN_CMDCMPLTEN |
2435 DWC3_DEVTEN_ERRTICERREN |
2436 DWC3_DEVTEN_WKUPEVTEN |
2437 DWC3_DEVTEN_ULSTCNGEN |
2438 DWC3_DEVTEN_CONNECTDONEEN |
2439 DWC3_DEVTEN_USBRSTEN |
2440 DWC3_DEVTEN_DISCONNEVTEN);
2441 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2442
2443 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2444 if (dwc->revision >= DWC3_REVISION_194A) {
2445 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2446 reg |= DWC3_DCFG_LPM_CAP;
2447 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2448
2449 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2450 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2451
2452 /* TODO: This should be configurable */
2453 reg |= DWC3_DCTL_HIRD_THRES(28);
2454
2455 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2456
2457 dwc3_gadget_usb2_phy_suspend(dwc, false);
2458 dwc3_gadget_usb3_phy_suspend(dwc, false);
2459 }
2460
2461 ret = device_register(&dwc->gadget.dev);
2462 if (ret) {
2463 dev_err(dwc->dev, "failed to register gadget device\n");
2464 put_device(&dwc->gadget.dev);
2465 goto err6;
2466 }
2467
2468 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2469 if (ret) {
2470 dev_err(dwc->dev, "failed to register udc\n");
2471 goto err7;
2472 }
2473
2474 return 0;
2475
2476 err7:
2477 device_unregister(&dwc->gadget.dev);
2478
2479 err6:
2480 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2481 free_irq(irq, dwc);
2482
2483 err5:
2484 dwc3_gadget_free_endpoints(dwc);
2485
2486 err4:
2487 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2488 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2489
2490 err3:
2491 kfree(dwc->setup_buf);
2492
2493 err2:
2494 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2495 dwc->ep0_trb, dwc->ep0_trb_addr);
2496
2497 err1:
2498 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2499 dwc->ctrl_req, dwc->ctrl_req_addr);
2500
2501 err0:
2502 return ret;
2503 }
2504
2505 void dwc3_gadget_exit(struct dwc3 *dwc)
2506 {
2507 int irq;
2508
2509 usb_del_gadget_udc(&dwc->gadget);
2510 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2511
2512 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2513 free_irq(irq, dwc);
2514
2515 dwc3_gadget_free_endpoints(dwc);
2516
2517 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2518 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2519
2520 kfree(dwc->setup_buf);
2521
2522 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2523 dwc->ep0_trb, dwc->ep0_trb_addr);
2524
2525 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2526 dwc->ctrl_req, dwc->ctrl_req_addr);
2527
2528 device_unregister(&dwc->gadget.dev);
2529 }
Linux kernel - Deliverables
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