2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
51 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
52 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
66 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
82 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
84 return DWC3_DSTS_USBLNKST(reg
);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc
->revision
>= DWC3_REVISION_194A
) {
106 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
107 if (reg
& DWC3_DSTS_DCNRD
)
117 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
118 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
120 /* set requested state */
121 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
122 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc
->revision
>= DWC3_REVISION_194A
)
131 /* wait for a change in DSTS */
134 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
136 if (DWC3_DSTS_USBLNKST(reg
) == state
)
142 dev_vdbg(dwc
->dev
, "link state change request timed out\n");
148 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
149 * @dwc: pointer to our context structure
151 * This function will a best effort FIFO allocation in order
152 * to improve FIFO usage and throughput, while still allowing
153 * us to enable as many endpoints as possible.
155 * Keep in mind that this operation will be highly dependent
156 * on the configured size for RAM1 - which contains TxFifo -,
157 * the amount of endpoints enabled on coreConsultant tool, and
158 * the width of the Master Bus.
160 * In the ideal world, we would always be able to satisfy the
161 * following equation:
163 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
164 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
166 * Unfortunately, due to many variables that's not always the case.
168 int dwc3_gadget_resize_tx_fifos(struct dwc3
*dwc
)
170 int last_fifo_depth
= 0;
176 if (!dwc
->needs_fifo_resize
)
179 ram1_depth
= DWC3_RAM1_DEPTH(dwc
->hwparams
.hwparams7
);
180 mdwidth
= DWC3_MDWIDTH(dwc
->hwparams
.hwparams0
);
182 /* MDWIDTH is represented in bits, we need it in bytes */
186 * FIXME For now we will only allocate 1 wMaxPacketSize space
187 * for each enabled endpoint, later patches will come to
188 * improve this algorithm so that we better use the internal
191 for (num
= 0; num
< dwc
->num_in_eps
; num
++) {
192 /* bit0 indicates direction; 1 means IN ep */
193 struct dwc3_ep
*dep
= dwc
->eps
[(num
<< 1) | 1];
197 if (!(dep
->flags
& DWC3_EP_ENABLED
))
200 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)
201 || usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
205 * REVISIT: the following assumes we will always have enough
206 * space available on the FIFO RAM for all possible use cases.
207 * Make sure that's true somehow and change FIFO allocation
210 * If we have Bulk or Isochronous endpoints, we want
211 * them to be able to be very, very fast. So we're giving
212 * those endpoints a fifo_size which is enough for 3 full
215 tmp
= mult
* (dep
->endpoint
.maxpacket
+ mdwidth
);
218 fifo_size
= DIV_ROUND_UP(tmp
, mdwidth
);
220 fifo_size
|= (last_fifo_depth
<< 16);
222 dev_vdbg(dwc
->dev
, "%s: Fifo Addr %04x Size %d\n",
223 dep
->name
, last_fifo_depth
, fifo_size
& 0xffff);
225 dwc3_writel(dwc
->regs
, DWC3_GTXFIFOSIZ(num
), fifo_size
);
227 last_fifo_depth
+= (fifo_size
& 0xffff);
233 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
236 struct dwc3
*dwc
= dep
->dwc
;
244 * Skip LINK TRB. We can't use req->trb and check for
245 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
246 * just completed (not the LINK TRB).
248 if (((dep
->busy_slot
& DWC3_TRB_MASK
) ==
250 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
252 } while(++i
< req
->request
.num_mapped_sgs
);
255 list_del(&req
->list
);
258 if (req
->request
.status
== -EINPROGRESS
)
259 req
->request
.status
= status
;
261 if (dwc
->ep0_bounced
&& dep
->number
== 0)
262 dwc
->ep0_bounced
= false;
264 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
267 dev_dbg(dwc
->dev
, "request %p from %s completed %d/%d ===> %d\n",
268 req
, dep
->name
, req
->request
.actual
,
269 req
->request
.length
, status
);
270 trace_dwc3_gadget_giveback(req
);
272 spin_unlock(&dwc
->lock
);
273 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
274 spin_lock(&dwc
->lock
);
277 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
282 trace_dwc3_gadget_generic_cmd(cmd
, param
);
284 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
285 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
288 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
289 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
290 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
291 DWC3_DGCMD_STATUS(reg
));
296 * We can't sleep here, because it's also called from
306 int dwc3_send_gadget_ep_cmd(struct dwc3
*dwc
, unsigned ep
,
307 unsigned cmd
, struct dwc3_gadget_ep_cmd_params
*params
)
309 struct dwc3_ep
*dep
= dwc
->eps
[ep
];
313 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
);
315 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR0(ep
), params
->param0
);
316 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR1(ep
), params
->param1
);
317 dwc3_writel(dwc
->regs
, DWC3_DEPCMDPAR2(ep
), params
->param2
);
319 dwc3_writel(dwc
->regs
, DWC3_DEPCMD(ep
), cmd
| DWC3_DEPCMD_CMDACT
);
321 reg
= dwc3_readl(dwc
->regs
, DWC3_DEPCMD(ep
));
322 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
323 dev_vdbg(dwc
->dev
, "Command Complete --> %d\n",
324 DWC3_DEPCMD_STATUS(reg
));
329 * We can't sleep here, because it is also called from
340 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
341 struct dwc3_trb
*trb
)
343 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
345 return dep
->trb_pool_dma
+ offset
;
348 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
350 struct dwc3
*dwc
= dep
->dwc
;
355 if (dep
->number
== 0 || dep
->number
== 1)
358 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
359 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
360 &dep
->trb_pool_dma
, GFP_KERNEL
);
361 if (!dep
->trb_pool
) {
362 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
370 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
372 struct dwc3
*dwc
= dep
->dwc
;
374 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
375 dep
->trb_pool
, dep
->trb_pool_dma
);
377 dep
->trb_pool
= NULL
;
378 dep
->trb_pool_dma
= 0;
381 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
383 struct dwc3_gadget_ep_cmd_params params
;
386 memset(¶ms
, 0x00, sizeof(params
));
388 if (dep
->number
!= 1) {
389 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
390 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
391 if (dep
->number
> 1) {
392 if (dwc
->start_config_issued
)
394 dwc
->start_config_issued
= true;
395 cmd
|= DWC3_DEPCMD_PARAM(2);
398 return dwc3_send_gadget_ep_cmd(dwc
, 0, cmd
, ¶ms
);
404 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
405 const struct usb_endpoint_descriptor
*desc
,
406 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
407 bool ignore
, bool restore
)
409 struct dwc3_gadget_ep_cmd_params params
;
411 memset(¶ms
, 0x00, sizeof(params
));
413 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
414 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
416 /* Burst size is only needed in SuperSpeed mode */
417 if (dwc
->gadget
.speed
== USB_SPEED_SUPER
) {
418 u32 burst
= dep
->endpoint
.maxburst
- 1;
420 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
);
424 params
.param0
|= DWC3_DEPCFG_IGN_SEQ_NUM
;
427 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
428 params
.param2
|= dep
->saved_state
;
431 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
432 | DWC3_DEPCFG_XFER_NOT_READY_EN
;
434 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
435 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
436 | DWC3_DEPCFG_STREAM_EVENT_EN
;
437 dep
->stream_capable
= true;
440 if (!usb_endpoint_xfer_control(desc
))
441 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
444 * We are doing 1:1 mapping for endpoints, meaning
445 * Physical Endpoints 2 maps to Logical Endpoint 2 and
446 * so on. We consider the direction bit as part of the physical
447 * endpoint number. So USB endpoint 0x81 is 0x03.
449 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
452 * We must use the lower 16 TX FIFOs even though
456 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
458 if (desc
->bInterval
) {
459 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
460 dep
->interval
= 1 << (desc
->bInterval
- 1);
463 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
464 DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
467 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
469 struct dwc3_gadget_ep_cmd_params params
;
471 memset(¶ms
, 0x00, sizeof(params
));
473 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
475 return dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
476 DWC3_DEPCMD_SETTRANSFRESOURCE
, ¶ms
);
480 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
481 * @dep: endpoint to be initialized
482 * @desc: USB Endpoint Descriptor
484 * Caller should take care of locking
486 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
487 const struct usb_endpoint_descriptor
*desc
,
488 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
489 bool ignore
, bool restore
)
491 struct dwc3
*dwc
= dep
->dwc
;
495 dev_vdbg(dwc
->dev
, "Enabling %s\n", dep
->name
);
497 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
498 ret
= dwc3_gadget_start_config(dwc
, dep
);
503 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, ignore
,
508 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
509 struct dwc3_trb
*trb_st_hw
;
510 struct dwc3_trb
*trb_link
;
512 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
516 dep
->endpoint
.desc
= desc
;
517 dep
->comp_desc
= comp_desc
;
518 dep
->type
= usb_endpoint_type(desc
);
519 dep
->flags
|= DWC3_EP_ENABLED
;
521 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
522 reg
|= DWC3_DALEPENA_EP(dep
->number
);
523 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
525 if (!usb_endpoint_xfer_isoc(desc
))
528 /* Link TRB for ISOC. The HWO bit is never reset */
529 trb_st_hw
= &dep
->trb_pool
[0];
531 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
532 memset(trb_link
, 0, sizeof(*trb_link
));
534 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
535 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
536 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
537 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
543 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
544 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
546 struct dwc3_request
*req
;
548 if (!list_empty(&dep
->req_queued
)) {
549 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
551 /* - giveback all requests to gadget driver */
552 while (!list_empty(&dep
->req_queued
)) {
553 req
= next_request(&dep
->req_queued
);
555 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
559 while (!list_empty(&dep
->request_list
)) {
560 req
= next_request(&dep
->request_list
);
562 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
567 * __dwc3_gadget_ep_disable - Disables a HW endpoint
568 * @dep: the endpoint to disable
570 * This function also removes requests which are currently processed ny the
571 * hardware and those which are not yet scheduled.
572 * Caller should take care of locking.
574 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
576 struct dwc3
*dwc
= dep
->dwc
;
579 dwc3_remove_requests(dwc
, dep
);
581 /* make sure HW endpoint isn't stalled */
582 if (dep
->flags
& DWC3_EP_STALL
)
583 __dwc3_gadget_ep_set_halt(dep
, 0, false);
585 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
586 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
587 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
589 dep
->stream_capable
= false;
590 dep
->endpoint
.desc
= NULL
;
591 dep
->comp_desc
= NULL
;
598 /* -------------------------------------------------------------------------- */
600 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
601 const struct usb_endpoint_descriptor
*desc
)
606 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
611 /* -------------------------------------------------------------------------- */
613 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
614 const struct usb_endpoint_descriptor
*desc
)
621 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
622 pr_debug("dwc3: invalid parameters\n");
626 if (!desc
->wMaxPacketSize
) {
627 pr_debug("dwc3: missing wMaxPacketSize\n");
631 dep
= to_dwc3_ep(ep
);
634 if (dep
->flags
& DWC3_EP_ENABLED
) {
635 dev_WARN_ONCE(dwc
->dev
, true, "%s is already enabled\n",
640 switch (usb_endpoint_type(desc
)) {
641 case USB_ENDPOINT_XFER_CONTROL
:
642 strlcat(dep
->name
, "-control", sizeof(dep
->name
));
644 case USB_ENDPOINT_XFER_ISOC
:
645 strlcat(dep
->name
, "-isoc", sizeof(dep
->name
));
647 case USB_ENDPOINT_XFER_BULK
:
648 strlcat(dep
->name
, "-bulk", sizeof(dep
->name
));
650 case USB_ENDPOINT_XFER_INT
:
651 strlcat(dep
->name
, "-int", sizeof(dep
->name
));
654 dev_err(dwc
->dev
, "invalid endpoint transfer type\n");
657 spin_lock_irqsave(&dwc
->lock
, flags
);
658 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false, false);
659 spin_unlock_irqrestore(&dwc
->lock
, flags
);
664 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
672 pr_debug("dwc3: invalid parameters\n");
676 dep
= to_dwc3_ep(ep
);
679 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
680 dev_WARN_ONCE(dwc
->dev
, true, "%s is already disabled\n",
685 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s",
687 (dep
->number
& 1) ? "in" : "out");
689 spin_lock_irqsave(&dwc
->lock
, flags
);
690 ret
= __dwc3_gadget_ep_disable(dep
);
691 spin_unlock_irqrestore(&dwc
->lock
, flags
);
696 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
699 struct dwc3_request
*req
;
700 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
702 req
= kzalloc(sizeof(*req
), gfp_flags
);
706 req
->epnum
= dep
->number
;
709 trace_dwc3_alloc_request(req
);
711 return &req
->request
;
714 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
715 struct usb_request
*request
)
717 struct dwc3_request
*req
= to_dwc3_request(request
);
719 trace_dwc3_free_request(req
);
724 * dwc3_prepare_one_trb - setup one TRB from one request
725 * @dep: endpoint for which this request is prepared
726 * @req: dwc3_request pointer
728 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
729 struct dwc3_request
*req
, dma_addr_t dma
,
730 unsigned length
, unsigned last
, unsigned chain
, unsigned node
)
732 struct dwc3
*dwc
= dep
->dwc
;
733 struct dwc3_trb
*trb
;
735 dev_vdbg(dwc
->dev
, "%s: req %p dma %08llx length %d%s%s\n",
736 dep
->name
, req
, (unsigned long long) dma
,
737 length
, last
? " last" : "",
738 chain
? " chain" : "");
741 trb
= &dep
->trb_pool
[dep
->free_slot
& DWC3_TRB_MASK
];
744 dwc3_gadget_move_request_queued(req
);
746 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
747 req
->start_slot
= dep
->free_slot
& DWC3_TRB_MASK
;
751 /* Skip the LINK-TRB on ISOC */
752 if (((dep
->free_slot
& DWC3_TRB_MASK
) == DWC3_TRB_NUM
- 1) &&
753 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
756 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
757 trb
->bpl
= lower_32_bits(dma
);
758 trb
->bph
= upper_32_bits(dma
);
760 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
761 case USB_ENDPOINT_XFER_CONTROL
:
762 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
765 case USB_ENDPOINT_XFER_ISOC
:
767 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
769 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
772 case USB_ENDPOINT_XFER_BULK
:
773 case USB_ENDPOINT_XFER_INT
:
774 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
778 * This is only possible with faulty memory because we
779 * checked it already :)
784 if (!req
->request
.no_interrupt
&& !chain
)
785 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
787 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
788 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
789 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
791 trb
->ctrl
|= DWC3_TRB_CTRL_LST
;
795 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
797 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
798 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
800 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
802 trace_dwc3_prepare_trb(dep
, trb
);
806 * dwc3_prepare_trbs - setup TRBs from requests
807 * @dep: endpoint for which requests are being prepared
808 * @starting: true if the endpoint is idle and no requests are queued.
810 * The function goes through the requests list and sets up TRBs for the
811 * transfers. The function returns once there are no more TRBs available or
812 * it runs out of requests.
814 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
, bool starting
)
816 struct dwc3_request
*req
, *n
;
819 unsigned int last_one
= 0;
821 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
823 /* the first request must not be queued */
824 trbs_left
= (dep
->busy_slot
- dep
->free_slot
) & DWC3_TRB_MASK
;
826 /* Can't wrap around on a non-isoc EP since there's no link TRB */
827 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
828 max
= DWC3_TRB_NUM
- (dep
->free_slot
& DWC3_TRB_MASK
);
834 * If busy & slot are equal than it is either full or empty. If we are
835 * starting to process requests then we are empty. Otherwise we are
836 * full and don't do anything
841 trbs_left
= DWC3_TRB_NUM
;
843 * In case we start from scratch, we queue the ISOC requests
844 * starting from slot 1. This is done because we use ring
845 * buffer and have no LST bit to stop us. Instead, we place
846 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
847 * after the first request so we start at slot 1 and have
848 * 7 requests proceed before we hit the first IOC.
849 * Other transfer types don't use the ring buffer and are
850 * processed from the first TRB until the last one. Since we
851 * don't wrap around we have to start at the beginning.
853 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
862 /* The last TRB is a link TRB, not used for xfer */
863 if ((trbs_left
<= 1) && usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
866 list_for_each_entry_safe(req
, n
, &dep
->request_list
, list
) {
871 if (req
->request
.num_mapped_sgs
> 0) {
872 struct usb_request
*request
= &req
->request
;
873 struct scatterlist
*sg
= request
->sg
;
874 struct scatterlist
*s
;
877 for_each_sg(sg
, s
, request
->num_mapped_sgs
, i
) {
878 unsigned chain
= true;
880 length
= sg_dma_len(s
);
881 dma
= sg_dma_address(s
);
883 if (i
== (request
->num_mapped_sgs
- 1) ||
885 if (list_is_last(&req
->list
,
898 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
905 dma
= req
->request
.dma
;
906 length
= req
->request
.length
;
912 /* Is this the last request? */
913 if (list_is_last(&req
->list
, &dep
->request_list
))
916 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
925 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
,
928 struct dwc3_gadget_ep_cmd_params params
;
929 struct dwc3_request
*req
;
930 struct dwc3
*dwc
= dep
->dwc
;
934 if (start_new
&& (dep
->flags
& DWC3_EP_BUSY
)) {
935 dev_vdbg(dwc
->dev
, "%s: endpoint busy\n", dep
->name
);
938 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
941 * If we are getting here after a short-out-packet we don't enqueue any
942 * new requests as we try to set the IOC bit only on the last request.
945 if (list_empty(&dep
->req_queued
))
946 dwc3_prepare_trbs(dep
, start_new
);
948 /* req points to the first request which will be sent */
949 req
= next_request(&dep
->req_queued
);
951 dwc3_prepare_trbs(dep
, start_new
);
954 * req points to the first request where HWO changed from 0 to 1
956 req
= next_request(&dep
->req_queued
);
959 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
963 memset(¶ms
, 0, sizeof(params
));
966 params
.param0
= upper_32_bits(req
->trb_dma
);
967 params
.param1
= lower_32_bits(req
->trb_dma
);
968 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
970 cmd
= DWC3_DEPCMD_UPDATETRANSFER
;
973 cmd
|= DWC3_DEPCMD_PARAM(cmd_param
);
974 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
976 dev_dbg(dwc
->dev
, "failed to send STARTTRANSFER command\n");
979 * FIXME we need to iterate over the list of requests
980 * here and stop, unmap, free and del each of the linked
981 * requests instead of what we do now.
983 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
985 list_del(&req
->list
);
989 dep
->flags
|= DWC3_EP_BUSY
;
992 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dwc
,
994 WARN_ON_ONCE(!dep
->resource_index
);
1000 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1001 struct dwc3_ep
*dep
, u32 cur_uf
)
1005 if (list_empty(&dep
->request_list
)) {
1006 dev_vdbg(dwc
->dev
, "ISOC ep %s run out for requests.\n",
1008 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1012 /* 4 micro frames in the future */
1013 uf
= cur_uf
+ dep
->interval
* 4;
1015 __dwc3_gadget_kick_transfer(dep
, uf
, 1);
1018 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1019 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1023 mask
= ~(dep
->interval
- 1);
1024 cur_uf
= event
->parameters
& mask
;
1026 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1029 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1031 struct dwc3
*dwc
= dep
->dwc
;
1034 req
->request
.actual
= 0;
1035 req
->request
.status
= -EINPROGRESS
;
1036 req
->direction
= dep
->direction
;
1037 req
->epnum
= dep
->number
;
1040 * We only add to our list of requests now and
1041 * start consuming the list once we get XferNotReady
1044 * That way, we avoid doing anything that we don't need
1045 * to do now and defer it until the point we receive a
1046 * particular token from the Host side.
1048 * This will also avoid Host cancelling URBs due to too
1051 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1056 list_add_tail(&req
->list
, &dep
->request_list
);
1059 * There are a few special cases:
1061 * 1. XferNotReady with empty list of requests. We need to kick the
1062 * transfer here in that situation, otherwise we will be NAKing
1063 * forever. If we get XferNotReady before gadget driver has a
1064 * chance to queue a request, we will ACK the IRQ but won't be
1065 * able to receive the data until the next request is queued.
1066 * The following code is handling exactly that.
1069 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
1071 * If xfernotready is already elapsed and it is a case
1072 * of isoc transfer, then issue END TRANSFER, so that
1073 * you can receive xfernotready again and can have
1074 * notion of current microframe.
1076 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1077 if (list_empty(&dep
->req_queued
)) {
1078 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1079 dep
->flags
= DWC3_EP_ENABLED
;
1084 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1085 if (ret
&& ret
!= -EBUSY
)
1086 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1092 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1093 * kick the transfer here after queuing a request, otherwise the
1094 * core may not see the modified TRB(s).
1096 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1097 (dep
->flags
& DWC3_EP_BUSY
) &&
1098 !(dep
->flags
& DWC3_EP_MISSED_ISOC
)) {
1099 WARN_ON_ONCE(!dep
->resource_index
);
1100 ret
= __dwc3_gadget_kick_transfer(dep
, dep
->resource_index
,
1102 if (ret
&& ret
!= -EBUSY
)
1103 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1109 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1110 * right away, otherwise host will not know we have streams to be
1113 if (dep
->stream_capable
) {
1116 ret
= __dwc3_gadget_kick_transfer(dep
, 0, true);
1117 if (ret
&& ret
!= -EBUSY
) {
1118 struct dwc3
*dwc
= dep
->dwc
;
1120 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1128 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1131 struct dwc3_request
*req
= to_dwc3_request(request
);
1132 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1133 struct dwc3
*dwc
= dep
->dwc
;
1135 unsigned long flags
;
1139 spin_lock_irqsave(&dwc
->lock
, flags
);
1140 if (!dep
->endpoint
.desc
) {
1141 dev_dbg(dwc
->dev
, "trying to queue request %p to disabled %s\n",
1143 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1147 dev_vdbg(dwc
->dev
, "queing request %p to %s length %d\n",
1148 request
, ep
->name
, request
->length
);
1149 trace_dwc3_ep_queue(req
);
1151 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1152 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1157 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1158 struct usb_request
*request
)
1160 struct dwc3_request
*req
= to_dwc3_request(request
);
1161 struct dwc3_request
*r
= NULL
;
1163 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1164 struct dwc3
*dwc
= dep
->dwc
;
1166 unsigned long flags
;
1169 trace_dwc3_ep_dequeue(req
);
1171 spin_lock_irqsave(&dwc
->lock
, flags
);
1173 list_for_each_entry(r
, &dep
->request_list
, list
) {
1179 list_for_each_entry(r
, &dep
->req_queued
, list
) {
1184 /* wait until it is processed */
1185 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1188 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1195 /* giveback the request */
1196 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1199 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1204 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1206 struct dwc3_gadget_ep_cmd_params params
;
1207 struct dwc3
*dwc
= dep
->dwc
;
1210 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1211 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1215 memset(¶ms
, 0x00, sizeof(params
));
1218 if (!protocol
&& ((dep
->direction
&& dep
->flags
& DWC3_EP_BUSY
) ||
1219 (!list_empty(&dep
->req_queued
) ||
1220 !list_empty(&dep
->request_list
)))) {
1221 dev_dbg(dwc
->dev
, "%s: pending request, cannot halt\n",
1226 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1227 DWC3_DEPCMD_SETSTALL
, ¶ms
);
1229 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1232 dep
->flags
|= DWC3_EP_STALL
;
1234 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
1235 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
1237 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1240 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1246 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1248 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1249 struct dwc3
*dwc
= dep
->dwc
;
1251 unsigned long flags
;
1255 spin_lock_irqsave(&dwc
->lock
, flags
);
1256 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1257 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1262 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1264 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1265 struct dwc3
*dwc
= dep
->dwc
;
1266 unsigned long flags
;
1269 spin_lock_irqsave(&dwc
->lock
, flags
);
1270 dep
->flags
|= DWC3_EP_WEDGE
;
1272 if (dep
->number
== 0 || dep
->number
== 1)
1273 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1275 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1276 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1281 /* -------------------------------------------------------------------------- */
1283 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1284 .bLength
= USB_DT_ENDPOINT_SIZE
,
1285 .bDescriptorType
= USB_DT_ENDPOINT
,
1286 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1289 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1290 .enable
= dwc3_gadget_ep0_enable
,
1291 .disable
= dwc3_gadget_ep0_disable
,
1292 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1293 .free_request
= dwc3_gadget_ep_free_request
,
1294 .queue
= dwc3_gadget_ep0_queue
,
1295 .dequeue
= dwc3_gadget_ep_dequeue
,
1296 .set_halt
= dwc3_gadget_ep0_set_halt
,
1297 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1300 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1301 .enable
= dwc3_gadget_ep_enable
,
1302 .disable
= dwc3_gadget_ep_disable
,
1303 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1304 .free_request
= dwc3_gadget_ep_free_request
,
1305 .queue
= dwc3_gadget_ep_queue
,
1306 .dequeue
= dwc3_gadget_ep_dequeue
,
1307 .set_halt
= dwc3_gadget_ep_set_halt
,
1308 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1311 /* -------------------------------------------------------------------------- */
1313 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1315 struct dwc3
*dwc
= gadget_to_dwc(g
);
1318 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1319 return DWC3_DSTS_SOFFN(reg
);
1322 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1324 struct dwc3
*dwc
= gadget_to_dwc(g
);
1326 unsigned long timeout
;
1327 unsigned long flags
;
1336 spin_lock_irqsave(&dwc
->lock
, flags
);
1339 * According to the Databook Remote wakeup request should
1340 * be issued only when the device is in early suspend state.
1342 * We can check that via USB Link State bits in DSTS register.
1344 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1346 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1347 if (speed
== DWC3_DSTS_SUPERSPEED
) {
1348 dev_dbg(dwc
->dev
, "no wakeup on SuperSpeed\n");
1353 link_state
= DWC3_DSTS_USBLNKST(reg
);
1355 switch (link_state
) {
1356 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1357 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1360 dev_dbg(dwc
->dev
, "can't wakeup from link state %d\n",
1366 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1368 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1372 /* Recent versions do this automatically */
1373 if (dwc
->revision
< DWC3_REVISION_194A
) {
1374 /* write zeroes to Link Change Request */
1375 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1376 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1377 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1380 /* poll until Link State changes to ON */
1381 timeout
= jiffies
+ msecs_to_jiffies(100);
1383 while (!time_after(jiffies
, timeout
)) {
1384 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1386 /* in HS, means ON */
1387 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1391 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1392 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1397 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1402 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1405 struct dwc3
*dwc
= gadget_to_dwc(g
);
1406 unsigned long flags
;
1408 spin_lock_irqsave(&dwc
->lock
, flags
);
1409 dwc
->is_selfpowered
= !!is_selfpowered
;
1410 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1415 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1420 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1422 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1423 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1424 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1427 if (dwc
->revision
>= DWC3_REVISION_194A
)
1428 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1429 reg
|= DWC3_DCTL_RUN_STOP
;
1431 if (dwc
->has_hibernation
)
1432 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1434 dwc
->pullups_connected
= true;
1436 reg
&= ~DWC3_DCTL_RUN_STOP
;
1438 if (dwc
->has_hibernation
&& !suspend
)
1439 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1441 dwc
->pullups_connected
= false;
1444 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1447 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1449 if (!(reg
& DWC3_DSTS_DEVCTRLHLT
))
1452 if (reg
& DWC3_DSTS_DEVCTRLHLT
)
1461 dev_vdbg(dwc
->dev
, "gadget %s data soft-%s\n",
1463 ? dwc
->gadget_driver
->function
: "no-function",
1464 is_on
? "connect" : "disconnect");
1469 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1471 struct dwc3
*dwc
= gadget_to_dwc(g
);
1472 unsigned long flags
;
1477 spin_lock_irqsave(&dwc
->lock
, flags
);
1478 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1479 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1484 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1488 /* Enable all but Start and End of Frame IRQs */
1489 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1490 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1491 DWC3_DEVTEN_CMDCMPLTEN
|
1492 DWC3_DEVTEN_ERRTICERREN
|
1493 DWC3_DEVTEN_WKUPEVTEN
|
1494 DWC3_DEVTEN_ULSTCNGEN
|
1495 DWC3_DEVTEN_CONNECTDONEEN
|
1496 DWC3_DEVTEN_USBRSTEN
|
1497 DWC3_DEVTEN_DISCONNEVTEN
);
1499 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1502 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1504 /* mask all interrupts */
1505 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1508 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1509 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1511 static int dwc3_gadget_start(struct usb_gadget
*g
,
1512 struct usb_gadget_driver
*driver
)
1514 struct dwc3
*dwc
= gadget_to_dwc(g
);
1515 struct dwc3_ep
*dep
;
1516 unsigned long flags
;
1521 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
1522 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1523 IRQF_SHARED
, "dwc3", dwc
);
1525 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1530 spin_lock_irqsave(&dwc
->lock
, flags
);
1532 if (dwc
->gadget_driver
) {
1533 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1535 dwc
->gadget_driver
->driver
.name
);
1540 dwc
->gadget_driver
= driver
;
1542 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1543 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1546 * WORKAROUND: DWC3 revision < 2.20a have an issue
1547 * which would cause metastability state on Run/Stop
1548 * bit if we try to force the IP to USB2-only mode.
1550 * Because of that, we cannot configure the IP to any
1551 * speed other than the SuperSpeed
1555 * STAR#9000525659: Clock Domain Crossing on DCTL in
1558 if (dwc
->revision
< DWC3_REVISION_220A
) {
1559 reg
|= DWC3_DCFG_SUPERSPEED
;
1561 switch (dwc
->maximum_speed
) {
1563 reg
|= DWC3_DSTS_LOWSPEED
;
1565 case USB_SPEED_FULL
:
1566 reg
|= DWC3_DSTS_FULLSPEED1
;
1568 case USB_SPEED_HIGH
:
1569 reg
|= DWC3_DSTS_HIGHSPEED
;
1571 case USB_SPEED_SUPER
: /* FALLTHROUGH */
1572 case USB_SPEED_UNKNOWN
: /* FALTHROUGH */
1574 reg
|= DWC3_DSTS_SUPERSPEED
;
1577 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1579 dwc
->start_config_issued
= false;
1581 /* Start with SuperSpeed Default */
1582 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1585 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1588 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1593 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1596 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1600 /* begin to receive SETUP packets */
1601 dwc
->ep0state
= EP0_SETUP_PHASE
;
1602 dwc3_ep0_out_start(dwc
);
1604 dwc3_gadget_enable_irq(dwc
);
1606 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1611 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1614 dwc
->gadget_driver
= NULL
;
1617 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1625 static int dwc3_gadget_stop(struct usb_gadget
*g
,
1626 struct usb_gadget_driver
*driver
)
1628 struct dwc3
*dwc
= gadget_to_dwc(g
);
1629 unsigned long flags
;
1632 spin_lock_irqsave(&dwc
->lock
, flags
);
1634 dwc3_gadget_disable_irq(dwc
);
1635 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1636 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1638 dwc
->gadget_driver
= NULL
;
1640 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1642 irq
= platform_get_irq(to_platform_device(dwc
->dev
), 0);
1648 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1649 .get_frame
= dwc3_gadget_get_frame
,
1650 .wakeup
= dwc3_gadget_wakeup
,
1651 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1652 .pullup
= dwc3_gadget_pullup
,
1653 .udc_start
= dwc3_gadget_start
,
1654 .udc_stop
= dwc3_gadget_stop
,
1657 /* -------------------------------------------------------------------------- */
1659 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1660 u8 num
, u32 direction
)
1662 struct dwc3_ep
*dep
;
1665 for (i
= 0; i
< num
; i
++) {
1666 u8 epnum
= (i
<< 1) | (!!direction
);
1668 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1673 dep
->number
= epnum
;
1674 dep
->direction
= !!direction
;
1675 dwc
->eps
[epnum
] = dep
;
1677 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1678 (epnum
& 1) ? "in" : "out");
1680 dep
->endpoint
.name
= dep
->name
;
1682 dev_vdbg(dwc
->dev
, "initializing %s\n", dep
->name
);
1684 if (epnum
== 0 || epnum
== 1) {
1685 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1686 dep
->endpoint
.maxburst
= 1;
1687 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1689 dwc
->gadget
.ep0
= &dep
->endpoint
;
1693 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1694 dep
->endpoint
.max_streams
= 15;
1695 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1696 list_add_tail(&dep
->endpoint
.ep_list
,
1697 &dwc
->gadget
.ep_list
);
1699 ret
= dwc3_alloc_trb_pool(dep
);
1704 INIT_LIST_HEAD(&dep
->request_list
);
1705 INIT_LIST_HEAD(&dep
->req_queued
);
1711 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1715 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1717 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1719 dev_vdbg(dwc
->dev
, "failed to allocate OUT endpoints\n");
1723 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1725 dev_vdbg(dwc
->dev
, "failed to allocate IN endpoints\n");
1732 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1734 struct dwc3_ep
*dep
;
1737 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1738 dep
= dwc
->eps
[epnum
];
1742 * Physical endpoints 0 and 1 are special; they form the
1743 * bi-directional USB endpoint 0.
1745 * For those two physical endpoints, we don't allocate a TRB
1746 * pool nor do we add them the endpoints list. Due to that, we
1747 * shouldn't do these two operations otherwise we would end up
1748 * with all sorts of bugs when removing dwc3.ko.
1750 if (epnum
!= 0 && epnum
!= 1) {
1751 dwc3_free_trb_pool(dep
);
1752 list_del(&dep
->endpoint
.ep_list
);
1759 /* -------------------------------------------------------------------------- */
1761 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1762 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
1763 const struct dwc3_event_depevt
*event
, int status
)
1766 unsigned int s_pkt
= 0;
1767 unsigned int trb_status
;
1769 trace_dwc3_complete_trb(dep
, trb
);
1771 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
1773 * We continue despite the error. There is not much we
1774 * can do. If we don't clean it up we loop forever. If
1775 * we skip the TRB then it gets overwritten after a
1776 * while since we use them in a ring buffer. A BUG()
1777 * would help. Lets hope that if this occurs, someone
1778 * fixes the root cause instead of looking away :)
1780 dev_err(dwc
->dev
, "%s's TRB (%p) still owned by HW\n",
1782 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
1784 if (dep
->direction
) {
1786 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
1787 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
1788 dev_dbg(dwc
->dev
, "incomplete IN transfer %s\n",
1791 * If missed isoc occurred and there is
1792 * no request queued then issue END
1793 * TRANSFER, so that core generates
1794 * next xfernotready and we will issue
1795 * a fresh START TRANSFER.
1796 * If there are still queued request
1797 * then wait, do not issue either END
1798 * or UPDATE TRANSFER, just attach next
1799 * request in request_list during
1800 * giveback.If any future queued request
1801 * is successfully transferred then we
1802 * will issue UPDATE TRANSFER for all
1803 * request in the request_list.
1805 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
1807 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
1809 status
= -ECONNRESET
;
1812 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
1815 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
1820 * We assume here we will always receive the entire data block
1821 * which we should receive. Meaning, if we program RX to
1822 * receive 4K but we receive only 2K, we assume that's all we
1823 * should receive and we simply bounce the request back to the
1824 * gadget driver for further processing.
1826 req
->request
.actual
+= req
->request
.length
- count
;
1829 if ((event
->status
& DEPEVT_STATUS_LST
) &&
1830 (trb
->ctrl
& (DWC3_TRB_CTRL_LST
|
1831 DWC3_TRB_CTRL_HWO
)))
1833 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
1834 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
1839 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1840 const struct dwc3_event_depevt
*event
, int status
)
1842 struct dwc3_request
*req
;
1843 struct dwc3_trb
*trb
;
1849 req
= next_request(&dep
->req_queued
);
1856 slot
= req
->start_slot
+ i
;
1857 if ((slot
== DWC3_TRB_NUM
- 1) &&
1858 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
))
1860 slot
%= DWC3_TRB_NUM
;
1861 trb
= &dep
->trb_pool
[slot
];
1863 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
1867 }while (++i
< req
->request
.num_mapped_sgs
);
1869 dwc3_gadget_giveback(dep
, req
, status
);
1875 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
1876 list_empty(&dep
->req_queued
)) {
1877 if (list_empty(&dep
->request_list
)) {
1879 * If there is no entry in request list then do
1880 * not issue END TRANSFER now. Just set PENDING
1881 * flag, so that END TRANSFER is issued when an
1882 * entry is added into request list.
1884 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
1886 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1887 dep
->flags
= DWC3_EP_ENABLED
;
1895 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
1896 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1898 unsigned status
= 0;
1901 if (event
->status
& DEPEVT_STATUS_BUSERR
)
1902 status
= -ECONNRESET
;
1904 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
1906 dep
->flags
&= ~DWC3_EP_BUSY
;
1909 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1910 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1912 if (dwc
->revision
< DWC3_REVISION_183A
) {
1916 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
1919 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1922 if (!list_empty(&dep
->req_queued
))
1926 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1928 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1934 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
1935 const struct dwc3_event_depevt
*event
)
1937 struct dwc3_ep
*dep
;
1938 u8 epnum
= event
->endpoint_number
;
1940 dep
= dwc
->eps
[epnum
];
1942 if (!(dep
->flags
& DWC3_EP_ENABLED
))
1945 if (epnum
== 0 || epnum
== 1) {
1946 dwc3_ep0_interrupt(dwc
, event
);
1950 switch (event
->endpoint_event
) {
1951 case DWC3_DEPEVT_XFERCOMPLETE
:
1952 dep
->resource_index
= 0;
1954 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1955 dev_dbg(dwc
->dev
, "%s is an Isochronous endpoint\n",
1960 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
1962 case DWC3_DEPEVT_XFERINPROGRESS
:
1963 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
1965 case DWC3_DEPEVT_XFERNOTREADY
:
1966 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1967 dwc3_gadget_start_isoc(dwc
, dep
, event
);
1971 dev_vdbg(dwc
->dev
, "%s: reason %s\n",
1972 dep
->name
, event
->status
&
1973 DEPEVT_STATUS_TRANSFER_ACTIVE
1975 : "Transfer Not Active");
1977 ret
= __dwc3_gadget_kick_transfer(dep
, 0, 1);
1978 if (!ret
|| ret
== -EBUSY
)
1981 dev_dbg(dwc
->dev
, "%s: failed to kick transfers\n",
1986 case DWC3_DEPEVT_STREAMEVT
:
1987 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
1988 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
1993 switch (event
->status
) {
1994 case DEPEVT_STREAMEVT_FOUND
:
1995 dev_vdbg(dwc
->dev
, "Stream %d found and started\n",
1999 case DEPEVT_STREAMEVT_NOTFOUND
:
2002 dev_dbg(dwc
->dev
, "Couldn't find suitable stream\n");
2005 case DWC3_DEPEVT_RXTXFIFOEVT
:
2006 dev_dbg(dwc
->dev
, "%s FIFO Overrun\n", dep
->name
);
2008 case DWC3_DEPEVT_EPCMDCMPLT
:
2009 dev_vdbg(dwc
->dev
, "Endpoint Command Complete\n");
2014 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2016 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2017 spin_unlock(&dwc
->lock
);
2018 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2019 spin_lock(&dwc
->lock
);
2023 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2025 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2026 spin_unlock(&dwc
->lock
);
2027 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2028 spin_lock(&dwc
->lock
);
2032 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2034 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2035 spin_unlock(&dwc
->lock
);
2036 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2037 spin_lock(&dwc
->lock
);
2041 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2043 struct dwc3_ep
*dep
;
2044 struct dwc3_gadget_ep_cmd_params params
;
2048 dep
= dwc
->eps
[epnum
];
2050 if (!dep
->resource_index
)
2054 * NOTICE: We are violating what the Databook says about the
2055 * EndTransfer command. Ideally we would _always_ wait for the
2056 * EndTransfer Command Completion IRQ, but that's causing too
2057 * much trouble synchronizing between us and gadget driver.
2059 * We have discussed this with the IP Provider and it was
2060 * suggested to giveback all requests here, but give HW some
2061 * extra time to synchronize with the interconnect. We're using
2062 * an arbitraty 100us delay for that.
2064 * Note also that a similar handling was tested by Synopsys
2065 * (thanks a lot Paul) and nothing bad has come out of it.
2066 * In short, what we're doing is:
2068 * - Issue EndTransfer WITH CMDIOC bit set
2072 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2073 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2074 cmd
|= DWC3_DEPCMD_CMDIOC
;
2075 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2076 memset(¶ms
, 0, sizeof(params
));
2077 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
, cmd
, ¶ms
);
2079 dep
->resource_index
= 0;
2080 dep
->flags
&= ~DWC3_EP_BUSY
;
2084 static void dwc3_stop_active_transfers(struct dwc3
*dwc
)
2088 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2089 struct dwc3_ep
*dep
;
2091 dep
= dwc
->eps
[epnum
];
2095 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2098 dwc3_remove_requests(dwc
, dep
);
2102 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2106 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2107 struct dwc3_ep
*dep
;
2108 struct dwc3_gadget_ep_cmd_params params
;
2111 dep
= dwc
->eps
[epnum
];
2115 if (!(dep
->flags
& DWC3_EP_STALL
))
2118 dep
->flags
&= ~DWC3_EP_STALL
;
2120 memset(¶ms
, 0, sizeof(params
));
2121 ret
= dwc3_send_gadget_ep_cmd(dwc
, dep
->number
,
2122 DWC3_DEPCMD_CLEARSTALL
, ¶ms
);
2127 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2131 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2132 reg
&= ~DWC3_DCTL_INITU1ENA
;
2133 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2135 reg
&= ~DWC3_DCTL_INITU2ENA
;
2136 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2138 dwc3_disconnect_gadget(dwc
);
2139 dwc
->start_config_issued
= false;
2141 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2142 dwc
->setup_packet_pending
= false;
2145 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2150 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2151 * would cause a missing Disconnect Event if there's a
2152 * pending Setup Packet in the FIFO.
2154 * There's no suggested workaround on the official Bug
2155 * report, which states that "unless the driver/application
2156 * is doing any special handling of a disconnect event,
2157 * there is no functional issue".
2159 * Unfortunately, it turns out that we _do_ some special
2160 * handling of a disconnect event, namely complete all
2161 * pending transfers, notify gadget driver of the
2162 * disconnection, and so on.
2164 * Our suggested workaround is to follow the Disconnect
2165 * Event steps here, instead, based on a setup_packet_pending
2166 * flag. Such flag gets set whenever we have a XferNotReady
2167 * event on EP0 and gets cleared on XferComplete for the
2172 * STAR#9000466709: RTL: Device : Disconnect event not
2173 * generated if setup packet pending in FIFO
2175 if (dwc
->revision
< DWC3_REVISION_188A
) {
2176 if (dwc
->setup_packet_pending
)
2177 dwc3_gadget_disconnect_interrupt(dwc
);
2180 /* after reset -> Default State */
2181 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_DEFAULT
);
2183 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
)
2184 dwc3_disconnect_gadget(dwc
);
2186 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2187 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2188 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2189 dwc
->test_mode
= false;
2191 dwc3_stop_active_transfers(dwc
);
2192 dwc3_clear_stall_all_ep(dwc
);
2193 dwc
->start_config_issued
= false;
2195 /* Reset device address to zero */
2196 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2197 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2198 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2201 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2204 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2207 * We change the clock only at SS but I dunno why I would want to do
2208 * this. Maybe it becomes part of the power saving plan.
2211 if (speed
!= DWC3_DSTS_SUPERSPEED
)
2215 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2216 * each time on Connect Done.
2221 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2222 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2223 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2226 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2228 struct dwc3_ep
*dep
;
2233 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2234 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2237 dwc3_update_ram_clk_sel(dwc
, speed
);
2240 case DWC3_DCFG_SUPERSPEED
:
2242 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2243 * would cause a missing USB3 Reset event.
2245 * In such situations, we should force a USB3 Reset
2246 * event by calling our dwc3_gadget_reset_interrupt()
2251 * STAR#9000483510: RTL: SS : USB3 reset event may
2252 * not be generated always when the link enters poll
2254 if (dwc
->revision
< DWC3_REVISION_190A
)
2255 dwc3_gadget_reset_interrupt(dwc
);
2257 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2258 dwc
->gadget
.ep0
->maxpacket
= 512;
2259 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2261 case DWC3_DCFG_HIGHSPEED
:
2262 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2263 dwc
->gadget
.ep0
->maxpacket
= 64;
2264 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2266 case DWC3_DCFG_FULLSPEED2
:
2267 case DWC3_DCFG_FULLSPEED1
:
2268 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2269 dwc
->gadget
.ep0
->maxpacket
= 64;
2270 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2272 case DWC3_DCFG_LOWSPEED
:
2273 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2274 dwc
->gadget
.ep0
->maxpacket
= 8;
2275 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2279 /* Enable USB2 LPM Capability */
2281 if ((dwc
->revision
> DWC3_REVISION_194A
)
2282 && (speed
!= DWC3_DCFG_SUPERSPEED
)) {
2283 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2284 reg
|= DWC3_DCFG_LPM_CAP
;
2285 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2287 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2288 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2291 * TODO: This should be configurable. For now using
2292 * maximum allowed HIRD threshold value of 0b1100
2294 reg
|= DWC3_DCTL_HIRD_THRES(12);
2296 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2298 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2299 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2300 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2304 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2307 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2312 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2315 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2320 * Configure PHY via GUSB3PIPECTLn if required.
2322 * Update GTXFIFOSIZn
2324 * In both cases reset values should be sufficient.
2328 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2331 * TODO take core out of low power mode when that's
2335 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2338 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2339 unsigned int evtinfo
)
2341 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2342 unsigned int pwropt
;
2345 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2346 * Hibernation mode enabled which would show up when device detects
2347 * host-initiated U3 exit.
2349 * In that case, device will generate a Link State Change Interrupt
2350 * from U3 to RESUME which is only necessary if Hibernation is
2353 * There are no functional changes due to such spurious event and we
2354 * just need to ignore it.
2358 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2361 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2362 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2363 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2364 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2365 (next
== DWC3_LINK_STATE_RESUME
)) {
2366 dev_vdbg(dwc
->dev
, "ignoring transition U3 -> Resume\n");
2372 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2373 * on the link partner, the USB session might do multiple entry/exit
2374 * of low power states before a transfer takes place.
2376 * Due to this problem, we might experience lower throughput. The
2377 * suggested workaround is to disable DCTL[12:9] bits if we're
2378 * transitioning from U1/U2 to U0 and enable those bits again
2379 * after a transfer completes and there are no pending transfers
2380 * on any of the enabled endpoints.
2382 * This is the first half of that workaround.
2386 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2387 * core send LGO_Ux entering U0
2389 if (dwc
->revision
< DWC3_REVISION_183A
) {
2390 if (next
== DWC3_LINK_STATE_U0
) {
2394 switch (dwc
->link_state
) {
2395 case DWC3_LINK_STATE_U1
:
2396 case DWC3_LINK_STATE_U2
:
2397 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2398 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2399 | DWC3_DCTL_ACCEPTU2ENA
2400 | DWC3_DCTL_INITU1ENA
2401 | DWC3_DCTL_ACCEPTU1ENA
);
2404 dwc
->u1u2
= reg
& u1u2
;
2408 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2418 case DWC3_LINK_STATE_U1
:
2419 if (dwc
->speed
== USB_SPEED_SUPER
)
2420 dwc3_suspend_gadget(dwc
);
2422 case DWC3_LINK_STATE_U2
:
2423 case DWC3_LINK_STATE_U3
:
2424 dwc3_suspend_gadget(dwc
);
2426 case DWC3_LINK_STATE_RESUME
:
2427 dwc3_resume_gadget(dwc
);
2434 dwc
->link_state
= next
;
2437 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2438 unsigned int evtinfo
)
2440 unsigned int is_ss
= evtinfo
& BIT(4);
2443 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2444 * have a known issue which can cause USB CV TD.9.23 to fail
2447 * Because of this issue, core could generate bogus hibernation
2448 * events which SW needs to ignore.
2452 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2453 * Device Fallback from SuperSpeed
2455 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2458 /* enter hibernation here */
2461 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2462 const struct dwc3_event_devt
*event
)
2464 switch (event
->type
) {
2465 case DWC3_DEVICE_EVENT_DISCONNECT
:
2466 dwc3_gadget_disconnect_interrupt(dwc
);
2468 case DWC3_DEVICE_EVENT_RESET
:
2469 dwc3_gadget_reset_interrupt(dwc
);
2471 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2472 dwc3_gadget_conndone_interrupt(dwc
);
2474 case DWC3_DEVICE_EVENT_WAKEUP
:
2475 dwc3_gadget_wakeup_interrupt(dwc
);
2477 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2478 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2479 "unexpected hibernation event\n"))
2482 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2484 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2485 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2487 case DWC3_DEVICE_EVENT_EOPF
:
2488 dev_vdbg(dwc
->dev
, "End of Periodic Frame\n");
2490 case DWC3_DEVICE_EVENT_SOF
:
2491 dev_vdbg(dwc
->dev
, "Start of Periodic Frame\n");
2493 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2494 dev_vdbg(dwc
->dev
, "Erratic Error\n");
2496 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2497 dev_vdbg(dwc
->dev
, "Command Complete\n");
2499 case DWC3_DEVICE_EVENT_OVERFLOW
:
2500 dev_vdbg(dwc
->dev
, "Overflow\n");
2503 dev_dbg(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2507 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2508 const union dwc3_event
*event
)
2510 trace_dwc3_event(event
->raw
);
2512 /* Endpoint IRQ, handle it and return early */
2513 if (event
->type
.is_devspec
== 0) {
2515 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2518 switch (event
->type
.type
) {
2519 case DWC3_EVENT_TYPE_DEV
:
2520 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2522 /* REVISIT what to do with Carkit and I2C events ? */
2524 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2528 static irqreturn_t
dwc3_process_event_buf(struct dwc3
*dwc
, u32 buf
)
2530 struct dwc3_event_buffer
*evt
;
2531 irqreturn_t ret
= IRQ_NONE
;
2535 evt
= dwc
->ev_buffs
[buf
];
2538 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2542 union dwc3_event event
;
2544 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2546 dwc3_process_event_entry(dwc
, &event
);
2549 * FIXME we wrap around correctly to the next entry as
2550 * almost all entries are 4 bytes in size. There is one
2551 * entry which has 12 bytes which is a regular entry
2552 * followed by 8 bytes data. ATM I don't know how
2553 * things are organized if we get next to the a
2554 * boundary so I worry about that once we try to handle
2557 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2560 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(buf
), 4);
2564 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2567 /* Unmask interrupt */
2568 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(buf
));
2569 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2570 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(buf
), reg
);
2575 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
)
2577 struct dwc3
*dwc
= _dwc
;
2578 unsigned long flags
;
2579 irqreturn_t ret
= IRQ_NONE
;
2582 spin_lock_irqsave(&dwc
->lock
, flags
);
2584 for (i
= 0; i
< dwc
->num_event_buffers
; i
++)
2585 ret
|= dwc3_process_event_buf(dwc
, i
);
2587 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2592 static irqreturn_t
dwc3_check_event_buf(struct dwc3
*dwc
, u32 buf
)
2594 struct dwc3_event_buffer
*evt
;
2598 evt
= dwc
->ev_buffs
[buf
];
2600 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(buf
));
2601 count
&= DWC3_GEVNTCOUNT_MASK
;
2606 evt
->flags
|= DWC3_EVENT_PENDING
;
2608 /* Mask interrupt */
2609 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(buf
));
2610 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2611 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(buf
), reg
);
2613 return IRQ_WAKE_THREAD
;
2616 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
)
2618 struct dwc3
*dwc
= _dwc
;
2620 irqreturn_t ret
= IRQ_NONE
;
2622 spin_lock(&dwc
->lock
);
2624 for (i
= 0; i
< dwc
->num_event_buffers
; i
++) {
2627 status
= dwc3_check_event_buf(dwc
, i
);
2628 if (status
== IRQ_WAKE_THREAD
)
2632 spin_unlock(&dwc
->lock
);
2638 * dwc3_gadget_init - Initializes gadget related registers
2639 * @dwc: pointer to our controller context structure
2641 * Returns 0 on success otherwise negative errno.
2643 int dwc3_gadget_init(struct dwc3
*dwc
)
2647 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2648 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2649 if (!dwc
->ctrl_req
) {
2650 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2655 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2656 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2657 if (!dwc
->ep0_trb
) {
2658 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2663 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2664 if (!dwc
->setup_buf
) {
2669 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2670 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2672 if (!dwc
->ep0_bounce
) {
2673 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
2678 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
2679 dwc
->gadget
.max_speed
= USB_SPEED_SUPER
;
2680 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2681 dwc
->gadget
.sg_supported
= true;
2682 dwc
->gadget
.name
= "dwc3-gadget";
2685 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2688 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
2691 * REVISIT: Here we should clear all pending IRQs to be
2692 * sure we're starting from a well known location.
2695 ret
= dwc3_gadget_init_endpoints(dwc
);
2699 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
2701 dev_err(dwc
->dev
, "failed to register udc\n");
2708 dwc3_gadget_free_endpoints(dwc
);
2709 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2710 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2713 kfree(dwc
->setup_buf
);
2716 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2717 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2720 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2721 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2727 /* -------------------------------------------------------------------------- */
2729 void dwc3_gadget_exit(struct dwc3
*dwc
)
2731 usb_del_gadget_udc(&dwc
->gadget
);
2733 dwc3_gadget_free_endpoints(dwc
);
2735 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
2736 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
2738 kfree(dwc
->setup_buf
);
2740 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
),
2741 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
2743 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2744 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
2747 int dwc3_gadget_prepare(struct dwc3
*dwc
)
2749 if (dwc
->pullups_connected
) {
2750 dwc3_gadget_disable_irq(dwc
);
2751 dwc3_gadget_run_stop(dwc
, true, true);
2757 void dwc3_gadget_complete(struct dwc3
*dwc
)
2759 if (dwc
->pullups_connected
) {
2760 dwc3_gadget_enable_irq(dwc
);
2761 dwc3_gadget_run_stop(dwc
, true, false);
2765 int dwc3_gadget_suspend(struct dwc3
*dwc
)
2767 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
2768 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
2770 dwc
->dcfg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2775 int dwc3_gadget_resume(struct dwc3
*dwc
)
2777 struct dwc3_ep
*dep
;
2780 /* Start with SuperSpeed Default */
2781 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2784 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
2790 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
2795 /* begin to receive SETUP packets */
2796 dwc
->ep0state
= EP0_SETUP_PHASE
;
2797 dwc3_ep0_out_start(dwc
);
2799 dwc3_writel(dwc
->regs
, DWC3_DCFG
, dwc
->dcfg
);
2804 __dwc3_gadget_ep_disable(dwc
->eps
[0]);