2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/timer.h>
27 #include <linux/list.h>
28 #include <linux/interrupt.h>
29 #include <linux/proc_fs.h>
31 #include <linux/moduleparam.h>
32 #include <linux/platform_device.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/otg.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/err.h>
39 #include <linux/prefetch.h>
42 #include <asm/byteorder.h>
44 #include <asm/unaligned.h>
45 #include <asm/mach-types.h>
55 /* bulk DMA seems to be behaving for both IN and OUT */
61 #define DRIVER_DESC "OMAP UDC driver"
62 #define DRIVER_VERSION "4 October 2004"
65 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
66 * D+ pullup to allow enumeration. That's too early for the gadget
67 * framework to use from usb_endpoint_enable(), which happens after
68 * enumeration as part of activating an interface. (But if we add an
69 * optional new "UDC not yet running" state to the gadget driver model,
70 * even just during driver binding, the endpoint autoconfig logic is the
71 * natural spot to manufacture new endpoints.)
73 * So instead of using endpoint enable calls to control the hardware setup,
74 * this driver defines a "fifo mode" parameter. It's used during driver
75 * initialization to choose among a set of pre-defined endpoint configs.
76 * See omap_udc_setup() for available modes, or to add others. That code
77 * lives in an init section, so use this driver as a module if you need
78 * to change the fifo mode after the kernel boots.
80 * Gadget drivers normally ignore endpoints they don't care about, and
81 * won't include them in configuration descriptors. That means only
82 * misbehaving hosts would even notice they exist.
85 static unsigned fifo_mode
= 3;
87 static unsigned fifo_mode
;
90 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
91 * boot parameter "omap_udc:fifo_mode=42"
93 module_param(fifo_mode
, uint
, 0);
94 MODULE_PARM_DESC(fifo_mode
, "endpoint configuration");
97 static bool use_dma
= 1;
99 /* "modprobe omap_udc use_dma=y", or else as a kernel
100 * boot parameter "omap_udc:use_dma=y"
102 module_param(use_dma
, bool, 0);
103 MODULE_PARM_DESC(use_dma
, "enable/disable DMA");
106 /* save a bit of code */
108 #endif /* !USE_DMA */
111 static const char driver_name
[] = "omap_udc";
112 static const char driver_desc
[] = DRIVER_DESC
;
114 /*-------------------------------------------------------------------------*/
116 /* there's a notion of "current endpoint" for modifying endpoint
117 * state, and PIO access to its FIFO.
120 static void use_ep(struct omap_ep
*ep
, u16 select
)
122 u16 num
= ep
->bEndpointAddress
& 0x0f;
124 if (ep
->bEndpointAddress
& USB_DIR_IN
)
126 omap_writew(num
| select
, UDC_EP_NUM
);
127 /* when select, MUST deselect later !! */
130 static inline void deselect_ep(void)
134 w
= omap_readw(UDC_EP_NUM
);
136 omap_writew(w
, UDC_EP_NUM
);
137 /* 6 wait states before TX will happen */
140 static void dma_channel_claim(struct omap_ep
*ep
, unsigned preferred
);
142 /*-------------------------------------------------------------------------*/
144 static int omap_ep_enable(struct usb_ep
*_ep
,
145 const struct usb_endpoint_descriptor
*desc
)
147 struct omap_ep
*ep
= container_of(_ep
, struct omap_ep
, ep
);
148 struct omap_udc
*udc
;
152 /* catch various bogus parameters */
154 || desc
->bDescriptorType
!= USB_DT_ENDPOINT
155 || ep
->bEndpointAddress
!= desc
->bEndpointAddress
156 || ep
->maxpacket
< usb_endpoint_maxp(desc
)) {
157 DBG("%s, bad ep or descriptor\n", __func__
);
160 maxp
= usb_endpoint_maxp(desc
);
161 if ((desc
->bmAttributes
== USB_ENDPOINT_XFER_BULK
162 && maxp
!= ep
->maxpacket
)
163 || usb_endpoint_maxp(desc
) > ep
->maxpacket
164 || !desc
->wMaxPacketSize
) {
165 DBG("%s, bad %s maxpacket\n", __func__
, _ep
->name
);
170 if ((desc
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
171 && desc
->bInterval
!= 1)) {
172 /* hardware wants period = 1; USB allows 2^(Interval-1) */
173 DBG("%s, unsupported ISO period %dms\n", _ep
->name
,
174 1 << (desc
->bInterval
- 1));
178 if (desc
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
179 DBG("%s, ISO nyet\n", _ep
->name
);
184 /* xfer types must match, except that interrupt ~= bulk */
185 if (ep
->bmAttributes
!= desc
->bmAttributes
186 && ep
->bmAttributes
!= USB_ENDPOINT_XFER_BULK
187 && desc
->bmAttributes
!= USB_ENDPOINT_XFER_INT
) {
188 DBG("%s, %s type mismatch\n", __func__
, _ep
->name
);
193 if (!udc
->driver
|| udc
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
194 DBG("%s, bogus device state\n", __func__
);
198 spin_lock_irqsave(&udc
->lock
, flags
);
203 ep
->ep
.maxpacket
= maxp
;
205 /* set endpoint to initial state */
209 use_ep(ep
, UDC_EP_SEL
);
210 omap_writew(udc
->clr_halt
, UDC_CTRL
);
214 if (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
)
215 list_add(&ep
->iso
, &udc
->iso
);
217 /* maybe assign a DMA channel to this endpoint */
218 if (use_dma
&& desc
->bmAttributes
== USB_ENDPOINT_XFER_BULK
)
219 /* FIXME ISO can dma, but prefers first channel */
220 dma_channel_claim(ep
, 0);
222 /* PIO OUT may RX packets */
223 if (desc
->bmAttributes
!= USB_ENDPOINT_XFER_ISOC
225 && !(ep
->bEndpointAddress
& USB_DIR_IN
)) {
226 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
227 ep
->ackwait
= 1 + ep
->double_buf
;
230 spin_unlock_irqrestore(&udc
->lock
, flags
);
231 VDBG("%s enabled\n", _ep
->name
);
235 static void nuke(struct omap_ep
*, int status
);
237 static int omap_ep_disable(struct usb_ep
*_ep
)
239 struct omap_ep
*ep
= container_of(_ep
, struct omap_ep
, ep
);
242 if (!_ep
|| !ep
->ep
.desc
) {
243 DBG("%s, %s not enabled\n", __func__
,
244 _ep
? ep
->ep
.name
: NULL
);
248 spin_lock_irqsave(&ep
->udc
->lock
, flags
);
250 nuke(ep
, -ESHUTDOWN
);
251 ep
->ep
.maxpacket
= ep
->maxpacket
;
253 omap_writew(UDC_SET_HALT
, UDC_CTRL
);
254 list_del_init(&ep
->iso
);
255 del_timer(&ep
->timer
);
257 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
259 VDBG("%s disabled\n", _ep
->name
);
263 /*-------------------------------------------------------------------------*/
265 static struct usb_request
*
266 omap_alloc_request(struct usb_ep
*ep
, gfp_t gfp_flags
)
268 struct omap_req
*req
;
270 req
= kzalloc(sizeof(*req
), gfp_flags
);
274 INIT_LIST_HEAD(&req
->queue
);
280 omap_free_request(struct usb_ep
*ep
, struct usb_request
*_req
)
282 struct omap_req
*req
= container_of(_req
, struct omap_req
, req
);
287 /*-------------------------------------------------------------------------*/
290 done(struct omap_ep
*ep
, struct omap_req
*req
, int status
)
292 struct omap_udc
*udc
= ep
->udc
;
293 unsigned stopped
= ep
->stopped
;
295 list_del_init(&req
->queue
);
297 if (req
->req
.status
== -EINPROGRESS
)
298 req
->req
.status
= status
;
300 status
= req
->req
.status
;
302 if (use_dma
&& ep
->has_dma
)
303 usb_gadget_unmap_request(&udc
->gadget
, &req
->req
,
304 (ep
->bEndpointAddress
& USB_DIR_IN
));
307 if (status
&& status
!= -ESHUTDOWN
)
309 VDBG("complete %s req %p stat %d len %u/%u\n",
310 ep
->ep
.name
, &req
->req
, status
,
311 req
->req
.actual
, req
->req
.length
);
313 /* don't modify queue heads during completion callback */
315 spin_unlock(&ep
->udc
->lock
);
316 req
->req
.complete(&ep
->ep
, &req
->req
);
317 spin_lock(&ep
->udc
->lock
);
318 ep
->stopped
= stopped
;
321 /*-------------------------------------------------------------------------*/
323 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
324 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
326 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
327 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
330 write_packet(u8
*buf
, struct omap_req
*req
, unsigned max
)
335 len
= min(req
->req
.length
- req
->req
.actual
, max
);
336 req
->req
.actual
+= len
;
339 if (likely((((int)buf
) & 1) == 0)) {
342 omap_writew(*wp
++, UDC_DATA
);
348 omap_writeb(*buf
++, UDC_DATA
);
352 /* FIXME change r/w fifo calling convention */
355 /* return: 0 = still running, 1 = completed, negative = errno */
356 static int write_fifo(struct omap_ep
*ep
, struct omap_req
*req
)
363 buf
= req
->req
.buf
+ req
->req
.actual
;
366 /* PIO-IN isn't double buffered except for iso */
367 ep_stat
= omap_readw(UDC_STAT_FLG
);
368 if (ep_stat
& UDC_FIFO_UNWRITABLE
)
371 count
= ep
->ep
.maxpacket
;
372 count
= write_packet(buf
, req
, count
);
373 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
376 /* last packet is often short (sometimes a zlp) */
377 if (count
!= ep
->ep
.maxpacket
)
379 else if (req
->req
.length
== req
->req
.actual
385 /* NOTE: requests complete when all IN data is in a
386 * FIFO (or sometimes later, if a zlp was needed).
387 * Use usb_ep_fifo_status() where needed.
395 read_packet(u8
*buf
, struct omap_req
*req
, unsigned avail
)
400 len
= min(req
->req
.length
- req
->req
.actual
, avail
);
401 req
->req
.actual
+= len
;
404 if (likely((((int)buf
) & 1) == 0)) {
407 *wp
++ = omap_readw(UDC_DATA
);
413 *buf
++ = omap_readb(UDC_DATA
);
417 /* return: 0 = still running, 1 = queue empty, negative = errno */
418 static int read_fifo(struct omap_ep
*ep
, struct omap_req
*req
)
421 unsigned count
, avail
;
424 buf
= req
->req
.buf
+ req
->req
.actual
;
428 u16 ep_stat
= omap_readw(UDC_STAT_FLG
);
431 if (ep_stat
& FIFO_EMPTY
) {
436 if (ep_stat
& UDC_EP_HALTED
)
439 if (ep_stat
& UDC_FIFO_FULL
)
440 avail
= ep
->ep
.maxpacket
;
442 avail
= omap_readw(UDC_RXFSTAT
);
443 ep
->fnf
= ep
->double_buf
;
445 count
= read_packet(buf
, req
, avail
);
447 /* partial packet reads may not be errors */
448 if (count
< ep
->ep
.maxpacket
) {
450 /* overflowed this request? flush extra data */
451 if (count
!= avail
) {
452 req
->req
.status
= -EOVERFLOW
;
455 omap_readw(UDC_DATA
);
457 } else if (req
->req
.length
== req
->req
.actual
)
462 if (!ep
->bEndpointAddress
)
471 /*-------------------------------------------------------------------------*/
473 static u16
dma_src_len(struct omap_ep
*ep
, dma_addr_t start
)
477 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
478 * the last transfer's bytecount by more than a FIFO's worth.
480 if (cpu_is_omap15xx())
483 end
= omap_get_dma_src_pos(ep
->lch
);
484 if (end
== ep
->dma_counter
)
487 end
|= start
& (0xffff << 16);
493 static u16
dma_dest_len(struct omap_ep
*ep
, dma_addr_t start
)
497 end
= omap_get_dma_dst_pos(ep
->lch
);
498 if (end
== ep
->dma_counter
)
501 end
|= start
& (0xffff << 16);
502 if (cpu_is_omap15xx())
510 /* Each USB transfer request using DMA maps to one or more DMA transfers.
511 * When DMA completion isn't request completion, the UDC continues with
512 * the next DMA transfer for that USB transfer.
515 static void next_in_dma(struct omap_ep
*ep
, struct omap_req
*req
)
518 unsigned length
= req
->req
.length
- req
->req
.actual
;
519 const int sync_mode
= cpu_is_omap15xx()
520 ? OMAP_DMA_SYNC_FRAME
521 : OMAP_DMA_SYNC_ELEMENT
;
524 /* measure length in either bytes or packets */
525 if ((cpu_is_omap16xx() && length
<= UDC_TXN_TSC
)
526 || (cpu_is_omap15xx() && length
< ep
->maxpacket
)) {
527 txdma_ctrl
= UDC_TXN_EOT
| length
;
528 omap_set_dma_transfer_params(ep
->lch
, OMAP_DMA_DATA_TYPE_S8
,
529 length
, 1, sync_mode
, dma_trigger
, 0);
531 length
= min(length
/ ep
->maxpacket
,
532 (unsigned) UDC_TXN_TSC
+ 1);
534 omap_set_dma_transfer_params(ep
->lch
, OMAP_DMA_DATA_TYPE_S16
,
535 ep
->ep
.maxpacket
>> 1, length
, sync_mode
,
537 length
*= ep
->maxpacket
;
539 omap_set_dma_src_params(ep
->lch
, OMAP_DMA_PORT_EMIFF
,
540 OMAP_DMA_AMODE_POST_INC
, req
->req
.dma
+ req
->req
.actual
,
543 omap_start_dma(ep
->lch
);
544 ep
->dma_counter
= omap_get_dma_src_pos(ep
->lch
);
545 w
= omap_readw(UDC_DMA_IRQ_EN
);
546 w
|= UDC_TX_DONE_IE(ep
->dma_channel
);
547 omap_writew(w
, UDC_DMA_IRQ_EN
);
548 omap_writew(UDC_TXN_START
| txdma_ctrl
, UDC_TXDMA(ep
->dma_channel
));
549 req
->dma_bytes
= length
;
552 static void finish_in_dma(struct omap_ep
*ep
, struct omap_req
*req
, int status
)
557 req
->req
.actual
+= req
->dma_bytes
;
559 /* return if this request needs to send data or zlp */
560 if (req
->req
.actual
< req
->req
.length
)
563 && req
->dma_bytes
!= 0
564 && (req
->req
.actual
% ep
->maxpacket
) == 0)
567 req
->req
.actual
+= dma_src_len(ep
, req
->req
.dma
571 omap_stop_dma(ep
->lch
);
572 w
= omap_readw(UDC_DMA_IRQ_EN
);
573 w
&= ~UDC_TX_DONE_IE(ep
->dma_channel
);
574 omap_writew(w
, UDC_DMA_IRQ_EN
);
575 done(ep
, req
, status
);
578 static void next_out_dma(struct omap_ep
*ep
, struct omap_req
*req
)
580 unsigned packets
= req
->req
.length
- req
->req
.actual
;
584 /* set up this DMA transfer, enable the fifo, start */
585 packets
/= ep
->ep
.maxpacket
;
586 packets
= min(packets
, (unsigned)UDC_RXN_TC
+ 1);
587 req
->dma_bytes
= packets
* ep
->ep
.maxpacket
;
588 omap_set_dma_transfer_params(ep
->lch
, OMAP_DMA_DATA_TYPE_S16
,
589 ep
->ep
.maxpacket
>> 1, packets
,
590 OMAP_DMA_SYNC_ELEMENT
,
592 omap_set_dma_dest_params(ep
->lch
, OMAP_DMA_PORT_EMIFF
,
593 OMAP_DMA_AMODE_POST_INC
, req
->req
.dma
+ req
->req
.actual
,
595 ep
->dma_counter
= omap_get_dma_dst_pos(ep
->lch
);
597 omap_writew(UDC_RXN_STOP
| (packets
- 1), UDC_RXDMA(ep
->dma_channel
));
598 w
= omap_readw(UDC_DMA_IRQ_EN
);
599 w
|= UDC_RX_EOT_IE(ep
->dma_channel
);
600 omap_writew(w
, UDC_DMA_IRQ_EN
);
601 omap_writew(ep
->bEndpointAddress
& 0xf, UDC_EP_NUM
);
602 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
604 omap_start_dma(ep
->lch
);
608 finish_out_dma(struct omap_ep
*ep
, struct omap_req
*req
, int status
, int one
)
613 ep
->dma_counter
= (u16
) (req
->req
.dma
+ req
->req
.actual
);
614 count
= dma_dest_len(ep
, req
->req
.dma
+ req
->req
.actual
);
615 count
+= req
->req
.actual
;
618 if (count
<= req
->req
.length
)
619 req
->req
.actual
= count
;
621 if (count
!= req
->dma_bytes
|| status
)
622 omap_stop_dma(ep
->lch
);
624 /* if this wasn't short, request may need another transfer */
625 else if (req
->req
.actual
< req
->req
.length
)
629 w
= omap_readw(UDC_DMA_IRQ_EN
);
630 w
&= ~UDC_RX_EOT_IE(ep
->dma_channel
);
631 omap_writew(w
, UDC_DMA_IRQ_EN
);
632 done(ep
, req
, status
);
635 static void dma_irq(struct omap_udc
*udc
, u16 irq_src
)
637 u16 dman_stat
= omap_readw(UDC_DMAN_STAT
);
639 struct omap_req
*req
;
641 /* IN dma: tx to host */
642 if (irq_src
& UDC_TXN_DONE
) {
643 ep
= &udc
->ep
[16 + UDC_DMA_TX_SRC(dman_stat
)];
645 /* can see TXN_DONE after dma abort */
646 if (!list_empty(&ep
->queue
)) {
647 req
= container_of(ep
->queue
.next
,
648 struct omap_req
, queue
);
649 finish_in_dma(ep
, req
, 0);
651 omap_writew(UDC_TXN_DONE
, UDC_IRQ_SRC
);
653 if (!list_empty(&ep
->queue
)) {
654 req
= container_of(ep
->queue
.next
,
655 struct omap_req
, queue
);
656 next_in_dma(ep
, req
);
660 /* OUT dma: rx from host */
661 if (irq_src
& UDC_RXN_EOT
) {
662 ep
= &udc
->ep
[UDC_DMA_RX_SRC(dman_stat
)];
664 /* can see RXN_EOT after dma abort */
665 if (!list_empty(&ep
->queue
)) {
666 req
= container_of(ep
->queue
.next
,
667 struct omap_req
, queue
);
668 finish_out_dma(ep
, req
, 0, dman_stat
& UDC_DMA_RX_SB
);
670 omap_writew(UDC_RXN_EOT
, UDC_IRQ_SRC
);
672 if (!list_empty(&ep
->queue
)) {
673 req
= container_of(ep
->queue
.next
,
674 struct omap_req
, queue
);
675 next_out_dma(ep
, req
);
679 if (irq_src
& UDC_RXN_CNT
) {
680 ep
= &udc
->ep
[UDC_DMA_RX_SRC(dman_stat
)];
682 /* omap15xx does this unasked... */
683 VDBG("%s, RX_CNT irq?\n", ep
->ep
.name
);
684 omap_writew(UDC_RXN_CNT
, UDC_IRQ_SRC
);
688 static void dma_error(int lch
, u16 ch_status
, void *data
)
690 struct omap_ep
*ep
= data
;
692 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
693 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
694 ERR("%s dma error, lch %d status %02x\n", ep
->ep
.name
, lch
, ch_status
);
696 /* complete current transfer ... */
699 static void dma_channel_claim(struct omap_ep
*ep
, unsigned channel
)
702 int status
, restart
, is_in
;
705 is_in
= ep
->bEndpointAddress
& USB_DIR_IN
;
707 reg
= omap_readw(UDC_TXDMA_CFG
);
709 reg
= omap_readw(UDC_RXDMA_CFG
);
710 reg
|= UDC_DMA_REQ
; /* "pulse" activated */
714 if (channel
== 0 || channel
> 3) {
715 if ((reg
& 0x0f00) == 0)
717 else if ((reg
& 0x00f0) == 0)
719 else if ((reg
& 0x000f) == 0) /* preferred for ISO */
726 reg
|= (0x0f & ep
->bEndpointAddress
) << (4 * (channel
- 1));
727 ep
->dma_channel
= channel
;
730 dma_channel
= OMAP_DMA_USB_W2FC_TX0
- 1 + channel
;
731 status
= omap_request_dma(dma_channel
,
732 ep
->ep
.name
, dma_error
, ep
, &ep
->lch
);
734 omap_writew(reg
, UDC_TXDMA_CFG
);
736 omap_set_dma_src_burst_mode(ep
->lch
,
737 OMAP_DMA_DATA_BURST_4
);
738 omap_set_dma_src_data_pack(ep
->lch
, 1);
740 omap_set_dma_dest_params(ep
->lch
,
742 OMAP_DMA_AMODE_CONSTANT
,
747 dma_channel
= OMAP_DMA_USB_W2FC_RX0
- 1 + channel
;
748 status
= omap_request_dma(dma_channel
,
749 ep
->ep
.name
, dma_error
, ep
, &ep
->lch
);
751 omap_writew(reg
, UDC_RXDMA_CFG
);
753 omap_set_dma_src_params(ep
->lch
,
755 OMAP_DMA_AMODE_CONSTANT
,
759 omap_set_dma_dest_burst_mode(ep
->lch
,
760 OMAP_DMA_DATA_BURST_4
);
761 omap_set_dma_dest_data_pack(ep
->lch
, 1);
768 omap_disable_dma_irq(ep
->lch
, OMAP_DMA_BLOCK_IRQ
);
770 /* channel type P: hw synch (fifo) */
771 if (!cpu_is_omap15xx())
772 omap_set_dma_channel_mode(ep
->lch
, OMAP_DMA_LCH_P
);
776 /* restart any queue, even if the claim failed */
777 restart
= !ep
->stopped
&& !list_empty(&ep
->queue
);
780 DBG("%s no dma channel: %d%s\n", ep
->ep
.name
, status
,
781 restart
? " (restart)" : "");
783 DBG("%s claimed %cxdma%d lch %d%s\n", ep
->ep
.name
,
785 ep
->dma_channel
- 1, ep
->lch
,
786 restart
? " (restart)" : "");
789 struct omap_req
*req
;
790 req
= container_of(ep
->queue
.next
, struct omap_req
, queue
);
792 (is_in
? next_in_dma
: next_out_dma
)(ep
, req
);
794 use_ep(ep
, UDC_EP_SEL
);
795 (is_in
? write_fifo
: read_fifo
)(ep
, req
);
798 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
799 ep
->ackwait
= 1 + ep
->double_buf
;
801 /* IN: 6 wait states before it'll tx */
806 static void dma_channel_release(struct omap_ep
*ep
)
808 int shift
= 4 * (ep
->dma_channel
- 1);
809 u16 mask
= 0x0f << shift
;
810 struct omap_req
*req
;
813 /* abort any active usb transfer request */
814 if (!list_empty(&ep
->queue
))
815 req
= container_of(ep
->queue
.next
, struct omap_req
, queue
);
819 active
= omap_get_dma_active_status(ep
->lch
);
821 DBG("%s release %s %cxdma%d %p\n", ep
->ep
.name
,
822 active
? "active" : "idle",
823 (ep
->bEndpointAddress
& USB_DIR_IN
) ? 't' : 'r',
824 ep
->dma_channel
- 1, req
);
826 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
827 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
830 /* wait till current packet DMA finishes, and fifo empties */
831 if (ep
->bEndpointAddress
& USB_DIR_IN
) {
832 omap_writew((omap_readw(UDC_TXDMA_CFG
) & ~mask
) | UDC_DMA_REQ
,
836 finish_in_dma(ep
, req
, -ECONNRESET
);
838 /* clear FIFO; hosts probably won't empty it */
839 use_ep(ep
, UDC_EP_SEL
);
840 omap_writew(UDC_CLR_EP
, UDC_CTRL
);
843 while (omap_readw(UDC_TXDMA_CFG
) & mask
)
846 omap_writew((omap_readw(UDC_RXDMA_CFG
) & ~mask
) | UDC_DMA_REQ
,
849 /* dma empties the fifo */
850 while (omap_readw(UDC_RXDMA_CFG
) & mask
)
853 finish_out_dma(ep
, req
, -ECONNRESET
, 0);
855 omap_free_dma(ep
->lch
);
858 /* has_dma still set, till endpoint is fully quiesced */
862 /*-------------------------------------------------------------------------*/
865 omap_ep_queue(struct usb_ep
*_ep
, struct usb_request
*_req
, gfp_t gfp_flags
)
867 struct omap_ep
*ep
= container_of(_ep
, struct omap_ep
, ep
);
868 struct omap_req
*req
= container_of(_req
, struct omap_req
, req
);
869 struct omap_udc
*udc
;
873 /* catch various bogus parameters */
874 if (!_req
|| !req
->req
.complete
|| !req
->req
.buf
875 || !list_empty(&req
->queue
)) {
876 DBG("%s, bad params\n", __func__
);
879 if (!_ep
|| (!ep
->ep
.desc
&& ep
->bEndpointAddress
)) {
880 DBG("%s, bad ep\n", __func__
);
883 if (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
884 if (req
->req
.length
> ep
->ep
.maxpacket
)
889 /* this isn't bogus, but OMAP DMA isn't the only hardware to
890 * have a hard time with partial packet reads... reject it.
894 && ep
->bEndpointAddress
!= 0
895 && (ep
->bEndpointAddress
& USB_DIR_IN
) == 0
896 && (req
->req
.length
% ep
->ep
.maxpacket
) != 0) {
897 DBG("%s, no partial packet OUT reads\n", __func__
);
902 if (!udc
->driver
|| udc
->gadget
.speed
== USB_SPEED_UNKNOWN
)
905 if (use_dma
&& ep
->has_dma
)
906 usb_gadget_map_request(&udc
->gadget
, &req
->req
,
907 (ep
->bEndpointAddress
& USB_DIR_IN
));
909 VDBG("%s queue req %p, len %d buf %p\n",
910 ep
->ep
.name
, _req
, _req
->length
, _req
->buf
);
912 spin_lock_irqsave(&udc
->lock
, flags
);
914 req
->req
.status
= -EINPROGRESS
;
917 /* maybe kickstart non-iso i/o queues */
921 w
= omap_readw(UDC_IRQ_EN
);
923 omap_writew(w
, UDC_IRQ_EN
);
924 } else if (list_empty(&ep
->queue
) && !ep
->stopped
&& !ep
->ackwait
) {
927 if (ep
->bEndpointAddress
== 0) {
928 if (!udc
->ep0_pending
|| !list_empty(&ep
->queue
)) {
929 spin_unlock_irqrestore(&udc
->lock
, flags
);
933 /* empty DATA stage? */
935 if (!req
->req
.length
) {
937 /* chip became CONFIGURED or ADDRESSED
938 * earlier; drivers may already have queued
939 * requests to non-control endpoints
941 if (udc
->ep0_set_config
) {
942 u16 irq_en
= omap_readw(UDC_IRQ_EN
);
944 irq_en
|= UDC_DS_CHG_IE
| UDC_EP0_IE
;
945 if (!udc
->ep0_reset_config
)
946 irq_en
|= UDC_EPN_RX_IE
948 omap_writew(irq_en
, UDC_IRQ_EN
);
951 /* STATUS for zero length DATA stages is
952 * always an IN ... even for IN transfers,
953 * a weird case which seem to stall OMAP.
955 omap_writew(UDC_EP_SEL
| UDC_EP_DIR
,
957 omap_writew(UDC_CLR_EP
, UDC_CTRL
);
958 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
959 omap_writew(UDC_EP_DIR
, UDC_EP_NUM
);
962 udc
->ep0_pending
= 0;
966 /* non-empty DATA stage */
968 omap_writew(UDC_EP_SEL
| UDC_EP_DIR
,
973 omap_writew(UDC_EP_SEL
, UDC_EP_NUM
);
976 is_in
= ep
->bEndpointAddress
& USB_DIR_IN
;
978 use_ep(ep
, UDC_EP_SEL
);
979 /* if ISO: SOF IRQs must be enabled/disabled! */
983 (is_in
? next_in_dma
: next_out_dma
)(ep
, req
);
985 if ((is_in
? write_fifo
: read_fifo
)(ep
, req
) == 1)
989 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
990 ep
->ackwait
= 1 + ep
->double_buf
;
992 /* IN: 6 wait states before it'll tx */
997 /* irq handler advances the queue */
999 list_add_tail(&req
->queue
, &ep
->queue
);
1000 spin_unlock_irqrestore(&udc
->lock
, flags
);
1005 static int omap_ep_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
1007 struct omap_ep
*ep
= container_of(_ep
, struct omap_ep
, ep
);
1008 struct omap_req
*req
;
1009 unsigned long flags
;
1014 spin_lock_irqsave(&ep
->udc
->lock
, flags
);
1016 /* make sure it's actually queued on this endpoint */
1017 list_for_each_entry(req
, &ep
->queue
, queue
) {
1018 if (&req
->req
== _req
)
1021 if (&req
->req
!= _req
) {
1022 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
1026 if (use_dma
&& ep
->dma_channel
&& ep
->queue
.next
== &req
->queue
) {
1027 int channel
= ep
->dma_channel
;
1029 /* releasing the channel cancels the request,
1030 * reclaiming the channel restarts the queue
1032 dma_channel_release(ep
);
1033 dma_channel_claim(ep
, channel
);
1035 done(ep
, req
, -ECONNRESET
);
1036 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
1040 /*-------------------------------------------------------------------------*/
1042 static int omap_ep_set_halt(struct usb_ep
*_ep
, int value
)
1044 struct omap_ep
*ep
= container_of(_ep
, struct omap_ep
, ep
);
1045 unsigned long flags
;
1046 int status
= -EOPNOTSUPP
;
1048 spin_lock_irqsave(&ep
->udc
->lock
, flags
);
1050 /* just use protocol stalls for ep0; real halts are annoying */
1051 if (ep
->bEndpointAddress
== 0) {
1052 if (!ep
->udc
->ep0_pending
)
1055 if (ep
->udc
->ep0_set_config
) {
1056 WARNING("error changing config?\n");
1057 omap_writew(UDC_CLR_CFG
, UDC_SYSCON2
);
1059 omap_writew(UDC_STALL_CMD
, UDC_SYSCON2
);
1060 ep
->udc
->ep0_pending
= 0;
1065 /* otherwise, all active non-ISO endpoints can halt */
1066 } else if (ep
->bmAttributes
!= USB_ENDPOINT_XFER_ISOC
&& ep
->ep
.desc
) {
1068 /* IN endpoints must already be idle */
1069 if ((ep
->bEndpointAddress
& USB_DIR_IN
)
1070 && !list_empty(&ep
->queue
)) {
1078 if (use_dma
&& ep
->dma_channel
1079 && !list_empty(&ep
->queue
)) {
1080 channel
= ep
->dma_channel
;
1081 dma_channel_release(ep
);
1085 use_ep(ep
, UDC_EP_SEL
);
1086 if (omap_readw(UDC_STAT_FLG
) & UDC_NON_ISO_FIFO_EMPTY
) {
1087 omap_writew(UDC_SET_HALT
, UDC_CTRL
);
1094 dma_channel_claim(ep
, channel
);
1097 omap_writew(ep
->udc
->clr_halt
, UDC_CTRL
);
1099 if (!(ep
->bEndpointAddress
& USB_DIR_IN
)) {
1100 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1101 ep
->ackwait
= 1 + ep
->double_buf
;
1106 VDBG("%s %s halt stat %d\n", ep
->ep
.name
,
1107 value
? "set" : "clear", status
);
1109 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
1113 static struct usb_ep_ops omap_ep_ops
= {
1114 .enable
= omap_ep_enable
,
1115 .disable
= omap_ep_disable
,
1117 .alloc_request
= omap_alloc_request
,
1118 .free_request
= omap_free_request
,
1120 .queue
= omap_ep_queue
,
1121 .dequeue
= omap_ep_dequeue
,
1123 .set_halt
= omap_ep_set_halt
,
1124 /* fifo_status ... report bytes in fifo */
1125 /* fifo_flush ... flush fifo */
1128 /*-------------------------------------------------------------------------*/
1130 static int omap_get_frame(struct usb_gadget
*gadget
)
1132 u16 sof
= omap_readw(UDC_SOF
);
1133 return (sof
& UDC_TS_OK
) ? (sof
& UDC_TS
) : -EL2NSYNC
;
1136 static int omap_wakeup(struct usb_gadget
*gadget
)
1138 struct omap_udc
*udc
;
1139 unsigned long flags
;
1140 int retval
= -EHOSTUNREACH
;
1142 udc
= container_of(gadget
, struct omap_udc
, gadget
);
1144 spin_lock_irqsave(&udc
->lock
, flags
);
1145 if (udc
->devstat
& UDC_SUS
) {
1146 /* NOTE: OTG spec erratum says that OTG devices may
1147 * issue wakeups without host enable.
1149 if (udc
->devstat
& (UDC_B_HNP_ENABLE
|UDC_R_WK_OK
)) {
1150 DBG("remote wakeup...\n");
1151 omap_writew(UDC_RMT_WKP
, UDC_SYSCON2
);
1155 /* NOTE: non-OTG systems may use SRP TOO... */
1156 } else if (!(udc
->devstat
& UDC_ATT
)) {
1157 if (!IS_ERR_OR_NULL(udc
->transceiver
))
1158 retval
= otg_start_srp(udc
->transceiver
->otg
);
1160 spin_unlock_irqrestore(&udc
->lock
, flags
);
1166 omap_set_selfpowered(struct usb_gadget
*gadget
, int is_selfpowered
)
1168 struct omap_udc
*udc
;
1169 unsigned long flags
;
1172 udc
= container_of(gadget
, struct omap_udc
, gadget
);
1173 spin_lock_irqsave(&udc
->lock
, flags
);
1174 syscon1
= omap_readw(UDC_SYSCON1
);
1176 syscon1
|= UDC_SELF_PWR
;
1178 syscon1
&= ~UDC_SELF_PWR
;
1179 omap_writew(syscon1
, UDC_SYSCON1
);
1180 spin_unlock_irqrestore(&udc
->lock
, flags
);
1185 static int can_pullup(struct omap_udc
*udc
)
1187 return udc
->driver
&& udc
->softconnect
&& udc
->vbus_active
;
1190 static void pullup_enable(struct omap_udc
*udc
)
1194 w
= omap_readw(UDC_SYSCON1
);
1196 omap_writew(w
, UDC_SYSCON1
);
1197 if (!gadget_is_otg(&udc
->gadget
) && !cpu_is_omap15xx()) {
1200 l
= omap_readl(OTG_CTRL
);
1202 omap_writel(l
, OTG_CTRL
);
1204 omap_writew(UDC_DS_CHG_IE
, UDC_IRQ_EN
);
1207 static void pullup_disable(struct omap_udc
*udc
)
1211 if (!gadget_is_otg(&udc
->gadget
) && !cpu_is_omap15xx()) {
1214 l
= omap_readl(OTG_CTRL
);
1216 omap_writel(l
, OTG_CTRL
);
1218 omap_writew(UDC_DS_CHG_IE
, UDC_IRQ_EN
);
1219 w
= omap_readw(UDC_SYSCON1
);
1220 w
&= ~UDC_PULLUP_EN
;
1221 omap_writew(w
, UDC_SYSCON1
);
1224 static struct omap_udc
*udc
;
1226 static void omap_udc_enable_clock(int enable
)
1228 if (udc
== NULL
|| udc
->dc_clk
== NULL
|| udc
->hhc_clk
== NULL
)
1232 clk_enable(udc
->dc_clk
);
1233 clk_enable(udc
->hhc_clk
);
1236 clk_disable(udc
->hhc_clk
);
1237 clk_disable(udc
->dc_clk
);
1242 * Called by whatever detects VBUS sessions: external transceiver
1243 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1245 static int omap_vbus_session(struct usb_gadget
*gadget
, int is_active
)
1247 struct omap_udc
*udc
;
1248 unsigned long flags
;
1251 udc
= container_of(gadget
, struct omap_udc
, gadget
);
1252 spin_lock_irqsave(&udc
->lock
, flags
);
1253 VDBG("VBUS %s\n", is_active
? "on" : "off");
1254 udc
->vbus_active
= (is_active
!= 0);
1255 if (cpu_is_omap15xx()) {
1256 /* "software" detect, ignored if !VBUS_MODE_1510 */
1257 l
= omap_readl(FUNC_MUX_CTRL_0
);
1259 l
|= VBUS_CTRL_1510
;
1261 l
&= ~VBUS_CTRL_1510
;
1262 omap_writel(l
, FUNC_MUX_CTRL_0
);
1264 if (udc
->dc_clk
!= NULL
&& is_active
) {
1265 if (!udc
->clk_requested
) {
1266 omap_udc_enable_clock(1);
1267 udc
->clk_requested
= 1;
1270 if (can_pullup(udc
))
1273 pullup_disable(udc
);
1274 if (udc
->dc_clk
!= NULL
&& !is_active
) {
1275 if (udc
->clk_requested
) {
1276 omap_udc_enable_clock(0);
1277 udc
->clk_requested
= 0;
1280 spin_unlock_irqrestore(&udc
->lock
, flags
);
1284 static int omap_vbus_draw(struct usb_gadget
*gadget
, unsigned mA
)
1286 struct omap_udc
*udc
;
1288 udc
= container_of(gadget
, struct omap_udc
, gadget
);
1289 if (!IS_ERR_OR_NULL(udc
->transceiver
))
1290 return usb_phy_set_power(udc
->transceiver
, mA
);
1294 static int omap_pullup(struct usb_gadget
*gadget
, int is_on
)
1296 struct omap_udc
*udc
;
1297 unsigned long flags
;
1299 udc
= container_of(gadget
, struct omap_udc
, gadget
);
1300 spin_lock_irqsave(&udc
->lock
, flags
);
1301 udc
->softconnect
= (is_on
!= 0);
1302 if (can_pullup(udc
))
1305 pullup_disable(udc
);
1306 spin_unlock_irqrestore(&udc
->lock
, flags
);
1310 static int omap_udc_start(struct usb_gadget_driver
*driver
,
1311 int (*bind
)(struct usb_gadget
*));
1312 static int omap_udc_stop(struct usb_gadget_driver
*driver
);
1314 static struct usb_gadget_ops omap_gadget_ops
= {
1315 .get_frame
= omap_get_frame
,
1316 .wakeup
= omap_wakeup
,
1317 .set_selfpowered
= omap_set_selfpowered
,
1318 .vbus_session
= omap_vbus_session
,
1319 .vbus_draw
= omap_vbus_draw
,
1320 .pullup
= omap_pullup
,
1321 .start
= omap_udc_start
,
1322 .stop
= omap_udc_stop
,
1325 /*-------------------------------------------------------------------------*/
1327 /* dequeue ALL requests; caller holds udc->lock */
1328 static void nuke(struct omap_ep
*ep
, int status
)
1330 struct omap_req
*req
;
1334 if (use_dma
&& ep
->dma_channel
)
1335 dma_channel_release(ep
);
1338 omap_writew(UDC_CLR_EP
, UDC_CTRL
);
1339 if (ep
->bEndpointAddress
&& ep
->bmAttributes
!= USB_ENDPOINT_XFER_ISOC
)
1340 omap_writew(UDC_SET_HALT
, UDC_CTRL
);
1342 while (!list_empty(&ep
->queue
)) {
1343 req
= list_entry(ep
->queue
.next
, struct omap_req
, queue
);
1344 done(ep
, req
, status
);
1348 /* caller holds udc->lock */
1349 static void udc_quiesce(struct omap_udc
*udc
)
1353 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1354 nuke(&udc
->ep
[0], -ESHUTDOWN
);
1355 list_for_each_entry(ep
, &udc
->gadget
.ep_list
, ep
.ep_list
)
1356 nuke(ep
, -ESHUTDOWN
);
1359 /*-------------------------------------------------------------------------*/
1361 static void update_otg(struct omap_udc
*udc
)
1365 if (!gadget_is_otg(&udc
->gadget
))
1368 if (omap_readl(OTG_CTRL
) & OTG_ID
)
1369 devstat
= omap_readw(UDC_DEVSTAT
);
1373 udc
->gadget
.b_hnp_enable
= !!(devstat
& UDC_B_HNP_ENABLE
);
1374 udc
->gadget
.a_hnp_support
= !!(devstat
& UDC_A_HNP_SUPPORT
);
1375 udc
->gadget
.a_alt_hnp_support
= !!(devstat
& UDC_A_ALT_HNP_SUPPORT
);
1377 /* Enable HNP early, avoiding races on suspend irq path.
1378 * ASSUMES OTG state machine B_BUS_REQ input is true.
1380 if (udc
->gadget
.b_hnp_enable
) {
1383 l
= omap_readl(OTG_CTRL
);
1384 l
|= OTG_B_HNPEN
| OTG_B_BUSREQ
;
1386 omap_writel(l
, OTG_CTRL
);
1390 static void ep0_irq(struct omap_udc
*udc
, u16 irq_src
)
1392 struct omap_ep
*ep0
= &udc
->ep
[0];
1393 struct omap_req
*req
= NULL
;
1397 /* Clear any pending requests and then scrub any rx/tx state
1398 * before starting to handle the SETUP request.
1400 if (irq_src
& UDC_SETUP
) {
1401 u16 ack
= irq_src
& (UDC_EP0_TX
|UDC_EP0_RX
);
1405 omap_writew(ack
, UDC_IRQ_SRC
);
1406 irq_src
= UDC_SETUP
;
1410 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1411 * This driver uses only uses protocol stalls (ep0 never halts),
1412 * and if we got this far the gadget driver already had a
1413 * chance to stall. Tries to be forgiving of host oddities.
1415 * NOTE: the last chance gadget drivers have to stall control
1416 * requests is during their request completion callback.
1418 if (!list_empty(&ep0
->queue
))
1419 req
= container_of(ep0
->queue
.next
, struct omap_req
, queue
);
1421 /* IN == TX to host */
1422 if (irq_src
& UDC_EP0_TX
) {
1425 omap_writew(UDC_EP0_TX
, UDC_IRQ_SRC
);
1426 omap_writew(UDC_EP_SEL
|UDC_EP_DIR
, UDC_EP_NUM
);
1427 stat
= omap_readw(UDC_STAT_FLG
);
1428 if (stat
& UDC_ACK
) {
1430 /* write next IN packet from response,
1431 * or set up the status stage.
1434 stat
= write_fifo(ep0
, req
);
1435 omap_writew(UDC_EP_DIR
, UDC_EP_NUM
);
1436 if (!req
&& udc
->ep0_pending
) {
1437 omap_writew(UDC_EP_SEL
, UDC_EP_NUM
);
1438 omap_writew(UDC_CLR_EP
, UDC_CTRL
);
1439 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1440 omap_writew(0, UDC_EP_NUM
);
1441 udc
->ep0_pending
= 0;
1442 } /* else: 6 wait states before it'll tx */
1444 /* ack status stage of OUT transfer */
1445 omap_writew(UDC_EP_DIR
, UDC_EP_NUM
);
1450 } else if (stat
& UDC_STALL
) {
1451 omap_writew(UDC_CLR_HALT
, UDC_CTRL
);
1452 omap_writew(UDC_EP_DIR
, UDC_EP_NUM
);
1454 omap_writew(UDC_EP_DIR
, UDC_EP_NUM
);
1458 /* OUT == RX from host */
1459 if (irq_src
& UDC_EP0_RX
) {
1462 omap_writew(UDC_EP0_RX
, UDC_IRQ_SRC
);
1463 omap_writew(UDC_EP_SEL
, UDC_EP_NUM
);
1464 stat
= omap_readw(UDC_STAT_FLG
);
1465 if (stat
& UDC_ACK
) {
1468 /* read next OUT packet of request, maybe
1469 * reactiviting the fifo; stall on errors.
1471 stat
= read_fifo(ep0
, req
);
1472 if (!req
|| stat
< 0) {
1473 omap_writew(UDC_STALL_CMD
, UDC_SYSCON2
);
1474 udc
->ep0_pending
= 0;
1476 } else if (stat
== 0)
1477 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1478 omap_writew(0, UDC_EP_NUM
);
1480 /* activate status stage */
1483 /* that may have STALLed ep0... */
1484 omap_writew(UDC_EP_SEL
| UDC_EP_DIR
,
1486 omap_writew(UDC_CLR_EP
, UDC_CTRL
);
1487 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1488 omap_writew(UDC_EP_DIR
, UDC_EP_NUM
);
1489 udc
->ep0_pending
= 0;
1492 /* ack status stage of IN transfer */
1493 omap_writew(0, UDC_EP_NUM
);
1497 } else if (stat
& UDC_STALL
) {
1498 omap_writew(UDC_CLR_HALT
, UDC_CTRL
);
1499 omap_writew(0, UDC_EP_NUM
);
1501 omap_writew(0, UDC_EP_NUM
);
1505 /* SETUP starts all control transfers */
1506 if (irq_src
& UDC_SETUP
) {
1509 struct usb_ctrlrequest r
;
1511 int status
= -EINVAL
;
1514 /* read the (latest) SETUP message */
1516 omap_writew(UDC_SETUP_SEL
, UDC_EP_NUM
);
1517 /* two bytes at a time */
1518 u
.word
[0] = omap_readw(UDC_DATA
);
1519 u
.word
[1] = omap_readw(UDC_DATA
);
1520 u
.word
[2] = omap_readw(UDC_DATA
);
1521 u
.word
[3] = omap_readw(UDC_DATA
);
1522 omap_writew(0, UDC_EP_NUM
);
1523 } while (omap_readw(UDC_IRQ_SRC
) & UDC_SETUP
);
1525 #define w_value le16_to_cpu(u.r.wValue)
1526 #define w_index le16_to_cpu(u.r.wIndex)
1527 #define w_length le16_to_cpu(u.r.wLength)
1529 /* Delegate almost all control requests to the gadget driver,
1530 * except for a handful of ch9 status/feature requests that
1531 * hardware doesn't autodecode _and_ the gadget API hides.
1533 udc
->ep0_in
= (u
.r
.bRequestType
& USB_DIR_IN
) != 0;
1534 udc
->ep0_set_config
= 0;
1535 udc
->ep0_pending
= 1;
1538 switch (u
.r
.bRequest
) {
1539 case USB_REQ_SET_CONFIGURATION
:
1540 /* udc needs to know when ep != 0 is valid */
1541 if (u
.r
.bRequestType
!= USB_RECIP_DEVICE
)
1545 udc
->ep0_set_config
= 1;
1546 udc
->ep0_reset_config
= (w_value
== 0);
1547 VDBG("set config %d\n", w_value
);
1549 /* update udc NOW since gadget driver may start
1550 * queueing requests immediately; clear config
1551 * later if it fails the request.
1553 if (udc
->ep0_reset_config
)
1554 omap_writew(UDC_CLR_CFG
, UDC_SYSCON2
);
1556 omap_writew(UDC_DEV_CFG
, UDC_SYSCON2
);
1559 case USB_REQ_CLEAR_FEATURE
:
1560 /* clear endpoint halt */
1561 if (u
.r
.bRequestType
!= USB_RECIP_ENDPOINT
)
1563 if (w_value
!= USB_ENDPOINT_HALT
1566 ep
= &udc
->ep
[w_index
& 0xf];
1568 if (w_index
& USB_DIR_IN
)
1570 if (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
1574 omap_writew(udc
->clr_halt
, UDC_CTRL
);
1576 if (!(ep
->bEndpointAddress
& USB_DIR_IN
)) {
1577 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1578 ep
->ackwait
= 1 + ep
->double_buf
;
1580 /* NOTE: assumes the host behaves sanely,
1581 * only clearing real halts. Else we may
1582 * need to kill pending transfers and then
1583 * restart the queue... very messy for DMA!
1586 VDBG("%s halt cleared by host\n", ep
->name
);
1587 goto ep0out_status_stage
;
1588 case USB_REQ_SET_FEATURE
:
1589 /* set endpoint halt */
1590 if (u
.r
.bRequestType
!= USB_RECIP_ENDPOINT
)
1592 if (w_value
!= USB_ENDPOINT_HALT
1595 ep
= &udc
->ep
[w_index
& 0xf];
1596 if (w_index
& USB_DIR_IN
)
1598 if (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
1599 || ep
== ep0
|| !ep
->ep
.desc
)
1601 if (use_dma
&& ep
->has_dma
) {
1602 /* this has rude side-effects (aborts) and
1603 * can't really work if DMA-IN is active
1605 DBG("%s host set_halt, NYET\n", ep
->name
);
1609 /* can't halt if fifo isn't empty... */
1610 omap_writew(UDC_CLR_EP
, UDC_CTRL
);
1611 omap_writew(UDC_SET_HALT
, UDC_CTRL
);
1612 VDBG("%s halted by host\n", ep
->name
);
1613 ep0out_status_stage
:
1615 omap_writew(UDC_EP_SEL
|UDC_EP_DIR
, UDC_EP_NUM
);
1616 omap_writew(UDC_CLR_EP
, UDC_CTRL
);
1617 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1618 omap_writew(UDC_EP_DIR
, UDC_EP_NUM
);
1619 udc
->ep0_pending
= 0;
1621 case USB_REQ_GET_STATUS
:
1622 /* USB_ENDPOINT_HALT status? */
1623 if (u
.r
.bRequestType
!= (USB_DIR_IN
|USB_RECIP_ENDPOINT
))
1626 /* ep0 never stalls */
1627 if (!(w_index
& 0xf))
1630 /* only active endpoints count */
1631 ep
= &udc
->ep
[w_index
& 0xf];
1632 if (w_index
& USB_DIR_IN
)
1637 /* iso never stalls */
1638 if (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
)
1641 /* FIXME don't assume non-halted endpoints!! */
1642 ERR("%s status, can't report\n", ep
->ep
.name
);
1646 /* return interface status. if we were pedantic,
1647 * we'd detect non-existent interfaces, and stall.
1649 if (u
.r
.bRequestType
1650 != (USB_DIR_IN
|USB_RECIP_INTERFACE
))
1654 /* return two zero bytes */
1655 omap_writew(UDC_EP_SEL
|UDC_EP_DIR
, UDC_EP_NUM
);
1656 omap_writew(0, UDC_DATA
);
1657 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1658 omap_writew(UDC_EP_DIR
, UDC_EP_NUM
);
1660 VDBG("GET_STATUS, interface %d\n", w_index
);
1661 /* next, status stage */
1665 /* activate the ep0out fifo right away */
1666 if (!udc
->ep0_in
&& w_length
) {
1667 omap_writew(0, UDC_EP_NUM
);
1668 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1671 /* gadget drivers see class/vendor specific requests,
1672 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1675 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1676 u
.r
.bRequestType
, u
.r
.bRequest
,
1677 w_value
, w_index
, w_length
);
1683 /* The gadget driver may return an error here,
1684 * causing an immediate protocol stall.
1686 * Else it must issue a response, either queueing a
1687 * response buffer for the DATA stage, or halting ep0
1688 * (causing a protocol stall, not a real halt). A
1689 * zero length buffer means no DATA stage.
1691 * It's fine to issue that response after the setup()
1692 * call returns, and this IRQ was handled.
1695 spin_unlock(&udc
->lock
);
1696 status
= udc
->driver
->setup(&udc
->gadget
, &u
.r
);
1697 spin_lock(&udc
->lock
);
1703 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1704 u
.r
.bRequestType
, u
.r
.bRequest
, status
);
1705 if (udc
->ep0_set_config
) {
1706 if (udc
->ep0_reset_config
)
1707 WARNING("error resetting config?\n");
1709 omap_writew(UDC_CLR_CFG
, UDC_SYSCON2
);
1711 omap_writew(UDC_STALL_CMD
, UDC_SYSCON2
);
1712 udc
->ep0_pending
= 0;
1717 /*-------------------------------------------------------------------------*/
1719 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1721 static void devstate_irq(struct omap_udc
*udc
, u16 irq_src
)
1723 u16 devstat
, change
;
1725 devstat
= omap_readw(UDC_DEVSTAT
);
1726 change
= devstat
^ udc
->devstat
;
1727 udc
->devstat
= devstat
;
1729 if (change
& (UDC_USB_RESET
|UDC_ATT
)) {
1732 if (change
& UDC_ATT
) {
1733 /* driver for any external transceiver will
1734 * have called omap_vbus_session() already
1736 if (devstat
& UDC_ATT
) {
1737 udc
->gadget
.speed
= USB_SPEED_FULL
;
1739 if (IS_ERR_OR_NULL(udc
->transceiver
))
1741 /* if (driver->connect) call it */
1742 } else if (udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
1743 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1744 if (IS_ERR_OR_NULL(udc
->transceiver
))
1745 pullup_disable(udc
);
1746 DBG("disconnect, gadget %s\n",
1747 udc
->driver
->driver
.name
);
1748 if (udc
->driver
->disconnect
) {
1749 spin_unlock(&udc
->lock
);
1750 udc
->driver
->disconnect(&udc
->gadget
);
1751 spin_lock(&udc
->lock
);
1757 if (change
& UDC_USB_RESET
) {
1758 if (devstat
& UDC_USB_RESET
) {
1761 udc
->gadget
.speed
= USB_SPEED_FULL
;
1762 INFO("USB reset done, gadget %s\n",
1763 udc
->driver
->driver
.name
);
1764 /* ep0 traffic is legal from now on */
1765 omap_writew(UDC_DS_CHG_IE
| UDC_EP0_IE
,
1768 change
&= ~UDC_USB_RESET
;
1771 if (change
& UDC_SUS
) {
1772 if (udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
1773 /* FIXME tell isp1301 to suspend/resume (?) */
1774 if (devstat
& UDC_SUS
) {
1777 /* HNP could be under way already */
1778 if (udc
->gadget
.speed
== USB_SPEED_FULL
1779 && udc
->driver
->suspend
) {
1780 spin_unlock(&udc
->lock
);
1781 udc
->driver
->suspend(&udc
->gadget
);
1782 spin_lock(&udc
->lock
);
1784 if (!IS_ERR_OR_NULL(udc
->transceiver
))
1785 usb_phy_set_suspend(
1786 udc
->transceiver
, 1);
1789 if (!IS_ERR_OR_NULL(udc
->transceiver
))
1790 usb_phy_set_suspend(
1791 udc
->transceiver
, 0);
1792 if (udc
->gadget
.speed
== USB_SPEED_FULL
1793 && udc
->driver
->resume
) {
1794 spin_unlock(&udc
->lock
);
1795 udc
->driver
->resume(&udc
->gadget
);
1796 spin_lock(&udc
->lock
);
1802 if (!cpu_is_omap15xx() && (change
& OTG_FLAGS
)) {
1804 change
&= ~OTG_FLAGS
;
1807 change
&= ~(UDC_CFG
|UDC_DEF
|UDC_ADD
);
1809 VDBG("devstat %03x, ignore change %03x\n",
1812 omap_writew(UDC_DS_CHG
, UDC_IRQ_SRC
);
1815 static irqreturn_t
omap_udc_irq(int irq
, void *_udc
)
1817 struct omap_udc
*udc
= _udc
;
1819 irqreturn_t status
= IRQ_NONE
;
1820 unsigned long flags
;
1822 spin_lock_irqsave(&udc
->lock
, flags
);
1823 irq_src
= omap_readw(UDC_IRQ_SRC
);
1825 /* Device state change (usb ch9 stuff) */
1826 if (irq_src
& UDC_DS_CHG
) {
1827 devstate_irq(_udc
, irq_src
);
1828 status
= IRQ_HANDLED
;
1829 irq_src
&= ~UDC_DS_CHG
;
1832 /* EP0 control transfers */
1833 if (irq_src
& (UDC_EP0_RX
|UDC_SETUP
|UDC_EP0_TX
)) {
1834 ep0_irq(_udc
, irq_src
);
1835 status
= IRQ_HANDLED
;
1836 irq_src
&= ~(UDC_EP0_RX
|UDC_SETUP
|UDC_EP0_TX
);
1839 /* DMA transfer completion */
1840 if (use_dma
&& (irq_src
& (UDC_TXN_DONE
|UDC_RXN_CNT
|UDC_RXN_EOT
))) {
1841 dma_irq(_udc
, irq_src
);
1842 status
= IRQ_HANDLED
;
1843 irq_src
&= ~(UDC_TXN_DONE
|UDC_RXN_CNT
|UDC_RXN_EOT
);
1846 irq_src
&= ~(UDC_IRQ_SOF
| UDC_EPN_TX
|UDC_EPN_RX
);
1848 DBG("udc_irq, unhandled %03x\n", irq_src
);
1849 spin_unlock_irqrestore(&udc
->lock
, flags
);
1854 /* workaround for seemingly-lost IRQs for RX ACKs... */
1855 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1856 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1858 static void pio_out_timer(unsigned long _ep
)
1860 struct omap_ep
*ep
= (void *) _ep
;
1861 unsigned long flags
;
1864 spin_lock_irqsave(&ep
->udc
->lock
, flags
);
1865 if (!list_empty(&ep
->queue
) && ep
->ackwait
) {
1866 use_ep(ep
, UDC_EP_SEL
);
1867 stat_flg
= omap_readw(UDC_STAT_FLG
);
1869 if ((stat_flg
& UDC_ACK
) && (!(stat_flg
& UDC_FIFO_EN
)
1870 || (ep
->double_buf
&& HALF_FULL(stat_flg
)))) {
1871 struct omap_req
*req
;
1873 VDBG("%s: lose, %04x\n", ep
->ep
.name
, stat_flg
);
1874 req
= container_of(ep
->queue
.next
,
1875 struct omap_req
, queue
);
1876 (void) read_fifo(ep
, req
);
1877 omap_writew(ep
->bEndpointAddress
, UDC_EP_NUM
);
1878 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1879 ep
->ackwait
= 1 + ep
->double_buf
;
1883 mod_timer(&ep
->timer
, PIO_OUT_TIMEOUT
);
1884 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
1887 static irqreturn_t
omap_udc_pio_irq(int irq
, void *_dev
)
1889 u16 epn_stat
, irq_src
;
1890 irqreturn_t status
= IRQ_NONE
;
1893 struct omap_udc
*udc
= _dev
;
1894 struct omap_req
*req
;
1895 unsigned long flags
;
1897 spin_lock_irqsave(&udc
->lock
, flags
);
1898 epn_stat
= omap_readw(UDC_EPN_STAT
);
1899 irq_src
= omap_readw(UDC_IRQ_SRC
);
1901 /* handle OUT first, to avoid some wasteful NAKs */
1902 if (irq_src
& UDC_EPN_RX
) {
1903 epnum
= (epn_stat
>> 8) & 0x0f;
1904 omap_writew(UDC_EPN_RX
, UDC_IRQ_SRC
);
1905 status
= IRQ_HANDLED
;
1906 ep
= &udc
->ep
[epnum
];
1909 omap_writew(epnum
| UDC_EP_SEL
, UDC_EP_NUM
);
1911 if (omap_readw(UDC_STAT_FLG
) & UDC_ACK
) {
1913 if (!list_empty(&ep
->queue
)) {
1915 req
= container_of(ep
->queue
.next
,
1916 struct omap_req
, queue
);
1917 stat
= read_fifo(ep
, req
);
1918 if (!ep
->double_buf
)
1922 /* min 6 clock delay before clearing EP_SEL ... */
1923 epn_stat
= omap_readw(UDC_EPN_STAT
);
1924 epn_stat
= omap_readw(UDC_EPN_STAT
);
1925 omap_writew(epnum
, UDC_EP_NUM
);
1927 /* enabling fifo _after_ clearing ACK, contrary to docs,
1928 * reduces lossage; timer still needed though (sigh).
1931 omap_writew(UDC_SET_FIFO_EN
, UDC_CTRL
);
1932 ep
->ackwait
= 1 + ep
->double_buf
;
1934 mod_timer(&ep
->timer
, PIO_OUT_TIMEOUT
);
1937 /* then IN transfers */
1938 else if (irq_src
& UDC_EPN_TX
) {
1939 epnum
= epn_stat
& 0x0f;
1940 omap_writew(UDC_EPN_TX
, UDC_IRQ_SRC
);
1941 status
= IRQ_HANDLED
;
1942 ep
= &udc
->ep
[16 + epnum
];
1945 omap_writew(epnum
| UDC_EP_DIR
| UDC_EP_SEL
, UDC_EP_NUM
);
1946 if (omap_readw(UDC_STAT_FLG
) & UDC_ACK
) {
1948 if (!list_empty(&ep
->queue
)) {
1949 req
= container_of(ep
->queue
.next
,
1950 struct omap_req
, queue
);
1951 (void) write_fifo(ep
, req
);
1954 /* min 6 clock delay before clearing EP_SEL ... */
1955 epn_stat
= omap_readw(UDC_EPN_STAT
);
1956 epn_stat
= omap_readw(UDC_EPN_STAT
);
1957 omap_writew(epnum
| UDC_EP_DIR
, UDC_EP_NUM
);
1958 /* then 6 clocks before it'd tx */
1961 spin_unlock_irqrestore(&udc
->lock
, flags
);
1966 static irqreturn_t
omap_udc_iso_irq(int irq
, void *_dev
)
1968 struct omap_udc
*udc
= _dev
;
1971 unsigned long flags
;
1973 spin_lock_irqsave(&udc
->lock
, flags
);
1975 /* handle all non-DMA ISO transfers */
1976 list_for_each_entry(ep
, &udc
->iso
, iso
) {
1978 struct omap_req
*req
;
1980 if (ep
->has_dma
|| list_empty(&ep
->queue
))
1982 req
= list_entry(ep
->queue
.next
, struct omap_req
, queue
);
1984 use_ep(ep
, UDC_EP_SEL
);
1985 stat
= omap_readw(UDC_STAT_FLG
);
1987 /* NOTE: like the other controller drivers, this isn't
1988 * currently reporting lost or damaged frames.
1990 if (ep
->bEndpointAddress
& USB_DIR_IN
) {
1991 if (stat
& UDC_MISS_IN
)
1992 /* done(ep, req, -EPROTO) */;
1994 write_fifo(ep
, req
);
1998 if (stat
& UDC_NO_RXPACKET
)
1999 status
= -EREMOTEIO
;
2000 else if (stat
& UDC_ISO_ERR
)
2002 else if (stat
& UDC_DATA_FLUSH
)
2006 /* done(ep, req, status) */;
2011 /* 6 wait states before next EP */
2014 if (!list_empty(&ep
->queue
))
2020 w
= omap_readw(UDC_IRQ_EN
);
2022 omap_writew(w
, UDC_IRQ_EN
);
2024 omap_writew(UDC_IRQ_SOF
, UDC_IRQ_SRC
);
2026 spin_unlock_irqrestore(&udc
->lock
, flags
);
2031 /*-------------------------------------------------------------------------*/
2033 static inline int machine_without_vbus_sense(void)
2035 return machine_is_omap_innovator()
2036 || machine_is_omap_osk()
2038 /* No known omap7xx boards with vbus sense */
2039 || cpu_is_omap7xx();
2042 static int omap_udc_start(struct usb_gadget_driver
*driver
,
2043 int (*bind
)(struct usb_gadget
*))
2045 int status
= -ENODEV
;
2047 unsigned long flags
;
2049 /* basic sanity tests */
2053 /* FIXME if otg, check: driver->is_otg */
2054 || driver
->max_speed
< USB_SPEED_FULL
2055 || !bind
|| !driver
->setup
)
2058 spin_lock_irqsave(&udc
->lock
, flags
);
2060 spin_unlock_irqrestore(&udc
->lock
, flags
);
2065 list_for_each_entry(ep
, &udc
->gadget
.ep_list
, ep
.ep_list
) {
2067 if (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
)
2070 omap_writew(UDC_SET_HALT
, UDC_CTRL
);
2072 udc
->ep0_pending
= 0;
2073 udc
->ep
[0].irqs
= 0;
2074 udc
->softconnect
= 1;
2076 /* hook up the driver */
2077 driver
->driver
.bus
= NULL
;
2078 udc
->driver
= driver
;
2079 udc
->gadget
.dev
.driver
= &driver
->driver
;
2080 spin_unlock_irqrestore(&udc
->lock
, flags
);
2082 if (udc
->dc_clk
!= NULL
)
2083 omap_udc_enable_clock(1);
2085 status
= bind(&udc
->gadget
);
2087 DBG("bind to %s --> %d\n", driver
->driver
.name
, status
);
2088 udc
->gadget
.dev
.driver
= NULL
;
2092 DBG("bound to driver %s\n", driver
->driver
.name
);
2094 omap_writew(UDC_IRQ_SRC_MASK
, UDC_IRQ_SRC
);
2096 /* connect to bus through transceiver */
2097 if (!IS_ERR_OR_NULL(udc
->transceiver
)) {
2098 status
= otg_set_peripheral(udc
->transceiver
->otg
,
2101 ERR("can't bind to transceiver\n");
2102 if (driver
->unbind
) {
2103 driver
->unbind(&udc
->gadget
);
2104 udc
->gadget
.dev
.driver
= NULL
;
2110 if (can_pullup(udc
))
2113 pullup_disable(udc
);
2116 /* boards that don't have VBUS sensing can't autogate 48MHz;
2117 * can't enter deep sleep while a gadget driver is active.
2119 if (machine_without_vbus_sense())
2120 omap_vbus_session(&udc
->gadget
, 1);
2123 if (udc
->dc_clk
!= NULL
)
2124 omap_udc_enable_clock(0);
2128 static int omap_udc_stop(struct usb_gadget_driver
*driver
)
2130 unsigned long flags
;
2131 int status
= -ENODEV
;
2135 if (!driver
|| driver
!= udc
->driver
|| !driver
->unbind
)
2138 if (udc
->dc_clk
!= NULL
)
2139 omap_udc_enable_clock(1);
2141 if (machine_without_vbus_sense())
2142 omap_vbus_session(&udc
->gadget
, 0);
2144 if (!IS_ERR_OR_NULL(udc
->transceiver
))
2145 (void) otg_set_peripheral(udc
->transceiver
->otg
, NULL
);
2147 pullup_disable(udc
);
2149 spin_lock_irqsave(&udc
->lock
, flags
);
2151 spin_unlock_irqrestore(&udc
->lock
, flags
);
2153 driver
->unbind(&udc
->gadget
);
2154 udc
->gadget
.dev
.driver
= NULL
;
2157 if (udc
->dc_clk
!= NULL
)
2158 omap_udc_enable_clock(0);
2159 DBG("unregistered driver '%s'\n", driver
->driver
.name
);
2163 /*-------------------------------------------------------------------------*/
2165 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2167 #include <linux/seq_file.h>
2169 static const char proc_filename
[] = "driver/udc";
2171 #define FOURBITS "%s%s%s%s"
2172 #define EIGHTBITS "%s%s%s%s%s%s%s%s"
2174 static void proc_ep_show(struct seq_file
*s
, struct omap_ep
*ep
)
2177 struct omap_req
*req
;
2182 if (use_dma
&& ep
->has_dma
)
2183 snprintf(buf
, sizeof buf
, "(%cxdma%d lch%d) ",
2184 (ep
->bEndpointAddress
& USB_DIR_IN
) ? 't' : 'r',
2185 ep
->dma_channel
- 1, ep
->lch
);
2189 stat_flg
= omap_readw(UDC_STAT_FLG
);
2191 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS
"%s\n",
2193 ep
->double_buf
? "dbuf " : "",
2195 switch (ep
->ackwait
) {
2210 (stat_flg
& UDC_NO_RXPACKET
) ? "no_rxpacket " : "",
2211 (stat_flg
& UDC_MISS_IN
) ? "miss_in " : "",
2212 (stat_flg
& UDC_DATA_FLUSH
) ? "data_flush " : "",
2213 (stat_flg
& UDC_ISO_ERR
) ? "iso_err " : "",
2214 (stat_flg
& UDC_ISO_FIFO_EMPTY
) ? "iso_fifo_empty " : "",
2215 (stat_flg
& UDC_ISO_FIFO_FULL
) ? "iso_fifo_full " : "",
2216 (stat_flg
& UDC_EP_HALTED
) ? "HALT " : "",
2217 (stat_flg
& UDC_STALL
) ? "STALL " : "",
2218 (stat_flg
& UDC_NAK
) ? "NAK " : "",
2219 (stat_flg
& UDC_ACK
) ? "ACK " : "",
2220 (stat_flg
& UDC_FIFO_EN
) ? "fifo_en " : "",
2221 (stat_flg
& UDC_NON_ISO_FIFO_EMPTY
) ? "fifo_empty " : "",
2222 (stat_flg
& UDC_NON_ISO_FIFO_FULL
) ? "fifo_full " : "");
2224 if (list_empty(&ep
->queue
))
2225 seq_printf(s
, "\t(queue empty)\n");
2227 list_for_each_entry(req
, &ep
->queue
, queue
) {
2228 unsigned length
= req
->req
.actual
;
2230 if (use_dma
&& buf
[0]) {
2231 length
+= ((ep
->bEndpointAddress
& USB_DIR_IN
)
2232 ? dma_src_len
: dma_dest_len
)
2233 (ep
, req
->req
.dma
+ length
);
2236 seq_printf(s
, "\treq %p len %d/%d buf %p\n",
2238 req
->req
.length
, req
->req
.buf
);
2242 static char *trx_mode(unsigned m
, int enabled
)
2246 return enabled
? "*6wire" : "unused";
2258 static int proc_otg_show(struct seq_file
*s
)
2262 char *ctrl_name
= "(UNKNOWN)";
2264 tmp
= omap_readl(OTG_REV
);
2265 ctrl_name
= "tranceiver_ctrl";
2266 trans
= omap_readw(USB_TRANSCEIVER_CTRL
);
2267 seq_printf(s
, "\nOTG rev %d.%d, %s %05x\n",
2268 tmp
>> 4, tmp
& 0xf, ctrl_name
, trans
);
2269 tmp
= omap_readw(OTG_SYSCON_1
);
2270 seq_printf(s
, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2272 trx_mode(USB2_TRX_MODE(tmp
), trans
& CONF_USB2_UNI_R
),
2273 trx_mode(USB1_TRX_MODE(tmp
), trans
& CONF_USB1_UNI_R
),
2274 (USB0_TRX_MODE(tmp
) == 0 && !cpu_is_omap1710())
2276 : trx_mode(USB0_TRX_MODE(tmp
), 1),
2277 (tmp
& OTG_IDLE_EN
) ? " !otg" : "",
2278 (tmp
& HST_IDLE_EN
) ? " !host" : "",
2279 (tmp
& DEV_IDLE_EN
) ? " !dev" : "",
2280 (tmp
& OTG_RESET_DONE
) ? " reset_done" : " reset_active");
2281 tmp
= omap_readl(OTG_SYSCON_2
);
2282 seq_printf(s
, "otg_syscon2 %08x%s" EIGHTBITS
2283 " b_ase_brst=%d hmc=%d\n", tmp
,
2284 (tmp
& OTG_EN
) ? " otg_en" : "",
2285 (tmp
& USBX_SYNCHRO
) ? " synchro" : "",
2286 /* much more SRP stuff */
2287 (tmp
& SRP_DATA
) ? " srp_data" : "",
2288 (tmp
& SRP_VBUS
) ? " srp_vbus" : "",
2289 (tmp
& OTG_PADEN
) ? " otg_paden" : "",
2290 (tmp
& HMC_PADEN
) ? " hmc_paden" : "",
2291 (tmp
& UHOST_EN
) ? " uhost_en" : "",
2292 (tmp
& HMC_TLLSPEED
) ? " tllspeed" : "",
2293 (tmp
& HMC_TLLATTACH
) ? " tllattach" : "",
2296 tmp
= omap_readl(OTG_CTRL
);
2297 seq_printf(s
, "otg_ctrl %06x" EIGHTBITS EIGHTBITS
"%s\n", tmp
,
2298 (tmp
& OTG_ASESSVLD
) ? " asess" : "",
2299 (tmp
& OTG_BSESSEND
) ? " bsess_end" : "",
2300 (tmp
& OTG_BSESSVLD
) ? " bsess" : "",
2301 (tmp
& OTG_VBUSVLD
) ? " vbus" : "",
2302 (tmp
& OTG_ID
) ? " id" : "",
2303 (tmp
& OTG_DRIVER_SEL
) ? " DEVICE" : " HOST",
2304 (tmp
& OTG_A_SETB_HNPEN
) ? " a_setb_hnpen" : "",
2305 (tmp
& OTG_A_BUSREQ
) ? " a_bus" : "",
2306 (tmp
& OTG_B_HNPEN
) ? " b_hnpen" : "",
2307 (tmp
& OTG_B_BUSREQ
) ? " b_bus" : "",
2308 (tmp
& OTG_BUSDROP
) ? " busdrop" : "",
2309 (tmp
& OTG_PULLDOWN
) ? " down" : "",
2310 (tmp
& OTG_PULLUP
) ? " up" : "",
2311 (tmp
& OTG_DRV_VBUS
) ? " drv" : "",
2312 (tmp
& OTG_PD_VBUS
) ? " pd_vb" : "",
2313 (tmp
& OTG_PU_VBUS
) ? " pu_vb" : "",
2314 (tmp
& OTG_PU_ID
) ? " pu_id" : ""
2316 tmp
= omap_readw(OTG_IRQ_EN
);
2317 seq_printf(s
, "otg_irq_en %04x" "\n", tmp
);
2318 tmp
= omap_readw(OTG_IRQ_SRC
);
2319 seq_printf(s
, "otg_irq_src %04x" "\n", tmp
);
2320 tmp
= omap_readw(OTG_OUTCTRL
);
2321 seq_printf(s
, "otg_outctrl %04x" "\n", tmp
);
2322 tmp
= omap_readw(OTG_TEST
);
2323 seq_printf(s
, "otg_test %04x" "\n", tmp
);
2327 static int proc_udc_show(struct seq_file
*s
, void *_
)
2331 unsigned long flags
;
2333 spin_lock_irqsave(&udc
->lock
, flags
);
2335 seq_printf(s
, "%s, version: " DRIVER_VERSION
2341 use_dma
? " (dma)" : "");
2343 tmp
= omap_readw(UDC_REV
) & 0xff;
2345 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2346 "hmc %d, transceiver %s\n",
2347 tmp
>> 4, tmp
& 0xf,
2349 udc
->driver
? udc
->driver
->driver
.name
: "(none)",
2352 ? udc
->transceiver
->label
2353 : (cpu_is_omap1710()
2354 ? "external" : "(none)"));
2355 seq_printf(s
, "ULPD control %04x req %04x status %04x\n",
2356 omap_readw(ULPD_CLOCK_CTRL
),
2357 omap_readw(ULPD_SOFT_REQ
),
2358 omap_readw(ULPD_STATUS_REQ
));
2360 /* OTG controller registers */
2361 if (!cpu_is_omap15xx())
2364 tmp
= omap_readw(UDC_SYSCON1
);
2365 seq_printf(s
, "\nsyscon1 %04x" EIGHTBITS
"\n", tmp
,
2366 (tmp
& UDC_CFG_LOCK
) ? " cfg_lock" : "",
2367 (tmp
& UDC_DATA_ENDIAN
) ? " data_endian" : "",
2368 (tmp
& UDC_DMA_ENDIAN
) ? " dma_endian" : "",
2369 (tmp
& UDC_NAK_EN
) ? " nak" : "",
2370 (tmp
& UDC_AUTODECODE_DIS
) ? " autodecode_dis" : "",
2371 (tmp
& UDC_SELF_PWR
) ? " self_pwr" : "",
2372 (tmp
& UDC_SOFF_DIS
) ? " soff_dis" : "",
2373 (tmp
& UDC_PULLUP_EN
) ? " PULLUP" : "");
2374 /* syscon2 is write-only */
2376 /* UDC controller registers */
2377 if (!(tmp
& UDC_PULLUP_EN
)) {
2378 seq_printf(s
, "(suspended)\n");
2379 spin_unlock_irqrestore(&udc
->lock
, flags
);
2383 tmp
= omap_readw(UDC_DEVSTAT
);
2384 seq_printf(s
, "devstat %04x" EIGHTBITS
"%s%s\n", tmp
,
2385 (tmp
& UDC_B_HNP_ENABLE
) ? " b_hnp" : "",
2386 (tmp
& UDC_A_HNP_SUPPORT
) ? " a_hnp" : "",
2387 (tmp
& UDC_A_ALT_HNP_SUPPORT
) ? " a_alt_hnp" : "",
2388 (tmp
& UDC_R_WK_OK
) ? " r_wk_ok" : "",
2389 (tmp
& UDC_USB_RESET
) ? " usb_reset" : "",
2390 (tmp
& UDC_SUS
) ? " SUS" : "",
2391 (tmp
& UDC_CFG
) ? " CFG" : "",
2392 (tmp
& UDC_ADD
) ? " ADD" : "",
2393 (tmp
& UDC_DEF
) ? " DEF" : "",
2394 (tmp
& UDC_ATT
) ? " ATT" : "");
2395 seq_printf(s
, "sof %04x\n", omap_readw(UDC_SOF
));
2396 tmp
= omap_readw(UDC_IRQ_EN
);
2397 seq_printf(s
, "irq_en %04x" FOURBITS
"%s\n", tmp
,
2398 (tmp
& UDC_SOF_IE
) ? " sof" : "",
2399 (tmp
& UDC_EPN_RX_IE
) ? " epn_rx" : "",
2400 (tmp
& UDC_EPN_TX_IE
) ? " epn_tx" : "",
2401 (tmp
& UDC_DS_CHG_IE
) ? " ds_chg" : "",
2402 (tmp
& UDC_EP0_IE
) ? " ep0" : "");
2403 tmp
= omap_readw(UDC_IRQ_SRC
);
2404 seq_printf(s
, "irq_src %04x" EIGHTBITS
"%s%s\n", tmp
,
2405 (tmp
& UDC_TXN_DONE
) ? " txn_done" : "",
2406 (tmp
& UDC_RXN_CNT
) ? " rxn_cnt" : "",
2407 (tmp
& UDC_RXN_EOT
) ? " rxn_eot" : "",
2408 (tmp
& UDC_IRQ_SOF
) ? " sof" : "",
2409 (tmp
& UDC_EPN_RX
) ? " epn_rx" : "",
2410 (tmp
& UDC_EPN_TX
) ? " epn_tx" : "",
2411 (tmp
& UDC_DS_CHG
) ? " ds_chg" : "",
2412 (tmp
& UDC_SETUP
) ? " setup" : "",
2413 (tmp
& UDC_EP0_RX
) ? " ep0out" : "",
2414 (tmp
& UDC_EP0_TX
) ? " ep0in" : "");
2418 tmp
= omap_readw(UDC_DMA_IRQ_EN
);
2419 seq_printf(s
, "dma_irq_en %04x%s" EIGHTBITS
"\n", tmp
,
2420 (tmp
& UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2421 (tmp
& UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2422 (tmp
& UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2424 (tmp
& UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2425 (tmp
& UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2426 (tmp
& UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2428 (tmp
& UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2429 (tmp
& UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2430 (tmp
& UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2432 tmp
= omap_readw(UDC_RXDMA_CFG
);
2433 seq_printf(s
, "rxdma_cfg %04x\n", tmp
);
2435 for (i
= 0; i
< 3; i
++) {
2436 if ((tmp
& (0x0f << (i
* 4))) == 0)
2438 seq_printf(s
, "rxdma[%d] %04x\n", i
,
2439 omap_readw(UDC_RXDMA(i
+ 1)));
2442 tmp
= omap_readw(UDC_TXDMA_CFG
);
2443 seq_printf(s
, "txdma_cfg %04x\n", tmp
);
2445 for (i
= 0; i
< 3; i
++) {
2446 if (!(tmp
& (0x0f << (i
* 4))))
2448 seq_printf(s
, "txdma[%d] %04x\n", i
,
2449 omap_readw(UDC_TXDMA(i
+ 1)));
2454 tmp
= omap_readw(UDC_DEVSTAT
);
2455 if (tmp
& UDC_ATT
) {
2456 proc_ep_show(s
, &udc
->ep
[0]);
2457 if (tmp
& UDC_ADD
) {
2458 list_for_each_entry(ep
, &udc
->gadget
.ep_list
,
2461 proc_ep_show(s
, ep
);
2465 spin_unlock_irqrestore(&udc
->lock
, flags
);
2469 static int proc_udc_open(struct inode
*inode
, struct file
*file
)
2471 return single_open(file
, proc_udc_show
, NULL
);
2474 static const struct file_operations proc_ops
= {
2475 .owner
= THIS_MODULE
,
2476 .open
= proc_udc_open
,
2478 .llseek
= seq_lseek
,
2479 .release
= single_release
,
2482 static void create_proc_file(void)
2484 proc_create(proc_filename
, 0, NULL
, &proc_ops
);
2487 static void remove_proc_file(void)
2489 remove_proc_entry(proc_filename
, NULL
);
2494 static inline void create_proc_file(void) {}
2495 static inline void remove_proc_file(void) {}
2499 /*-------------------------------------------------------------------------*/
2501 /* Before this controller can enumerate, we need to pick an endpoint
2502 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2503 * buffer space among the endpoints we'll be operating.
2505 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2506 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2507 * capability yet though.
2509 static unsigned __devinit
2510 omap_ep_setup(char *name
, u8 addr
, u8 type
,
2511 unsigned buf
, unsigned maxp
, int dbuf
)
2516 /* OUT endpoints first, then IN */
2517 ep
= &udc
->ep
[addr
& 0xf];
2518 if (addr
& USB_DIR_IN
)
2521 /* in case of ep init table bugs */
2522 BUG_ON(ep
->name
[0]);
2524 /* chip setup ... bit values are same for IN, OUT */
2525 if (type
== USB_ENDPOINT_XFER_ISOC
) {
2551 epn_rxtx
|= UDC_EPN_RX_ISO
;
2554 /* double-buffering "not supported" on 15xx,
2555 * and ignored for PIO-IN on newer chips
2556 * (for more reliable behavior)
2558 if (!use_dma
|| cpu_is_omap15xx())
2578 epn_rxtx
|= UDC_EPN_RX_DB
;
2579 init_timer(&ep
->timer
);
2580 ep
->timer
.function
= pio_out_timer
;
2581 ep
->timer
.data
= (unsigned long) ep
;
2584 epn_rxtx
|= UDC_EPN_RX_VALID
;
2586 epn_rxtx
|= buf
>> 3;
2588 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2589 name
, addr
, epn_rxtx
, maxp
, dbuf
? "x2" : "", buf
);
2591 if (addr
& USB_DIR_IN
)
2592 omap_writew(epn_rxtx
, UDC_EP_TX(addr
& 0xf));
2594 omap_writew(epn_rxtx
, UDC_EP_RX(addr
));
2596 /* next endpoint's buffer starts after this one's */
2602 /* set up driver data structures */
2603 BUG_ON(strlen(name
) >= sizeof ep
->name
);
2604 strlcpy(ep
->name
, name
, sizeof ep
->name
);
2605 INIT_LIST_HEAD(&ep
->queue
);
2606 INIT_LIST_HEAD(&ep
->iso
);
2607 ep
->bEndpointAddress
= addr
;
2608 ep
->bmAttributes
= type
;
2609 ep
->double_buf
= dbuf
;
2612 ep
->ep
.name
= ep
->name
;
2613 ep
->ep
.ops
= &omap_ep_ops
;
2614 ep
->ep
.maxpacket
= ep
->maxpacket
= maxp
;
2615 list_add_tail(&ep
->ep
.ep_list
, &udc
->gadget
.ep_list
);
2620 static void omap_udc_release(struct device
*dev
)
2622 complete(udc
->done
);
2627 static int __devinit
2628 omap_udc_setup(struct platform_device
*odev
, struct usb_phy
*xceiv
)
2632 /* abolish any previous hardware state */
2633 omap_writew(0, UDC_SYSCON1
);
2634 omap_writew(0, UDC_IRQ_EN
);
2635 omap_writew(UDC_IRQ_SRC_MASK
, UDC_IRQ_SRC
);
2636 omap_writew(0, UDC_DMA_IRQ_EN
);
2637 omap_writew(0, UDC_RXDMA_CFG
);
2638 omap_writew(0, UDC_TXDMA_CFG
);
2640 /* UDC_PULLUP_EN gates the chip clock */
2641 /* OTG_SYSCON_1 |= DEV_IDLE_EN; */
2643 udc
= kzalloc(sizeof(*udc
), GFP_KERNEL
);
2647 spin_lock_init(&udc
->lock
);
2649 udc
->gadget
.ops
= &omap_gadget_ops
;
2650 udc
->gadget
.ep0
= &udc
->ep
[0].ep
;
2651 INIT_LIST_HEAD(&udc
->gadget
.ep_list
);
2652 INIT_LIST_HEAD(&udc
->iso
);
2653 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2654 udc
->gadget
.max_speed
= USB_SPEED_FULL
;
2655 udc
->gadget
.name
= driver_name
;
2657 device_initialize(&udc
->gadget
.dev
);
2658 dev_set_name(&udc
->gadget
.dev
, "gadget");
2659 udc
->gadget
.dev
.release
= omap_udc_release
;
2660 udc
->gadget
.dev
.parent
= &odev
->dev
;
2662 udc
->gadget
.dev
.dma_mask
= odev
->dev
.dma_mask
;
2664 udc
->transceiver
= xceiv
;
2666 /* ep0 is special; put it right after the SETUP buffer */
2667 buf
= omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL
,
2668 8 /* after SETUP */, 64 /* maxpacket */, 0);
2669 list_del_init(&udc
->ep
[0].ep
.ep_list
);
2671 /* initially disable all non-ep0 endpoints */
2672 for (tmp
= 1; tmp
< 15; tmp
++) {
2673 omap_writew(0, UDC_EP_RX(tmp
));
2674 omap_writew(0, UDC_EP_TX(tmp
));
2677 #define OMAP_BULK_EP(name, addr) \
2678 buf = omap_ep_setup(name "-bulk", addr, \
2679 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2680 #define OMAP_INT_EP(name, addr, maxp) \
2681 buf = omap_ep_setup(name "-int", addr, \
2682 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2683 #define OMAP_ISO_EP(name, addr, maxp) \
2684 buf = omap_ep_setup(name "-iso", addr, \
2685 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2687 switch (fifo_mode
) {
2689 OMAP_BULK_EP("ep1in", USB_DIR_IN
| 1);
2690 OMAP_BULK_EP("ep2out", USB_DIR_OUT
| 2);
2691 OMAP_INT_EP("ep3in", USB_DIR_IN
| 3, 16);
2694 OMAP_BULK_EP("ep1in", USB_DIR_IN
| 1);
2695 OMAP_BULK_EP("ep2out", USB_DIR_OUT
| 2);
2696 OMAP_INT_EP("ep9in", USB_DIR_IN
| 9, 16);
2698 OMAP_BULK_EP("ep3in", USB_DIR_IN
| 3);
2699 OMAP_BULK_EP("ep4out", USB_DIR_OUT
| 4);
2700 OMAP_INT_EP("ep10in", USB_DIR_IN
| 10, 16);
2702 OMAP_BULK_EP("ep5in", USB_DIR_IN
| 5);
2703 OMAP_BULK_EP("ep5out", USB_DIR_OUT
| 5);
2704 OMAP_INT_EP("ep11in", USB_DIR_IN
| 11, 16);
2706 OMAP_BULK_EP("ep6in", USB_DIR_IN
| 6);
2707 OMAP_BULK_EP("ep6out", USB_DIR_OUT
| 6);
2708 OMAP_INT_EP("ep12in", USB_DIR_IN
| 12, 16);
2710 OMAP_BULK_EP("ep7in", USB_DIR_IN
| 7);
2711 OMAP_BULK_EP("ep7out", USB_DIR_OUT
| 7);
2712 OMAP_INT_EP("ep13in", USB_DIR_IN
| 13, 16);
2713 OMAP_INT_EP("ep13out", USB_DIR_OUT
| 13, 16);
2715 OMAP_BULK_EP("ep8in", USB_DIR_IN
| 8);
2716 OMAP_BULK_EP("ep8out", USB_DIR_OUT
| 8);
2717 OMAP_INT_EP("ep14in", USB_DIR_IN
| 14, 16);
2718 OMAP_INT_EP("ep14out", USB_DIR_OUT
| 14, 16);
2720 OMAP_BULK_EP("ep15in", USB_DIR_IN
| 15);
2721 OMAP_BULK_EP("ep15out", USB_DIR_OUT
| 15);
2726 case 2: /* mixed iso/bulk */
2727 OMAP_ISO_EP("ep1in", USB_DIR_IN
| 1, 256);
2728 OMAP_ISO_EP("ep2out", USB_DIR_OUT
| 2, 256);
2729 OMAP_ISO_EP("ep3in", USB_DIR_IN
| 3, 128);
2730 OMAP_ISO_EP("ep4out", USB_DIR_OUT
| 4, 128);
2732 OMAP_INT_EP("ep5in", USB_DIR_IN
| 5, 16);
2734 OMAP_BULK_EP("ep6in", USB_DIR_IN
| 6);
2735 OMAP_BULK_EP("ep7out", USB_DIR_OUT
| 7);
2736 OMAP_INT_EP("ep8in", USB_DIR_IN
| 8, 16);
2738 case 3: /* mixed bulk/iso */
2739 OMAP_BULK_EP("ep1in", USB_DIR_IN
| 1);
2740 OMAP_BULK_EP("ep2out", USB_DIR_OUT
| 2);
2741 OMAP_INT_EP("ep3in", USB_DIR_IN
| 3, 16);
2743 OMAP_BULK_EP("ep4in", USB_DIR_IN
| 4);
2744 OMAP_BULK_EP("ep5out", USB_DIR_OUT
| 5);
2745 OMAP_INT_EP("ep6in", USB_DIR_IN
| 6, 16);
2747 OMAP_ISO_EP("ep7in", USB_DIR_IN
| 7, 256);
2748 OMAP_ISO_EP("ep8out", USB_DIR_OUT
| 8, 256);
2749 OMAP_INT_EP("ep9in", USB_DIR_IN
| 9, 16);
2753 /* add more modes as needed */
2756 ERR("unsupported fifo_mode #%d\n", fifo_mode
);
2759 omap_writew(UDC_CFG_LOCK
|UDC_SELF_PWR
, UDC_SYSCON1
);
2760 INFO("fifo mode %d, %d bytes not used\n", fifo_mode
, 2048 - buf
);
2764 static int __devinit
omap_udc_probe(struct platform_device
*pdev
)
2766 int status
= -ENODEV
;
2768 struct usb_phy
*xceiv
= NULL
;
2769 const char *type
= NULL
;
2770 struct omap_usb_config
*config
= pdev
->dev
.platform_data
;
2771 struct clk
*dc_clk
= NULL
;
2772 struct clk
*hhc_clk
= NULL
;
2774 if (cpu_is_omap7xx())
2777 /* NOTE: "knows" the order of the resources! */
2778 if (!request_mem_region(pdev
->resource
[0].start
,
2779 pdev
->resource
[0].end
- pdev
->resource
[0].start
+ 1,
2781 DBG("request_mem_region failed\n");
2785 if (cpu_is_omap16xx()) {
2786 dc_clk
= clk_get(&pdev
->dev
, "usb_dc_ck");
2787 hhc_clk
= clk_get(&pdev
->dev
, "usb_hhc_ck");
2788 BUG_ON(IS_ERR(dc_clk
) || IS_ERR(hhc_clk
));
2789 /* can't use omap_udc_enable_clock yet */
2791 clk_enable(hhc_clk
);
2795 if (cpu_is_omap7xx()) {
2796 dc_clk
= clk_get(&pdev
->dev
, "usb_dc_ck");
2797 hhc_clk
= clk_get(&pdev
->dev
, "l3_ocpi_ck");
2798 BUG_ON(IS_ERR(dc_clk
) || IS_ERR(hhc_clk
));
2799 /* can't use omap_udc_enable_clock yet */
2801 clk_enable(hhc_clk
);
2805 INFO("OMAP UDC rev %d.%d%s\n",
2806 omap_readw(UDC_REV
) >> 4, omap_readw(UDC_REV
) & 0xf,
2807 config
->otg
? ", Mini-AB" : "");
2809 /* use the mode given to us by board init code */
2810 if (cpu_is_omap15xx()) {
2814 if (machine_without_vbus_sense()) {
2815 /* just set up software VBUS detect, and then
2816 * later rig it so we always report VBUS.
2817 * FIXME without really sensing VBUS, we can't
2818 * know when to turn PULLUP_EN on/off; and that
2819 * means we always "need" the 48MHz clock.
2821 u32 tmp
= omap_readl(FUNC_MUX_CTRL_0
);
2822 tmp
&= ~VBUS_CTRL_1510
;
2823 omap_writel(tmp
, FUNC_MUX_CTRL_0
);
2824 tmp
|= VBUS_MODE_1510
;
2825 tmp
&= ~VBUS_CTRL_1510
;
2826 omap_writel(tmp
, FUNC_MUX_CTRL_0
);
2829 /* The transceiver may package some GPIO logic or handle
2830 * loopback and/or transceiverless setup; if we find one,
2831 * use it. Except for OTG, we don't _need_ to talk to one;
2832 * but not having one probably means no VBUS detection.
2834 xceiv
= usb_get_phy(USB_PHY_TYPE_USB2
);
2835 if (!IS_ERR_OR_NULL(xceiv
))
2836 type
= xceiv
->label
;
2837 else if (config
->otg
) {
2838 DBG("OTG requires external transceiver!\n");
2845 case 0: /* POWERUP DEFAULT == 0 */
2849 if (!cpu_is_omap1710()) {
2850 type
= "integrated";
2859 if (IS_ERR_OR_NULL(xceiv
)) {
2860 DBG("external transceiver not registered!\n");
2864 case 21: /* internal loopback */
2867 case 14: /* transceiverless */
2868 if (cpu_is_omap1710())
2878 ERR("unrecognized UDC HMC mode %d\n", hmc
);
2883 INFO("hmc mode %d, %s transceiver\n", hmc
, type
);
2885 /* a "gadget" abstracts/virtualizes the controller */
2886 status
= omap_udc_setup(pdev
, xceiv
);
2891 /* "udc" is now valid */
2892 pullup_disable(udc
);
2893 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2894 udc
->gadget
.is_otg
= (config
->otg
!= 0);
2897 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2898 if (omap_readw(UDC_REV
) >= 0x61)
2899 udc
->clr_halt
= UDC_RESET_EP
| UDC_CLRDATA_TOGGLE
;
2901 udc
->clr_halt
= UDC_RESET_EP
;
2903 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2904 status
= request_irq(pdev
->resource
[1].start
, omap_udc_irq
,
2905 0, driver_name
, udc
);
2907 ERR("can't get irq %d, err %d\n",
2908 (int) pdev
->resource
[1].start
, status
);
2912 /* USB "non-iso" IRQ (PIO for all but ep0) */
2913 status
= request_irq(pdev
->resource
[2].start
, omap_udc_pio_irq
,
2914 0, "omap_udc pio", udc
);
2916 ERR("can't get irq %d, err %d\n",
2917 (int) pdev
->resource
[2].start
, status
);
2921 status
= request_irq(pdev
->resource
[3].start
, omap_udc_iso_irq
,
2922 0, "omap_udc iso", udc
);
2924 ERR("can't get irq %d, err %d\n",
2925 (int) pdev
->resource
[3].start
, status
);
2929 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2930 udc
->dc_clk
= dc_clk
;
2931 udc
->hhc_clk
= hhc_clk
;
2932 clk_disable(hhc_clk
);
2933 clk_disable(dc_clk
);
2937 status
= device_add(&udc
->gadget
.dev
);
2941 status
= usb_add_gadget_udc(&pdev
->dev
, &udc
->gadget
);
2944 /* If fail, fall through */
2950 free_irq(pdev
->resource
[2].start
, udc
);
2954 free_irq(pdev
->resource
[1].start
, udc
);
2961 if (!IS_ERR_OR_NULL(xceiv
))
2964 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2965 clk_disable(hhc_clk
);
2966 clk_disable(dc_clk
);
2971 release_mem_region(pdev
->resource
[0].start
,
2972 pdev
->resource
[0].end
- pdev
->resource
[0].start
+ 1);
2977 static int __devexit
omap_udc_remove(struct platform_device
*pdev
)
2979 DECLARE_COMPLETION_ONSTACK(done
);
2984 usb_del_gadget_udc(&udc
->gadget
);
2990 pullup_disable(udc
);
2991 if (!IS_ERR_OR_NULL(udc
->transceiver
)) {
2992 usb_put_phy(udc
->transceiver
);
2993 udc
->transceiver
= NULL
;
2995 omap_writew(0, UDC_SYSCON1
);
3000 free_irq(pdev
->resource
[3].start
, udc
);
3002 free_irq(pdev
->resource
[2].start
, udc
);
3003 free_irq(pdev
->resource
[1].start
, udc
);
3006 if (udc
->clk_requested
)
3007 omap_udc_enable_clock(0);
3008 clk_put(udc
->hhc_clk
);
3009 clk_put(udc
->dc_clk
);
3012 release_mem_region(pdev
->resource
[0].start
,
3013 pdev
->resource
[0].end
- pdev
->resource
[0].start
+ 1);
3015 device_unregister(&udc
->gadget
.dev
);
3016 wait_for_completion(&done
);
3021 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3022 * system is forced into deep sleep
3024 * REVISIT we should probably reject suspend requests when there's a host
3025 * session active, rather than disconnecting, at least on boards that can
3026 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3027 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3028 * may involve talking to an external transceiver (e.g. isp1301).
3031 static int omap_udc_suspend(struct platform_device
*dev
, pm_message_t message
)
3035 devstat
= omap_readw(UDC_DEVSTAT
);
3037 /* we're requesting 48 MHz clock if the pullup is enabled
3038 * (== we're attached to the host) and we're not suspended,
3039 * which would prevent entry to deep sleep...
3041 if ((devstat
& UDC_ATT
) != 0 && (devstat
& UDC_SUS
) == 0) {
3042 WARNING("session active; suspend requires disconnect\n");
3043 omap_pullup(&udc
->gadget
, 0);
3049 static int omap_udc_resume(struct platform_device
*dev
)
3051 DBG("resume + wakeup/SRP\n");
3052 omap_pullup(&udc
->gadget
, 1);
3054 /* maybe the host would enumerate us if we nudged it */
3056 return omap_wakeup(&udc
->gadget
);
3059 /*-------------------------------------------------------------------------*/
3061 static struct platform_driver udc_driver
= {
3062 .probe
= omap_udc_probe
,
3063 .remove
= __devexit_p(omap_udc_remove
),
3064 .suspend
= omap_udc_suspend
,
3065 .resume
= omap_udc_resume
,
3067 .owner
= THIS_MODULE
,
3068 .name
= (char *) driver_name
,
3072 module_platform_driver(udc_driver
);
3074 MODULE_DESCRIPTION(DRIVER_DESC
);
3075 MODULE_LICENSE("GPL");
3076 MODULE_ALIAS("platform:omap_udc");