2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/of_platform.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/phy.h>
37 #include <linux/platform_data/s3c-hsotg.h>
41 #include "s3c-hsotg.h"
43 static const char * const s3c_hsotg_supply_names
[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
51 * Unfortunately there seems to be a limit of the amount of data that can
52 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
53 * packets (which practically means 1 packet and 63 bytes of data) when the
56 * This means if we are wanting to move >127 bytes of data, we need to
57 * split the transactions up, but just doing one packet at a time does
58 * not work (this may be an implicit DATA0 PID on first packet of the
59 * transaction) and doing 2 packets is outside the controller's limits.
61 * If we try to lower the MPS size for EP0, then no transfers work properly
62 * for EP0, and the system will fail basic enumeration. As no cause for this
63 * has currently been found, we cannot support any large IN transfers for
66 #define EP0_MPS_LIMIT 64
72 * struct s3c_hsotg_ep - driver endpoint definition.
73 * @ep: The gadget layer representation of the endpoint.
74 * @name: The driver generated name for the endpoint.
75 * @queue: Queue of requests for this endpoint.
76 * @parent: Reference back to the parent device structure.
77 * @req: The current request that the endpoint is processing. This is
78 * used to indicate an request has been loaded onto the endpoint
79 * and has yet to be completed (maybe due to data move, or simply
80 * awaiting an ack from the core all the data has been completed).
81 * @debugfs: File entry for debugfs file for this endpoint.
82 * @lock: State lock to protect contents of endpoint.
83 * @dir_in: Set to true if this endpoint is of the IN direction, which
84 * means that it is sending data to the Host.
85 * @index: The index for the endpoint registers.
86 * @mc: Multi Count - number of transactions per microframe
87 * @interval - Interval for periodic endpoints
88 * @name: The name array passed to the USB core.
89 * @halted: Set if the endpoint has been halted.
90 * @periodic: Set if this is a periodic ep, such as Interrupt
91 * @isochronous: Set if this is a isochronous ep
92 * @sent_zlp: Set if we've sent a zero-length packet.
93 * @total_data: The total number of data bytes done.
94 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
95 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
96 * @last_load: The offset of data for the last start of request.
97 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
99 * This is the driver's state for each registered enpoint, allowing it
100 * to keep track of transactions that need doing. Each endpoint has a
101 * lock to protect the state, to try and avoid using an overall lock
102 * for the host controller as much as possible.
104 * For periodic IN endpoints, we have fifo_size and fifo_load to try
105 * and keep track of the amount of data in the periodic FIFO for each
106 * of these as we don't have a status register that tells us how much
107 * is in each of them. (note, this may actually be useless information
108 * as in shared-fifo mode periodic in acts like a single-frame packet
109 * buffer than a fifo)
111 struct s3c_hsotg_ep
{
113 struct list_head queue
;
114 struct s3c_hsotg
*parent
;
115 struct s3c_hsotg_req
*req
;
116 struct dentry
*debugfs
;
119 unsigned long total_data
;
120 unsigned int size_loaded
;
121 unsigned int last_load
;
122 unsigned int fifo_load
;
123 unsigned short fifo_size
;
125 unsigned char dir_in
;
128 unsigned char interval
;
130 unsigned int halted
:1;
131 unsigned int periodic
:1;
132 unsigned int isochronous
:1;
133 unsigned int sent_zlp
:1;
139 * struct s3c_hsotg - driver state.
140 * @dev: The parent device supplied to the probe function
141 * @driver: USB gadget driver
142 * @phy: The otg phy transceiver structure for phy control.
143 * @plat: The platform specific configuration data. This can be removed once
144 * all SoCs support usb transceiver.
145 * @regs: The memory area mapped for accessing registers.
146 * @irq: The IRQ number we are using
147 * @supplies: Definition of USB power supplies
148 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
149 * @num_of_eps: Number of available EPs (excluding EP0)
150 * @debug_root: root directrory for debugfs.
151 * @debug_file: main status file for debugfs.
152 * @debug_fifo: FIFO status file for debugfs.
153 * @ep0_reply: Request used for ep0 reply.
154 * @ep0_buff: Buffer for EP0 reply data, if needed.
155 * @ctrl_buff: Buffer for EP0 control requests.
156 * @ctrl_req: Request for EP0 control packets.
157 * @setup: NAK management for EP0 SETUP
158 * @last_rst: Time of last reset
159 * @eps: The endpoints being supplied to the gadget framework
163 struct usb_gadget_driver
*driver
;
165 struct s3c_hsotg_plat
*plat
;
173 struct regulator_bulk_data supplies
[ARRAY_SIZE(s3c_hsotg_supply_names
)];
175 unsigned int dedicated_fifos
:1;
176 unsigned char num_of_eps
;
178 struct dentry
*debug_root
;
179 struct dentry
*debug_file
;
180 struct dentry
*debug_fifo
;
182 struct usb_request
*ep0_reply
;
183 struct usb_request
*ctrl_req
;
187 struct usb_gadget gadget
;
189 unsigned long last_rst
;
190 struct s3c_hsotg_ep
*eps
;
194 * struct s3c_hsotg_req - data transfer request
195 * @req: The USB gadget request
196 * @queue: The list of requests for the endpoint this is queued for.
197 * @in_progress: Has already had size/packets written to core
198 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
200 struct s3c_hsotg_req
{
201 struct usb_request req
;
202 struct list_head queue
;
203 unsigned char in_progress
;
204 unsigned char mapped
;
207 /* conversion functions */
208 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
210 return container_of(req
, struct s3c_hsotg_req
, req
);
213 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
215 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
218 static inline struct s3c_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
220 return container_of(gadget
, struct s3c_hsotg
, gadget
);
223 static inline void __orr32(void __iomem
*ptr
, u32 val
)
225 writel(readl(ptr
) | val
, ptr
);
228 static inline void __bic32(void __iomem
*ptr
, u32 val
)
230 writel(readl(ptr
) & ~val
, ptr
);
233 /* forward decleration of functions */
234 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
);
237 * using_dma - return the DMA status of the driver.
238 * @hsotg: The driver state.
240 * Return true if we're using DMA.
242 * Currently, we have the DMA support code worked into everywhere
243 * that needs it, but the AMBA DMA implementation in the hardware can
244 * only DMA from 32bit aligned addresses. This means that gadgets such
245 * as the CDC Ethernet cannot work as they often pass packets which are
248 * Unfortunately the choice to use DMA or not is global to the controller
249 * and seems to be only settable when the controller is being put through
250 * a core reset. This means we either need to fix the gadgets to take
251 * account of DMA alignment, or add bounce buffers (yuerk).
253 * Until this issue is sorted out, we always return 'false'.
255 static inline bool using_dma(struct s3c_hsotg
*hsotg
)
257 return false; /* support is not complete */
261 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
262 * @hsotg: The device state
263 * @ints: A bitmask of the interrupts to enable
265 static void s3c_hsotg_en_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
267 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
270 new_gsintmsk
= gsintmsk
| ints
;
272 if (new_gsintmsk
!= gsintmsk
) {
273 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
274 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
279 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
280 * @hsotg: The device state
281 * @ints: A bitmask of the interrupts to enable
283 static void s3c_hsotg_disable_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
285 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
288 new_gsintmsk
= gsintmsk
& ~ints
;
290 if (new_gsintmsk
!= gsintmsk
)
291 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
295 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
296 * @hsotg: The device state
297 * @ep: The endpoint index
298 * @dir_in: True if direction is in.
299 * @en: The enable value, true to enable
301 * Set or clear the mask for an individual endpoint's interrupt
304 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg
*hsotg
,
305 unsigned int ep
, unsigned int dir_in
,
315 local_irq_save(flags
);
316 daint
= readl(hsotg
->regs
+ DAINTMSK
);
321 writel(daint
, hsotg
->regs
+ DAINTMSK
);
322 local_irq_restore(flags
);
326 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
327 * @hsotg: The device instance.
329 static void s3c_hsotg_init_fifo(struct s3c_hsotg
*hsotg
)
337 /* set FIFO sizes to 2048/1024 */
339 writel(2048, hsotg
->regs
+ GRXFSIZ
);
340 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
341 GNPTXFSIZ_NPTxFDep(1024),
342 hsotg
->regs
+ GNPTXFSIZ
);
345 * arange all the rest of the TX FIFOs, as some versions of this
346 * block have overlapping default addresses. This also ensures
347 * that if the settings have been changed, then they are set to
351 /* start at the end of the GNPTXFSIZ, rounded up */
356 * currently we allocate TX FIFOs for all possible endpoints,
357 * and assume that they are all the same size.
360 for (ep
= 1; ep
<= 15; ep
++) {
362 val
|= size
<< DPTXFSIZn_DPTxFSize_SHIFT
;
365 writel(val
, hsotg
->regs
+ DPTXFSIZn(ep
));
369 * according to p428 of the design guide, we need to ensure that
370 * all fifos are flushed before continuing
373 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh
|
374 GRSTCTL_RxFFlsh
, hsotg
->regs
+ GRSTCTL
);
376 /* wait until the fifos are both flushed */
379 val
= readl(hsotg
->regs
+ GRSTCTL
);
381 if ((val
& (GRSTCTL_TxFFlsh
| GRSTCTL_RxFFlsh
)) == 0)
384 if (--timeout
== 0) {
386 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
393 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
397 * @ep: USB endpoint to allocate request for.
398 * @flags: Allocation flags
400 * Allocate a new USB request structure appropriate for the specified endpoint
402 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
405 struct s3c_hsotg_req
*req
;
407 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
411 INIT_LIST_HEAD(&req
->queue
);
417 * is_ep_periodic - return true if the endpoint is in periodic mode.
418 * @hs_ep: The endpoint to query.
420 * Returns true if the endpoint is in periodic mode, meaning it is being
421 * used for an Interrupt or ISO transfer.
423 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
425 return hs_ep
->periodic
;
429 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
430 * @hsotg: The device state.
431 * @hs_ep: The endpoint for the request
432 * @hs_req: The request being processed.
434 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
435 * of a request to ensure the buffer is ready for access by the caller.
437 static void s3c_hsotg_unmap_dma(struct s3c_hsotg
*hsotg
,
438 struct s3c_hsotg_ep
*hs_ep
,
439 struct s3c_hsotg_req
*hs_req
)
441 struct usb_request
*req
= &hs_req
->req
;
443 /* ignore this if we're not moving any data */
444 if (hs_req
->req
.length
== 0)
447 usb_gadget_unmap_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
451 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
452 * @hsotg: The controller state.
453 * @hs_ep: The endpoint we're going to write for.
454 * @hs_req: The request to write data for.
456 * This is called when the TxFIFO has some space in it to hold a new
457 * transmission and we have something to give it. The actual setup of
458 * the data size is done elsewhere, so all we have to do is to actually
461 * The return value is zero if there is more space (or nothing was done)
462 * otherwise -ENOSPC is returned if the FIFO space was used up.
464 * This routine is only needed for PIO
466 static int s3c_hsotg_write_fifo(struct s3c_hsotg
*hsotg
,
467 struct s3c_hsotg_ep
*hs_ep
,
468 struct s3c_hsotg_req
*hs_req
)
470 bool periodic
= is_ep_periodic(hs_ep
);
471 u32 gnptxsts
= readl(hsotg
->regs
+ GNPTXSTS
);
472 int buf_pos
= hs_req
->req
.actual
;
473 int to_write
= hs_ep
->size_loaded
;
479 to_write
-= (buf_pos
- hs_ep
->last_load
);
481 /* if there's nothing to write, get out early */
485 if (periodic
&& !hsotg
->dedicated_fifos
) {
486 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
491 * work out how much data was loaded so we can calculate
492 * how much data is left in the fifo.
495 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
498 * if shared fifo, we cannot write anything until the
499 * previous data has been completely sent.
501 if (hs_ep
->fifo_load
!= 0) {
502 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
506 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
508 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
510 /* how much of the data has moved */
511 size_done
= hs_ep
->size_loaded
- size_left
;
513 /* how much data is left in the fifo */
514 can_write
= hs_ep
->fifo_load
- size_done
;
515 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
516 __func__
, can_write
);
518 can_write
= hs_ep
->fifo_size
- can_write
;
519 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
520 __func__
, can_write
);
522 if (can_write
<= 0) {
523 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
526 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
527 can_write
= readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
532 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts
) == 0) {
534 "%s: no queue slots available (0x%08x)\n",
537 s3c_hsotg_en_gsint(hsotg
, GINTSTS_NPTxFEmp
);
541 can_write
= GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts
);
542 can_write
*= 4; /* fifo size is in 32bit quantities. */
545 max_transfer
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
547 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
548 __func__
, gnptxsts
, can_write
, to_write
, max_transfer
);
551 * limit to 512 bytes of data, it seems at least on the non-periodic
552 * FIFO, requests of >512 cause the endpoint to get stuck with a
553 * fragment of the end of the transfer in it.
559 * limit the write to one max-packet size worth of data, but allow
560 * the transfer to return that it did not run out of fifo space
563 if (to_write
> max_transfer
) {
564 to_write
= max_transfer
;
566 /* it's needed only when we do not use dedicated fifos */
567 if (!hsotg
->dedicated_fifos
)
568 s3c_hsotg_en_gsint(hsotg
,
569 periodic
? GINTSTS_PTxFEmp
:
573 /* see if we can write data */
575 if (to_write
> can_write
) {
576 to_write
= can_write
;
577 pkt_round
= to_write
% max_transfer
;
580 * Round the write down to an
581 * exact number of packets.
583 * Note, we do not currently check to see if we can ever
584 * write a full packet or not to the FIFO.
588 to_write
-= pkt_round
;
591 * enable correct FIFO interrupt to alert us when there
595 /* it's needed only when we do not use dedicated fifos */
596 if (!hsotg
->dedicated_fifos
)
597 s3c_hsotg_en_gsint(hsotg
,
598 periodic
? GINTSTS_PTxFEmp
:
602 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
603 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
608 hs_req
->req
.actual
= buf_pos
+ to_write
;
609 hs_ep
->total_data
+= to_write
;
612 hs_ep
->fifo_load
+= to_write
;
614 to_write
= DIV_ROUND_UP(to_write
, 4);
615 data
= hs_req
->req
.buf
+ buf_pos
;
617 writesl(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
619 return (to_write
>= can_write
) ? -ENOSPC
: 0;
623 * get_ep_limit - get the maximum data legnth for this endpoint
624 * @hs_ep: The endpoint
626 * Return the maximum data that can be queued in one go on a given endpoint
627 * so that transfers that are too long can be split.
629 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
631 int index
= hs_ep
->index
;
636 maxsize
= DxEPTSIZ_XferSize_LIMIT
+ 1;
637 maxpkt
= DxEPTSIZ_PktCnt_LIMIT
+ 1;
641 maxpkt
= DIEPTSIZ0_PktCnt_LIMIT
+ 1;
646 /* we made the constant loading easier above by using +1 */
651 * constrain by packet count if maxpkts*pktsize is greater
652 * than the length register size.
655 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
656 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
662 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
663 * @hsotg: The controller state.
664 * @hs_ep: The endpoint to process a request for
665 * @hs_req: The request to start.
666 * @continuing: True if we are doing more for the current request.
668 * Start the given request running by setting the endpoint registers
669 * appropriately, and writing any data to the FIFOs.
671 static void s3c_hsotg_start_req(struct s3c_hsotg
*hsotg
,
672 struct s3c_hsotg_ep
*hs_ep
,
673 struct s3c_hsotg_req
*hs_req
,
676 struct usb_request
*ureq
= &hs_req
->req
;
677 int index
= hs_ep
->index
;
678 int dir_in
= hs_ep
->dir_in
;
688 if (hs_ep
->req
&& !continuing
) {
689 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
692 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
694 "%s: continue different req\n", __func__
);
700 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
701 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
703 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
704 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
705 hs_ep
->dir_in
? "in" : "out");
707 /* If endpoint is stalled, we will restart request later */
708 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
710 if (ctrl
& DxEPCTL_Stall
) {
711 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
715 length
= ureq
->length
- ureq
->actual
;
716 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
717 ureq
->length
, ureq
->actual
);
720 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
721 ureq
->buf
, length
, ureq
->dma
,
722 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
724 maxreq
= get_ep_limit(hs_ep
);
725 if (length
> maxreq
) {
726 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
728 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
729 __func__
, length
, maxreq
, round
);
731 /* round down to multiple of packets */
739 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
741 packets
= 1; /* send one packet if length is zero. */
743 if (hs_ep
->isochronous
&& length
> (hs_ep
->mc
* hs_ep
->ep
.maxpacket
)) {
744 dev_err(hsotg
->dev
, "req length > maxpacket*mc\n");
748 if (dir_in
&& index
!= 0)
749 if (hs_ep
->isochronous
)
750 epsize
= DxEPTSIZ_MC(packets
);
752 epsize
= DxEPTSIZ_MC(1);
756 if (index
!= 0 && ureq
->zero
) {
758 * test for the packets being exactly right for the
762 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
766 epsize
|= DxEPTSIZ_PktCnt(packets
);
767 epsize
|= DxEPTSIZ_XferSize(length
);
769 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
770 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
772 /* store the request as the current one we're doing */
775 /* write size / packets */
776 writel(epsize
, hsotg
->regs
+ epsize_reg
);
778 if (using_dma(hsotg
) && !continuing
) {
779 unsigned int dma_reg
;
782 * write DMA address to control register, buffer already
783 * synced by s3c_hsotg_ep_queue().
786 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
787 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
789 dev_dbg(hsotg
->dev
, "%s: 0x%08x => 0x%08x\n",
790 __func__
, ureq
->dma
, dma_reg
);
793 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
794 ctrl
|= DxEPCTL_USBActEp
;
796 dev_dbg(hsotg
->dev
, "setup req:%d\n", hsotg
->setup
);
798 /* For Setup request do not clear NAK */
799 if (hsotg
->setup
&& index
== 0)
802 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
805 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
806 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
809 * set these, it seems that DMA support increments past the end
810 * of the packet buffer so we need to calculate the length from
813 hs_ep
->size_loaded
= length
;
814 hs_ep
->last_load
= ureq
->actual
;
816 if (dir_in
&& !using_dma(hsotg
)) {
817 /* set these anyway, we may need them for non-periodic in */
818 hs_ep
->fifo_load
= 0;
820 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
824 * clear the INTknTXFEmpMsk when we start request, more as a aide
825 * to debugging to see what is going on.
828 writel(DIEPMSK_INTknTXFEmpMsk
,
829 hsotg
->regs
+ DIEPINT(index
));
832 * Note, trying to clear the NAK here causes problems with transmit
833 * on the S3C6400 ending up with the TXFIFO becoming full.
836 /* check ep is enabled */
837 if (!(readl(hsotg
->regs
+ epctrl_reg
) & DxEPCTL_EPEna
))
839 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
840 index
, readl(hsotg
->regs
+ epctrl_reg
));
842 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n",
843 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
847 * s3c_hsotg_map_dma - map the DMA memory being used for the request
848 * @hsotg: The device state.
849 * @hs_ep: The endpoint the request is on.
850 * @req: The request being processed.
852 * We've been asked to queue a request, so ensure that the memory buffer
853 * is correctly setup for DMA. If we've been passed an extant DMA address
854 * then ensure the buffer has been synced to memory. If our buffer has no
855 * DMA memory, then we map the memory and mark our request to allow us to
856 * cleanup on completion.
858 static int s3c_hsotg_map_dma(struct s3c_hsotg
*hsotg
,
859 struct s3c_hsotg_ep
*hs_ep
,
860 struct usb_request
*req
)
862 struct s3c_hsotg_req
*hs_req
= our_req(req
);
865 /* if the length is zero, ignore the DMA data */
866 if (hs_req
->req
.length
== 0)
869 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
876 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
877 __func__
, req
->buf
, req
->length
);
882 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
885 struct s3c_hsotg_req
*hs_req
= our_req(req
);
886 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
887 struct s3c_hsotg
*hs
= hs_ep
->parent
;
890 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
891 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
892 req
->zero
, req
->short_not_ok
);
894 /* initialise status of the request */
895 INIT_LIST_HEAD(&hs_req
->queue
);
897 req
->status
= -EINPROGRESS
;
899 /* if we're using DMA, sync the buffers as necessary */
901 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
906 first
= list_empty(&hs_ep
->queue
);
907 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
910 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
915 static int s3c_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
918 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
919 struct s3c_hsotg
*hs
= hs_ep
->parent
;
920 unsigned long flags
= 0;
923 spin_lock_irqsave(&hs
->lock
, flags
);
924 ret
= s3c_hsotg_ep_queue(ep
, req
, gfp_flags
);
925 spin_unlock_irqrestore(&hs
->lock
, flags
);
930 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
931 struct usb_request
*req
)
933 struct s3c_hsotg_req
*hs_req
= our_req(req
);
939 * s3c_hsotg_complete_oursetup - setup completion callback
940 * @ep: The endpoint the request was on.
941 * @req: The request completed.
943 * Called on completion of any requests the driver itself
944 * submitted that need cleaning up.
946 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
947 struct usb_request
*req
)
949 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
950 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
952 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
954 s3c_hsotg_ep_free_request(ep
, req
);
958 * ep_from_windex - convert control wIndex value to endpoint
959 * @hsotg: The driver state.
960 * @windex: The control request wIndex field (in host order).
962 * Convert the given wIndex into a pointer to an driver endpoint
963 * structure, or return NULL if it is not a valid endpoint.
965 static struct s3c_hsotg_ep
*ep_from_windex(struct s3c_hsotg
*hsotg
,
968 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
969 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
970 int idx
= windex
& 0x7F;
975 if (idx
> hsotg
->num_of_eps
)
978 if (idx
&& ep
->dir_in
!= dir
)
985 * s3c_hsotg_send_reply - send reply to control request
986 * @hsotg: The device state
988 * @buff: Buffer for request
989 * @length: Length of reply.
991 * Create a request and queue it on the given endpoint. This is useful as
992 * an internal method of sending replies to certain control requests, etc.
994 static int s3c_hsotg_send_reply(struct s3c_hsotg
*hsotg
,
995 struct s3c_hsotg_ep
*ep
,
999 struct usb_request
*req
;
1002 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1004 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1005 hsotg
->ep0_reply
= req
;
1007 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1011 req
->buf
= hsotg
->ep0_buff
;
1012 req
->length
= length
;
1013 req
->zero
= 1; /* always do zero-length final transfer */
1014 req
->complete
= s3c_hsotg_complete_oursetup
;
1017 memcpy(req
->buf
, buff
, length
);
1021 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1023 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1031 * s3c_hsotg_process_req_status - process request GET_STATUS
1032 * @hsotg: The device state
1033 * @ctrl: USB control request
1035 static int s3c_hsotg_process_req_status(struct s3c_hsotg
*hsotg
,
1036 struct usb_ctrlrequest
*ctrl
)
1038 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1039 struct s3c_hsotg_ep
*ep
;
1043 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1046 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1050 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1051 case USB_RECIP_DEVICE
:
1052 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1053 * bit 1 => remote wakeup */
1056 case USB_RECIP_INTERFACE
:
1057 /* currently, the data result should be zero */
1058 reply
= cpu_to_le16(0);
1061 case USB_RECIP_ENDPOINT
:
1062 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1066 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1073 if (le16_to_cpu(ctrl
->wLength
) != 2)
1076 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1078 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1085 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1088 * get_ep_head - return the first request on the endpoint
1089 * @hs_ep: The controller endpoint to get
1091 * Get the first request on the endpoint.
1093 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
1095 if (list_empty(&hs_ep
->queue
))
1098 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
1102 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1103 * @hsotg: The device state
1104 * @ctrl: USB control request
1106 static int s3c_hsotg_process_req_feature(struct s3c_hsotg
*hsotg
,
1107 struct usb_ctrlrequest
*ctrl
)
1109 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1110 struct s3c_hsotg_req
*hs_req
;
1112 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1113 struct s3c_hsotg_ep
*ep
;
1116 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1117 __func__
, set
? "SET" : "CLEAR");
1119 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
1120 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1122 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1123 __func__
, le16_to_cpu(ctrl
->wIndex
));
1127 switch (le16_to_cpu(ctrl
->wValue
)) {
1128 case USB_ENDPOINT_HALT
:
1129 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
1131 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1134 "%s: failed to send reply\n", __func__
);
1140 * If we have request in progress,
1146 list_del_init(&hs_req
->queue
);
1147 hs_req
->req
.complete(&ep
->ep
,
1151 /* If we have pending request, then start it */
1152 restart
= !list_empty(&ep
->queue
);
1154 hs_req
= get_ep_head(ep
);
1155 s3c_hsotg_start_req(hsotg
, ep
,
1166 return -ENOENT
; /* currently only deal with endpoint */
1171 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
);
1174 * s3c_hsotg_process_control - process a control request
1175 * @hsotg: The device state
1176 * @ctrl: The control request received
1178 * The controller has received the SETUP phase of a control request, and
1179 * needs to work out what to do next (and whether to pass it on to the
1182 static void s3c_hsotg_process_control(struct s3c_hsotg
*hsotg
,
1183 struct usb_ctrlrequest
*ctrl
)
1185 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1191 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1192 ctrl
->bRequest
, ctrl
->bRequestType
,
1193 ctrl
->wValue
, ctrl
->wLength
);
1196 * record the direction of the request, for later use when enquing
1200 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1201 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1204 * if we've no data with this request, then the last part of the
1205 * transaction is going to implicitly be IN.
1207 if (ctrl
->wLength
== 0)
1210 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1211 switch (ctrl
->bRequest
) {
1212 case USB_REQ_SET_ADDRESS
:
1213 dcfg
= readl(hsotg
->regs
+ DCFG
);
1214 dcfg
&= ~DCFG_DevAddr_MASK
;
1215 dcfg
|= ctrl
->wValue
<< DCFG_DevAddr_SHIFT
;
1216 writel(dcfg
, hsotg
->regs
+ DCFG
);
1218 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1220 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1223 case USB_REQ_GET_STATUS
:
1224 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1227 case USB_REQ_CLEAR_FEATURE
:
1228 case USB_REQ_SET_FEATURE
:
1229 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1234 /* as a fallback, try delivering it to the driver to deal with */
1236 if (ret
== 0 && hsotg
->driver
) {
1237 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1239 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1243 * the request is either unhandlable, or is not formatted correctly
1244 * so respond with a STALL for the status stage to indicate failure.
1251 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1252 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1255 * DxEPCTL_Stall will be cleared by EP once it has
1256 * taken effect, so no need to clear later.
1259 ctrl
= readl(hsotg
->regs
+ reg
);
1260 ctrl
|= DxEPCTL_Stall
;
1261 ctrl
|= DxEPCTL_CNAK
;
1262 writel(ctrl
, hsotg
->regs
+ reg
);
1265 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1266 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1269 * don't believe we need to anything more to get the EP
1270 * to reply with a STALL packet
1274 * complete won't be called, so we enqueue
1275 * setup request here
1277 s3c_hsotg_enqueue_setup(hsotg
);
1282 * s3c_hsotg_complete_setup - completion of a setup transfer
1283 * @ep: The endpoint the request was on.
1284 * @req: The request completed.
1286 * Called on completion of any requests the driver itself submitted for
1289 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1290 struct usb_request
*req
)
1292 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1293 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
1295 if (req
->status
< 0) {
1296 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1300 if (req
->actual
== 0)
1301 s3c_hsotg_enqueue_setup(hsotg
);
1303 s3c_hsotg_process_control(hsotg
, req
->buf
);
1307 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1308 * @hsotg: The device state.
1310 * Enqueue a request on EP0 if necessary to received any SETUP packets
1311 * received from the host.
1313 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
)
1315 struct usb_request
*req
= hsotg
->ctrl_req
;
1316 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1319 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1323 req
->buf
= hsotg
->ctrl_buff
;
1324 req
->complete
= s3c_hsotg_complete_setup
;
1326 if (!list_empty(&hs_req
->queue
)) {
1327 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1331 hsotg
->eps
[0].dir_in
= 0;
1333 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1335 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1337 * Don't think there's much we can do other than watch the
1344 * s3c_hsotg_complete_request - complete a request given to us
1345 * @hsotg: The device state.
1346 * @hs_ep: The endpoint the request was on.
1347 * @hs_req: The request to complete.
1348 * @result: The result code (0 => Ok, otherwise errno)
1350 * The given request has finished, so call the necessary completion
1351 * if it has one and then look to see if we can start a new request
1354 * Note, expects the ep to already be locked as appropriate.
1356 static void s3c_hsotg_complete_request(struct s3c_hsotg
*hsotg
,
1357 struct s3c_hsotg_ep
*hs_ep
,
1358 struct s3c_hsotg_req
*hs_req
,
1364 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1368 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1369 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1372 * only replace the status if we've not already set an error
1373 * from a previous transaction
1376 if (hs_req
->req
.status
== -EINPROGRESS
)
1377 hs_req
->req
.status
= result
;
1380 list_del_init(&hs_req
->queue
);
1382 if (using_dma(hsotg
))
1383 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1386 * call the complete request with the locks off, just in case the
1387 * request tries to queue more work for this endpoint.
1390 if (hs_req
->req
.complete
) {
1391 spin_unlock(&hsotg
->lock
);
1392 hs_req
->req
.complete(&hs_ep
->ep
, &hs_req
->req
);
1393 spin_lock(&hsotg
->lock
);
1397 * Look to see if there is anything else to do. Note, the completion
1398 * of the previous request may have caused a new request to be started
1399 * so be careful when doing this.
1402 if (!hs_ep
->req
&& result
>= 0) {
1403 restart
= !list_empty(&hs_ep
->queue
);
1405 hs_req
= get_ep_head(hs_ep
);
1406 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1412 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1413 * @hsotg: The device state.
1414 * @ep_idx: The endpoint index for the data
1415 * @size: The size of data in the fifo, in bytes
1417 * The FIFO status shows there is data to read from the FIFO for a given
1418 * endpoint, so sort out whether we need to read the data into a request
1419 * that has been made for that endpoint.
1421 static void s3c_hsotg_rx_data(struct s3c_hsotg
*hsotg
, int ep_idx
, int size
)
1423 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1424 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1425 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1432 u32 epctl
= readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1435 dev_warn(hsotg
->dev
,
1436 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1437 __func__
, size
, ep_idx
, epctl
);
1439 /* dump the data from the FIFO, we've nothing we can do */
1440 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1447 read_ptr
= hs_req
->req
.actual
;
1448 max_req
= hs_req
->req
.length
- read_ptr
;
1450 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1451 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1453 if (to_read
> max_req
) {
1455 * more data appeared than we where willing
1456 * to deal with in this request.
1459 /* currently we don't deal this */
1463 hs_ep
->total_data
+= to_read
;
1464 hs_req
->req
.actual
+= to_read
;
1465 to_read
= DIV_ROUND_UP(to_read
, 4);
1468 * note, we might over-write the buffer end by 3 bytes depending on
1469 * alignment of the data.
1471 readsl(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1475 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1476 * @hsotg: The device instance
1477 * @req: The request currently on this endpoint
1479 * Generate a zero-length IN packet request for terminating a SETUP
1482 * Note, since we don't write any data to the TxFIFO, then it is
1483 * currently believed that we do not need to wait for any space in
1486 static void s3c_hsotg_send_zlp(struct s3c_hsotg
*hsotg
,
1487 struct s3c_hsotg_req
*req
)
1492 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1496 if (req
->req
.length
== 0) {
1497 hsotg
->eps
[0].sent_zlp
= 1;
1498 s3c_hsotg_enqueue_setup(hsotg
);
1502 hsotg
->eps
[0].dir_in
= 1;
1503 hsotg
->eps
[0].sent_zlp
= 1;
1505 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1507 /* issue a zero-sized packet to terminate this */
1508 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1509 DxEPTSIZ_XferSize(0), hsotg
->regs
+ DIEPTSIZ(0));
1511 ctrl
= readl(hsotg
->regs
+ DIEPCTL0
);
1512 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
1513 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
1514 ctrl
|= DxEPCTL_USBActEp
;
1515 writel(ctrl
, hsotg
->regs
+ DIEPCTL0
);
1519 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1520 * @hsotg: The device instance
1521 * @epnum: The endpoint received from
1522 * @was_setup: Set if processing a SetupDone event.
1524 * The RXFIFO has delivered an OutDone event, which means that the data
1525 * transfer for an OUT endpoint has been completed, either by a short
1526 * packet or by the finish of a transfer.
1528 static void s3c_hsotg_handle_outdone(struct s3c_hsotg
*hsotg
,
1529 int epnum
, bool was_setup
)
1531 u32 epsize
= readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1532 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1533 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1534 struct usb_request
*req
= &hs_req
->req
;
1535 unsigned size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1539 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1543 if (using_dma(hsotg
)) {
1547 * Calculate the size of the transfer by checking how much
1548 * is left in the endpoint size register and then working it
1549 * out from the amount we loaded for the transfer.
1551 * We need to do this as DMA pointers are always 32bit aligned
1552 * so may overshoot/undershoot the transfer.
1555 size_done
= hs_ep
->size_loaded
- size_left
;
1556 size_done
+= hs_ep
->last_load
;
1558 req
->actual
= size_done
;
1561 /* if there is more request to do, schedule new transfer */
1562 if (req
->actual
< req
->length
&& size_left
== 0) {
1563 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1565 } else if (epnum
== 0) {
1567 * After was_setup = 1 =>
1568 * set CNAK for non Setup requests
1570 hsotg
->setup
= was_setup
? 0 : 1;
1573 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1574 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1575 __func__
, req
->actual
, req
->length
);
1578 * todo - what should we return here? there's no one else
1579 * even bothering to check the status.
1585 * Condition req->complete != s3c_hsotg_complete_setup says:
1586 * send ZLP when we have an asynchronous request from gadget
1588 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1589 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1592 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1596 * s3c_hsotg_read_frameno - read current frame number
1597 * @hsotg: The device instance
1599 * Return the current frame number
1601 static u32
s3c_hsotg_read_frameno(struct s3c_hsotg
*hsotg
)
1605 dsts
= readl(hsotg
->regs
+ DSTS
);
1606 dsts
&= DSTS_SOFFN_MASK
;
1607 dsts
>>= DSTS_SOFFN_SHIFT
;
1613 * s3c_hsotg_handle_rx - RX FIFO has data
1614 * @hsotg: The device instance
1616 * The IRQ handler has detected that the RX FIFO has some data in it
1617 * that requires processing, so find out what is in there and do the
1620 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1621 * chunks, so if you have x packets received on an endpoint you'll get x
1622 * FIFO events delivered, each with a packet's worth of data in it.
1624 * When using DMA, we should not be processing events from the RXFIFO
1625 * as the actual data should be sent to the memory directly and we turn
1626 * on the completion interrupts to get notifications of transfer completion.
1628 static void s3c_hsotg_handle_rx(struct s3c_hsotg
*hsotg
)
1630 u32 grxstsr
= readl(hsotg
->regs
+ GRXSTSP
);
1631 u32 epnum
, status
, size
;
1633 WARN_ON(using_dma(hsotg
));
1635 epnum
= grxstsr
& GRXSTS_EPNum_MASK
;
1636 status
= grxstsr
& GRXSTS_PktSts_MASK
;
1638 size
= grxstsr
& GRXSTS_ByteCnt_MASK
;
1639 size
>>= GRXSTS_ByteCnt_SHIFT
;
1642 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1643 __func__
, grxstsr
, size
, epnum
);
1645 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1647 switch (status
>> GRXSTS_PktSts_SHIFT
) {
1648 case __status(GRXSTS_PktSts_GlobalOutNAK
):
1649 dev_dbg(hsotg
->dev
, "GlobalOutNAK\n");
1652 case __status(GRXSTS_PktSts_OutDone
):
1653 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1654 s3c_hsotg_read_frameno(hsotg
));
1656 if (!using_dma(hsotg
))
1657 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1660 case __status(GRXSTS_PktSts_SetupDone
):
1662 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1663 s3c_hsotg_read_frameno(hsotg
),
1664 readl(hsotg
->regs
+ DOEPCTL(0)));
1666 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1669 case __status(GRXSTS_PktSts_OutRX
):
1670 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1673 case __status(GRXSTS_PktSts_SetupRX
):
1675 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1676 s3c_hsotg_read_frameno(hsotg
),
1677 readl(hsotg
->regs
+ DOEPCTL(0)));
1679 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1683 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1686 s3c_hsotg_dump(hsotg
);
1692 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1693 * @mps: The maximum packet size in bytes.
1695 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1699 return D0EPCTL_MPS_64
;
1701 return D0EPCTL_MPS_32
;
1703 return D0EPCTL_MPS_16
;
1705 return D0EPCTL_MPS_8
;
1708 /* bad max packet size, warn and return invalid result */
1714 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1715 * @hsotg: The driver state.
1716 * @ep: The index number of the endpoint
1717 * @mps: The maximum packet size in bytes
1719 * Configure the maximum packet size for the given endpoint, updating
1720 * the hardware control registers to reflect this.
1722 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg
*hsotg
,
1723 unsigned int ep
, unsigned int mps
)
1725 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1726 void __iomem
*regs
= hsotg
->regs
;
1732 /* EP0 is a special case */
1733 mpsval
= s3c_hsotg_ep0_mps(mps
);
1736 hs_ep
->ep
.maxpacket
= mps
;
1739 mpsval
= mps
& DxEPCTL_MPS_MASK
;
1742 mcval
= ((mps
>> 11) & 0x3) + 1;
1746 hs_ep
->ep
.maxpacket
= mpsval
;
1750 * update both the in and out endpoint controldir_ registers, even
1751 * if one of the directions may not be in use.
1754 reg
= readl(regs
+ DIEPCTL(ep
));
1755 reg
&= ~DxEPCTL_MPS_MASK
;
1757 writel(reg
, regs
+ DIEPCTL(ep
));
1760 reg
= readl(regs
+ DOEPCTL(ep
));
1761 reg
&= ~DxEPCTL_MPS_MASK
;
1763 writel(reg
, regs
+ DOEPCTL(ep
));
1769 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1773 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1774 * @hsotg: The driver state
1775 * @idx: The index for the endpoint (0..15)
1777 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg
*hsotg
, unsigned int idx
)
1782 writel(GRSTCTL_TxFNum(idx
) | GRSTCTL_TxFFlsh
,
1783 hsotg
->regs
+ GRSTCTL
);
1785 /* wait until the fifo is flushed */
1789 val
= readl(hsotg
->regs
+ GRSTCTL
);
1791 if ((val
& (GRSTCTL_TxFFlsh
)) == 0)
1794 if (--timeout
== 0) {
1796 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1805 * s3c_hsotg_trytx - check to see if anything needs transmitting
1806 * @hsotg: The driver state
1807 * @hs_ep: The driver endpoint to check.
1809 * Check to see if there is a request that has data to send, and if so
1810 * make an attempt to write data into the FIFO.
1812 static int s3c_hsotg_trytx(struct s3c_hsotg
*hsotg
,
1813 struct s3c_hsotg_ep
*hs_ep
)
1815 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1817 if (!hs_ep
->dir_in
|| !hs_req
)
1820 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1821 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1823 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1830 * s3c_hsotg_complete_in - complete IN transfer
1831 * @hsotg: The device state.
1832 * @hs_ep: The endpoint that has just completed.
1834 * An IN transfer has been completed, update the transfer's state and then
1835 * call the relevant completion routines.
1837 static void s3c_hsotg_complete_in(struct s3c_hsotg
*hsotg
,
1838 struct s3c_hsotg_ep
*hs_ep
)
1840 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1841 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1842 int size_left
, size_done
;
1845 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1849 /* Finish ZLP handling for IN EP0 transactions */
1850 if (hsotg
->eps
[0].sent_zlp
) {
1851 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1852 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1857 * Calculate the size of the transfer by checking how much is left
1858 * in the endpoint size register and then working it out from
1859 * the amount we loaded for the transfer.
1861 * We do this even for DMA, as the transfer may have incremented
1862 * past the end of the buffer (DMA transfers are always 32bit
1866 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1868 size_done
= hs_ep
->size_loaded
- size_left
;
1869 size_done
+= hs_ep
->last_load
;
1871 if (hs_req
->req
.actual
!= size_done
)
1872 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1873 __func__
, hs_req
->req
.actual
, size_done
);
1875 hs_req
->req
.actual
= size_done
;
1876 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1877 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1880 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1881 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1882 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1883 * inform the host that no more data is available.
1884 * The state of req.zero member is checked to be sure that the value to
1885 * send is smaller than wValue expected from host.
1886 * Check req.length to NOT send another ZLP when the current one is
1887 * under completion (the one for which this completion has been called).
1889 if (hs_req
->req
.length
&& hs_ep
->index
== 0 && hs_req
->req
.zero
&&
1890 hs_req
->req
.length
== hs_req
->req
.actual
&&
1891 !(hs_req
->req
.length
% hs_ep
->ep
.maxpacket
)) {
1893 dev_dbg(hsotg
->dev
, "ep0 zlp IN packet sent\n");
1894 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1899 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1900 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1901 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1903 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1907 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1908 * @hsotg: The driver state
1909 * @idx: The index for the endpoint (0..15)
1910 * @dir_in: Set if this is an IN endpoint
1912 * Process and clear any interrupt pending for an individual endpoint
1914 static void s3c_hsotg_epint(struct s3c_hsotg
*hsotg
, unsigned int idx
,
1917 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1918 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1919 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1920 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1924 ints
= readl(hsotg
->regs
+ epint_reg
);
1925 ctrl
= readl(hsotg
->regs
+ epctl_reg
);
1927 /* Clear endpoint interrupts */
1928 writel(ints
, hsotg
->regs
+ epint_reg
);
1930 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1931 __func__
, idx
, dir_in
? "in" : "out", ints
);
1933 if (ints
& DxEPINT_XferCompl
) {
1934 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1) {
1935 if (ctrl
& DxEPCTL_EOFrNum
)
1936 ctrl
|= DxEPCTL_SetEvenFr
;
1938 ctrl
|= DxEPCTL_SetOddFr
;
1939 writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1943 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1944 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1945 readl(hsotg
->regs
+ epsiz_reg
));
1948 * we get OutDone from the FIFO, so we only need to look
1949 * at completing IN requests here
1952 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1954 if (idx
== 0 && !hs_ep
->req
)
1955 s3c_hsotg_enqueue_setup(hsotg
);
1956 } else if (using_dma(hsotg
)) {
1958 * We're using DMA, we need to fire an OutDone here
1959 * as we ignore the RXFIFO.
1962 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1966 if (ints
& DxEPINT_EPDisbld
) {
1967 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1970 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1972 s3c_hsotg_txfifo_flush(hsotg
, idx
);
1974 if ((epctl
& DxEPCTL_Stall
) &&
1975 (epctl
& DxEPCTL_EPType_Bulk
)) {
1976 int dctl
= readl(hsotg
->regs
+ DCTL
);
1978 dctl
|= DCTL_CGNPInNAK
;
1979 writel(dctl
, hsotg
->regs
+ DCTL
);
1984 if (ints
& DxEPINT_AHBErr
)
1985 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1987 if (ints
& DxEPINT_Setup
) { /* Setup or Timeout */
1988 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1990 if (using_dma(hsotg
) && idx
== 0) {
1992 * this is the notification we've received a
1993 * setup packet. In non-DMA mode we'd get this
1994 * from the RXFIFO, instead we need to process
2001 s3c_hsotg_handle_outdone(hsotg
, 0, true);
2005 if (ints
& DxEPINT_Back2BackSetup
)
2006 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
2008 if (dir_in
&& !hs_ep
->isochronous
) {
2009 /* not sure if this is important, but we'll clear it anyway */
2010 if (ints
& DIEPMSK_INTknTXFEmpMsk
) {
2011 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
2015 /* this probably means something bad is happening */
2016 if (ints
& DIEPMSK_INTknEPMisMsk
) {
2017 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
2021 /* FIFO has space or is empty (see GAHBCFG) */
2022 if (hsotg
->dedicated_fifos
&&
2023 ints
& DIEPMSK_TxFIFOEmpty
) {
2024 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
2026 if (!using_dma(hsotg
))
2027 s3c_hsotg_trytx(hsotg
, hs_ep
);
2033 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2034 * @hsotg: The device state.
2036 * Handle updating the device settings after the enumeration phase has
2039 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg
*hsotg
)
2041 u32 dsts
= readl(hsotg
->regs
+ DSTS
);
2042 int ep0_mps
= 0, ep_mps
;
2045 * This should signal the finish of the enumeration phase
2046 * of the USB handshaking, so we should now know what rate
2050 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2053 * note, since we're limited by the size of transfer on EP0, and
2054 * it seems IN transfers must be a even number of packets we do
2055 * not advertise a 64byte MPS on EP0.
2058 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2059 switch (dsts
& DSTS_EnumSpd_MASK
) {
2060 case DSTS_EnumSpd_FS
:
2061 case DSTS_EnumSpd_FS48
:
2062 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2063 ep0_mps
= EP0_MPS_LIMIT
;
2067 case DSTS_EnumSpd_HS
:
2068 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
2069 ep0_mps
= EP0_MPS_LIMIT
;
2073 case DSTS_EnumSpd_LS
:
2074 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
2076 * note, we don't actually support LS in this driver at the
2077 * moment, and the documentation seems to imply that it isn't
2078 * supported by the PHYs on some of the devices.
2082 dev_info(hsotg
->dev
, "new device is %s\n",
2083 usb_speed_string(hsotg
->gadget
.speed
));
2086 * we should now know the maximum packet size for an
2087 * endpoint, so set the endpoints to a default value.
2092 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
2093 for (i
= 1; i
< hsotg
->num_of_eps
; i
++)
2094 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
2097 /* ensure after enumeration our EP0 is active */
2099 s3c_hsotg_enqueue_setup(hsotg
);
2101 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2102 readl(hsotg
->regs
+ DIEPCTL0
),
2103 readl(hsotg
->regs
+ DOEPCTL0
));
2107 * kill_all_requests - remove all requests from the endpoint's queue
2108 * @hsotg: The device state.
2109 * @ep: The endpoint the requests may be on.
2110 * @result: The result code to use.
2111 * @force: Force removal of any current requests
2113 * Go through the requests on the given endpoint and mark them
2114 * completed with the given result code.
2116 static void kill_all_requests(struct s3c_hsotg
*hsotg
,
2117 struct s3c_hsotg_ep
*ep
,
2118 int result
, bool force
)
2120 struct s3c_hsotg_req
*req
, *treq
;
2122 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2124 * currently, we can't do much about an already
2125 * running request on an in endpoint
2128 if (ep
->req
== req
&& ep
->dir_in
&& !force
)
2131 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2136 #define call_gadget(_hs, _entry) \
2138 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2139 (_hs)->driver && (_hs)->driver->_entry) { \
2140 spin_unlock(&_hs->lock); \
2141 (_hs)->driver->_entry(&(_hs)->gadget); \
2142 spin_lock(&_hs->lock); \
2147 * s3c_hsotg_disconnect - disconnect service
2148 * @hsotg: The device state.
2150 * The device has been disconnected. Remove all current
2151 * transactions and signal the gadget driver that this
2154 static void s3c_hsotg_disconnect(struct s3c_hsotg
*hsotg
)
2158 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2159 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
, true);
2161 call_gadget(hsotg
, disconnect
);
2165 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2166 * @hsotg: The device state:
2167 * @periodic: True if this is a periodic FIFO interrupt
2169 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg
*hsotg
, bool periodic
)
2171 struct s3c_hsotg_ep
*ep
;
2174 /* look through for any more data to transmit */
2176 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2177 ep
= &hsotg
->eps
[epno
];
2182 if ((periodic
&& !ep
->periodic
) ||
2183 (!periodic
&& ep
->periodic
))
2186 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2192 /* IRQ flags which will trigger a retry around the IRQ loop */
2193 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2198 * s3c_hsotg_corereset - issue softreset to the core
2199 * @hsotg: The device state
2201 * Issue a soft reset to the core, and await the core finishing it.
2203 static int s3c_hsotg_corereset(struct s3c_hsotg
*hsotg
)
2208 dev_dbg(hsotg
->dev
, "resetting core\n");
2210 /* issue soft reset */
2211 writel(GRSTCTL_CSftRst
, hsotg
->regs
+ GRSTCTL
);
2215 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2216 } while ((grstctl
& GRSTCTL_CSftRst
) && timeout
-- > 0);
2218 if (grstctl
& GRSTCTL_CSftRst
) {
2219 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2226 u32 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2228 if (timeout
-- < 0) {
2229 dev_info(hsotg
->dev
,
2230 "%s: reset failed, GRSTCTL=%08x\n",
2235 if (!(grstctl
& GRSTCTL_AHBIdle
))
2238 break; /* reset done */
2241 dev_dbg(hsotg
->dev
, "reset successful\n");
2246 * s3c_hsotg_core_init - issue softreset to the core
2247 * @hsotg: The device state
2249 * Issue a soft reset to the core, and await the core finishing it.
2251 static void s3c_hsotg_core_init(struct s3c_hsotg
*hsotg
)
2253 s3c_hsotg_corereset(hsotg
);
2256 * we must now enable ep0 ready for host detection and then
2257 * set configuration.
2260 /* set the PLL on, remove the HNP/SRP and set the PHY */
2261 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) |
2262 (0x5 << 10), hsotg
->regs
+ GUSBCFG
);
2264 s3c_hsotg_init_fifo(hsotg
);
2266 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2268 writel(1 << 18 | DCFG_DevSpd_HS
, hsotg
->regs
+ DCFG
);
2270 /* Clear any pending OTG interrupts */
2271 writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2273 /* Clear any pending interrupts */
2274 writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2276 writel(GINTSTS_ErlySusp
| GINTSTS_SessReqInt
|
2277 GINTSTS_GOUTNakEff
| GINTSTS_GINNakEff
|
2278 GINTSTS_ConIDStsChng
| GINTSTS_USBRst
|
2279 GINTSTS_EnumDone
| GINTSTS_OTGInt
|
2280 GINTSTS_USBSusp
| GINTSTS_WkUpInt
,
2281 hsotg
->regs
+ GINTMSK
);
2283 if (using_dma(hsotg
))
2284 writel(GAHBCFG_GlblIntrEn
| GAHBCFG_DMAEn
|
2285 GAHBCFG_HBstLen_Incr4
,
2286 hsotg
->regs
+ GAHBCFG
);
2288 writel(GAHBCFG_GlblIntrEn
, hsotg
->regs
+ GAHBCFG
);
2291 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2292 * up being flooded with interrupts if the host is polling the
2293 * endpoint to try and read data.
2296 writel(((hsotg
->dedicated_fifos
) ? DIEPMSK_TxFIFOEmpty
: 0) |
2297 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
|
2298 DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2299 DIEPMSK_INTknEPMisMsk
,
2300 hsotg
->regs
+ DIEPMSK
);
2303 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2304 * DMA mode we may need this.
2306 writel((using_dma(hsotg
) ? (DIEPMSK_XferComplMsk
|
2307 DIEPMSK_TimeOUTMsk
) : 0) |
2308 DOEPMSK_EPDisbldMsk
| DOEPMSK_AHBErrMsk
|
2310 hsotg
->regs
+ DOEPMSK
);
2312 writel(0, hsotg
->regs
+ DAINTMSK
);
2314 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2315 readl(hsotg
->regs
+ DIEPCTL0
),
2316 readl(hsotg
->regs
+ DOEPCTL0
));
2318 /* enable in and out endpoint interrupts */
2319 s3c_hsotg_en_gsint(hsotg
, GINTSTS_OEPInt
| GINTSTS_IEPInt
);
2322 * Enable the RXFIFO when in slave mode, as this is how we collect
2323 * the data. In DMA mode, we get events from the FIFO but also
2324 * things we cannot process, so do not use it.
2326 if (!using_dma(hsotg
))
2327 s3c_hsotg_en_gsint(hsotg
, GINTSTS_RxFLvl
);
2329 /* Enable interrupts for EP0 in and out */
2330 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2331 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2333 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2334 udelay(10); /* see openiboot */
2335 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2337 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ DCTL
));
2340 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2341 * writing to the EPCTL register..
2344 /* set to read 1 8byte packet */
2345 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2346 DxEPTSIZ_XferSize(8), hsotg
->regs
+ DOEPTSIZ0
);
2348 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2349 DxEPCTL_CNAK
| DxEPCTL_EPEna
|
2351 hsotg
->regs
+ DOEPCTL0
);
2353 /* enable, but don't activate EP0in */
2354 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2355 DxEPCTL_USBActEp
, hsotg
->regs
+ DIEPCTL0
);
2357 s3c_hsotg_enqueue_setup(hsotg
);
2359 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2360 readl(hsotg
->regs
+ DIEPCTL0
),
2361 readl(hsotg
->regs
+ DOEPCTL0
));
2363 /* clear global NAKs */
2364 writel(DCTL_CGOUTNak
| DCTL_CGNPInNAK
,
2365 hsotg
->regs
+ DCTL
);
2367 /* must be at-least 3ms to allow bus to see disconnect */
2370 /* remove the soft-disconnect and let's go */
2371 __bic32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2375 * s3c_hsotg_irq - handle device interrupt
2376 * @irq: The IRQ number triggered
2377 * @pw: The pw value when registered the handler.
2379 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2381 struct s3c_hsotg
*hsotg
= pw
;
2382 int retry_count
= 8;
2386 spin_lock(&hsotg
->lock
);
2388 gintsts
= readl(hsotg
->regs
+ GINTSTS
);
2389 gintmsk
= readl(hsotg
->regs
+ GINTMSK
);
2391 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2392 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2396 if (gintsts
& GINTSTS_OTGInt
) {
2397 u32 otgint
= readl(hsotg
->regs
+ GOTGINT
);
2399 dev_info(hsotg
->dev
, "OTGInt: %08x\n", otgint
);
2401 writel(otgint
, hsotg
->regs
+ GOTGINT
);
2404 if (gintsts
& GINTSTS_SessReqInt
) {
2405 dev_dbg(hsotg
->dev
, "%s: SessReqInt\n", __func__
);
2406 writel(GINTSTS_SessReqInt
, hsotg
->regs
+ GINTSTS
);
2409 if (gintsts
& GINTSTS_EnumDone
) {
2410 writel(GINTSTS_EnumDone
, hsotg
->regs
+ GINTSTS
);
2412 s3c_hsotg_irq_enumdone(hsotg
);
2415 if (gintsts
& GINTSTS_ConIDStsChng
) {
2416 dev_dbg(hsotg
->dev
, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2417 readl(hsotg
->regs
+ DSTS
),
2418 readl(hsotg
->regs
+ GOTGCTL
));
2420 writel(GINTSTS_ConIDStsChng
, hsotg
->regs
+ GINTSTS
);
2423 if (gintsts
& (GINTSTS_OEPInt
| GINTSTS_IEPInt
)) {
2424 u32 daint
= readl(hsotg
->regs
+ DAINT
);
2425 u32 daint_out
= daint
>> DAINT_OutEP_SHIFT
;
2426 u32 daint_in
= daint
& ~(daint_out
<< DAINT_OutEP_SHIFT
);
2429 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2431 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2433 s3c_hsotg_epint(hsotg
, ep
, 0);
2436 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2438 s3c_hsotg_epint(hsotg
, ep
, 1);
2442 if (gintsts
& GINTSTS_USBRst
) {
2444 u32 usb_status
= readl(hsotg
->regs
+ GOTGCTL
);
2446 dev_info(hsotg
->dev
, "%s: USBRst\n", __func__
);
2447 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2448 readl(hsotg
->regs
+ GNPTXSTS
));
2450 writel(GINTSTS_USBRst
, hsotg
->regs
+ GINTSTS
);
2452 if (usb_status
& GOTGCTL_BSESVLD
) {
2453 if (time_after(jiffies
, hsotg
->last_rst
+
2454 msecs_to_jiffies(200))) {
2456 kill_all_requests(hsotg
, &hsotg
->eps
[0],
2459 s3c_hsotg_core_init(hsotg
);
2460 hsotg
->last_rst
= jiffies
;
2465 /* check both FIFOs */
2467 if (gintsts
& GINTSTS_NPTxFEmp
) {
2468 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2471 * Disable the interrupt to stop it happening again
2472 * unless one of these endpoint routines decides that
2473 * it needs re-enabling
2476 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_NPTxFEmp
);
2477 s3c_hsotg_irq_fifoempty(hsotg
, false);
2480 if (gintsts
& GINTSTS_PTxFEmp
) {
2481 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2483 /* See note in GINTSTS_NPTxFEmp */
2485 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_PTxFEmp
);
2486 s3c_hsotg_irq_fifoempty(hsotg
, true);
2489 if (gintsts
& GINTSTS_RxFLvl
) {
2491 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2492 * we need to retry s3c_hsotg_handle_rx if this is still
2496 s3c_hsotg_handle_rx(hsotg
);
2499 if (gintsts
& GINTSTS_ModeMis
) {
2500 dev_warn(hsotg
->dev
, "warning, mode mismatch triggered\n");
2501 writel(GINTSTS_ModeMis
, hsotg
->regs
+ GINTSTS
);
2504 if (gintsts
& GINTSTS_USBSusp
) {
2505 dev_info(hsotg
->dev
, "GINTSTS_USBSusp\n");
2506 writel(GINTSTS_USBSusp
, hsotg
->regs
+ GINTSTS
);
2508 call_gadget(hsotg
, suspend
);
2509 s3c_hsotg_disconnect(hsotg
);
2512 if (gintsts
& GINTSTS_WkUpInt
) {
2513 dev_info(hsotg
->dev
, "GINTSTS_WkUpIn\n");
2514 writel(GINTSTS_WkUpInt
, hsotg
->regs
+ GINTSTS
);
2516 call_gadget(hsotg
, resume
);
2519 if (gintsts
& GINTSTS_ErlySusp
) {
2520 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2521 writel(GINTSTS_ErlySusp
, hsotg
->regs
+ GINTSTS
);
2525 * these next two seem to crop-up occasionally causing the core
2526 * to shutdown the USB transfer, so try clearing them and logging
2530 if (gintsts
& GINTSTS_GOUTNakEff
) {
2531 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2533 writel(DCTL_CGOUTNak
, hsotg
->regs
+ DCTL
);
2535 s3c_hsotg_dump(hsotg
);
2538 if (gintsts
& GINTSTS_GINNakEff
) {
2539 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2541 writel(DCTL_CGNPInNAK
, hsotg
->regs
+ DCTL
);
2543 s3c_hsotg_dump(hsotg
);
2547 * if we've had fifo events, we should try and go around the
2548 * loop again to see if there's any point in returning yet.
2551 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2554 spin_unlock(&hsotg
->lock
);
2560 * s3c_hsotg_ep_enable - enable the given endpoint
2561 * @ep: The USB endpint to configure
2562 * @desc: The USB endpoint descriptor to configure with.
2564 * This is called from the USB gadget code's usb_ep_enable().
2566 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2567 const struct usb_endpoint_descriptor
*desc
)
2569 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2570 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2571 unsigned long flags
;
2572 int index
= hs_ep
->index
;
2580 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2581 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2582 desc
->wMaxPacketSize
, desc
->bInterval
);
2584 /* not to be called for EP0 */
2585 WARN_ON(index
== 0);
2587 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2588 if (dir_in
!= hs_ep
->dir_in
) {
2589 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2593 mps
= usb_endpoint_maxp(desc
);
2595 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2597 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2598 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2600 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2601 __func__
, epctrl
, epctrl_reg
);
2603 spin_lock_irqsave(&hsotg
->lock
, flags
);
2605 epctrl
&= ~(DxEPCTL_EPType_MASK
| DxEPCTL_MPS_MASK
);
2606 epctrl
|= DxEPCTL_MPS(mps
);
2609 * mark the endpoint as active, otherwise the core may ignore
2610 * transactions entirely for this endpoint
2612 epctrl
|= DxEPCTL_USBActEp
;
2615 * set the NAK status on the endpoint, otherwise we might try and
2616 * do something with data that we've yet got a request to process
2617 * since the RXFIFO will take data for an endpoint even if the
2618 * size register hasn't been set.
2621 epctrl
|= DxEPCTL_SNAK
;
2623 /* update the endpoint state */
2624 s3c_hsotg_set_ep_maxpacket(hsotg
, hs_ep
->index
, mps
);
2626 /* default, set to non-periodic */
2627 hs_ep
->isochronous
= 0;
2628 hs_ep
->periodic
= 0;
2629 hs_ep
->interval
= desc
->bInterval
;
2631 if (hs_ep
->interval
> 1 && hs_ep
->mc
> 1)
2632 dev_err(hsotg
->dev
, "MC > 1 when interval is not 1\n");
2634 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2635 case USB_ENDPOINT_XFER_ISOC
:
2636 epctrl
|= DxEPCTL_EPType_Iso
;
2637 epctrl
|= DxEPCTL_SetEvenFr
;
2638 hs_ep
->isochronous
= 1;
2640 hs_ep
->periodic
= 1;
2643 case USB_ENDPOINT_XFER_BULK
:
2644 epctrl
|= DxEPCTL_EPType_Bulk
;
2647 case USB_ENDPOINT_XFER_INT
:
2650 * Allocate our TxFNum by simply using the index
2651 * of the endpoint for the moment. We could do
2652 * something better if the host indicates how
2653 * many FIFOs we are expecting to use.
2656 hs_ep
->periodic
= 1;
2657 epctrl
|= DxEPCTL_TxFNum(index
);
2660 epctrl
|= DxEPCTL_EPType_Intterupt
;
2663 case USB_ENDPOINT_XFER_CONTROL
:
2664 epctrl
|= DxEPCTL_EPType_Control
;
2669 * if the hardware has dedicated fifos, we must give each IN EP
2670 * a unique tx-fifo even if it is non-periodic.
2672 if (dir_in
&& hsotg
->dedicated_fifos
)
2673 epctrl
|= DxEPCTL_TxFNum(index
);
2675 /* for non control endpoints, set PID to D0 */
2677 epctrl
|= DxEPCTL_SetD0PID
;
2679 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2682 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2683 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2684 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2686 /* enable the endpoint interrupt */
2687 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2689 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2694 * s3c_hsotg_ep_disable - disable given endpoint
2695 * @ep: The endpoint to disable.
2697 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2699 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2700 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2701 int dir_in
= hs_ep
->dir_in
;
2702 int index
= hs_ep
->index
;
2703 unsigned long flags
;
2707 dev_info(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2709 if (ep
== &hsotg
->eps
[0].ep
) {
2710 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2714 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2716 spin_lock_irqsave(&hsotg
->lock
, flags
);
2717 /* terminate all requests with shutdown */
2718 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
, false);
2721 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2722 ctrl
&= ~DxEPCTL_EPEna
;
2723 ctrl
&= ~DxEPCTL_USBActEp
;
2724 ctrl
|= DxEPCTL_SNAK
;
2726 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2727 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2729 /* disable endpoint interrupts */
2730 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2732 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2737 * on_list - check request is on the given endpoint
2738 * @ep: The endpoint to check.
2739 * @test: The request to test if it is on the endpoint.
2741 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2743 struct s3c_hsotg_req
*req
, *treq
;
2745 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2754 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2755 * @ep: The endpoint to dequeue.
2756 * @req: The request to be removed from a queue.
2758 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2760 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2761 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2762 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2763 unsigned long flags
;
2765 dev_info(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2767 spin_lock_irqsave(&hs
->lock
, flags
);
2769 if (!on_list(hs_ep
, hs_req
)) {
2770 spin_unlock_irqrestore(&hs
->lock
, flags
);
2774 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2775 spin_unlock_irqrestore(&hs
->lock
, flags
);
2781 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2782 * @ep: The endpoint to set halt.
2783 * @value: Set or unset the halt.
2785 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2787 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2788 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2789 int index
= hs_ep
->index
;
2794 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2796 /* write both IN and OUT control registers */
2798 epreg
= DIEPCTL(index
);
2799 epctl
= readl(hs
->regs
+ epreg
);
2802 epctl
|= DxEPCTL_Stall
+ DxEPCTL_SNAK
;
2803 if (epctl
& DxEPCTL_EPEna
)
2804 epctl
|= DxEPCTL_EPDis
;
2806 epctl
&= ~DxEPCTL_Stall
;
2807 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2808 if (xfertype
== DxEPCTL_EPType_Bulk
||
2809 xfertype
== DxEPCTL_EPType_Intterupt
)
2810 epctl
|= DxEPCTL_SetD0PID
;
2813 writel(epctl
, hs
->regs
+ epreg
);
2815 epreg
= DOEPCTL(index
);
2816 epctl
= readl(hs
->regs
+ epreg
);
2819 epctl
|= DxEPCTL_Stall
;
2821 epctl
&= ~DxEPCTL_Stall
;
2822 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2823 if (xfertype
== DxEPCTL_EPType_Bulk
||
2824 xfertype
== DxEPCTL_EPType_Intterupt
)
2825 epctl
|= DxEPCTL_SetD0PID
;
2828 writel(epctl
, hs
->regs
+ epreg
);
2834 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2835 * @ep: The endpoint to set halt.
2836 * @value: Set or unset the halt.
2838 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
2840 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2841 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2842 unsigned long flags
= 0;
2845 spin_lock_irqsave(&hs
->lock
, flags
);
2846 ret
= s3c_hsotg_ep_sethalt(ep
, value
);
2847 spin_unlock_irqrestore(&hs
->lock
, flags
);
2852 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2853 .enable
= s3c_hsotg_ep_enable
,
2854 .disable
= s3c_hsotg_ep_disable
,
2855 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2856 .free_request
= s3c_hsotg_ep_free_request
,
2857 .queue
= s3c_hsotg_ep_queue_lock
,
2858 .dequeue
= s3c_hsotg_ep_dequeue
,
2859 .set_halt
= s3c_hsotg_ep_sethalt_lock
,
2860 /* note, don't believe we have any call for the fifo routines */
2864 * s3c_hsotg_phy_enable - enable platform phy dev
2865 * @hsotg: The driver state
2867 * A wrapper for platform code responsible for controlling
2868 * low-level USB code
2870 static void s3c_hsotg_phy_enable(struct s3c_hsotg
*hsotg
)
2872 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2874 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
2877 usb_phy_init(hsotg
->phy
);
2878 else if (hsotg
->plat
->phy_init
)
2879 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
2883 * s3c_hsotg_phy_disable - disable platform phy dev
2884 * @hsotg: The driver state
2886 * A wrapper for platform code responsible for controlling
2887 * low-level USB code
2889 static void s3c_hsotg_phy_disable(struct s3c_hsotg
*hsotg
)
2891 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2894 usb_phy_shutdown(hsotg
->phy
);
2895 else if (hsotg
->plat
->phy_exit
)
2896 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
2900 * s3c_hsotg_init - initalize the usb core
2901 * @hsotg: The driver state
2903 static void s3c_hsotg_init(struct s3c_hsotg
*hsotg
)
2905 /* unmask subset of endpoint interrupts */
2907 writel(DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2908 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
,
2909 hsotg
->regs
+ DIEPMSK
);
2911 writel(DOEPMSK_SetupMsk
| DOEPMSK_AHBErrMsk
|
2912 DOEPMSK_EPDisbldMsk
| DOEPMSK_XferComplMsk
,
2913 hsotg
->regs
+ DOEPMSK
);
2915 writel(0, hsotg
->regs
+ DAINTMSK
);
2917 /* Be in disconnected state until gadget is registered */
2918 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2921 /* post global nak until we're ready */
2922 writel(DCTL_SGNPInNAK
| DCTL_SGOUTNak
,
2923 hsotg
->regs
+ DCTL
);
2928 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2929 readl(hsotg
->regs
+ GRXFSIZ
),
2930 readl(hsotg
->regs
+ GNPTXFSIZ
));
2932 s3c_hsotg_init_fifo(hsotg
);
2934 /* set the PLL on, remove the HNP/SRP and set the PHY */
2935 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) | (0x5 << 10),
2936 hsotg
->regs
+ GUSBCFG
);
2938 writel(using_dma(hsotg
) ? GAHBCFG_DMAEn
: 0x0,
2939 hsotg
->regs
+ GAHBCFG
);
2943 * s3c_hsotg_udc_start - prepare the udc for work
2944 * @gadget: The usb gadget state
2945 * @driver: The usb gadget driver
2947 * Perform initialization to prepare udc device and driver
2950 static int s3c_hsotg_udc_start(struct usb_gadget
*gadget
,
2951 struct usb_gadget_driver
*driver
)
2953 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2957 pr_err("%s: called with no device\n", __func__
);
2962 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2966 if (driver
->max_speed
< USB_SPEED_FULL
)
2967 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2969 if (!driver
->setup
) {
2970 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2974 WARN_ON(hsotg
->driver
);
2976 driver
->driver
.bus
= NULL
;
2977 hsotg
->driver
= driver
;
2978 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
2979 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2981 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
2984 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
2988 hsotg
->last_rst
= jiffies
;
2989 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2993 hsotg
->driver
= NULL
;
2998 * s3c_hsotg_udc_stop - stop the udc
2999 * @gadget: The usb gadget state
3000 * @driver: The usb gadget driver
3002 * Stop udc hw block and stay tunned for future transmissions
3004 static int s3c_hsotg_udc_stop(struct usb_gadget
*gadget
,
3005 struct usb_gadget_driver
*driver
)
3007 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
3008 unsigned long flags
= 0;
3014 /* all endpoints should be shutdown */
3015 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
3016 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
3018 spin_lock_irqsave(&hsotg
->lock
, flags
);
3020 s3c_hsotg_phy_disable(hsotg
);
3023 hsotg
->driver
= NULL
;
3025 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3027 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3029 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3035 * s3c_hsotg_gadget_getframe - read the frame number
3036 * @gadget: The usb gadget state
3038 * Read the {micro} frame number
3040 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
3042 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
3046 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3047 * @gadget: The usb gadget state
3048 * @is_on: Current state of the USB PHY
3050 * Connect/Disconnect the USB PHY pullup
3052 static int s3c_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
3054 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
3055 unsigned long flags
= 0;
3057 dev_dbg(hsotg
->dev
, "%s: is_in: %d\n", __func__
, is_on
);
3059 spin_lock_irqsave(&hsotg
->lock
, flags
);
3061 s3c_hsotg_phy_enable(hsotg
);
3062 s3c_hsotg_core_init(hsotg
);
3064 s3c_hsotg_disconnect(hsotg
);
3065 s3c_hsotg_phy_disable(hsotg
);
3068 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3069 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3074 static const struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
3075 .get_frame
= s3c_hsotg_gadget_getframe
,
3076 .udc_start
= s3c_hsotg_udc_start
,
3077 .udc_stop
= s3c_hsotg_udc_stop
,
3078 .pullup
= s3c_hsotg_pullup
,
3082 * s3c_hsotg_initep - initialise a single endpoint
3083 * @hsotg: The device state.
3084 * @hs_ep: The endpoint to be initialised.
3085 * @epnum: The endpoint number
3087 * Initialise the given endpoint (as part of the probe and device state
3088 * creation) to give to the gadget driver. Setup the endpoint name, any
3089 * direction information and other state that may be required.
3091 static void s3c_hsotg_initep(struct s3c_hsotg
*hsotg
,
3092 struct s3c_hsotg_ep
*hs_ep
,
3100 else if ((epnum
% 2) == 0) {
3107 hs_ep
->index
= epnum
;
3109 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3111 INIT_LIST_HEAD(&hs_ep
->queue
);
3112 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3114 /* add to the list of endpoints known by the gadget driver */
3116 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3118 hs_ep
->parent
= hsotg
;
3119 hs_ep
->ep
.name
= hs_ep
->name
;
3120 hs_ep
->ep
.maxpacket
= epnum
? 1024 : EP0_MPS_LIMIT
;
3121 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
3124 * Read the FIFO size for the Periodic TX FIFO, even if we're
3125 * an OUT endpoint, we may as well do this if in future the
3126 * code is changed to make each endpoint's direction changeable.
3129 ptxfifo
= readl(hsotg
->regs
+ DPTXFSIZn(epnum
));
3130 hs_ep
->fifo_size
= DPTXFSIZn_DPTxFSize_GET(ptxfifo
) * 4;
3133 * if we're using dma, we need to set the next-endpoint pointer
3134 * to be something valid.
3137 if (using_dma(hsotg
)) {
3138 u32 next
= DxEPCTL_NextEp((epnum
+ 1) % 15);
3139 writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3140 writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3145 * s3c_hsotg_hw_cfg - read HW configuration registers
3146 * @param: The device state
3148 * Read the USB core HW configuration registers
3150 static void s3c_hsotg_hw_cfg(struct s3c_hsotg
*hsotg
)
3153 /* check hardware configuration */
3155 cfg2
= readl(hsotg
->regs
+ 0x48);
3156 hsotg
->num_of_eps
= (cfg2
>> 10) & 0xF;
3158 dev_info(hsotg
->dev
, "EPs:%d\n", hsotg
->num_of_eps
);
3160 cfg4
= readl(hsotg
->regs
+ 0x50);
3161 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
3163 dev_info(hsotg
->dev
, "%s fifos\n",
3164 hsotg
->dedicated_fifos
? "dedicated" : "shared");
3168 * s3c_hsotg_dump - dump state of the udc
3169 * @param: The device state
3171 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
)
3174 struct device
*dev
= hsotg
->dev
;
3175 void __iomem
*regs
= hsotg
->regs
;
3179 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3180 readl(regs
+ DCFG
), readl(regs
+ DCTL
),
3181 readl(regs
+ DIEPMSK
));
3183 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3184 readl(regs
+ GAHBCFG
), readl(regs
+ 0x44));
3186 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3187 readl(regs
+ GRXFSIZ
), readl(regs
+ GNPTXFSIZ
));
3189 /* show periodic fifo settings */
3191 for (idx
= 1; idx
<= 15; idx
++) {
3192 val
= readl(regs
+ DPTXFSIZn(idx
));
3193 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3194 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3195 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3198 for (idx
= 0; idx
< 15; idx
++) {
3200 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3201 readl(regs
+ DIEPCTL(idx
)),
3202 readl(regs
+ DIEPTSIZ(idx
)),
3203 readl(regs
+ DIEPDMA(idx
)));
3205 val
= readl(regs
+ DOEPCTL(idx
));
3207 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3208 idx
, readl(regs
+ DOEPCTL(idx
)),
3209 readl(regs
+ DOEPTSIZ(idx
)),
3210 readl(regs
+ DOEPDMA(idx
)));
3214 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3215 readl(regs
+ DVBUSDIS
), readl(regs
+ DVBUSPULSE
));
3220 * state_show - debugfs: show overall driver and device state.
3221 * @seq: The seq file to write to.
3222 * @v: Unused parameter.
3224 * This debugfs entry shows the overall state of the hardware and
3225 * some general information about each of the endpoints available
3228 static int state_show(struct seq_file
*seq
, void *v
)
3230 struct s3c_hsotg
*hsotg
= seq
->private;
3231 void __iomem
*regs
= hsotg
->regs
;
3234 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3237 readl(regs
+ DSTS
));
3239 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3240 readl(regs
+ DIEPMSK
), readl(regs
+ DOEPMSK
));
3242 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3243 readl(regs
+ GINTMSK
),
3244 readl(regs
+ GINTSTS
));
3246 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3247 readl(regs
+ DAINTMSK
),
3248 readl(regs
+ DAINT
));
3250 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3251 readl(regs
+ GNPTXSTS
),
3252 readl(regs
+ GRXSTSR
));
3254 seq_puts(seq
, "\nEndpoint status:\n");
3256 for (idx
= 0; idx
< 15; idx
++) {
3259 in
= readl(regs
+ DIEPCTL(idx
));
3260 out
= readl(regs
+ DOEPCTL(idx
));
3262 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3265 in
= readl(regs
+ DIEPTSIZ(idx
));
3266 out
= readl(regs
+ DOEPTSIZ(idx
));
3268 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3271 seq_puts(seq
, "\n");
3277 static int state_open(struct inode
*inode
, struct file
*file
)
3279 return single_open(file
, state_show
, inode
->i_private
);
3282 static const struct file_operations state_fops
= {
3283 .owner
= THIS_MODULE
,
3286 .llseek
= seq_lseek
,
3287 .release
= single_release
,
3291 * fifo_show - debugfs: show the fifo information
3292 * @seq: The seq_file to write data to.
3293 * @v: Unused parameter.
3295 * Show the FIFO information for the overall fifo and all the
3296 * periodic transmission FIFOs.
3298 static int fifo_show(struct seq_file
*seq
, void *v
)
3300 struct s3c_hsotg
*hsotg
= seq
->private;
3301 void __iomem
*regs
= hsotg
->regs
;
3305 seq_puts(seq
, "Non-periodic FIFOs:\n");
3306 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ GRXFSIZ
));
3308 val
= readl(regs
+ GNPTXFSIZ
);
3309 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3310 val
>> GNPTXFSIZ_NPTxFDep_SHIFT
,
3311 val
& GNPTXFSIZ_NPTxFStAddr_MASK
);
3313 seq_puts(seq
, "\nPeriodic TXFIFOs:\n");
3315 for (idx
= 1; idx
<= 15; idx
++) {
3316 val
= readl(regs
+ DPTXFSIZn(idx
));
3318 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3319 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3320 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3326 static int fifo_open(struct inode
*inode
, struct file
*file
)
3328 return single_open(file
, fifo_show
, inode
->i_private
);
3331 static const struct file_operations fifo_fops
= {
3332 .owner
= THIS_MODULE
,
3335 .llseek
= seq_lseek
,
3336 .release
= single_release
,
3340 static const char *decode_direction(int is_in
)
3342 return is_in
? "in" : "out";
3346 * ep_show - debugfs: show the state of an endpoint.
3347 * @seq: The seq_file to write data to.
3348 * @v: Unused parameter.
3350 * This debugfs entry shows the state of the given endpoint (one is
3351 * registered for each available).
3353 static int ep_show(struct seq_file
*seq
, void *v
)
3355 struct s3c_hsotg_ep
*ep
= seq
->private;
3356 struct s3c_hsotg
*hsotg
= ep
->parent
;
3357 struct s3c_hsotg_req
*req
;
3358 void __iomem
*regs
= hsotg
->regs
;
3359 int index
= ep
->index
;
3360 int show_limit
= 15;
3361 unsigned long flags
;
3363 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3364 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3366 /* first show the register state */
3368 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3369 readl(regs
+ DIEPCTL(index
)),
3370 readl(regs
+ DOEPCTL(index
)));
3372 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3373 readl(regs
+ DIEPDMA(index
)),
3374 readl(regs
+ DOEPDMA(index
)));
3376 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3377 readl(regs
+ DIEPINT(index
)),
3378 readl(regs
+ DOEPINT(index
)));
3380 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3381 readl(regs
+ DIEPTSIZ(index
)),
3382 readl(regs
+ DOEPTSIZ(index
)));
3384 seq_puts(seq
, "\n");
3385 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3386 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3388 seq_printf(seq
, "request list (%p,%p):\n",
3389 ep
->queue
.next
, ep
->queue
.prev
);
3391 spin_lock_irqsave(&hsotg
->lock
, flags
);
3393 list_for_each_entry(req
, &ep
->queue
, queue
) {
3394 if (--show_limit
< 0) {
3395 seq_puts(seq
, "not showing more requests...\n");
3399 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3400 req
== ep
->req
? '*' : ' ',
3401 req
, req
->req
.length
, req
->req
.buf
);
3402 seq_printf(seq
, "%d done, res %d\n",
3403 req
->req
.actual
, req
->req
.status
);
3406 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3411 static int ep_open(struct inode
*inode
, struct file
*file
)
3413 return single_open(file
, ep_show
, inode
->i_private
);
3416 static const struct file_operations ep_fops
= {
3417 .owner
= THIS_MODULE
,
3420 .llseek
= seq_lseek
,
3421 .release
= single_release
,
3425 * s3c_hsotg_create_debug - create debugfs directory and files
3426 * @hsotg: The driver state
3428 * Create the debugfs files to allow the user to get information
3429 * about the state of the system. The directory name is created
3430 * with the same name as the device itself, in case we end up
3431 * with multiple blocks in future systems.
3433 static void s3c_hsotg_create_debug(struct s3c_hsotg
*hsotg
)
3435 struct dentry
*root
;
3438 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3439 hsotg
->debug_root
= root
;
3441 dev_err(hsotg
->dev
, "cannot create debug root\n");
3445 /* create general state file */
3447 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3448 hsotg
, &state_fops
);
3450 if (IS_ERR(hsotg
->debug_file
))
3451 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3453 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3456 if (IS_ERR(hsotg
->debug_fifo
))
3457 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3459 /* create one file for each endpoint */
3461 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3462 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3464 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3465 root
, ep
, &ep_fops
);
3467 if (IS_ERR(ep
->debugfs
))
3468 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3474 * s3c_hsotg_delete_debug - cleanup debugfs entries
3475 * @hsotg: The driver state
3477 * Cleanup (remove) the debugfs files for use on module exit.
3479 static void s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg
)
3483 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3484 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3485 debugfs_remove(ep
->debugfs
);
3488 debugfs_remove(hsotg
->debug_file
);
3489 debugfs_remove(hsotg
->debug_fifo
);
3490 debugfs_remove(hsotg
->debug_root
);
3494 * s3c_hsotg_probe - probe function for hsotg driver
3495 * @pdev: The platform information for the driver
3498 static int s3c_hsotg_probe(struct platform_device
*pdev
)
3500 struct s3c_hsotg_plat
*plat
= dev_get_platdata(&pdev
->dev
);
3501 struct usb_phy
*phy
;
3502 struct device
*dev
= &pdev
->dev
;
3503 struct s3c_hsotg_ep
*eps
;
3504 struct s3c_hsotg
*hsotg
;
3505 struct resource
*res
;
3510 hsotg
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c_hsotg
), GFP_KERNEL
);
3512 dev_err(dev
, "cannot get memory\n");
3516 phy
= devm_usb_get_phy(dev
, USB_PHY_TYPE_USB2
);
3518 /* Fallback for pdata */
3519 plat
= dev_get_platdata(&pdev
->dev
);
3521 dev_err(&pdev
->dev
, "no platform data or transceiver defined\n");
3522 return -EPROBE_DEFER
;
3532 hsotg
->clk
= devm_clk_get(&pdev
->dev
, "otg");
3533 if (IS_ERR(hsotg
->clk
)) {
3534 dev_err(dev
, "cannot get otg clock\n");
3535 return PTR_ERR(hsotg
->clk
);
3538 platform_set_drvdata(pdev
, hsotg
);
3540 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3542 hsotg
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
3543 if (IS_ERR(hsotg
->regs
)) {
3544 ret
= PTR_ERR(hsotg
->regs
);
3548 ret
= platform_get_irq(pdev
, 0);
3550 dev_err(dev
, "cannot find IRQ\n");
3554 spin_lock_init(&hsotg
->lock
);
3558 ret
= devm_request_irq(&pdev
->dev
, hsotg
->irq
, s3c_hsotg_irq
, 0,
3559 dev_name(dev
), hsotg
);
3561 dev_err(dev
, "cannot claim IRQ\n");
3565 dev_info(dev
, "regs %p, irq %d\n", hsotg
->regs
, hsotg
->irq
);
3567 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3568 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3569 hsotg
->gadget
.name
= dev_name(dev
);
3571 /* reset the system */
3573 clk_prepare_enable(hsotg
->clk
);
3577 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3578 hsotg
->supplies
[i
].supply
= s3c_hsotg_supply_names
[i
];
3580 ret
= devm_regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3583 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3587 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3591 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
3595 /* usb phy enable */
3596 s3c_hsotg_phy_enable(hsotg
);
3598 s3c_hsotg_corereset(hsotg
);
3599 s3c_hsotg_init(hsotg
);
3600 s3c_hsotg_hw_cfg(hsotg
);
3602 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3604 if (hsotg
->num_of_eps
== 0) {
3605 dev_err(dev
, "wrong number of EPs (zero)\n");
3610 eps
= kcalloc(hsotg
->num_of_eps
+ 1, sizeof(struct s3c_hsotg_ep
),
3613 dev_err(dev
, "cannot get memory\n");
3620 /* setup endpoint information */
3622 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3623 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3625 /* allocate EP0 request */
3627 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3629 if (!hsotg
->ctrl_req
) {
3630 dev_err(dev
, "failed to allocate ctrl req\n");
3635 /* initialise the endpoints now the core has been initialised */
3636 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++)
3637 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3639 /* disable power and clock */
3641 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3644 dev_err(hsotg
->dev
, "failed to disable supplies: %d\n", ret
);
3648 s3c_hsotg_phy_disable(hsotg
);
3650 ret
= usb_add_gadget_udc(&pdev
->dev
, &hsotg
->gadget
);
3654 s3c_hsotg_create_debug(hsotg
);
3656 s3c_hsotg_dump(hsotg
);
3663 s3c_hsotg_phy_disable(hsotg
);
3665 clk_disable_unprepare(hsotg
->clk
);
3671 * s3c_hsotg_remove - remove function for hsotg driver
3672 * @pdev: The platform information for the driver
3674 static int s3c_hsotg_remove(struct platform_device
*pdev
)
3676 struct s3c_hsotg
*hsotg
= platform_get_drvdata(pdev
);
3678 usb_del_gadget_udc(&hsotg
->gadget
);
3680 s3c_hsotg_delete_debug(hsotg
);
3682 if (hsotg
->driver
) {
3683 /* should have been done already by driver model core */
3684 usb_gadget_unregister_driver(hsotg
->driver
);
3687 s3c_hsotg_phy_disable(hsotg
);
3688 clk_disable_unprepare(hsotg
->clk
);
3694 #define s3c_hsotg_suspend NULL
3695 #define s3c_hsotg_resume NULL
3699 static const struct of_device_id s3c_hsotg_of_ids
[] = {
3700 { .compatible
= "samsung,s3c6400-hsotg", },
3703 MODULE_DEVICE_TABLE(of
, s3c_hsotg_of_ids
);
3706 static struct platform_driver s3c_hsotg_driver
= {
3708 .name
= "s3c-hsotg",
3709 .owner
= THIS_MODULE
,
3710 .of_match_table
= of_match_ptr(s3c_hsotg_of_ids
),
3712 .probe
= s3c_hsotg_probe
,
3713 .remove
= s3c_hsotg_remove
,
3714 .suspend
= s3c_hsotg_suspend
,
3715 .resume
= s3c_hsotg_resume
,
3718 module_platform_driver(s3c_hsotg_driver
);
3720 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3721 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3722 MODULE_LICENSE("GPL");
3723 MODULE_ALIAS("platform:s3c-hsotg");