USB: s3c-hsotg: Remove DEBUG define
[deliverable/linux.git] / drivers / usb / host / ehci-sched.c
1 /*
2 * Copyright (c) 2001-2004 by David Brownell
3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software Foundation,
17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 /* this file is part of ehci-hcd.c */
21
22 /*-------------------------------------------------------------------------*/
23
24 /*
25 * EHCI scheduled transaction support: interrupt, iso, split iso
26 * These are called "periodic" transactions in the EHCI spec.
27 *
28 * Note that for interrupt transfers, the QH/QTD manipulation is shared
29 * with the "asynchronous" transaction support (control/bulk transfers).
30 * The only real difference is in how interrupt transfers are scheduled.
31 *
32 * For ISO, we make an "iso_stream" head to serve the same role as a QH.
33 * It keeps track of every ITD (or SITD) that's linked, and holds enough
34 * pre-calculated schedule data to make appending to the queue be quick.
35 */
36
37 static int ehci_get_frame (struct usb_hcd *hcd);
38
39 /*-------------------------------------------------------------------------*/
40
41 /*
42 * periodic_next_shadow - return "next" pointer on shadow list
43 * @periodic: host pointer to qh/itd/sitd
44 * @tag: hardware tag for type of this record
45 */
46 static union ehci_shadow *
47 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic,
48 __hc32 tag)
49 {
50 switch (hc32_to_cpu(ehci, tag)) {
51 case Q_TYPE_QH:
52 return &periodic->qh->qh_next;
53 case Q_TYPE_FSTN:
54 return &periodic->fstn->fstn_next;
55 case Q_TYPE_ITD:
56 return &periodic->itd->itd_next;
57 // case Q_TYPE_SITD:
58 default:
59 return &periodic->sitd->sitd_next;
60 }
61 }
62
63 static __hc32 *
64 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic,
65 __hc32 tag)
66 {
67 switch (hc32_to_cpu(ehci, tag)) {
68 /* our ehci_shadow.qh is actually software part */
69 case Q_TYPE_QH:
70 return &periodic->qh->hw->hw_next;
71 /* others are hw parts */
72 default:
73 return periodic->hw_next;
74 }
75 }
76
77 /* caller must hold ehci->lock */
78 static void periodic_unlink (struct ehci_hcd *ehci, unsigned frame, void *ptr)
79 {
80 union ehci_shadow *prev_p = &ehci->pshadow[frame];
81 __hc32 *hw_p = &ehci->periodic[frame];
82 union ehci_shadow here = *prev_p;
83
84 /* find predecessor of "ptr"; hw and shadow lists are in sync */
85 while (here.ptr && here.ptr != ptr) {
86 prev_p = periodic_next_shadow(ehci, prev_p,
87 Q_NEXT_TYPE(ehci, *hw_p));
88 hw_p = shadow_next_periodic(ehci, &here,
89 Q_NEXT_TYPE(ehci, *hw_p));
90 here = *prev_p;
91 }
92 /* an interrupt entry (at list end) could have been shared */
93 if (!here.ptr)
94 return;
95
96 /* update shadow and hardware lists ... the old "next" pointers
97 * from ptr may still be in use, the caller updates them.
98 */
99 *prev_p = *periodic_next_shadow(ehci, &here,
100 Q_NEXT_TYPE(ehci, *hw_p));
101 *hw_p = *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p));
102 }
103
104 /* how many of the uframe's 125 usecs are allocated? */
105 static unsigned short
106 periodic_usecs (struct ehci_hcd *ehci, unsigned frame, unsigned uframe)
107 {
108 __hc32 *hw_p = &ehci->periodic [frame];
109 union ehci_shadow *q = &ehci->pshadow [frame];
110 unsigned usecs = 0;
111 struct ehci_qh_hw *hw;
112
113 while (q->ptr) {
114 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
115 case Q_TYPE_QH:
116 hw = q->qh->hw;
117 /* is it in the S-mask? */
118 if (hw->hw_info2 & cpu_to_hc32(ehci, 1 << uframe))
119 usecs += q->qh->usecs;
120 /* ... or C-mask? */
121 if (hw->hw_info2 & cpu_to_hc32(ehci,
122 1 << (8 + uframe)))
123 usecs += q->qh->c_usecs;
124 hw_p = &hw->hw_next;
125 q = &q->qh->qh_next;
126 break;
127 // case Q_TYPE_FSTN:
128 default:
129 /* for "save place" FSTNs, count the relevant INTR
130 * bandwidth from the previous frame
131 */
132 if (q->fstn->hw_prev != EHCI_LIST_END(ehci)) {
133 ehci_dbg (ehci, "ignoring FSTN cost ...\n");
134 }
135 hw_p = &q->fstn->hw_next;
136 q = &q->fstn->fstn_next;
137 break;
138 case Q_TYPE_ITD:
139 if (q->itd->hw_transaction[uframe])
140 usecs += q->itd->stream->usecs;
141 hw_p = &q->itd->hw_next;
142 q = &q->itd->itd_next;
143 break;
144 case Q_TYPE_SITD:
145 /* is it in the S-mask? (count SPLIT, DATA) */
146 if (q->sitd->hw_uframe & cpu_to_hc32(ehci,
147 1 << uframe)) {
148 if (q->sitd->hw_fullspeed_ep &
149 cpu_to_hc32(ehci, 1<<31))
150 usecs += q->sitd->stream->usecs;
151 else /* worst case for OUT start-split */
152 usecs += HS_USECS_ISO (188);
153 }
154
155 /* ... C-mask? (count CSPLIT, DATA) */
156 if (q->sitd->hw_uframe &
157 cpu_to_hc32(ehci, 1 << (8 + uframe))) {
158 /* worst case for IN complete-split */
159 usecs += q->sitd->stream->c_usecs;
160 }
161
162 hw_p = &q->sitd->hw_next;
163 q = &q->sitd->sitd_next;
164 break;
165 }
166 }
167 #ifdef DEBUG
168 if (usecs > 100)
169 ehci_err (ehci, "uframe %d sched overrun: %d usecs\n",
170 frame * 8 + uframe, usecs);
171 #endif
172 return usecs;
173 }
174
175 /*-------------------------------------------------------------------------*/
176
177 static int same_tt (struct usb_device *dev1, struct usb_device *dev2)
178 {
179 if (!dev1->tt || !dev2->tt)
180 return 0;
181 if (dev1->tt != dev2->tt)
182 return 0;
183 if (dev1->tt->multi)
184 return dev1->ttport == dev2->ttport;
185 else
186 return 1;
187 }
188
189 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
190
191 /* Which uframe does the low/fullspeed transfer start in?
192 *
193 * The parameter is the mask of ssplits in "H-frame" terms
194 * and this returns the transfer start uframe in "B-frame" terms,
195 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0
196 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag
197 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7.
198 */
199 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
200 {
201 unsigned char smask = QH_SMASK & hc32_to_cpu(ehci, mask);
202 if (!smask) {
203 ehci_err(ehci, "invalid empty smask!\n");
204 /* uframe 7 can't have bw so this will indicate failure */
205 return 7;
206 }
207 return ffs(smask) - 1;
208 }
209
210 static const unsigned char
211 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
212
213 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
214 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
215 {
216 int i;
217 for (i=0; i<7; i++) {
218 if (max_tt_usecs[i] < tt_usecs[i]) {
219 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i];
220 tt_usecs[i] = max_tt_usecs[i];
221 }
222 }
223 }
224
225 /* How many of the tt's periodic downstream 1000 usecs are allocated?
226 *
227 * While this measures the bandwidth in terms of usecs/uframe,
228 * the low/fullspeed bus has no notion of uframes, so any particular
229 * low/fullspeed transfer can "carry over" from one uframe to the next,
230 * since the TT just performs downstream transfers in sequence.
231 *
232 * For example two separate 100 usec transfers can start in the same uframe,
233 * and the second one would "carry over" 75 usecs into the next uframe.
234 */
235 static void
236 periodic_tt_usecs (
237 struct ehci_hcd *ehci,
238 struct usb_device *dev,
239 unsigned frame,
240 unsigned short tt_usecs[8]
241 )
242 {
243 __hc32 *hw_p = &ehci->periodic [frame];
244 union ehci_shadow *q = &ehci->pshadow [frame];
245 unsigned char uf;
246
247 memset(tt_usecs, 0, 16);
248
249 while (q->ptr) {
250 switch (hc32_to_cpu(ehci, Q_NEXT_TYPE(ehci, *hw_p))) {
251 case Q_TYPE_ITD:
252 hw_p = &q->itd->hw_next;
253 q = &q->itd->itd_next;
254 continue;
255 case Q_TYPE_QH:
256 if (same_tt(dev, q->qh->dev)) {
257 uf = tt_start_uframe(ehci, q->qh->hw->hw_info2);
258 tt_usecs[uf] += q->qh->tt_usecs;
259 }
260 hw_p = &q->qh->hw->hw_next;
261 q = &q->qh->qh_next;
262 continue;
263 case Q_TYPE_SITD:
264 if (same_tt(dev, q->sitd->urb->dev)) {
265 uf = tt_start_uframe(ehci, q->sitd->hw_uframe);
266 tt_usecs[uf] += q->sitd->stream->tt_usecs;
267 }
268 hw_p = &q->sitd->hw_next;
269 q = &q->sitd->sitd_next;
270 continue;
271 // case Q_TYPE_FSTN:
272 default:
273 ehci_dbg(ehci, "ignoring periodic frame %d FSTN\n",
274 frame);
275 hw_p = &q->fstn->hw_next;
276 q = &q->fstn->fstn_next;
277 }
278 }
279
280 carryover_tt_bandwidth(tt_usecs);
281
282 if (max_tt_usecs[7] < tt_usecs[7])
283 ehci_err(ehci, "frame %d tt sched overrun: %d usecs\n",
284 frame, tt_usecs[7] - max_tt_usecs[7]);
285 }
286
287 /*
288 * Return true if the device's tt's downstream bus is available for a
289 * periodic transfer of the specified length (usecs), starting at the
290 * specified frame/uframe. Note that (as summarized in section 11.19
291 * of the usb 2.0 spec) TTs can buffer multiple transactions for each
292 * uframe.
293 *
294 * The uframe parameter is when the fullspeed/lowspeed transfer
295 * should be executed in "B-frame" terms, which is the same as the
296 * highspeed ssplit's uframe (which is in "H-frame" terms). For example
297 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0.
298 * See the EHCI spec sec 4.5 and fig 4.7.
299 *
300 * This checks if the full/lowspeed bus, at the specified starting uframe,
301 * has the specified bandwidth available, according to rules listed
302 * in USB 2.0 spec section 11.18.1 fig 11-60.
303 *
304 * This does not check if the transfer would exceed the max ssplit
305 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4,
306 * since proper scheduling limits ssplits to less than 16 per uframe.
307 */
308 static int tt_available (
309 struct ehci_hcd *ehci,
310 unsigned period,
311 struct usb_device *dev,
312 unsigned frame,
313 unsigned uframe,
314 u16 usecs
315 )
316 {
317 if ((period == 0) || (uframe >= 7)) /* error */
318 return 0;
319
320 for (; frame < ehci->periodic_size; frame += period) {
321 unsigned short tt_usecs[8];
322
323 periodic_tt_usecs (ehci, dev, frame, tt_usecs);
324
325 ehci_vdbg(ehci, "tt frame %d check %d usecs start uframe %d in"
326 " schedule %d/%d/%d/%d/%d/%d/%d/%d\n",
327 frame, usecs, uframe,
328 tt_usecs[0], tt_usecs[1], tt_usecs[2], tt_usecs[3],
329 tt_usecs[4], tt_usecs[5], tt_usecs[6], tt_usecs[7]);
330
331 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) {
332 ehci_vdbg(ehci, "frame %d uframe %d fully scheduled\n",
333 frame, uframe);
334 return 0;
335 }
336
337 /* special case for isoc transfers larger than 125us:
338 * the first and each subsequent fully used uframe
339 * must be empty, so as to not illegally delay
340 * already scheduled transactions
341 */
342 if (125 < usecs) {
343 int ufs = (usecs / 125);
344 int i;
345 for (i = uframe; i < (uframe + ufs) && i < 8; i++)
346 if (0 < tt_usecs[i]) {
347 ehci_vdbg(ehci,
348 "multi-uframe xfer can't fit "
349 "in frame %d uframe %d\n",
350 frame, i);
351 return 0;
352 }
353 }
354
355 tt_usecs[uframe] += usecs;
356
357 carryover_tt_bandwidth(tt_usecs);
358
359 /* fail if the carryover pushed bw past the last uframe's limit */
360 if (max_tt_usecs[7] < tt_usecs[7]) {
361 ehci_vdbg(ehci,
362 "tt unavailable usecs %d frame %d uframe %d\n",
363 usecs, frame, uframe);
364 return 0;
365 }
366 }
367
368 return 1;
369 }
370
371 #else
372
373 /* return true iff the device's transaction translator is available
374 * for a periodic transfer starting at the specified frame, using
375 * all the uframes in the mask.
376 */
377 static int tt_no_collision (
378 struct ehci_hcd *ehci,
379 unsigned period,
380 struct usb_device *dev,
381 unsigned frame,
382 u32 uf_mask
383 )
384 {
385 if (period == 0) /* error */
386 return 0;
387
388 /* note bandwidth wastage: split never follows csplit
389 * (different dev or endpoint) until the next uframe.
390 * calling convention doesn't make that distinction.
391 */
392 for (; frame < ehci->periodic_size; frame += period) {
393 union ehci_shadow here;
394 __hc32 type;
395 struct ehci_qh_hw *hw;
396
397 here = ehci->pshadow [frame];
398 type = Q_NEXT_TYPE(ehci, ehci->periodic [frame]);
399 while (here.ptr) {
400 switch (hc32_to_cpu(ehci, type)) {
401 case Q_TYPE_ITD:
402 type = Q_NEXT_TYPE(ehci, here.itd->hw_next);
403 here = here.itd->itd_next;
404 continue;
405 case Q_TYPE_QH:
406 hw = here.qh->hw;
407 if (same_tt (dev, here.qh->dev)) {
408 u32 mask;
409
410 mask = hc32_to_cpu(ehci,
411 hw->hw_info2);
412 /* "knows" no gap is needed */
413 mask |= mask >> 8;
414 if (mask & uf_mask)
415 break;
416 }
417 type = Q_NEXT_TYPE(ehci, hw->hw_next);
418 here = here.qh->qh_next;
419 continue;
420 case Q_TYPE_SITD:
421 if (same_tt (dev, here.sitd->urb->dev)) {
422 u16 mask;
423
424 mask = hc32_to_cpu(ehci, here.sitd
425 ->hw_uframe);
426 /* FIXME assumes no gap for IN! */
427 mask |= mask >> 8;
428 if (mask & uf_mask)
429 break;
430 }
431 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next);
432 here = here.sitd->sitd_next;
433 continue;
434 // case Q_TYPE_FSTN:
435 default:
436 ehci_dbg (ehci,
437 "periodic frame %d bogus type %d\n",
438 frame, type);
439 }
440
441 /* collision or error */
442 return 0;
443 }
444 }
445
446 /* no collision */
447 return 1;
448 }
449
450 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */
451
452 /*-------------------------------------------------------------------------*/
453
454 static int enable_periodic (struct ehci_hcd *ehci)
455 {
456 u32 cmd;
457 int status;
458
459 if (ehci->periodic_sched++)
460 return 0;
461
462 /* did clearing PSE did take effect yet?
463 * takes effect only at frame boundaries...
464 */
465 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
466 STS_PSS, 0, 9 * 125);
467 if (status)
468 return status;
469
470 cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
471 ehci_writel(ehci, cmd, &ehci->regs->command);
472 /* posted write ... PSS happens later */
473 ehci_to_hcd(ehci)->state = HC_STATE_RUNNING;
474
475 /* make sure ehci_work scans these */
476 ehci->next_uframe = ehci_readl(ehci, &ehci->regs->frame_index)
477 % (ehci->periodic_size << 3);
478 if (unlikely(ehci->broken_periodic))
479 ehci->last_periodic_enable = ktime_get_real();
480 return 0;
481 }
482
483 static int disable_periodic (struct ehci_hcd *ehci)
484 {
485 u32 cmd;
486 int status;
487
488 if (--ehci->periodic_sched)
489 return 0;
490
491 if (unlikely(ehci->broken_periodic)) {
492 /* delay experimentally determined */
493 ktime_t safe = ktime_add_us(ehci->last_periodic_enable, 1000);
494 ktime_t now = ktime_get_real();
495 s64 delay = ktime_us_delta(safe, now);
496
497 if (unlikely(delay > 0))
498 udelay(delay);
499 }
500
501 /* did setting PSE not take effect yet?
502 * takes effect only at frame boundaries...
503 */
504 status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
505 STS_PSS, STS_PSS, 9 * 125);
506 if (status)
507 return status;
508
509 cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
510 ehci_writel(ehci, cmd, &ehci->regs->command);
511 /* posted write ... */
512
513 free_cached_lists(ehci);
514
515 ehci->next_uframe = -1;
516 return 0;
517 }
518
519 /*-------------------------------------------------------------------------*/
520
521 /* periodic schedule slots have iso tds (normal or split) first, then a
522 * sparse tree for active interrupt transfers.
523 *
524 * this just links in a qh; caller guarantees uframe masks are set right.
525 * no FSTN support (yet; ehci 0.96+)
526 */
527 static int qh_link_periodic (struct ehci_hcd *ehci, struct ehci_qh *qh)
528 {
529 unsigned i;
530 unsigned period = qh->period;
531
532 dev_dbg (&qh->dev->dev,
533 "link qh%d-%04x/%p start %d [%d/%d us]\n",
534 period, hc32_to_cpup(ehci, &qh->hw->hw_info2)
535 & (QH_CMASK | QH_SMASK),
536 qh, qh->start, qh->usecs, qh->c_usecs);
537
538 /* high bandwidth, or otherwise every microframe */
539 if (period == 0)
540 period = 1;
541
542 for (i = qh->start; i < ehci->periodic_size; i += period) {
543 union ehci_shadow *prev = &ehci->pshadow[i];
544 __hc32 *hw_p = &ehci->periodic[i];
545 union ehci_shadow here = *prev;
546 __hc32 type = 0;
547
548 /* skip the iso nodes at list head */
549 while (here.ptr) {
550 type = Q_NEXT_TYPE(ehci, *hw_p);
551 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
552 break;
553 prev = periodic_next_shadow(ehci, prev, type);
554 hw_p = shadow_next_periodic(ehci, &here, type);
555 here = *prev;
556 }
557
558 /* sorting each branch by period (slow-->fast)
559 * enables sharing interior tree nodes
560 */
561 while (here.ptr && qh != here.qh) {
562 if (qh->period > here.qh->period)
563 break;
564 prev = &here.qh->qh_next;
565 hw_p = &here.qh->hw->hw_next;
566 here = *prev;
567 }
568 /* link in this qh, unless some earlier pass did that */
569 if (qh != here.qh) {
570 qh->qh_next = here;
571 if (here.qh)
572 qh->hw->hw_next = *hw_p;
573 wmb ();
574 prev->qh = qh;
575 *hw_p = QH_NEXT (ehci, qh->qh_dma);
576 }
577 }
578 qh->qh_state = QH_STATE_LINKED;
579 qh->xacterrs = 0;
580 qh_get (qh);
581
582 /* update per-qh bandwidth for usbfs */
583 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->period
584 ? ((qh->usecs + qh->c_usecs) / qh->period)
585 : (qh->usecs * 8);
586
587 /* maybe enable periodic schedule processing */
588 return enable_periodic(ehci);
589 }
590
591 static int qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh)
592 {
593 unsigned i;
594 unsigned period;
595
596 // FIXME:
597 // IF this isn't high speed
598 // and this qh is active in the current uframe
599 // (and overlay token SplitXstate is false?)
600 // THEN
601 // qh->hw_info1 |= cpu_to_hc32(1 << 7 /* "ignore" */);
602
603 /* high bandwidth, or otherwise part of every microframe */
604 if ((period = qh->period) == 0)
605 period = 1;
606
607 for (i = qh->start; i < ehci->periodic_size; i += period)
608 periodic_unlink (ehci, i, qh);
609
610 /* update per-qh bandwidth for usbfs */
611 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->period
612 ? ((qh->usecs + qh->c_usecs) / qh->period)
613 : (qh->usecs * 8);
614
615 dev_dbg (&qh->dev->dev,
616 "unlink qh%d-%04x/%p start %d [%d/%d us]\n",
617 qh->period,
618 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK),
619 qh, qh->start, qh->usecs, qh->c_usecs);
620
621 /* qh->qh_next still "live" to HC */
622 qh->qh_state = QH_STATE_UNLINK;
623 qh->qh_next.ptr = NULL;
624 qh_put (qh);
625
626 /* maybe turn off periodic schedule */
627 return disable_periodic(ehci);
628 }
629
630 static void intr_deschedule (struct ehci_hcd *ehci, struct ehci_qh *qh)
631 {
632 unsigned wait;
633 struct ehci_qh_hw *hw = qh->hw;
634 int rc;
635
636 /* If the QH isn't linked then there's nothing we can do
637 * unless we were called during a giveback, in which case
638 * qh_completions() has to deal with it.
639 */
640 if (qh->qh_state != QH_STATE_LINKED) {
641 if (qh->qh_state == QH_STATE_COMPLETING)
642 qh->needs_rescan = 1;
643 return;
644 }
645
646 qh_unlink_periodic (ehci, qh);
647
648 /* simple/paranoid: always delay, expecting the HC needs to read
649 * qh->hw_next or finish a writeback after SPLIT/CSPLIT ... and
650 * expect khubd to clean up after any CSPLITs we won't issue.
651 * active high speed queues may need bigger delays...
652 */
653 if (list_empty (&qh->qtd_list)
654 || (cpu_to_hc32(ehci, QH_CMASK)
655 & hw->hw_info2) != 0)
656 wait = 2;
657 else
658 wait = 55; /* worst case: 3 * 1024 */
659
660 udelay (wait);
661 qh->qh_state = QH_STATE_IDLE;
662 hw->hw_next = EHCI_LIST_END(ehci);
663 wmb ();
664
665 qh_completions(ehci, qh);
666
667 /* reschedule QH iff another request is queued */
668 if (!list_empty(&qh->qtd_list) &&
669 HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
670 rc = qh_schedule(ehci, qh);
671
672 /* An error here likely indicates handshake failure
673 * or no space left in the schedule. Neither fault
674 * should happen often ...
675 *
676 * FIXME kill the now-dysfunctional queued urbs
677 */
678 if (rc != 0)
679 ehci_err(ehci, "can't reschedule qh %p, err %d\n",
680 qh, rc);
681 }
682 }
683
684 /*-------------------------------------------------------------------------*/
685
686 static int check_period (
687 struct ehci_hcd *ehci,
688 unsigned frame,
689 unsigned uframe,
690 unsigned period,
691 unsigned usecs
692 ) {
693 int claimed;
694
695 /* complete split running into next frame?
696 * given FSTN support, we could sometimes check...
697 */
698 if (uframe >= 8)
699 return 0;
700
701 /*
702 * 80% periodic == 100 usec/uframe available
703 * convert "usecs we need" to "max already claimed"
704 */
705 usecs = 100 - usecs;
706
707 /* we "know" 2 and 4 uframe intervals were rejected; so
708 * for period 0, check _every_ microframe in the schedule.
709 */
710 if (unlikely (period == 0)) {
711 do {
712 for (uframe = 0; uframe < 7; uframe++) {
713 claimed = periodic_usecs (ehci, frame, uframe);
714 if (claimed > usecs)
715 return 0;
716 }
717 } while ((frame += 1) < ehci->periodic_size);
718
719 /* just check the specified uframe, at that period */
720 } else {
721 do {
722 claimed = periodic_usecs (ehci, frame, uframe);
723 if (claimed > usecs)
724 return 0;
725 } while ((frame += period) < ehci->periodic_size);
726 }
727
728 // success!
729 return 1;
730 }
731
732 static int check_intr_schedule (
733 struct ehci_hcd *ehci,
734 unsigned frame,
735 unsigned uframe,
736 const struct ehci_qh *qh,
737 __hc32 *c_maskp
738 )
739 {
740 int retval = -ENOSPC;
741 u8 mask = 0;
742
743 if (qh->c_usecs && uframe >= 6) /* FSTN territory? */
744 goto done;
745
746 if (!check_period (ehci, frame, uframe, qh->period, qh->usecs))
747 goto done;
748 if (!qh->c_usecs) {
749 retval = 0;
750 *c_maskp = 0;
751 goto done;
752 }
753
754 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
755 if (tt_available (ehci, qh->period, qh->dev, frame, uframe,
756 qh->tt_usecs)) {
757 unsigned i;
758
759 /* TODO : this may need FSTN for SSPLIT in uframe 5. */
760 for (i=uframe+1; i<8 && i<uframe+4; i++)
761 if (!check_period (ehci, frame, i,
762 qh->period, qh->c_usecs))
763 goto done;
764 else
765 mask |= 1 << i;
766
767 retval = 0;
768
769 *c_maskp = cpu_to_hc32(ehci, mask << 8);
770 }
771 #else
772 /* Make sure this tt's buffer is also available for CSPLITs.
773 * We pessimize a bit; probably the typical full speed case
774 * doesn't need the second CSPLIT.
775 *
776 * NOTE: both SPLIT and CSPLIT could be checked in just
777 * one smart pass...
778 */
779 mask = 0x03 << (uframe + qh->gap_uf);
780 *c_maskp = cpu_to_hc32(ehci, mask << 8);
781
782 mask |= 1 << uframe;
783 if (tt_no_collision (ehci, qh->period, qh->dev, frame, mask)) {
784 if (!check_period (ehci, frame, uframe + qh->gap_uf + 1,
785 qh->period, qh->c_usecs))
786 goto done;
787 if (!check_period (ehci, frame, uframe + qh->gap_uf,
788 qh->period, qh->c_usecs))
789 goto done;
790 retval = 0;
791 }
792 #endif
793 done:
794 return retval;
795 }
796
797 /* "first fit" scheduling policy used the first time through,
798 * or when the previous schedule slot can't be re-used.
799 */
800 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh)
801 {
802 int status;
803 unsigned uframe;
804 __hc32 c_mask;
805 unsigned frame; /* 0..(qh->period - 1), or NO_FRAME */
806 struct ehci_qh_hw *hw = qh->hw;
807
808 qh_refresh(ehci, qh);
809 hw->hw_next = EHCI_LIST_END(ehci);
810 frame = qh->start;
811
812 /* reuse the previous schedule slots, if we can */
813 if (frame < qh->period) {
814 uframe = ffs(hc32_to_cpup(ehci, &hw->hw_info2) & QH_SMASK);
815 status = check_intr_schedule (ehci, frame, --uframe,
816 qh, &c_mask);
817 } else {
818 uframe = 0;
819 c_mask = 0;
820 status = -ENOSPC;
821 }
822
823 /* else scan the schedule to find a group of slots such that all
824 * uframes have enough periodic bandwidth available.
825 */
826 if (status) {
827 /* "normal" case, uframing flexible except with splits */
828 if (qh->period) {
829 int i;
830
831 for (i = qh->period; status && i > 0; --i) {
832 frame = ++ehci->random_frame % qh->period;
833 for (uframe = 0; uframe < 8; uframe++) {
834 status = check_intr_schedule (ehci,
835 frame, uframe, qh,
836 &c_mask);
837 if (status == 0)
838 break;
839 }
840 }
841
842 /* qh->period == 0 means every uframe */
843 } else {
844 frame = 0;
845 status = check_intr_schedule (ehci, 0, 0, qh, &c_mask);
846 }
847 if (status)
848 goto done;
849 qh->start = frame;
850
851 /* reset S-frame and (maybe) C-frame masks */
852 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK));
853 hw->hw_info2 |= qh->period
854 ? cpu_to_hc32(ehci, 1 << uframe)
855 : cpu_to_hc32(ehci, QH_SMASK);
856 hw->hw_info2 |= c_mask;
857 } else
858 ehci_dbg (ehci, "reused qh %p schedule\n", qh);
859
860 /* stuff into the periodic schedule */
861 status = qh_link_periodic (ehci, qh);
862 done:
863 return status;
864 }
865
866 static int intr_submit (
867 struct ehci_hcd *ehci,
868 struct urb *urb,
869 struct list_head *qtd_list,
870 gfp_t mem_flags
871 ) {
872 unsigned epnum;
873 unsigned long flags;
874 struct ehci_qh *qh;
875 int status;
876 struct list_head empty;
877
878 /* get endpoint and transfer/schedule data */
879 epnum = urb->ep->desc.bEndpointAddress;
880
881 spin_lock_irqsave (&ehci->lock, flags);
882
883 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
884 status = -ESHUTDOWN;
885 goto done_not_linked;
886 }
887 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
888 if (unlikely(status))
889 goto done_not_linked;
890
891 /* get qh and force any scheduling errors */
892 INIT_LIST_HEAD (&empty);
893 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv);
894 if (qh == NULL) {
895 status = -ENOMEM;
896 goto done;
897 }
898 if (qh->qh_state == QH_STATE_IDLE) {
899 if ((status = qh_schedule (ehci, qh)) != 0)
900 goto done;
901 }
902
903 /* then queue the urb's tds to the qh */
904 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv);
905 BUG_ON (qh == NULL);
906
907 /* ... update usbfs periodic stats */
908 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++;
909
910 done:
911 if (unlikely(status))
912 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
913 done_not_linked:
914 spin_unlock_irqrestore (&ehci->lock, flags);
915 if (status)
916 qtd_list_free (ehci, urb, qtd_list);
917
918 return status;
919 }
920
921 /*-------------------------------------------------------------------------*/
922
923 /* ehci_iso_stream ops work with both ITD and SITD */
924
925 static struct ehci_iso_stream *
926 iso_stream_alloc (gfp_t mem_flags)
927 {
928 struct ehci_iso_stream *stream;
929
930 stream = kzalloc(sizeof *stream, mem_flags);
931 if (likely (stream != NULL)) {
932 INIT_LIST_HEAD(&stream->td_list);
933 INIT_LIST_HEAD(&stream->free_list);
934 stream->next_uframe = -1;
935 stream->refcount = 1;
936 }
937 return stream;
938 }
939
940 static void
941 iso_stream_init (
942 struct ehci_hcd *ehci,
943 struct ehci_iso_stream *stream,
944 struct usb_device *dev,
945 int pipe,
946 unsigned interval
947 )
948 {
949 static const u8 smask_out [] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f };
950
951 u32 buf1;
952 unsigned epnum, maxp;
953 int is_input;
954 long bandwidth;
955
956 /*
957 * this might be a "high bandwidth" highspeed endpoint,
958 * as encoded in the ep descriptor's wMaxPacket field
959 */
960 epnum = usb_pipeendpoint (pipe);
961 is_input = usb_pipein (pipe) ? USB_DIR_IN : 0;
962 maxp = usb_maxpacket(dev, pipe, !is_input);
963 if (is_input) {
964 buf1 = (1 << 11);
965 } else {
966 buf1 = 0;
967 }
968
969 /* knows about ITD vs SITD */
970 if (dev->speed == USB_SPEED_HIGH) {
971 unsigned multi = hb_mult(maxp);
972
973 stream->highspeed = 1;
974
975 maxp = max_packet(maxp);
976 buf1 |= maxp;
977 maxp *= multi;
978
979 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum);
980 stream->buf1 = cpu_to_hc32(ehci, buf1);
981 stream->buf2 = cpu_to_hc32(ehci, multi);
982
983 /* usbfs wants to report the average usecs per frame tied up
984 * when transfers on this endpoint are scheduled ...
985 */
986 stream->usecs = HS_USECS_ISO (maxp);
987 bandwidth = stream->usecs * 8;
988 bandwidth /= interval;
989
990 } else {
991 u32 addr;
992 int think_time;
993 int hs_transfers;
994
995 addr = dev->ttport << 24;
996 if (!ehci_is_TDI(ehci)
997 || (dev->tt->hub !=
998 ehci_to_hcd(ehci)->self.root_hub))
999 addr |= dev->tt->hub->devnum << 16;
1000 addr |= epnum << 8;
1001 addr |= dev->devnum;
1002 stream->usecs = HS_USECS_ISO (maxp);
1003 think_time = dev->tt ? dev->tt->think_time : 0;
1004 stream->tt_usecs = NS_TO_US (think_time + usb_calc_bus_time (
1005 dev->speed, is_input, 1, maxp));
1006 hs_transfers = max (1u, (maxp + 187) / 188);
1007 if (is_input) {
1008 u32 tmp;
1009
1010 addr |= 1 << 31;
1011 stream->c_usecs = stream->usecs;
1012 stream->usecs = HS_USECS_ISO (1);
1013 stream->raw_mask = 1;
1014
1015 /* c-mask as specified in USB 2.0 11.18.4 3.c */
1016 tmp = (1 << (hs_transfers + 2)) - 1;
1017 stream->raw_mask |= tmp << (8 + 2);
1018 } else
1019 stream->raw_mask = smask_out [hs_transfers - 1];
1020 bandwidth = stream->usecs + stream->c_usecs;
1021 bandwidth /= interval << 3;
1022
1023 /* stream->splits gets created from raw_mask later */
1024 stream->address = cpu_to_hc32(ehci, addr);
1025 }
1026 stream->bandwidth = bandwidth;
1027
1028 stream->udev = dev;
1029
1030 stream->bEndpointAddress = is_input | epnum;
1031 stream->interval = interval;
1032 stream->maxp = maxp;
1033 }
1034
1035 static void
1036 iso_stream_put(struct ehci_hcd *ehci, struct ehci_iso_stream *stream)
1037 {
1038 stream->refcount--;
1039
1040 /* free whenever just a dev->ep reference remains.
1041 * not like a QH -- no persistent state (toggle, halt)
1042 */
1043 if (stream->refcount == 1) {
1044 int is_in;
1045
1046 // BUG_ON (!list_empty(&stream->td_list));
1047
1048 while (!list_empty (&stream->free_list)) {
1049 struct list_head *entry;
1050
1051 entry = stream->free_list.next;
1052 list_del (entry);
1053
1054 /* knows about ITD vs SITD */
1055 if (stream->highspeed) {
1056 struct ehci_itd *itd;
1057
1058 itd = list_entry (entry, struct ehci_itd,
1059 itd_list);
1060 dma_pool_free (ehci->itd_pool, itd,
1061 itd->itd_dma);
1062 } else {
1063 struct ehci_sitd *sitd;
1064
1065 sitd = list_entry (entry, struct ehci_sitd,
1066 sitd_list);
1067 dma_pool_free (ehci->sitd_pool, sitd,
1068 sitd->sitd_dma);
1069 }
1070 }
1071
1072 is_in = (stream->bEndpointAddress & USB_DIR_IN) ? 0x10 : 0;
1073 stream->bEndpointAddress &= 0x0f;
1074 if (stream->ep)
1075 stream->ep->hcpriv = NULL;
1076
1077 kfree(stream);
1078 }
1079 }
1080
1081 static inline struct ehci_iso_stream *
1082 iso_stream_get (struct ehci_iso_stream *stream)
1083 {
1084 if (likely (stream != NULL))
1085 stream->refcount++;
1086 return stream;
1087 }
1088
1089 static struct ehci_iso_stream *
1090 iso_stream_find (struct ehci_hcd *ehci, struct urb *urb)
1091 {
1092 unsigned epnum;
1093 struct ehci_iso_stream *stream;
1094 struct usb_host_endpoint *ep;
1095 unsigned long flags;
1096
1097 epnum = usb_pipeendpoint (urb->pipe);
1098 if (usb_pipein(urb->pipe))
1099 ep = urb->dev->ep_in[epnum];
1100 else
1101 ep = urb->dev->ep_out[epnum];
1102
1103 spin_lock_irqsave (&ehci->lock, flags);
1104 stream = ep->hcpriv;
1105
1106 if (unlikely (stream == NULL)) {
1107 stream = iso_stream_alloc(GFP_ATOMIC);
1108 if (likely (stream != NULL)) {
1109 /* dev->ep owns the initial refcount */
1110 ep->hcpriv = stream;
1111 stream->ep = ep;
1112 iso_stream_init(ehci, stream, urb->dev, urb->pipe,
1113 urb->interval);
1114 }
1115
1116 /* if dev->ep [epnum] is a QH, hw is set */
1117 } else if (unlikely (stream->hw != NULL)) {
1118 ehci_dbg (ehci, "dev %s ep%d%s, not iso??\n",
1119 urb->dev->devpath, epnum,
1120 usb_pipein(urb->pipe) ? "in" : "out");
1121 stream = NULL;
1122 }
1123
1124 /* caller guarantees an eventual matching iso_stream_put */
1125 stream = iso_stream_get (stream);
1126
1127 spin_unlock_irqrestore (&ehci->lock, flags);
1128 return stream;
1129 }
1130
1131 /*-------------------------------------------------------------------------*/
1132
1133 /* ehci_iso_sched ops can be ITD-only or SITD-only */
1134
1135 static struct ehci_iso_sched *
1136 iso_sched_alloc (unsigned packets, gfp_t mem_flags)
1137 {
1138 struct ehci_iso_sched *iso_sched;
1139 int size = sizeof *iso_sched;
1140
1141 size += packets * sizeof (struct ehci_iso_packet);
1142 iso_sched = kzalloc(size, mem_flags);
1143 if (likely (iso_sched != NULL)) {
1144 INIT_LIST_HEAD (&iso_sched->td_list);
1145 }
1146 return iso_sched;
1147 }
1148
1149 static inline void
1150 itd_sched_init(
1151 struct ehci_hcd *ehci,
1152 struct ehci_iso_sched *iso_sched,
1153 struct ehci_iso_stream *stream,
1154 struct urb *urb
1155 )
1156 {
1157 unsigned i;
1158 dma_addr_t dma = urb->transfer_dma;
1159
1160 /* how many uframes are needed for these transfers */
1161 iso_sched->span = urb->number_of_packets * stream->interval;
1162
1163 /* figure out per-uframe itd fields that we'll need later
1164 * when we fit new itds into the schedule.
1165 */
1166 for (i = 0; i < urb->number_of_packets; i++) {
1167 struct ehci_iso_packet *uframe = &iso_sched->packet [i];
1168 unsigned length;
1169 dma_addr_t buf;
1170 u32 trans;
1171
1172 length = urb->iso_frame_desc [i].length;
1173 buf = dma + urb->iso_frame_desc [i].offset;
1174
1175 trans = EHCI_ISOC_ACTIVE;
1176 trans |= buf & 0x0fff;
1177 if (unlikely (((i + 1) == urb->number_of_packets))
1178 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1179 trans |= EHCI_ITD_IOC;
1180 trans |= length << 16;
1181 uframe->transaction = cpu_to_hc32(ehci, trans);
1182
1183 /* might need to cross a buffer page within a uframe */
1184 uframe->bufp = (buf & ~(u64)0x0fff);
1185 buf += length;
1186 if (unlikely ((uframe->bufp != (buf & ~(u64)0x0fff))))
1187 uframe->cross = 1;
1188 }
1189 }
1190
1191 static void
1192 iso_sched_free (
1193 struct ehci_iso_stream *stream,
1194 struct ehci_iso_sched *iso_sched
1195 )
1196 {
1197 if (!iso_sched)
1198 return;
1199 // caller must hold ehci->lock!
1200 list_splice (&iso_sched->td_list, &stream->free_list);
1201 kfree (iso_sched);
1202 }
1203
1204 static int
1205 itd_urb_transaction (
1206 struct ehci_iso_stream *stream,
1207 struct ehci_hcd *ehci,
1208 struct urb *urb,
1209 gfp_t mem_flags
1210 )
1211 {
1212 struct ehci_itd *itd;
1213 dma_addr_t itd_dma;
1214 int i;
1215 unsigned num_itds;
1216 struct ehci_iso_sched *sched;
1217 unsigned long flags;
1218
1219 sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1220 if (unlikely (sched == NULL))
1221 return -ENOMEM;
1222
1223 itd_sched_init(ehci, sched, stream, urb);
1224
1225 if (urb->interval < 8)
1226 num_itds = 1 + (sched->span + 7) / 8;
1227 else
1228 num_itds = urb->number_of_packets;
1229
1230 /* allocate/init ITDs */
1231 spin_lock_irqsave (&ehci->lock, flags);
1232 for (i = 0; i < num_itds; i++) {
1233
1234 /* free_list.next might be cache-hot ... but maybe
1235 * the HC caches it too. avoid that issue for now.
1236 */
1237
1238 /* prefer previously-allocated itds */
1239 if (likely (!list_empty(&stream->free_list))) {
1240 itd = list_entry (stream->free_list.prev,
1241 struct ehci_itd, itd_list);
1242 list_del (&itd->itd_list);
1243 itd_dma = itd->itd_dma;
1244 } else {
1245 spin_unlock_irqrestore (&ehci->lock, flags);
1246 itd = dma_pool_alloc (ehci->itd_pool, mem_flags,
1247 &itd_dma);
1248 spin_lock_irqsave (&ehci->lock, flags);
1249 if (!itd) {
1250 iso_sched_free(stream, sched);
1251 spin_unlock_irqrestore(&ehci->lock, flags);
1252 return -ENOMEM;
1253 }
1254 }
1255
1256 memset (itd, 0, sizeof *itd);
1257 itd->itd_dma = itd_dma;
1258 list_add (&itd->itd_list, &sched->td_list);
1259 }
1260 spin_unlock_irqrestore (&ehci->lock, flags);
1261
1262 /* temporarily store schedule info in hcpriv */
1263 urb->hcpriv = sched;
1264 urb->error_count = 0;
1265 return 0;
1266 }
1267
1268 /*-------------------------------------------------------------------------*/
1269
1270 static inline int
1271 itd_slot_ok (
1272 struct ehci_hcd *ehci,
1273 u32 mod,
1274 u32 uframe,
1275 u8 usecs,
1276 u32 period
1277 )
1278 {
1279 uframe %= period;
1280 do {
1281 /* can't commit more than 80% periodic == 100 usec */
1282 if (periodic_usecs (ehci, uframe >> 3, uframe & 0x7)
1283 > (100 - usecs))
1284 return 0;
1285
1286 /* we know urb->interval is 2^N uframes */
1287 uframe += period;
1288 } while (uframe < mod);
1289 return 1;
1290 }
1291
1292 static inline int
1293 sitd_slot_ok (
1294 struct ehci_hcd *ehci,
1295 u32 mod,
1296 struct ehci_iso_stream *stream,
1297 u32 uframe,
1298 struct ehci_iso_sched *sched,
1299 u32 period_uframes
1300 )
1301 {
1302 u32 mask, tmp;
1303 u32 frame, uf;
1304
1305 mask = stream->raw_mask << (uframe & 7);
1306
1307 /* for IN, don't wrap CSPLIT into the next frame */
1308 if (mask & ~0xffff)
1309 return 0;
1310
1311 /* this multi-pass logic is simple, but performance may
1312 * suffer when the schedule data isn't cached.
1313 */
1314
1315 /* check bandwidth */
1316 uframe %= period_uframes;
1317 do {
1318 u32 max_used;
1319
1320 frame = uframe >> 3;
1321 uf = uframe & 7;
1322
1323 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED
1324 /* The tt's fullspeed bus bandwidth must be available.
1325 * tt_available scheduling guarantees 10+% for control/bulk.
1326 */
1327 if (!tt_available (ehci, period_uframes << 3,
1328 stream->udev, frame, uf, stream->tt_usecs))
1329 return 0;
1330 #else
1331 /* tt must be idle for start(s), any gap, and csplit.
1332 * assume scheduling slop leaves 10+% for control/bulk.
1333 */
1334 if (!tt_no_collision (ehci, period_uframes << 3,
1335 stream->udev, frame, mask))
1336 return 0;
1337 #endif
1338
1339 /* check starts (OUT uses more than one) */
1340 max_used = 100 - stream->usecs;
1341 for (tmp = stream->raw_mask & 0xff; tmp; tmp >>= 1, uf++) {
1342 if (periodic_usecs (ehci, frame, uf) > max_used)
1343 return 0;
1344 }
1345
1346 /* for IN, check CSPLIT */
1347 if (stream->c_usecs) {
1348 uf = uframe & 7;
1349 max_used = 100 - stream->c_usecs;
1350 do {
1351 tmp = 1 << uf;
1352 tmp <<= 8;
1353 if ((stream->raw_mask & tmp) == 0)
1354 continue;
1355 if (periodic_usecs (ehci, frame, uf)
1356 > max_used)
1357 return 0;
1358 } while (++uf < 8);
1359 }
1360
1361 /* we know urb->interval is 2^N uframes */
1362 uframe += period_uframes;
1363 } while (uframe < mod);
1364
1365 stream->splits = cpu_to_hc32(ehci, stream->raw_mask << (uframe & 7));
1366 return 1;
1367 }
1368
1369 /*
1370 * This scheduler plans almost as far into the future as it has actual
1371 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to
1372 * "as small as possible" to be cache-friendlier.) That limits the size
1373 * transfers you can stream reliably; avoid more than 64 msec per urb.
1374 * Also avoid queue depths of less than ehci's worst irq latency (affected
1375 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter,
1376 * and other factors); or more than about 230 msec total (for portability,
1377 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler!
1378 */
1379
1380 #define SCHEDULE_SLOP 80 /* microframes */
1381
1382 static int
1383 iso_stream_schedule (
1384 struct ehci_hcd *ehci,
1385 struct urb *urb,
1386 struct ehci_iso_stream *stream
1387 )
1388 {
1389 u32 now, next, start, period, span;
1390 int status;
1391 unsigned mod = ehci->periodic_size << 3;
1392 struct ehci_iso_sched *sched = urb->hcpriv;
1393
1394 period = urb->interval;
1395 span = sched->span;
1396 if (!stream->highspeed) {
1397 period <<= 3;
1398 span <<= 3;
1399 }
1400
1401 if (span > mod - SCHEDULE_SLOP) {
1402 ehci_dbg (ehci, "iso request %p too long\n", urb);
1403 status = -EFBIG;
1404 goto fail;
1405 }
1406
1407 now = ehci_readl(ehci, &ehci->regs->frame_index) & (mod - 1);
1408
1409 /* Typical case: reuse current schedule, stream is still active.
1410 * Hopefully there are no gaps from the host falling behind
1411 * (irq delays etc), but if there are we'll take the next
1412 * slot in the schedule, implicitly assuming URB_ISO_ASAP.
1413 */
1414 if (likely (!list_empty (&stream->td_list))) {
1415 u32 excess;
1416
1417 /* For high speed devices, allow scheduling within the
1418 * isochronous scheduling threshold. For full speed devices
1419 * and Intel PCI-based controllers, don't (work around for
1420 * Intel ICH9 bug).
1421 */
1422 if (!stream->highspeed && ehci->fs_i_thresh)
1423 next = now + ehci->i_thresh;
1424 else
1425 next = now;
1426
1427 /* Fell behind (by up to twice the slop amount)?
1428 * We decide based on the time of the last currently-scheduled
1429 * slot, not the time of the next available slot.
1430 */
1431 excess = (stream->next_uframe - period - next) & (mod - 1);
1432 if (excess >= mod - 2 * SCHEDULE_SLOP)
1433 start = next + excess - mod + period *
1434 DIV_ROUND_UP(mod - excess, period);
1435 else
1436 start = next + excess + period;
1437 if (start - now >= mod) {
1438 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1439 urb, start - now - period, period,
1440 mod);
1441 status = -EFBIG;
1442 goto fail;
1443 }
1444 }
1445
1446 /* need to schedule; when's the next (u)frame we could start?
1447 * this is bigger than ehci->i_thresh allows; scheduling itself
1448 * isn't free, the slop should handle reasonably slow cpus. it
1449 * can also help high bandwidth if the dma and irq loads don't
1450 * jump until after the queue is primed.
1451 */
1452 else {
1453 start = SCHEDULE_SLOP + (now & ~0x07);
1454
1455 /* NOTE: assumes URB_ISO_ASAP, to limit complexity/bugs */
1456
1457 /* find a uframe slot with enough bandwidth */
1458 next = start + period;
1459 for (; start < next; start++) {
1460
1461 /* check schedule: enough space? */
1462 if (stream->highspeed) {
1463 if (itd_slot_ok(ehci, mod, start,
1464 stream->usecs, period))
1465 break;
1466 } else {
1467 if ((start % 8) >= 6)
1468 continue;
1469 if (sitd_slot_ok(ehci, mod, stream,
1470 start, sched, period))
1471 break;
1472 }
1473 }
1474
1475 /* no room in the schedule */
1476 if (start == next) {
1477 ehci_dbg(ehci, "iso resched full %p (now %d max %d)\n",
1478 urb, now, now + mod);
1479 status = -ENOSPC;
1480 goto fail;
1481 }
1482 }
1483
1484 /* Tried to schedule too far into the future? */
1485 if (unlikely(start - now + span - period
1486 >= mod - 2 * SCHEDULE_SLOP)) {
1487 ehci_dbg(ehci, "request %p would overflow (%d+%d >= %d)\n",
1488 urb, start - now, span - period,
1489 mod - 2 * SCHEDULE_SLOP);
1490 status = -EFBIG;
1491 goto fail;
1492 }
1493
1494 stream->next_uframe = start & (mod - 1);
1495
1496 /* report high speed start in uframes; full speed, in frames */
1497 urb->start_frame = stream->next_uframe;
1498 if (!stream->highspeed)
1499 urb->start_frame >>= 3;
1500 return 0;
1501
1502 fail:
1503 iso_sched_free(stream, sched);
1504 urb->hcpriv = NULL;
1505 return status;
1506 }
1507
1508 /*-------------------------------------------------------------------------*/
1509
1510 static inline void
1511 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream,
1512 struct ehci_itd *itd)
1513 {
1514 int i;
1515
1516 /* it's been recently zeroed */
1517 itd->hw_next = EHCI_LIST_END(ehci);
1518 itd->hw_bufp [0] = stream->buf0;
1519 itd->hw_bufp [1] = stream->buf1;
1520 itd->hw_bufp [2] = stream->buf2;
1521
1522 for (i = 0; i < 8; i++)
1523 itd->index[i] = -1;
1524
1525 /* All other fields are filled when scheduling */
1526 }
1527
1528 static inline void
1529 itd_patch(
1530 struct ehci_hcd *ehci,
1531 struct ehci_itd *itd,
1532 struct ehci_iso_sched *iso_sched,
1533 unsigned index,
1534 u16 uframe
1535 )
1536 {
1537 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1538 unsigned pg = itd->pg;
1539
1540 // BUG_ON (pg == 6 && uf->cross);
1541
1542 uframe &= 0x07;
1543 itd->index [uframe] = index;
1544
1545 itd->hw_transaction[uframe] = uf->transaction;
1546 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12);
1547 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0);
1548 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32));
1549
1550 /* iso_frame_desc[].offset must be strictly increasing */
1551 if (unlikely (uf->cross)) {
1552 u64 bufp = uf->bufp + 4096;
1553
1554 itd->pg = ++pg;
1555 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0);
1556 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32));
1557 }
1558 }
1559
1560 static inline void
1561 itd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd)
1562 {
1563 union ehci_shadow *prev = &ehci->pshadow[frame];
1564 __hc32 *hw_p = &ehci->periodic[frame];
1565 union ehci_shadow here = *prev;
1566 __hc32 type = 0;
1567
1568 /* skip any iso nodes which might belong to previous microframes */
1569 while (here.ptr) {
1570 type = Q_NEXT_TYPE(ehci, *hw_p);
1571 if (type == cpu_to_hc32(ehci, Q_TYPE_QH))
1572 break;
1573 prev = periodic_next_shadow(ehci, prev, type);
1574 hw_p = shadow_next_periodic(ehci, &here, type);
1575 here = *prev;
1576 }
1577
1578 itd->itd_next = here;
1579 itd->hw_next = *hw_p;
1580 prev->itd = itd;
1581 itd->frame = frame;
1582 wmb ();
1583 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD);
1584 }
1585
1586 /* fit urb's itds into the selected schedule slot; activate as needed */
1587 static int
1588 itd_link_urb (
1589 struct ehci_hcd *ehci,
1590 struct urb *urb,
1591 unsigned mod,
1592 struct ehci_iso_stream *stream
1593 )
1594 {
1595 int packet;
1596 unsigned next_uframe, uframe, frame;
1597 struct ehci_iso_sched *iso_sched = urb->hcpriv;
1598 struct ehci_itd *itd;
1599
1600 next_uframe = stream->next_uframe & (mod - 1);
1601
1602 if (unlikely (list_empty(&stream->td_list))) {
1603 ehci_to_hcd(ehci)->self.bandwidth_allocated
1604 += stream->bandwidth;
1605 ehci_vdbg (ehci,
1606 "schedule devp %s ep%d%s-iso period %d start %d.%d\n",
1607 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
1608 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
1609 urb->interval,
1610 next_uframe >> 3, next_uframe & 0x7);
1611 }
1612 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
1613
1614 /* fill iTDs uframe by uframe */
1615 for (packet = 0, itd = NULL; packet < urb->number_of_packets; ) {
1616 if (itd == NULL) {
1617 /* ASSERT: we have all necessary itds */
1618 // BUG_ON (list_empty (&iso_sched->td_list));
1619
1620 /* ASSERT: no itds for this endpoint in this uframe */
1621
1622 itd = list_entry (iso_sched->td_list.next,
1623 struct ehci_itd, itd_list);
1624 list_move_tail (&itd->itd_list, &stream->td_list);
1625 itd->stream = iso_stream_get (stream);
1626 itd->urb = urb;
1627 itd_init (ehci, stream, itd);
1628 }
1629
1630 uframe = next_uframe & 0x07;
1631 frame = next_uframe >> 3;
1632
1633 itd_patch(ehci, itd, iso_sched, packet, uframe);
1634
1635 next_uframe += stream->interval;
1636 next_uframe &= mod - 1;
1637 packet++;
1638
1639 /* link completed itds into the schedule */
1640 if (((next_uframe >> 3) != frame)
1641 || packet == urb->number_of_packets) {
1642 itd_link(ehci, frame & (ehci->periodic_size - 1), itd);
1643 itd = NULL;
1644 }
1645 }
1646 stream->next_uframe = next_uframe;
1647
1648 /* don't need that schedule data any more */
1649 iso_sched_free (stream, iso_sched);
1650 urb->hcpriv = NULL;
1651
1652 timer_action (ehci, TIMER_IO_WATCHDOG);
1653 return enable_periodic(ehci);
1654 }
1655
1656 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR)
1657
1658 /* Process and recycle a completed ITD. Return true iff its urb completed,
1659 * and hence its completion callback probably added things to the hardware
1660 * schedule.
1661 *
1662 * Note that we carefully avoid recycling this descriptor until after any
1663 * completion callback runs, so that it won't be reused quickly. That is,
1664 * assuming (a) no more than two urbs per frame on this endpoint, and also
1665 * (b) only this endpoint's completions submit URBs. It seems some silicon
1666 * corrupts things if you reuse completed descriptors very quickly...
1667 */
1668 static unsigned
1669 itd_complete (
1670 struct ehci_hcd *ehci,
1671 struct ehci_itd *itd
1672 ) {
1673 struct urb *urb = itd->urb;
1674 struct usb_iso_packet_descriptor *desc;
1675 u32 t;
1676 unsigned uframe;
1677 int urb_index = -1;
1678 struct ehci_iso_stream *stream = itd->stream;
1679 struct usb_device *dev;
1680 unsigned retval = false;
1681
1682 /* for each uframe with a packet */
1683 for (uframe = 0; uframe < 8; uframe++) {
1684 if (likely (itd->index[uframe] == -1))
1685 continue;
1686 urb_index = itd->index[uframe];
1687 desc = &urb->iso_frame_desc [urb_index];
1688
1689 t = hc32_to_cpup(ehci, &itd->hw_transaction [uframe]);
1690 itd->hw_transaction [uframe] = 0;
1691
1692 /* report transfer status */
1693 if (unlikely (t & ISO_ERRS)) {
1694 urb->error_count++;
1695 if (t & EHCI_ISOC_BUF_ERR)
1696 desc->status = usb_pipein (urb->pipe)
1697 ? -ENOSR /* hc couldn't read */
1698 : -ECOMM; /* hc couldn't write */
1699 else if (t & EHCI_ISOC_BABBLE)
1700 desc->status = -EOVERFLOW;
1701 else /* (t & EHCI_ISOC_XACTERR) */
1702 desc->status = -EPROTO;
1703
1704 /* HC need not update length with this error */
1705 if (!(t & EHCI_ISOC_BABBLE)) {
1706 desc->actual_length = EHCI_ITD_LENGTH(t);
1707 urb->actual_length += desc->actual_length;
1708 }
1709 } else if (likely ((t & EHCI_ISOC_ACTIVE) == 0)) {
1710 desc->status = 0;
1711 desc->actual_length = EHCI_ITD_LENGTH(t);
1712 urb->actual_length += desc->actual_length;
1713 } else {
1714 /* URB was too late */
1715 desc->status = -EXDEV;
1716 }
1717 }
1718
1719 /* handle completion now? */
1720 if (likely ((urb_index + 1) != urb->number_of_packets))
1721 goto done;
1722
1723 /* ASSERT: it's really the last itd for this urb
1724 list_for_each_entry (itd, &stream->td_list, itd_list)
1725 BUG_ON (itd->urb == urb);
1726 */
1727
1728 /* give urb back to the driver; completion often (re)submits */
1729 dev = urb->dev;
1730 ehci_urb_done(ehci, urb, 0);
1731 retval = true;
1732 urb = NULL;
1733 (void) disable_periodic(ehci);
1734 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
1735
1736 if (unlikely(list_is_singular(&stream->td_list))) {
1737 ehci_to_hcd(ehci)->self.bandwidth_allocated
1738 -= stream->bandwidth;
1739 ehci_vdbg (ehci,
1740 "deschedule devp %s ep%d%s-iso\n",
1741 dev->devpath, stream->bEndpointAddress & 0x0f,
1742 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
1743 }
1744 iso_stream_put (ehci, stream);
1745
1746 done:
1747 itd->urb = NULL;
1748 if (ehci->clock_frame != itd->frame || itd->index[7] != -1) {
1749 /* OK to recycle this ITD now. */
1750 itd->stream = NULL;
1751 list_move(&itd->itd_list, &stream->free_list);
1752 iso_stream_put(ehci, stream);
1753 } else {
1754 /* HW might remember this ITD, so we can't recycle it yet.
1755 * Move it to a safe place until a new frame starts.
1756 */
1757 list_move(&itd->itd_list, &ehci->cached_itd_list);
1758 if (stream->refcount == 2) {
1759 /* If iso_stream_put() were called here, stream
1760 * would be freed. Instead, just prevent reuse.
1761 */
1762 stream->ep->hcpriv = NULL;
1763 stream->ep = NULL;
1764 }
1765 }
1766 return retval;
1767 }
1768
1769 /*-------------------------------------------------------------------------*/
1770
1771 static int itd_submit (struct ehci_hcd *ehci, struct urb *urb,
1772 gfp_t mem_flags)
1773 {
1774 int status = -EINVAL;
1775 unsigned long flags;
1776 struct ehci_iso_stream *stream;
1777
1778 /* Get iso_stream head */
1779 stream = iso_stream_find (ehci, urb);
1780 if (unlikely (stream == NULL)) {
1781 ehci_dbg (ehci, "can't get iso stream\n");
1782 return -ENOMEM;
1783 }
1784 if (unlikely (urb->interval != stream->interval)) {
1785 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
1786 stream->interval, urb->interval);
1787 goto done;
1788 }
1789
1790 #ifdef EHCI_URB_TRACE
1791 ehci_dbg (ehci,
1792 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n",
1793 __func__, urb->dev->devpath, urb,
1794 usb_pipeendpoint (urb->pipe),
1795 usb_pipein (urb->pipe) ? "in" : "out",
1796 urb->transfer_buffer_length,
1797 urb->number_of_packets, urb->interval,
1798 stream);
1799 #endif
1800
1801 /* allocate ITDs w/o locking anything */
1802 status = itd_urb_transaction (stream, ehci, urb, mem_flags);
1803 if (unlikely (status < 0)) {
1804 ehci_dbg (ehci, "can't init itds\n");
1805 goto done;
1806 }
1807
1808 /* schedule ... need to lock */
1809 spin_lock_irqsave (&ehci->lock, flags);
1810 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
1811 status = -ESHUTDOWN;
1812 goto done_not_linked;
1813 }
1814 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
1815 if (unlikely(status))
1816 goto done_not_linked;
1817 status = iso_stream_schedule(ehci, urb, stream);
1818 if (likely (status == 0))
1819 itd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
1820 else
1821 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
1822 done_not_linked:
1823 spin_unlock_irqrestore (&ehci->lock, flags);
1824
1825 done:
1826 if (unlikely (status < 0))
1827 iso_stream_put (ehci, stream);
1828 return status;
1829 }
1830
1831 /*-------------------------------------------------------------------------*/
1832
1833 /*
1834 * "Split ISO TDs" ... used for USB 1.1 devices going through the
1835 * TTs in USB 2.0 hubs. These need microframe scheduling.
1836 */
1837
1838 static inline void
1839 sitd_sched_init(
1840 struct ehci_hcd *ehci,
1841 struct ehci_iso_sched *iso_sched,
1842 struct ehci_iso_stream *stream,
1843 struct urb *urb
1844 )
1845 {
1846 unsigned i;
1847 dma_addr_t dma = urb->transfer_dma;
1848
1849 /* how many frames are needed for these transfers */
1850 iso_sched->span = urb->number_of_packets * stream->interval;
1851
1852 /* figure out per-frame sitd fields that we'll need later
1853 * when we fit new sitds into the schedule.
1854 */
1855 for (i = 0; i < urb->number_of_packets; i++) {
1856 struct ehci_iso_packet *packet = &iso_sched->packet [i];
1857 unsigned length;
1858 dma_addr_t buf;
1859 u32 trans;
1860
1861 length = urb->iso_frame_desc [i].length & 0x03ff;
1862 buf = dma + urb->iso_frame_desc [i].offset;
1863
1864 trans = SITD_STS_ACTIVE;
1865 if (((i + 1) == urb->number_of_packets)
1866 && !(urb->transfer_flags & URB_NO_INTERRUPT))
1867 trans |= SITD_IOC;
1868 trans |= length << 16;
1869 packet->transaction = cpu_to_hc32(ehci, trans);
1870
1871 /* might need to cross a buffer page within a td */
1872 packet->bufp = buf;
1873 packet->buf1 = (buf + length) & ~0x0fff;
1874 if (packet->buf1 != (buf & ~(u64)0x0fff))
1875 packet->cross = 1;
1876
1877 /* OUT uses multiple start-splits */
1878 if (stream->bEndpointAddress & USB_DIR_IN)
1879 continue;
1880 length = (length + 187) / 188;
1881 if (length > 1) /* BEGIN vs ALL */
1882 length |= 1 << 3;
1883 packet->buf1 |= length;
1884 }
1885 }
1886
1887 static int
1888 sitd_urb_transaction (
1889 struct ehci_iso_stream *stream,
1890 struct ehci_hcd *ehci,
1891 struct urb *urb,
1892 gfp_t mem_flags
1893 )
1894 {
1895 struct ehci_sitd *sitd;
1896 dma_addr_t sitd_dma;
1897 int i;
1898 struct ehci_iso_sched *iso_sched;
1899 unsigned long flags;
1900
1901 iso_sched = iso_sched_alloc (urb->number_of_packets, mem_flags);
1902 if (iso_sched == NULL)
1903 return -ENOMEM;
1904
1905 sitd_sched_init(ehci, iso_sched, stream, urb);
1906
1907 /* allocate/init sITDs */
1908 spin_lock_irqsave (&ehci->lock, flags);
1909 for (i = 0; i < urb->number_of_packets; i++) {
1910
1911 /* NOTE: for now, we don't try to handle wraparound cases
1912 * for IN (using sitd->hw_backpointer, like a FSTN), which
1913 * means we never need two sitds for full speed packets.
1914 */
1915
1916 /* free_list.next might be cache-hot ... but maybe
1917 * the HC caches it too. avoid that issue for now.
1918 */
1919
1920 /* prefer previously-allocated sitds */
1921 if (!list_empty(&stream->free_list)) {
1922 sitd = list_entry (stream->free_list.prev,
1923 struct ehci_sitd, sitd_list);
1924 list_del (&sitd->sitd_list);
1925 sitd_dma = sitd->sitd_dma;
1926 } else {
1927 spin_unlock_irqrestore (&ehci->lock, flags);
1928 sitd = dma_pool_alloc (ehci->sitd_pool, mem_flags,
1929 &sitd_dma);
1930 spin_lock_irqsave (&ehci->lock, flags);
1931 if (!sitd) {
1932 iso_sched_free(stream, iso_sched);
1933 spin_unlock_irqrestore(&ehci->lock, flags);
1934 return -ENOMEM;
1935 }
1936 }
1937
1938 memset (sitd, 0, sizeof *sitd);
1939 sitd->sitd_dma = sitd_dma;
1940 list_add (&sitd->sitd_list, &iso_sched->td_list);
1941 }
1942
1943 /* temporarily store schedule info in hcpriv */
1944 urb->hcpriv = iso_sched;
1945 urb->error_count = 0;
1946
1947 spin_unlock_irqrestore (&ehci->lock, flags);
1948 return 0;
1949 }
1950
1951 /*-------------------------------------------------------------------------*/
1952
1953 static inline void
1954 sitd_patch(
1955 struct ehci_hcd *ehci,
1956 struct ehci_iso_stream *stream,
1957 struct ehci_sitd *sitd,
1958 struct ehci_iso_sched *iso_sched,
1959 unsigned index
1960 )
1961 {
1962 struct ehci_iso_packet *uf = &iso_sched->packet [index];
1963 u64 bufp = uf->bufp;
1964
1965 sitd->hw_next = EHCI_LIST_END(ehci);
1966 sitd->hw_fullspeed_ep = stream->address;
1967 sitd->hw_uframe = stream->splits;
1968 sitd->hw_results = uf->transaction;
1969 sitd->hw_backpointer = EHCI_LIST_END(ehci);
1970
1971 bufp = uf->bufp;
1972 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp);
1973 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32);
1974
1975 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1);
1976 if (uf->cross)
1977 bufp += 4096;
1978 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32);
1979 sitd->index = index;
1980 }
1981
1982 static inline void
1983 sitd_link (struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd)
1984 {
1985 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */
1986 sitd->sitd_next = ehci->pshadow [frame];
1987 sitd->hw_next = ehci->periodic [frame];
1988 ehci->pshadow [frame].sitd = sitd;
1989 sitd->frame = frame;
1990 wmb ();
1991 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD);
1992 }
1993
1994 /* fit urb's sitds into the selected schedule slot; activate as needed */
1995 static int
1996 sitd_link_urb (
1997 struct ehci_hcd *ehci,
1998 struct urb *urb,
1999 unsigned mod,
2000 struct ehci_iso_stream *stream
2001 )
2002 {
2003 int packet;
2004 unsigned next_uframe;
2005 struct ehci_iso_sched *sched = urb->hcpriv;
2006 struct ehci_sitd *sitd;
2007
2008 next_uframe = stream->next_uframe;
2009
2010 if (list_empty(&stream->td_list)) {
2011 /* usbfs ignores TT bandwidth */
2012 ehci_to_hcd(ehci)->self.bandwidth_allocated
2013 += stream->bandwidth;
2014 ehci_vdbg (ehci,
2015 "sched devp %s ep%d%s-iso [%d] %dms/%04x\n",
2016 urb->dev->devpath, stream->bEndpointAddress & 0x0f,
2017 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
2018 (next_uframe >> 3) & (ehci->periodic_size - 1),
2019 stream->interval, hc32_to_cpu(ehci, stream->splits));
2020 }
2021 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++;
2022
2023 /* fill sITDs frame by frame */
2024 for (packet = 0, sitd = NULL;
2025 packet < urb->number_of_packets;
2026 packet++) {
2027
2028 /* ASSERT: we have all necessary sitds */
2029 BUG_ON (list_empty (&sched->td_list));
2030
2031 /* ASSERT: no itds for this endpoint in this frame */
2032
2033 sitd = list_entry (sched->td_list.next,
2034 struct ehci_sitd, sitd_list);
2035 list_move_tail (&sitd->sitd_list, &stream->td_list);
2036 sitd->stream = iso_stream_get (stream);
2037 sitd->urb = urb;
2038
2039 sitd_patch(ehci, stream, sitd, sched, packet);
2040 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1),
2041 sitd);
2042
2043 next_uframe += stream->interval << 3;
2044 }
2045 stream->next_uframe = next_uframe & (mod - 1);
2046
2047 /* don't need that schedule data any more */
2048 iso_sched_free (stream, sched);
2049 urb->hcpriv = NULL;
2050
2051 timer_action (ehci, TIMER_IO_WATCHDOG);
2052 return enable_periodic(ehci);
2053 }
2054
2055 /*-------------------------------------------------------------------------*/
2056
2057 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \
2058 | SITD_STS_XACT | SITD_STS_MMF)
2059
2060 /* Process and recycle a completed SITD. Return true iff its urb completed,
2061 * and hence its completion callback probably added things to the hardware
2062 * schedule.
2063 *
2064 * Note that we carefully avoid recycling this descriptor until after any
2065 * completion callback runs, so that it won't be reused quickly. That is,
2066 * assuming (a) no more than two urbs per frame on this endpoint, and also
2067 * (b) only this endpoint's completions submit URBs. It seems some silicon
2068 * corrupts things if you reuse completed descriptors very quickly...
2069 */
2070 static unsigned
2071 sitd_complete (
2072 struct ehci_hcd *ehci,
2073 struct ehci_sitd *sitd
2074 ) {
2075 struct urb *urb = sitd->urb;
2076 struct usb_iso_packet_descriptor *desc;
2077 u32 t;
2078 int urb_index = -1;
2079 struct ehci_iso_stream *stream = sitd->stream;
2080 struct usb_device *dev;
2081 unsigned retval = false;
2082
2083 urb_index = sitd->index;
2084 desc = &urb->iso_frame_desc [urb_index];
2085 t = hc32_to_cpup(ehci, &sitd->hw_results);
2086
2087 /* report transfer status */
2088 if (t & SITD_ERRS) {
2089 urb->error_count++;
2090 if (t & SITD_STS_DBE)
2091 desc->status = usb_pipein (urb->pipe)
2092 ? -ENOSR /* hc couldn't read */
2093 : -ECOMM; /* hc couldn't write */
2094 else if (t & SITD_STS_BABBLE)
2095 desc->status = -EOVERFLOW;
2096 else /* XACT, MMF, etc */
2097 desc->status = -EPROTO;
2098 } else {
2099 desc->status = 0;
2100 desc->actual_length = desc->length - SITD_LENGTH(t);
2101 urb->actual_length += desc->actual_length;
2102 }
2103
2104 /* handle completion now? */
2105 if ((urb_index + 1) != urb->number_of_packets)
2106 goto done;
2107
2108 /* ASSERT: it's really the last sitd for this urb
2109 list_for_each_entry (sitd, &stream->td_list, sitd_list)
2110 BUG_ON (sitd->urb == urb);
2111 */
2112
2113 /* give urb back to the driver; completion often (re)submits */
2114 dev = urb->dev;
2115 ehci_urb_done(ehci, urb, 0);
2116 retval = true;
2117 urb = NULL;
2118 (void) disable_periodic(ehci);
2119 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--;
2120
2121 if (list_is_singular(&stream->td_list)) {
2122 ehci_to_hcd(ehci)->self.bandwidth_allocated
2123 -= stream->bandwidth;
2124 ehci_vdbg (ehci,
2125 "deschedule devp %s ep%d%s-iso\n",
2126 dev->devpath, stream->bEndpointAddress & 0x0f,
2127 (stream->bEndpointAddress & USB_DIR_IN) ? "in" : "out");
2128 }
2129 iso_stream_put (ehci, stream);
2130
2131 done:
2132 sitd->urb = NULL;
2133 if (ehci->clock_frame != sitd->frame) {
2134 /* OK to recycle this SITD now. */
2135 sitd->stream = NULL;
2136 list_move(&sitd->sitd_list, &stream->free_list);
2137 iso_stream_put(ehci, stream);
2138 } else {
2139 /* HW might remember this SITD, so we can't recycle it yet.
2140 * Move it to a safe place until a new frame starts.
2141 */
2142 list_move(&sitd->sitd_list, &ehci->cached_sitd_list);
2143 if (stream->refcount == 2) {
2144 /* If iso_stream_put() were called here, stream
2145 * would be freed. Instead, just prevent reuse.
2146 */
2147 stream->ep->hcpriv = NULL;
2148 stream->ep = NULL;
2149 }
2150 }
2151 return retval;
2152 }
2153
2154
2155 static int sitd_submit (struct ehci_hcd *ehci, struct urb *urb,
2156 gfp_t mem_flags)
2157 {
2158 int status = -EINVAL;
2159 unsigned long flags;
2160 struct ehci_iso_stream *stream;
2161
2162 /* Get iso_stream head */
2163 stream = iso_stream_find (ehci, urb);
2164 if (stream == NULL) {
2165 ehci_dbg (ehci, "can't get iso stream\n");
2166 return -ENOMEM;
2167 }
2168 if (urb->interval != stream->interval) {
2169 ehci_dbg (ehci, "can't change iso interval %d --> %d\n",
2170 stream->interval, urb->interval);
2171 goto done;
2172 }
2173
2174 #ifdef EHCI_URB_TRACE
2175 ehci_dbg (ehci,
2176 "submit %p dev%s ep%d%s-iso len %d\n",
2177 urb, urb->dev->devpath,
2178 usb_pipeendpoint (urb->pipe),
2179 usb_pipein (urb->pipe) ? "in" : "out",
2180 urb->transfer_buffer_length);
2181 #endif
2182
2183 /* allocate SITDs */
2184 status = sitd_urb_transaction (stream, ehci, urb, mem_flags);
2185 if (status < 0) {
2186 ehci_dbg (ehci, "can't init sitds\n");
2187 goto done;
2188 }
2189
2190 /* schedule ... need to lock */
2191 spin_lock_irqsave (&ehci->lock, flags);
2192 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) {
2193 status = -ESHUTDOWN;
2194 goto done_not_linked;
2195 }
2196 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb);
2197 if (unlikely(status))
2198 goto done_not_linked;
2199 status = iso_stream_schedule(ehci, urb, stream);
2200 if (status == 0)
2201 sitd_link_urb (ehci, urb, ehci->periodic_size << 3, stream);
2202 else
2203 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb);
2204 done_not_linked:
2205 spin_unlock_irqrestore (&ehci->lock, flags);
2206
2207 done:
2208 if (status < 0)
2209 iso_stream_put (ehci, stream);
2210 return status;
2211 }
2212
2213 /*-------------------------------------------------------------------------*/
2214
2215 static void free_cached_lists(struct ehci_hcd *ehci)
2216 {
2217 struct ehci_itd *itd, *n;
2218 struct ehci_sitd *sitd, *sn;
2219
2220 list_for_each_entry_safe(itd, n, &ehci->cached_itd_list, itd_list) {
2221 struct ehci_iso_stream *stream = itd->stream;
2222 itd->stream = NULL;
2223 list_move(&itd->itd_list, &stream->free_list);
2224 iso_stream_put(ehci, stream);
2225 }
2226
2227 list_for_each_entry_safe(sitd, sn, &ehci->cached_sitd_list, sitd_list) {
2228 struct ehci_iso_stream *stream = sitd->stream;
2229 sitd->stream = NULL;
2230 list_move(&sitd->sitd_list, &stream->free_list);
2231 iso_stream_put(ehci, stream);
2232 }
2233 }
2234
2235 /*-------------------------------------------------------------------------*/
2236
2237 static void
2238 scan_periodic (struct ehci_hcd *ehci)
2239 {
2240 unsigned now_uframe, frame, clock, clock_frame, mod;
2241 unsigned modified;
2242
2243 mod = ehci->periodic_size << 3;
2244
2245 /*
2246 * When running, scan from last scan point up to "now"
2247 * else clean up by scanning everything that's left.
2248 * Touches as few pages as possible: cache-friendly.
2249 */
2250 now_uframe = ehci->next_uframe;
2251 if (HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2252 clock = ehci_readl(ehci, &ehci->regs->frame_index);
2253 clock_frame = (clock >> 3) & (ehci->periodic_size - 1);
2254 } else {
2255 clock = now_uframe + mod - 1;
2256 clock_frame = -1;
2257 }
2258 if (ehci->clock_frame != clock_frame) {
2259 free_cached_lists(ehci);
2260 ehci->clock_frame = clock_frame;
2261 }
2262 clock &= mod - 1;
2263 clock_frame = clock >> 3;
2264
2265 for (;;) {
2266 union ehci_shadow q, *q_p;
2267 __hc32 type, *hw_p;
2268 unsigned incomplete = false;
2269
2270 frame = now_uframe >> 3;
2271
2272 restart:
2273 /* scan each element in frame's queue for completions */
2274 q_p = &ehci->pshadow [frame];
2275 hw_p = &ehci->periodic [frame];
2276 q.ptr = q_p->ptr;
2277 type = Q_NEXT_TYPE(ehci, *hw_p);
2278 modified = 0;
2279
2280 while (q.ptr != NULL) {
2281 unsigned uf;
2282 union ehci_shadow temp;
2283 int live;
2284
2285 live = HC_IS_RUNNING (ehci_to_hcd(ehci)->state);
2286 switch (hc32_to_cpu(ehci, type)) {
2287 case Q_TYPE_QH:
2288 /* handle any completions */
2289 temp.qh = qh_get (q.qh);
2290 type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
2291 q = q.qh->qh_next;
2292 modified = qh_completions (ehci, temp.qh);
2293 if (unlikely(list_empty(&temp.qh->qtd_list) ||
2294 temp.qh->needs_rescan))
2295 intr_deschedule (ehci, temp.qh);
2296 qh_put (temp.qh);
2297 break;
2298 case Q_TYPE_FSTN:
2299 /* for "save place" FSTNs, look at QH entries
2300 * in the previous frame for completions.
2301 */
2302 if (q.fstn->hw_prev != EHCI_LIST_END(ehci)) {
2303 dbg ("ignoring completions from FSTNs");
2304 }
2305 type = Q_NEXT_TYPE(ehci, q.fstn->hw_next);
2306 q = q.fstn->fstn_next;
2307 break;
2308 case Q_TYPE_ITD:
2309 /* If this ITD is still active, leave it for
2310 * later processing ... check the next entry.
2311 * No need to check for activity unless the
2312 * frame is current.
2313 */
2314 if (frame == clock_frame && live) {
2315 rmb();
2316 for (uf = 0; uf < 8; uf++) {
2317 if (q.itd->hw_transaction[uf] &
2318 ITD_ACTIVE(ehci))
2319 break;
2320 }
2321 if (uf < 8) {
2322 incomplete = true;
2323 q_p = &q.itd->itd_next;
2324 hw_p = &q.itd->hw_next;
2325 type = Q_NEXT_TYPE(ehci,
2326 q.itd->hw_next);
2327 q = *q_p;
2328 break;
2329 }
2330 }
2331
2332 /* Take finished ITDs out of the schedule
2333 * and process them: recycle, maybe report
2334 * URB completion. HC won't cache the
2335 * pointer for much longer, if at all.
2336 */
2337 *q_p = q.itd->itd_next;
2338 *hw_p = q.itd->hw_next;
2339 type = Q_NEXT_TYPE(ehci, q.itd->hw_next);
2340 wmb();
2341 modified = itd_complete (ehci, q.itd);
2342 q = *q_p;
2343 break;
2344 case Q_TYPE_SITD:
2345 /* If this SITD is still active, leave it for
2346 * later processing ... check the next entry.
2347 * No need to check for activity unless the
2348 * frame is current.
2349 */
2350 if (((frame == clock_frame) ||
2351 (((frame + 1) & (ehci->periodic_size - 1))
2352 == clock_frame))
2353 && live
2354 && (q.sitd->hw_results &
2355 SITD_ACTIVE(ehci))) {
2356
2357 incomplete = true;
2358 q_p = &q.sitd->sitd_next;
2359 hw_p = &q.sitd->hw_next;
2360 type = Q_NEXT_TYPE(ehci,
2361 q.sitd->hw_next);
2362 q = *q_p;
2363 break;
2364 }
2365
2366 /* Take finished SITDs out of the schedule
2367 * and process them: recycle, maybe report
2368 * URB completion.
2369 */
2370 *q_p = q.sitd->sitd_next;
2371 *hw_p = q.sitd->hw_next;
2372 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next);
2373 wmb();
2374 modified = sitd_complete (ehci, q.sitd);
2375 q = *q_p;
2376 break;
2377 default:
2378 dbg ("corrupt type %d frame %d shadow %p",
2379 type, frame, q.ptr);
2380 // BUG ();
2381 q.ptr = NULL;
2382 }
2383
2384 /* assume completion callbacks modify the queue */
2385 if (unlikely (modified)) {
2386 if (likely(ehci->periodic_sched > 0))
2387 goto restart;
2388 /* short-circuit this scan */
2389 now_uframe = clock;
2390 break;
2391 }
2392 }
2393
2394 /* If we can tell we caught up to the hardware, stop now.
2395 * We can't advance our scan without collecting the ISO
2396 * transfers that are still pending in this frame.
2397 */
2398 if (incomplete && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
2399 ehci->next_uframe = now_uframe;
2400 break;
2401 }
2402
2403 // FIXME: this assumes we won't get lapped when
2404 // latencies climb; that should be rare, but...
2405 // detect it, and just go all the way around.
2406 // FLR might help detect this case, so long as latencies
2407 // don't exceed periodic_size msec (default 1.024 sec).
2408
2409 // FIXME: likewise assumes HC doesn't halt mid-scan
2410
2411 if (now_uframe == clock) {
2412 unsigned now;
2413
2414 if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)
2415 || ehci->periodic_sched == 0)
2416 break;
2417 ehci->next_uframe = now_uframe;
2418 now = ehci_readl(ehci, &ehci->regs->frame_index) &
2419 (mod - 1);
2420 if (now_uframe == now)
2421 break;
2422
2423 /* rescan the rest of this frame, then ... */
2424 clock = now;
2425 clock_frame = clock >> 3;
2426 if (ehci->clock_frame != clock_frame) {
2427 free_cached_lists(ehci);
2428 ehci->clock_frame = clock_frame;
2429 }
2430 } else {
2431 now_uframe++;
2432 now_uframe &= mod - 1;
2433 }
2434 }
2435 }
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