2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 #include <linux/types.h>
12 #include <linux/kconfig.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/export.h>
18 #include <linux/acpi.h>
19 #include <linux/dmi.h>
20 #include "pci-quirks.h"
21 #include "xhci-ext-caps.h"
24 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
25 #define UHCI_USBCMD 0 /* command register */
26 #define UHCI_USBINTR 4 /* interrupt register */
27 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
28 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
29 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
30 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
31 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
32 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
33 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
35 #define OHCI_CONTROL 0x04
36 #define OHCI_CMDSTATUS 0x08
37 #define OHCI_INTRSTATUS 0x0c
38 #define OHCI_INTRENABLE 0x10
39 #define OHCI_INTRDISABLE 0x14
40 #define OHCI_FMINTERVAL 0x34
41 #define OHCI_HCFS (3 << 6) /* hc functional state */
42 #define OHCI_HCR (1 << 0) /* host controller reset */
43 #define OHCI_OCR (1 << 3) /* ownership change request */
44 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
45 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
46 #define OHCI_INTR_OC (1 << 30) /* ownership change */
48 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
49 #define EHCI_USBCMD 0 /* command register */
50 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
51 #define EHCI_USBSTS 4 /* status register */
52 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
53 #define EHCI_USBINTR 8 /* interrupt register */
54 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */
55 #define EHCI_USBLEGSUP 0 /* legacy support register */
56 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
57 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
58 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
59 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
62 #define AB_REG_BAR_LOW 0xe0
63 #define AB_REG_BAR_HIGH 0xe1
64 #define AB_REG_BAR_SB700 0xf0
65 #define AB_INDX(addr) ((addr) + 0x00)
66 #define AB_DATA(addr) ((addr) + 0x04)
70 #define NB_PCIE_INDX_ADDR 0xe0
71 #define NB_PCIE_INDX_DATA 0xe4
72 #define PCIE_P_CNTL 0x10040
73 #define BIF_NB 0x10002
74 #define NB_PIF0_PWRDOWN_0 0x01100012
75 #define NB_PIF0_PWRDOWN_1 0x01100013
77 #define USB_INTEL_XUSB2PR 0xD0
78 #define USB_INTEL_USB2PRM 0xD4
79 #define USB_INTEL_USB3_PSSEN 0xD8
80 #define USB_INTEL_USB3PRM 0xDC
82 static struct amd_chipset_info
{
83 struct pci_dev
*nb_dev
;
84 struct pci_dev
*smbus_dev
;
92 static DEFINE_SPINLOCK(amd_lock
);
94 int usb_amd_find_chipset_info(void)
98 struct amd_chipset_info info
;
101 spin_lock_irqsave(&amd_lock
, flags
);
103 /* probe only once */
104 if (amd_chipset
.probe_count
> 0) {
105 amd_chipset
.probe_count
++;
106 spin_unlock_irqrestore(&amd_lock
, flags
);
107 return amd_chipset
.probe_result
;
109 memset(&info
, 0, sizeof(info
));
110 spin_unlock_irqrestore(&amd_lock
, flags
);
112 info
.smbus_dev
= pci_get_device(PCI_VENDOR_ID_ATI
, 0x4385, NULL
);
113 if (info
.smbus_dev
) {
114 rev
= info
.smbus_dev
->revision
;
117 else if (rev
>= 0x30 && rev
<= 0x3b)
120 info
.smbus_dev
= pci_get_device(PCI_VENDOR_ID_AMD
,
122 if (!info
.smbus_dev
) {
127 rev
= info
.smbus_dev
->revision
;
128 if (rev
>= 0x11 && rev
<= 0x18)
132 if (info
.sb_type
== 0) {
133 if (info
.smbus_dev
) {
134 pci_dev_put(info
.smbus_dev
);
135 info
.smbus_dev
= NULL
;
141 info
.nb_dev
= pci_get_device(PCI_VENDOR_ID_AMD
, 0x9601, NULL
);
145 info
.nb_dev
= pci_get_device(PCI_VENDOR_ID_AMD
, 0x1510, NULL
);
149 info
.nb_dev
= pci_get_device(PCI_VENDOR_ID_AMD
,
156 ret
= info
.probe_result
= 1;
157 printk(KERN_DEBUG
"QUIRK: Enable AMD PLL fix\n");
161 spin_lock_irqsave(&amd_lock
, flags
);
162 if (amd_chipset
.probe_count
> 0) {
163 /* race - someone else was faster - drop devices */
165 /* Mark that we where here */
166 amd_chipset
.probe_count
++;
167 ret
= amd_chipset
.probe_result
;
169 spin_unlock_irqrestore(&amd_lock
, flags
);
172 pci_dev_put(info
.nb_dev
);
174 pci_dev_put(info
.smbus_dev
);
177 /* no race - commit the result */
180 spin_unlock_irqrestore(&amd_lock
, flags
);
185 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info
);
188 * The hardware normally enables the A-link power management feature, which
189 * lets the system lower the power consumption in idle states.
191 * This USB quirk prevents the link going into that lower power state
192 * during isochronous transfers.
194 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
195 * some AMD platforms may stutter or have breaks occasionally.
197 static void usb_amd_quirk_pll(int disable
)
199 u32 addr
, addr_low
, addr_high
, val
;
200 u32 bit
= disable
? 0 : 1;
203 spin_lock_irqsave(&amd_lock
, flags
);
206 amd_chipset
.isoc_reqs
++;
207 if (amd_chipset
.isoc_reqs
> 1) {
208 spin_unlock_irqrestore(&amd_lock
, flags
);
212 amd_chipset
.isoc_reqs
--;
213 if (amd_chipset
.isoc_reqs
> 0) {
214 spin_unlock_irqrestore(&amd_lock
, flags
);
219 if (amd_chipset
.sb_type
== 1 || amd_chipset
.sb_type
== 2) {
220 outb_p(AB_REG_BAR_LOW
, 0xcd6);
221 addr_low
= inb_p(0xcd7);
222 outb_p(AB_REG_BAR_HIGH
, 0xcd6);
223 addr_high
= inb_p(0xcd7);
224 addr
= addr_high
<< 8 | addr_low
;
226 outl_p(0x30, AB_INDX(addr
));
227 outl_p(0x40, AB_DATA(addr
));
228 outl_p(0x34, AB_INDX(addr
));
229 val
= inl_p(AB_DATA(addr
));
230 } else if (amd_chipset
.sb_type
== 3) {
231 pci_read_config_dword(amd_chipset
.smbus_dev
,
232 AB_REG_BAR_SB700
, &addr
);
233 outl(AX_INDXC
, AB_INDX(addr
));
234 outl(0x40, AB_DATA(addr
));
235 outl(AX_DATAC
, AB_INDX(addr
));
236 val
= inl(AB_DATA(addr
));
238 spin_unlock_irqrestore(&amd_lock
, flags
);
244 val
|= (1 << 4) | (1 << 9);
247 val
&= ~((1 << 4) | (1 << 9));
249 outl_p(val
, AB_DATA(addr
));
251 if (!amd_chipset
.nb_dev
) {
252 spin_unlock_irqrestore(&amd_lock
, flags
);
256 if (amd_chipset
.nb_type
== 1 || amd_chipset
.nb_type
== 3) {
258 pci_write_config_dword(amd_chipset
.nb_dev
,
259 NB_PCIE_INDX_ADDR
, addr
);
260 pci_read_config_dword(amd_chipset
.nb_dev
,
261 NB_PCIE_INDX_DATA
, &val
);
263 val
&= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
264 val
|= bit
| (bit
<< 3) | (bit
<< 12);
265 val
|= ((!bit
) << 4) | ((!bit
) << 9);
266 pci_write_config_dword(amd_chipset
.nb_dev
,
267 NB_PCIE_INDX_DATA
, val
);
270 pci_write_config_dword(amd_chipset
.nb_dev
,
271 NB_PCIE_INDX_ADDR
, addr
);
272 pci_read_config_dword(amd_chipset
.nb_dev
,
273 NB_PCIE_INDX_DATA
, &val
);
277 pci_write_config_dword(amd_chipset
.nb_dev
,
278 NB_PCIE_INDX_DATA
, val
);
279 } else if (amd_chipset
.nb_type
== 2) {
280 addr
= NB_PIF0_PWRDOWN_0
;
281 pci_write_config_dword(amd_chipset
.nb_dev
,
282 NB_PCIE_INDX_ADDR
, addr
);
283 pci_read_config_dword(amd_chipset
.nb_dev
,
284 NB_PCIE_INDX_DATA
, &val
);
290 pci_write_config_dword(amd_chipset
.nb_dev
,
291 NB_PCIE_INDX_DATA
, val
);
293 addr
= NB_PIF0_PWRDOWN_1
;
294 pci_write_config_dword(amd_chipset
.nb_dev
,
295 NB_PCIE_INDX_ADDR
, addr
);
296 pci_read_config_dword(amd_chipset
.nb_dev
,
297 NB_PCIE_INDX_DATA
, &val
);
303 pci_write_config_dword(amd_chipset
.nb_dev
,
304 NB_PCIE_INDX_DATA
, val
);
307 spin_unlock_irqrestore(&amd_lock
, flags
);
311 void usb_amd_quirk_pll_disable(void)
313 usb_amd_quirk_pll(1);
315 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable
);
317 void usb_amd_quirk_pll_enable(void)
319 usb_amd_quirk_pll(0);
321 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable
);
323 void usb_amd_dev_put(void)
325 struct pci_dev
*nb
, *smbus
;
328 spin_lock_irqsave(&amd_lock
, flags
);
330 amd_chipset
.probe_count
--;
331 if (amd_chipset
.probe_count
> 0) {
332 spin_unlock_irqrestore(&amd_lock
, flags
);
336 /* save them to pci_dev_put outside of spinlock */
337 nb
= amd_chipset
.nb_dev
;
338 smbus
= amd_chipset
.smbus_dev
;
340 amd_chipset
.nb_dev
= NULL
;
341 amd_chipset
.smbus_dev
= NULL
;
342 amd_chipset
.nb_type
= 0;
343 amd_chipset
.sb_type
= 0;
344 amd_chipset
.isoc_reqs
= 0;
345 amd_chipset
.probe_result
= 0;
347 spin_unlock_irqrestore(&amd_lock
, flags
);
354 EXPORT_SYMBOL_GPL(usb_amd_dev_put
);
357 * Make sure the controller is completely inactive, unable to
358 * generate interrupts or do DMA.
360 void uhci_reset_hc(struct pci_dev
*pdev
, unsigned long base
)
362 /* Turn off PIRQ enable and SMI enable. (This also turns off the
363 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
365 pci_write_config_word(pdev
, UHCI_USBLEGSUP
, UHCI_USBLEGSUP_RWC
);
367 /* Reset the HC - this will force us to get a
368 * new notification of any already connected
369 * ports due to the virtual disconnect that it
372 outw(UHCI_USBCMD_HCRESET
, base
+ UHCI_USBCMD
);
375 if (inw(base
+ UHCI_USBCMD
) & UHCI_USBCMD_HCRESET
)
376 dev_warn(&pdev
->dev
, "HCRESET not completed yet!\n");
378 /* Just to be safe, disable interrupt requests and
379 * make sure the controller is stopped.
381 outw(0, base
+ UHCI_USBINTR
);
382 outw(0, base
+ UHCI_USBCMD
);
384 EXPORT_SYMBOL_GPL(uhci_reset_hc
);
387 * Initialize a controller that was newly discovered or has just been
388 * resumed. In either case we can't be sure of its previous state.
390 * Returns: 1 if the controller was reset, 0 otherwise.
392 int uhci_check_and_reset_hc(struct pci_dev
*pdev
, unsigned long base
)
395 unsigned int cmd
, intr
;
398 * When restarting a suspended controller, we expect all the
399 * settings to be the same as we left them:
401 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
402 * Controller is stopped and configured with EGSM set;
403 * No interrupts enabled except possibly Resume Detect.
405 * If any of these conditions are violated we do a complete reset.
407 pci_read_config_word(pdev
, UHCI_USBLEGSUP
, &legsup
);
408 if (legsup
& ~(UHCI_USBLEGSUP_RO
| UHCI_USBLEGSUP_RWC
)) {
409 dev_dbg(&pdev
->dev
, "%s: legsup = 0x%04x\n",
414 cmd
= inw(base
+ UHCI_USBCMD
);
415 if ((cmd
& UHCI_USBCMD_RUN
) || !(cmd
& UHCI_USBCMD_CONFIGURE
) ||
416 !(cmd
& UHCI_USBCMD_EGSM
)) {
417 dev_dbg(&pdev
->dev
, "%s: cmd = 0x%04x\n",
422 intr
= inw(base
+ UHCI_USBINTR
);
423 if (intr
& (~UHCI_USBINTR_RESUME
)) {
424 dev_dbg(&pdev
->dev
, "%s: intr = 0x%04x\n",
431 dev_dbg(&pdev
->dev
, "Performing full reset\n");
432 uhci_reset_hc(pdev
, base
);
435 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc
);
437 static inline int io_type_enabled(struct pci_dev
*pdev
, unsigned int mask
)
440 return !pci_read_config_word(pdev
, PCI_COMMAND
, &cmd
) && (cmd
& mask
);
443 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
444 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
446 static void __devinit
quirk_usb_handoff_uhci(struct pci_dev
*pdev
)
448 unsigned long base
= 0;
451 if (!pio_enabled(pdev
))
454 for (i
= 0; i
< PCI_ROM_RESOURCE
; i
++)
455 if ((pci_resource_flags(pdev
, i
) & IORESOURCE_IO
)) {
456 base
= pci_resource_start(pdev
, i
);
461 uhci_check_and_reset_hc(pdev
, base
);
464 static int __devinit
mmio_resource_enabled(struct pci_dev
*pdev
, int idx
)
466 return pci_resource_start(pdev
, idx
) && mmio_enabled(pdev
);
469 static void __devinit
quirk_usb_handoff_ohci(struct pci_dev
*pdev
)
476 if (!mmio_resource_enabled(pdev
, 0))
479 base
= pci_ioremap_bar(pdev
, 0);
483 control
= readl(base
+ OHCI_CONTROL
);
485 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
487 #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
489 #define OHCI_CTRL_MASK OHCI_CTRL_RWC
491 if (control
& OHCI_CTRL_IR
) {
492 int wait_time
= 500; /* arbitrary; 5 seconds */
493 writel(OHCI_INTR_OC
, base
+ OHCI_INTRENABLE
);
494 writel(OHCI_OCR
, base
+ OHCI_CMDSTATUS
);
495 while (wait_time
> 0 &&
496 readl(base
+ OHCI_CONTROL
) & OHCI_CTRL_IR
) {
501 dev_warn(&pdev
->dev
, "OHCI: BIOS handoff failed"
502 " (BIOS bug?) %08x\n",
503 readl(base
+ OHCI_CONTROL
));
507 /* disable interrupts */
508 writel((u32
) ~0, base
+ OHCI_INTRDISABLE
);
510 /* Reset the USB bus, if the controller isn't already in RESET */
511 if (control
& OHCI_HCFS
) {
512 /* Go into RESET, preserving RWC (and possibly IR) */
513 writel(control
& OHCI_CTRL_MASK
, base
+ OHCI_CONTROL
);
514 readl(base
+ OHCI_CONTROL
);
516 /* drive bus reset for at least 50 ms (7.1.7.5) */
520 /* software reset of the controller, preserving HcFmInterval */
521 fminterval
= readl(base
+ OHCI_FMINTERVAL
);
522 writel(OHCI_HCR
, base
+ OHCI_CMDSTATUS
);
524 /* reset requires max 10 us delay */
525 for (cnt
= 30; cnt
> 0; --cnt
) { /* ... allow extra time */
526 if ((readl(base
+ OHCI_CMDSTATUS
) & OHCI_HCR
) == 0)
530 writel(fminterval
, base
+ OHCI_FMINTERVAL
);
532 /* Now the controller is safely in SUSPEND and nothing can wake it up */
536 static const struct dmi_system_id __devinitconst ehci_dmi_nohandoff_table
[] = {
538 /* Pegatron Lucid (ExoPC) */
540 DMI_MATCH(DMI_BOARD_NAME
, "EXOPG06411"),
541 DMI_MATCH(DMI_BIOS_VERSION
, "Lucid-CE-133"),
545 /* Pegatron Lucid (Ordissimo AIRIS) */
547 DMI_MATCH(DMI_BOARD_NAME
, "M11JB"),
548 DMI_MATCH(DMI_BIOS_VERSION
, "Lucid-GE-133"),
554 static void __devinit
ehci_bios_handoff(struct pci_dev
*pdev
,
555 void __iomem
*op_reg_base
,
558 int try_handoff
= 1, tried_handoff
= 0;
560 /* The Pegatron Lucid tablet sporadically waits for 98 seconds trying
561 * the handoff on its unused controller. Skip it. */
562 if (pdev
->vendor
== 0x8086 && pdev
->device
== 0x283a) {
563 if (dmi_check_system(ehci_dmi_nohandoff_table
))
567 if (try_handoff
&& (cap
& EHCI_USBLEGSUP_BIOS
)) {
568 dev_dbg(&pdev
->dev
, "EHCI: BIOS handoff\n");
571 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
572 * but that seems dubious in general (the BIOS left it off intentionally)
573 * and is known to prevent some systems from booting. so we won't do this
574 * unless maybe we can determine when we're on a system that needs SMI forced.
576 /* BIOS workaround (?): be sure the pre-Linux code
579 pci_read_config_dword(pdev
, offset
+ EHCI_USBLEGCTLSTS
, &val
);
580 pci_write_config_dword(pdev
, offset
+ EHCI_USBLEGCTLSTS
,
581 val
| EHCI_USBLEGCTLSTS_SOOE
);
584 /* some systems get upset if this semaphore is
585 * set for any other reason than forcing a BIOS
588 pci_write_config_byte(pdev
, offset
+ 3, 1);
591 /* if boot firmware now owns EHCI, spin till it hands it over. */
594 while ((cap
& EHCI_USBLEGSUP_BIOS
) && (msec
> 0)) {
598 pci_read_config_dword(pdev
, offset
, &cap
);
602 if (cap
& EHCI_USBLEGSUP_BIOS
) {
603 /* well, possibly buggy BIOS... try to shut it down,
604 * and hope nothing goes too wrong
607 dev_warn(&pdev
->dev
, "EHCI: BIOS handoff failed"
608 " (BIOS bug?) %08x\n", cap
);
609 pci_write_config_byte(pdev
, offset
+ 2, 0);
612 /* just in case, always disable EHCI SMIs */
613 pci_write_config_dword(pdev
, offset
+ EHCI_USBLEGCTLSTS
, 0);
615 /* If the BIOS ever owned the controller then we can't expect
616 * any power sessions to remain intact.
619 writel(0, op_reg_base
+ EHCI_CONFIGFLAG
);
622 static void __devinit
quirk_usb_disable_ehci(struct pci_dev
*pdev
)
624 void __iomem
*base
, *op_reg_base
;
625 u32 hcc_params
, cap
, val
;
626 u8 offset
, cap_length
;
627 int wait_time
, count
= 256/4;
629 if (!mmio_resource_enabled(pdev
, 0))
632 base
= pci_ioremap_bar(pdev
, 0);
636 cap_length
= readb(base
);
637 op_reg_base
= base
+ cap_length
;
639 /* EHCI 0.96 and later may have "extended capabilities"
640 * spec section 5.1 explains the bios handoff, e.g. for
641 * booting from USB disk or using a usb keyboard
643 hcc_params
= readl(base
+ EHCI_HCC_PARAMS
);
644 offset
= (hcc_params
>> 8) & 0xff;
645 while (offset
&& --count
) {
646 pci_read_config_dword(pdev
, offset
, &cap
);
648 switch (cap
& 0xff) {
650 ehci_bios_handoff(pdev
, op_reg_base
, cap
, offset
);
652 case 0: /* Illegal reserved cap, set cap=0 so we exit */
653 cap
= 0; /* then fallthrough... */
655 dev_warn(&pdev
->dev
, "EHCI: unrecognized capability "
656 "%02x\n", cap
& 0xff);
658 offset
= (cap
>> 8) & 0xff;
661 dev_printk(KERN_DEBUG
, &pdev
->dev
, "EHCI: capability loop?\n");
664 * halt EHCI & disable its interrupts in any case
666 val
= readl(op_reg_base
+ EHCI_USBSTS
);
667 if ((val
& EHCI_USBSTS_HALTED
) == 0) {
668 val
= readl(op_reg_base
+ EHCI_USBCMD
);
669 val
&= ~EHCI_USBCMD_RUN
;
670 writel(val
, op_reg_base
+ EHCI_USBCMD
);
674 writel(0x3f, op_reg_base
+ EHCI_USBSTS
);
677 val
= readl(op_reg_base
+ EHCI_USBSTS
);
678 if ((val
== ~(u32
)0) || (val
& EHCI_USBSTS_HALTED
)) {
681 } while (wait_time
> 0);
683 writel(0, op_reg_base
+ EHCI_USBINTR
);
684 writel(0x3f, op_reg_base
+ EHCI_USBSTS
);
690 * handshake - spin reading a register until handshake completes
691 * @ptr: address of hc register to be read
692 * @mask: bits to look at in result of read
693 * @done: value of those bits when handshake succeeds
694 * @wait_usec: timeout in microseconds
695 * @delay_usec: delay in microseconds to wait between polling
697 * Polls a register every delay_usec microseconds.
698 * Returns 0 when the mask bits have the value done.
699 * Returns -ETIMEDOUT if this condition is not true after
700 * wait_usec microseconds have passed.
702 static int handshake(void __iomem
*ptr
, u32 mask
, u32 done
,
703 int wait_usec
, int delay_usec
)
713 wait_usec
-= delay_usec
;
714 } while (wait_usec
> 0);
718 #define PCI_DEVICE_ID_INTEL_LYNX_POINT_XHCI 0x8C31
720 bool usb_is_intel_ppt_switchable_xhci(struct pci_dev
*pdev
)
722 return pdev
->class == PCI_CLASS_SERIAL_USB_XHCI
&&
723 pdev
->vendor
== PCI_VENDOR_ID_INTEL
&&
724 pdev
->device
== PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI
;
727 /* The Intel Lynx Point chipset also has switchable ports. */
728 bool usb_is_intel_lpt_switchable_xhci(struct pci_dev
*pdev
)
730 return pdev
->class == PCI_CLASS_SERIAL_USB_XHCI
&&
731 pdev
->vendor
== PCI_VENDOR_ID_INTEL
&&
732 pdev
->device
== PCI_DEVICE_ID_INTEL_LYNX_POINT_XHCI
;
735 bool usb_is_intel_switchable_xhci(struct pci_dev
*pdev
)
737 return usb_is_intel_ppt_switchable_xhci(pdev
) ||
738 usb_is_intel_lpt_switchable_xhci(pdev
);
740 EXPORT_SYMBOL_GPL(usb_is_intel_switchable_xhci
);
743 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
744 * share some number of ports. These ports can be switched between either
745 * controller. Not all of the ports under the EHCI host controller may be
748 * The ports should be switched over to xHCI before PCI probes for any device
749 * start. This avoids active devices under EHCI being disconnected during the
750 * port switchover, which could cause loss of data on USB storage devices, or
751 * failed boot when the root file system is on a USB mass storage device and is
752 * enumerated under EHCI first.
754 * We write into the xHC's PCI configuration space in some Intel-specific
755 * registers to switch the ports over. The USB 3.0 terminations and the USB
756 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
757 * terminations before switching the USB 2.0 wires over, so that USB 3.0
758 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
760 void usb_enable_xhci_ports(struct pci_dev
*xhci_pdev
)
764 /* Don't switchover the ports if the user hasn't compiled the xHCI
765 * driver. Otherwise they will see "dead" USB ports that don't power
768 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD
)) {
769 dev_warn(&xhci_pdev
->dev
,
770 "CONFIG_USB_XHCI_HCD is turned off, "
771 "defaulting to EHCI.\n");
772 dev_warn(&xhci_pdev
->dev
,
773 "USB 3.0 devices will work at USB 2.0 speeds.\n");
777 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
778 * Indicate the ports that can be changed from OS.
780 pci_read_config_dword(xhci_pdev
, USB_INTEL_USB3PRM
,
783 dev_dbg(&xhci_pdev
->dev
, "Configurable ports to enable SuperSpeed: 0x%x\n",
786 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
787 * Register, to turn on SuperSpeed terminations for the
790 pci_write_config_dword(xhci_pdev
, USB_INTEL_USB3_PSSEN
,
791 cpu_to_le32(ports_available
));
793 pci_read_config_dword(xhci_pdev
, USB_INTEL_USB3_PSSEN
,
795 dev_dbg(&xhci_pdev
->dev
, "USB 3.0 ports that are now enabled "
796 "under xHCI: 0x%x\n", ports_available
);
798 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
799 * Indicate the USB 2.0 ports to be controlled by the xHCI host.
802 pci_read_config_dword(xhci_pdev
, USB_INTEL_USB2PRM
,
805 dev_dbg(&xhci_pdev
->dev
, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
808 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
809 * switch the USB 2.0 power and data lines over to the xHCI
812 pci_write_config_dword(xhci_pdev
, USB_INTEL_XUSB2PR
,
813 cpu_to_le32(ports_available
));
815 pci_read_config_dword(xhci_pdev
, USB_INTEL_XUSB2PR
,
817 dev_dbg(&xhci_pdev
->dev
, "USB 2.0 ports that are now switched over "
818 "to xHCI: 0x%x\n", ports_available
);
820 EXPORT_SYMBOL_GPL(usb_enable_xhci_ports
);
822 void usb_disable_xhci_ports(struct pci_dev
*xhci_pdev
)
824 pci_write_config_dword(xhci_pdev
, USB_INTEL_USB3_PSSEN
, 0x0);
825 pci_write_config_dword(xhci_pdev
, USB_INTEL_XUSB2PR
, 0x0);
827 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports
);
830 * PCI Quirks for xHCI.
832 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
833 * It signals to the BIOS that the OS wants control of the host controller,
834 * and then waits 5 seconds for the BIOS to hand over control.
835 * If we timeout, assume the BIOS is broken and take control anyway.
837 static void __devinit
quirk_usb_handoff_xhci(struct pci_dev
*pdev
)
841 void __iomem
*op_reg_base
;
844 int len
= pci_resource_len(pdev
, 0);
846 if (!mmio_resource_enabled(pdev
, 0))
849 base
= ioremap_nocache(pci_resource_start(pdev
, 0), len
);
854 * Find the Legacy Support Capability register -
855 * this is optional for xHCI host controllers.
857 ext_cap_offset
= xhci_find_next_cap_offset(base
, XHCI_HCC_PARAMS_OFFSET
);
859 if ((ext_cap_offset
+ sizeof(val
)) > len
) {
860 /* We're reading garbage from the controller */
862 "xHCI controller failing to respond");
867 /* We've reached the end of the extended capabilities */
870 val
= readl(base
+ ext_cap_offset
);
871 if (XHCI_EXT_CAPS_ID(val
) == XHCI_EXT_CAPS_LEGACY
)
873 ext_cap_offset
= xhci_find_next_cap_offset(base
, ext_cap_offset
);
876 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
877 if (val
& XHCI_HC_BIOS_OWNED
) {
878 writel(val
| XHCI_HC_OS_OWNED
, base
+ ext_cap_offset
);
880 /* Wait for 5 seconds with 10 microsecond polling interval */
881 timeout
= handshake(base
+ ext_cap_offset
, XHCI_HC_BIOS_OWNED
,
884 /* Assume a buggy BIOS and take HC ownership anyway */
886 dev_warn(&pdev
->dev
, "xHCI BIOS handoff failed"
887 " (BIOS bug ?) %08x\n", val
);
888 writel(val
& ~XHCI_HC_BIOS_OWNED
, base
+ ext_cap_offset
);
892 val
= readl(base
+ ext_cap_offset
+ XHCI_LEGACY_CONTROL_OFFSET
);
893 /* Mask off (turn off) any enabled SMIs */
894 val
&= XHCI_LEGACY_DISABLE_SMI
;
895 /* Mask all SMI events bits, RW1C */
896 val
|= XHCI_LEGACY_SMI_EVENTS
;
897 /* Disable any BIOS SMIs and clear all SMI events*/
898 writel(val
, base
+ ext_cap_offset
+ XHCI_LEGACY_CONTROL_OFFSET
);
901 if (usb_is_intel_switchable_xhci(pdev
))
902 usb_enable_xhci_ports(pdev
);
904 op_reg_base
= base
+ XHCI_HC_LENGTH(readl(base
));
906 /* Wait for the host controller to be ready before writing any
907 * operational or runtime registers. Wait 5 seconds and no more.
909 timeout
= handshake(op_reg_base
+ XHCI_STS_OFFSET
, XHCI_STS_CNR
, 0,
911 /* Assume a buggy HC and start HC initialization anyway */
913 val
= readl(op_reg_base
+ XHCI_STS_OFFSET
);
915 "xHCI HW not ready after 5 sec (HC bug?) "
916 "status = 0x%x\n", val
);
919 /* Send the halt and disable interrupts command */
920 val
= readl(op_reg_base
+ XHCI_CMD_OFFSET
);
921 val
&= ~(XHCI_CMD_RUN
| XHCI_IRQS
);
922 writel(val
, op_reg_base
+ XHCI_CMD_OFFSET
);
924 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
925 timeout
= handshake(op_reg_base
+ XHCI_STS_OFFSET
, XHCI_STS_HALT
, 1,
926 XHCI_MAX_HALT_USEC
, 125);
928 val
= readl(op_reg_base
+ XHCI_STS_OFFSET
);
930 "xHCI HW did not halt within %d usec "
931 "status = 0x%x\n", XHCI_MAX_HALT_USEC
, val
);
937 static void __devinit
quirk_usb_early_handoff(struct pci_dev
*pdev
)
939 /* Skip Netlogic mips SoC's internal PCI USB controller.
940 * This device does not need/support EHCI/OHCI handoff
942 if (pdev
->vendor
== 0x184e) /* vendor Netlogic */
944 if (pdev
->class != PCI_CLASS_SERIAL_USB_UHCI
&&
945 pdev
->class != PCI_CLASS_SERIAL_USB_OHCI
&&
946 pdev
->class != PCI_CLASS_SERIAL_USB_EHCI
&&
947 pdev
->class != PCI_CLASS_SERIAL_USB_XHCI
)
950 if (pci_enable_device(pdev
) < 0) {
951 dev_warn(&pdev
->dev
, "Can't enable PCI device, "
952 "BIOS handoff failed.\n");
955 if (pdev
->class == PCI_CLASS_SERIAL_USB_UHCI
)
956 quirk_usb_handoff_uhci(pdev
);
957 else if (pdev
->class == PCI_CLASS_SERIAL_USB_OHCI
)
958 quirk_usb_handoff_ohci(pdev
);
959 else if (pdev
->class == PCI_CLASS_SERIAL_USB_EHCI
)
960 quirk_usb_disable_ehci(pdev
);
961 else if (pdev
->class == PCI_CLASS_SERIAL_USB_XHCI
)
962 quirk_usb_handoff_xhci(pdev
);
963 pci_disable_device(pdev
);
965 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
966 PCI_CLASS_SERIAL_USB
, 8, quirk_usb_early_handoff
);