2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/acpi.h>
29 #include "xhci-trace.h"
31 #define PORT2_SSIC_CONFIG_REG2 0x883c
32 #define PROG_DONE (1 << 30)
33 #define SSIC_PORT_UNUSED (1 << 31)
35 /* Device for a quirk */
36 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
37 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
38 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
40 #define PCI_VENDOR_ID_ETRON 0x1b6f
41 #define PCI_DEVICE_ID_EJ168 0x7023
43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
44 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
45 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
46 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
47 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
49 static const char hcd_name
[] = "xhci_hcd";
51 static struct hc_driver __read_mostly xhci_pci_hc_driver
;
53 static int xhci_pci_setup(struct usb_hcd
*hcd
);
55 static const struct xhci_driver_overrides xhci_pci_overrides __initconst
= {
56 .extra_priv_size
= sizeof(struct xhci_hcd
),
57 .reset
= xhci_pci_setup
,
60 /* called after powerup, by probe or system-pm "wakeup" */
61 static int xhci_pci_reinit(struct xhci_hcd
*xhci
, struct pci_dev
*pdev
)
64 * TODO: Implement finding debug ports later.
65 * TODO: see if there are any quirks that need to be added to handle
66 * new extended capabilities.
69 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
70 if (!pci_set_mwi(pdev
))
71 xhci_dbg(xhci
, "MWI active\n");
73 xhci_dbg(xhci
, "Finished xhci_pci_reinit\n");
77 static void xhci_pci_quirks(struct device
*dev
, struct xhci_hcd
*xhci
)
79 struct pci_dev
*pdev
= to_pci_dev(dev
);
81 /* Look for vendor-specific quirks */
82 if (pdev
->vendor
== PCI_VENDOR_ID_FRESCO_LOGIC
&&
83 (pdev
->device
== PCI_DEVICE_ID_FRESCO_LOGIC_PDK
||
84 pdev
->device
== PCI_DEVICE_ID_FRESCO_LOGIC_FL1400
)) {
85 if (pdev
->device
== PCI_DEVICE_ID_FRESCO_LOGIC_PDK
&&
86 pdev
->revision
== 0x0) {
87 xhci
->quirks
|= XHCI_RESET_EP_QUIRK
;
88 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
89 "QUIRK: Fresco Logic xHC needs configure"
90 " endpoint cmd after reset endpoint");
92 if (pdev
->device
== PCI_DEVICE_ID_FRESCO_LOGIC_PDK
&&
93 pdev
->revision
== 0x4) {
94 xhci
->quirks
|= XHCI_SLOW_SUSPEND
;
95 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
96 "QUIRK: Fresco Logic xHC revision %u"
97 "must be suspended extra slowly",
100 if (pdev
->device
== PCI_DEVICE_ID_FRESCO_LOGIC_PDK
)
101 xhci
->quirks
|= XHCI_BROKEN_STREAMS
;
102 /* Fresco Logic confirms: all revisions of this chip do not
103 * support MSI, even though some of them claim to in their PCI
106 xhci
->quirks
|= XHCI_BROKEN_MSI
;
107 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
108 "QUIRK: Fresco Logic revision %u "
109 "has broken MSI implementation",
111 xhci
->quirks
|= XHCI_TRUST_TX_LENGTH
;
114 if (pdev
->vendor
== PCI_VENDOR_ID_NEC
)
115 xhci
->quirks
|= XHCI_NEC_HOST
;
117 if (pdev
->vendor
== PCI_VENDOR_ID_AMD
&& xhci
->hci_version
== 0x96)
118 xhci
->quirks
|= XHCI_AMD_0x96_HOST
;
121 if (pdev
->vendor
== PCI_VENDOR_ID_AMD
&& usb_amd_find_chipset_info())
122 xhci
->quirks
|= XHCI_AMD_PLL_FIX
;
124 if (pdev
->vendor
== PCI_VENDOR_ID_AMD
)
125 xhci
->quirks
|= XHCI_TRUST_TX_LENGTH
;
127 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
) {
128 xhci
->quirks
|= XHCI_LPM_SUPPORT
;
129 xhci
->quirks
|= XHCI_INTEL_HOST
;
130 xhci
->quirks
|= XHCI_AVOID_BEI
;
132 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
&&
133 pdev
->device
== PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI
) {
134 xhci
->quirks
|= XHCI_EP_LIMIT_QUIRK
;
135 xhci
->limit_active_eps
= 64;
136 xhci
->quirks
|= XHCI_SW_BW_CHECKING
;
138 * PPT desktop boards DH77EB and DH77DF will power back on after
139 * a few seconds of being shutdown. The fix for this is to
140 * switch the ports from xHCI to EHCI on shutdown. We can't use
141 * DMI information to find those particular boards (since each
142 * vendor will change the board name), so we have to key off all
145 xhci
->quirks
|= XHCI_SPURIOUS_REBOOT
;
147 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
&&
148 pdev
->device
== PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI
) {
149 xhci
->quirks
|= XHCI_SPURIOUS_REBOOT
;
151 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
&&
152 (pdev
->device
== PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI
||
153 pdev
->device
== PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI
||
154 pdev
->device
== PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI
)) {
155 xhci
->quirks
|= XHCI_PME_STUCK_QUIRK
;
157 if (pdev
->vendor
== PCI_VENDOR_ID_ETRON
&&
158 pdev
->device
== PCI_DEVICE_ID_EJ168
) {
159 xhci
->quirks
|= XHCI_RESET_ON_RESUME
;
160 xhci
->quirks
|= XHCI_TRUST_TX_LENGTH
;
161 xhci
->quirks
|= XHCI_BROKEN_STREAMS
;
163 if (pdev
->vendor
== PCI_VENDOR_ID_RENESAS
&&
164 pdev
->device
== 0x0015)
165 xhci
->quirks
|= XHCI_RESET_ON_RESUME
;
166 if (pdev
->vendor
== PCI_VENDOR_ID_VIA
)
167 xhci
->quirks
|= XHCI_RESET_ON_RESUME
;
169 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
170 if (pdev
->vendor
== PCI_VENDOR_ID_VIA
&&
171 pdev
->device
== 0x3432)
172 xhci
->quirks
|= XHCI_BROKEN_STREAMS
;
174 if (pdev
->vendor
== PCI_VENDOR_ID_ASMEDIA
&&
175 pdev
->device
== 0x1042)
176 xhci
->quirks
|= XHCI_BROKEN_STREAMS
;
178 if (xhci
->quirks
& XHCI_RESET_ON_RESUME
)
179 xhci_dbg_trace(xhci
, trace_xhci_dbg_quirks
,
180 "QUIRK: Resetting on resume");
184 * In some Intel xHCI controllers, in order to get D3 working,
185 * through a vendor specific SSIC CONFIG register at offset 0x883c,
186 * SSIC PORT need to be marked as "unused" before putting xHCI
187 * into D3. After D3 exit, the SSIC port need to be marked as "used".
188 * Without this change, xHCI might not enter D3 state.
189 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
190 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
192 static void xhci_pme_quirk(struct usb_hcd
*hcd
, bool suspend
)
194 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
195 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
199 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
&&
200 pdev
->device
== PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI
) {
202 reg
= (void __iomem
*) xhci
->cap_regs
+ PORT2_SSIC_CONFIG_REG2
;
204 /* Notify SSIC that SSIC profile programming is not done */
205 val
= readl(reg
) & ~PROG_DONE
;
208 /* Mark SSIC port as unused(suspend) or used(resume) */
211 val
|= SSIC_PORT_UNUSED
;
213 val
&= ~SSIC_PORT_UNUSED
;
216 /* Notify SSIC that SSIC profile programming is done */
217 val
= readl(reg
) | PROG_DONE
;
222 reg
= (void __iomem
*) xhci
->cap_regs
+ 0x80a4;
224 writel(val
| BIT(28), reg
);
229 static void xhci_pme_acpi_rtd3_enable(struct pci_dev
*dev
)
231 static const u8 intel_dsm_uuid
[] = {
232 0xb7, 0x0c, 0x34, 0xac, 0x01, 0xe9, 0xbf, 0x45,
233 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23,
235 acpi_evaluate_dsm(ACPI_HANDLE(&dev
->dev
), intel_dsm_uuid
, 3, 1, NULL
);
238 static void xhci_pme_acpi_rtd3_enable(struct pci_dev
*dev
) { }
239 #endif /* CONFIG_ACPI */
241 /* called during probe() after chip reset completes */
242 static int xhci_pci_setup(struct usb_hcd
*hcd
)
244 struct xhci_hcd
*xhci
;
245 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
248 retval
= xhci_gen_setup(hcd
, xhci_pci_quirks
);
252 xhci
= hcd_to_xhci(hcd
);
253 if (!usb_hcd_is_primary_hcd(hcd
))
256 pci_read_config_byte(pdev
, XHCI_SBRN_OFFSET
, &xhci
->sbrn
);
257 xhci_dbg(xhci
, "Got SBRN %u\n", (unsigned int) xhci
->sbrn
);
259 /* Find any debug ports */
260 retval
= xhci_pci_reinit(xhci
, pdev
);
268 * We need to register our own PCI probe function (instead of the USB core's
269 * function) in order to create a second roothub under xHCI.
271 static int xhci_pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
274 struct xhci_hcd
*xhci
;
275 struct hc_driver
*driver
;
278 driver
= (struct hc_driver
*)id
->driver_data
;
280 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
281 pm_runtime_get_noresume(&dev
->dev
);
283 /* Register the USB 2.0 roothub.
284 * FIXME: USB core must know to register the USB 2.0 roothub first.
285 * This is sort of silly, because we could just set the HCD driver flags
286 * to say USB 2.0, but I'm not sure what the implications would be in
287 * the other parts of the HCD code.
289 retval
= usb_hcd_pci_probe(dev
, id
);
294 /* USB 2.0 roothub is stored in the PCI device now. */
295 hcd
= dev_get_drvdata(&dev
->dev
);
296 xhci
= hcd_to_xhci(hcd
);
297 xhci
->shared_hcd
= usb_create_shared_hcd(driver
, &dev
->dev
,
299 if (!xhci
->shared_hcd
) {
301 goto dealloc_usb2_hcd
;
304 retval
= usb_add_hcd(xhci
->shared_hcd
, dev
->irq
,
308 /* Roothub already marked as USB 3.0 speed */
310 if (!(xhci
->quirks
& XHCI_BROKEN_STREAMS
) &&
311 HCC_MAX_PSA(xhci
->hcc_params
) >= 4)
312 xhci
->shared_hcd
->can_do_streams
= 1;
314 if (xhci
->quirks
& XHCI_PME_STUCK_QUIRK
)
315 xhci_pme_acpi_rtd3_enable(dev
);
317 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
318 pm_runtime_put_noidle(&dev
->dev
);
323 usb_put_hcd(xhci
->shared_hcd
);
325 usb_hcd_pci_remove(dev
);
327 pm_runtime_put_noidle(&dev
->dev
);
331 static void xhci_pci_remove(struct pci_dev
*dev
)
333 struct xhci_hcd
*xhci
;
335 xhci
= hcd_to_xhci(pci_get_drvdata(dev
));
336 if (xhci
->shared_hcd
) {
337 usb_remove_hcd(xhci
->shared_hcd
);
338 usb_put_hcd(xhci
->shared_hcd
);
340 usb_hcd_pci_remove(dev
);
342 /* Workaround for spurious wakeups at shutdown with HSW */
343 if (xhci
->quirks
& XHCI_SPURIOUS_WAKEUP
)
344 pci_set_power_state(dev
, PCI_D3hot
);
348 static int xhci_pci_suspend(struct usb_hcd
*hcd
, bool do_wakeup
)
350 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
351 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
354 * Systems with the TI redriver that loses port status change events
355 * need to have the registers polled during D3, so avoid D3cold.
357 if (xhci
->quirks
& XHCI_COMP_MODE_QUIRK
)
358 pdev
->no_d3cold
= true;
360 if (xhci
->quirks
& XHCI_PME_STUCK_QUIRK
)
361 xhci_pme_quirk(hcd
, true);
363 return xhci_suspend(xhci
, do_wakeup
);
366 static int xhci_pci_resume(struct usb_hcd
*hcd
, bool hibernated
)
368 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
369 struct pci_dev
*pdev
= to_pci_dev(hcd
->self
.controller
);
372 /* The BIOS on systems with the Intel Panther Point chipset may or may
373 * not support xHCI natively. That means that during system resume, it
374 * may switch the ports back to EHCI so that users can use their
375 * keyboard to select a kernel from GRUB after resume from hibernate.
377 * The BIOS is supposed to remember whether the OS had xHCI ports
378 * enabled before resume, and switch the ports back to xHCI when the
379 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
382 * Unconditionally switch the ports back to xHCI after a system resume.
383 * It should not matter whether the EHCI or xHCI controller is
384 * resumed first. It's enough to do the switchover in xHCI because
385 * USB core won't notice anything as the hub driver doesn't start
386 * running again until after all the devices (including both EHCI and
387 * xHCI host controllers) have been resumed.
390 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
)
391 usb_enable_intel_xhci_ports(pdev
);
393 if (xhci
->quirks
& XHCI_PME_STUCK_QUIRK
)
394 xhci_pme_quirk(hcd
, false);
396 retval
= xhci_resume(xhci
, hibernated
);
399 #endif /* CONFIG_PM */
401 /*-------------------------------------------------------------------------*/
403 /* PCI driver selection metadata; PCI hotplugging uses this */
404 static const struct pci_device_id pci_ids
[] = { {
405 /* handle any USB 3.0 xHCI controller */
406 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI
, ~0),
407 .driver_data
= (unsigned long) &xhci_pci_hc_driver
,
409 { /* end: all zeroes */ }
411 MODULE_DEVICE_TABLE(pci
, pci_ids
);
413 /* pci driver glue; this is a "new style" PCI driver module */
414 static struct pci_driver xhci_pci_driver
= {
415 .name
= (char *) hcd_name
,
418 .probe
= xhci_pci_probe
,
419 .remove
= xhci_pci_remove
,
420 /* suspend and resume implemented later */
422 .shutdown
= usb_hcd_pci_shutdown
,
425 .pm
= &usb_hcd_pci_pm_ops
430 static int __init
xhci_pci_init(void)
432 xhci_init_driver(&xhci_pci_hc_driver
, &xhci_pci_overrides
);
434 xhci_pci_hc_driver
.pci_suspend
= xhci_pci_suspend
;
435 xhci_pci_hc_driver
.pci_resume
= xhci_pci_resume
;
437 return pci_register_driver(&xhci_pci_driver
);
439 module_init(xhci_pci_init
);
441 static void __exit
xhci_pci_exit(void)
443 pci_unregister_driver(&xhci_pci_driver
);
445 module_exit(xhci_pci_exit
);
447 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
448 MODULE_LICENSE("GPL");