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Merge tag 'md-3.5-fixes' of git://neil.brown.name/md
[deliverable/linux.git] / drivers / usb / musb / musb_core.c
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/prefetch.h>
100 #include <linux/platform_device.h>
101 #include <linux/io.h>
102
103 #include "musb_core.h"
104
105 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
106
107
108 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
109 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
110
111 #define MUSB_VERSION "6.0"
112
113 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
114
115 #define MUSB_DRIVER_NAME "musb-hdrc"
116 const char musb_driver_name[] = MUSB_DRIVER_NAME;
117
118 MODULE_DESCRIPTION(DRIVER_INFO);
119 MODULE_AUTHOR(DRIVER_AUTHOR);
120 MODULE_LICENSE("GPL");
121 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
122
123
124 /*-------------------------------------------------------------------------*/
125
126 static inline struct musb *dev_to_musb(struct device *dev)
127 {
128 return dev_get_drvdata(dev);
129 }
130
131 /*-------------------------------------------------------------------------*/
132
133 #ifndef CONFIG_BLACKFIN
134 static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
135 {
136 void __iomem *addr = phy->io_priv;
137 int i = 0;
138 u8 r;
139 u8 power;
140 int ret;
141
142 pm_runtime_get_sync(phy->io_dev);
143
144 /* Make sure the transceiver is not in low power mode */
145 power = musb_readb(addr, MUSB_POWER);
146 power &= ~MUSB_POWER_SUSPENDM;
147 musb_writeb(addr, MUSB_POWER, power);
148
149 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
150 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
151 */
152
153 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
154 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
155 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
156
157 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
158 & MUSB_ULPI_REG_CMPLT)) {
159 i++;
160 if (i == 10000) {
161 ret = -ETIMEDOUT;
162 goto out;
163 }
164
165 }
166 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
167 r &= ~MUSB_ULPI_REG_CMPLT;
168 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
169
170 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
171
172 out:
173 pm_runtime_put(phy->io_dev);
174
175 return ret;
176 }
177
178 static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
179 {
180 void __iomem *addr = phy->io_priv;
181 int i = 0;
182 u8 r = 0;
183 u8 power;
184 int ret = 0;
185
186 pm_runtime_get_sync(phy->io_dev);
187
188 /* Make sure the transceiver is not in low power mode */
189 power = musb_readb(addr, MUSB_POWER);
190 power &= ~MUSB_POWER_SUSPENDM;
191 musb_writeb(addr, MUSB_POWER, power);
192
193 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
194 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
195 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
196
197 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
198 & MUSB_ULPI_REG_CMPLT)) {
199 i++;
200 if (i == 10000) {
201 ret = -ETIMEDOUT;
202 goto out;
203 }
204 }
205
206 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
207 r &= ~MUSB_ULPI_REG_CMPLT;
208 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
209
210 out:
211 pm_runtime_put(phy->io_dev);
212
213 return ret;
214 }
215 #else
216 #define musb_ulpi_read NULL
217 #define musb_ulpi_write NULL
218 #endif
219
220 static struct usb_phy_io_ops musb_ulpi_access = {
221 .read = musb_ulpi_read,
222 .write = musb_ulpi_write,
223 };
224
225 /*-------------------------------------------------------------------------*/
226
227 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
228
229 /*
230 * Load an endpoint's FIFO
231 */
232 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
233 {
234 struct musb *musb = hw_ep->musb;
235 void __iomem *fifo = hw_ep->fifo;
236
237 prefetch((u8 *)src);
238
239 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
240 'T', hw_ep->epnum, fifo, len, src);
241
242 /* we can't assume unaligned reads work */
243 if (likely((0x01 & (unsigned long) src) == 0)) {
244 u16 index = 0;
245
246 /* best case is 32bit-aligned source address */
247 if ((0x02 & (unsigned long) src) == 0) {
248 if (len >= 4) {
249 writesl(fifo, src + index, len >> 2);
250 index += len & ~0x03;
251 }
252 if (len & 0x02) {
253 musb_writew(fifo, 0, *(u16 *)&src[index]);
254 index += 2;
255 }
256 } else {
257 if (len >= 2) {
258 writesw(fifo, src + index, len >> 1);
259 index += len & ~0x01;
260 }
261 }
262 if (len & 0x01)
263 musb_writeb(fifo, 0, src[index]);
264 } else {
265 /* byte aligned */
266 writesb(fifo, src, len);
267 }
268 }
269
270 #if !defined(CONFIG_USB_MUSB_AM35X)
271 /*
272 * Unload an endpoint's FIFO
273 */
274 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
275 {
276 struct musb *musb = hw_ep->musb;
277 void __iomem *fifo = hw_ep->fifo;
278
279 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
280 'R', hw_ep->epnum, fifo, len, dst);
281
282 /* we can't assume unaligned writes work */
283 if (likely((0x01 & (unsigned long) dst) == 0)) {
284 u16 index = 0;
285
286 /* best case is 32bit-aligned destination address */
287 if ((0x02 & (unsigned long) dst) == 0) {
288 if (len >= 4) {
289 readsl(fifo, dst, len >> 2);
290 index = len & ~0x03;
291 }
292 if (len & 0x02) {
293 *(u16 *)&dst[index] = musb_readw(fifo, 0);
294 index += 2;
295 }
296 } else {
297 if (len >= 2) {
298 readsw(fifo, dst, len >> 1);
299 index = len & ~0x01;
300 }
301 }
302 if (len & 0x01)
303 dst[index] = musb_readb(fifo, 0);
304 } else {
305 /* byte aligned */
306 readsb(fifo, dst, len);
307 }
308 }
309 #endif
310
311 #endif /* normal PIO */
312
313
314 /*-------------------------------------------------------------------------*/
315
316 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
317 static const u8 musb_test_packet[53] = {
318 /* implicit SYNC then DATA0 to start */
319
320 /* JKJKJKJK x9 */
321 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
322 /* JJKKJJKK x8 */
323 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
324 /* JJJJKKKK x8 */
325 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
326 /* JJJJJJJKKKKKKK x8 */
327 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
328 /* JJJJJJJK x8 */
329 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
330 /* JKKKKKKK x10, JK */
331 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
332
333 /* implicit CRC16 then EOP to end */
334 };
335
336 void musb_load_testpacket(struct musb *musb)
337 {
338 void __iomem *regs = musb->endpoints[0].regs;
339
340 musb_ep_select(musb->mregs, 0);
341 musb_write_fifo(musb->control_ep,
342 sizeof(musb_test_packet), musb_test_packet);
343 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
344 }
345
346 /*-------------------------------------------------------------------------*/
347
348 /*
349 * Handles OTG hnp timeouts, such as b_ase0_brst
350 */
351 void musb_otg_timer_func(unsigned long data)
352 {
353 struct musb *musb = (struct musb *)data;
354 unsigned long flags;
355
356 spin_lock_irqsave(&musb->lock, flags);
357 switch (musb->xceiv->state) {
358 case OTG_STATE_B_WAIT_ACON:
359 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
360 musb_g_disconnect(musb);
361 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
362 musb->is_active = 0;
363 break;
364 case OTG_STATE_A_SUSPEND:
365 case OTG_STATE_A_WAIT_BCON:
366 dev_dbg(musb->controller, "HNP: %s timeout\n",
367 otg_state_string(musb->xceiv->state));
368 musb_platform_set_vbus(musb, 0);
369 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
370 break;
371 default:
372 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
373 otg_state_string(musb->xceiv->state));
374 }
375 musb->ignore_disconnect = 0;
376 spin_unlock_irqrestore(&musb->lock, flags);
377 }
378
379 /*
380 * Stops the HNP transition. Caller must take care of locking.
381 */
382 void musb_hnp_stop(struct musb *musb)
383 {
384 struct usb_hcd *hcd = musb_to_hcd(musb);
385 void __iomem *mbase = musb->mregs;
386 u8 reg;
387
388 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
389
390 switch (musb->xceiv->state) {
391 case OTG_STATE_A_PERIPHERAL:
392 musb_g_disconnect(musb);
393 dev_dbg(musb->controller, "HNP: back to %s\n",
394 otg_state_string(musb->xceiv->state));
395 break;
396 case OTG_STATE_B_HOST:
397 dev_dbg(musb->controller, "HNP: Disabling HR\n");
398 hcd->self.is_b_host = 0;
399 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
400 MUSB_DEV_MODE(musb);
401 reg = musb_readb(mbase, MUSB_POWER);
402 reg |= MUSB_POWER_SUSPENDM;
403 musb_writeb(mbase, MUSB_POWER, reg);
404 /* REVISIT: Start SESSION_REQUEST here? */
405 break;
406 default:
407 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
408 otg_state_string(musb->xceiv->state));
409 }
410
411 /*
412 * When returning to A state after HNP, avoid hub_port_rebounce(),
413 * which cause occasional OPT A "Did not receive reset after connect"
414 * errors.
415 */
416 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
417 }
418
419 /*
420 * Interrupt Service Routine to record USB "global" interrupts.
421 * Since these do not happen often and signify things of
422 * paramount importance, it seems OK to check them individually;
423 * the order of the tests is specified in the manual
424 *
425 * @param musb instance pointer
426 * @param int_usb register contents
427 * @param devctl
428 * @param power
429 */
430
431 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
432 u8 devctl, u8 power)
433 {
434 struct usb_otg *otg = musb->xceiv->otg;
435 irqreturn_t handled = IRQ_NONE;
436
437 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
438 int_usb);
439
440 /* in host mode, the peripheral may issue remote wakeup.
441 * in peripheral mode, the host may resume the link.
442 * spurious RESUME irqs happen too, paired with SUSPEND.
443 */
444 if (int_usb & MUSB_INTR_RESUME) {
445 handled = IRQ_HANDLED;
446 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
447
448 if (devctl & MUSB_DEVCTL_HM) {
449 void __iomem *mbase = musb->mregs;
450
451 switch (musb->xceiv->state) {
452 case OTG_STATE_A_SUSPEND:
453 /* remote wakeup? later, GetPortStatus
454 * will stop RESUME signaling
455 */
456
457 if (power & MUSB_POWER_SUSPENDM) {
458 /* spurious */
459 musb->int_usb &= ~MUSB_INTR_SUSPEND;
460 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
461 break;
462 }
463
464 power &= ~MUSB_POWER_SUSPENDM;
465 musb_writeb(mbase, MUSB_POWER,
466 power | MUSB_POWER_RESUME);
467
468 musb->port1_status |=
469 (USB_PORT_STAT_C_SUSPEND << 16)
470 | MUSB_PORT_STAT_RESUME;
471 musb->rh_timer = jiffies
472 + msecs_to_jiffies(20);
473
474 musb->xceiv->state = OTG_STATE_A_HOST;
475 musb->is_active = 1;
476 usb_hcd_resume_root_hub(musb_to_hcd(musb));
477 break;
478 case OTG_STATE_B_WAIT_ACON:
479 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
480 musb->is_active = 1;
481 MUSB_DEV_MODE(musb);
482 break;
483 default:
484 WARNING("bogus %s RESUME (%s)\n",
485 "host",
486 otg_state_string(musb->xceiv->state));
487 }
488 } else {
489 switch (musb->xceiv->state) {
490 case OTG_STATE_A_SUSPEND:
491 /* possibly DISCONNECT is upcoming */
492 musb->xceiv->state = OTG_STATE_A_HOST;
493 usb_hcd_resume_root_hub(musb_to_hcd(musb));
494 break;
495 case OTG_STATE_B_WAIT_ACON:
496 case OTG_STATE_B_PERIPHERAL:
497 /* disconnect while suspended? we may
498 * not get a disconnect irq...
499 */
500 if ((devctl & MUSB_DEVCTL_VBUS)
501 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
502 ) {
503 musb->int_usb |= MUSB_INTR_DISCONNECT;
504 musb->int_usb &= ~MUSB_INTR_SUSPEND;
505 break;
506 }
507 musb_g_resume(musb);
508 break;
509 case OTG_STATE_B_IDLE:
510 musb->int_usb &= ~MUSB_INTR_SUSPEND;
511 break;
512 default:
513 WARNING("bogus %s RESUME (%s)\n",
514 "peripheral",
515 otg_state_string(musb->xceiv->state));
516 }
517 }
518 }
519
520 /* see manual for the order of the tests */
521 if (int_usb & MUSB_INTR_SESSREQ) {
522 void __iomem *mbase = musb->mregs;
523
524 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
525 && (devctl & MUSB_DEVCTL_BDEVICE)) {
526 dev_dbg(musb->controller, "SessReq while on B state\n");
527 return IRQ_HANDLED;
528 }
529
530 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
531 otg_state_string(musb->xceiv->state));
532
533 /* IRQ arrives from ID pin sense or (later, if VBUS power
534 * is removed) SRP. responses are time critical:
535 * - turn on VBUS (with silicon-specific mechanism)
536 * - go through A_WAIT_VRISE
537 * - ... to A_WAIT_BCON.
538 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
539 */
540 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
541 musb->ep0_stage = MUSB_EP0_START;
542 musb->xceiv->state = OTG_STATE_A_IDLE;
543 MUSB_HST_MODE(musb);
544 musb_platform_set_vbus(musb, 1);
545
546 handled = IRQ_HANDLED;
547 }
548
549 if (int_usb & MUSB_INTR_VBUSERROR) {
550 int ignore = 0;
551
552 /* During connection as an A-Device, we may see a short
553 * current spikes causing voltage drop, because of cable
554 * and peripheral capacitance combined with vbus draw.
555 * (So: less common with truly self-powered devices, where
556 * vbus doesn't act like a power supply.)
557 *
558 * Such spikes are short; usually less than ~500 usec, max
559 * of ~2 msec. That is, they're not sustained overcurrent
560 * errors, though they're reported using VBUSERROR irqs.
561 *
562 * Workarounds: (a) hardware: use self powered devices.
563 * (b) software: ignore non-repeated VBUS errors.
564 *
565 * REVISIT: do delays from lots of DEBUG_KERNEL checks
566 * make trouble here, keeping VBUS < 4.4V ?
567 */
568 switch (musb->xceiv->state) {
569 case OTG_STATE_A_HOST:
570 /* recovery is dicey once we've gotten past the
571 * initial stages of enumeration, but if VBUS
572 * stayed ok at the other end of the link, and
573 * another reset is due (at least for high speed,
574 * to redo the chirp etc), it might work OK...
575 */
576 case OTG_STATE_A_WAIT_BCON:
577 case OTG_STATE_A_WAIT_VRISE:
578 if (musb->vbuserr_retry) {
579 void __iomem *mbase = musb->mregs;
580
581 musb->vbuserr_retry--;
582 ignore = 1;
583 devctl |= MUSB_DEVCTL_SESSION;
584 musb_writeb(mbase, MUSB_DEVCTL, devctl);
585 } else {
586 musb->port1_status |=
587 USB_PORT_STAT_OVERCURRENT
588 | (USB_PORT_STAT_C_OVERCURRENT << 16);
589 }
590 break;
591 default:
592 break;
593 }
594
595 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
596 otg_state_string(musb->xceiv->state),
597 devctl,
598 ({ char *s;
599 switch (devctl & MUSB_DEVCTL_VBUS) {
600 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
601 s = "<SessEnd"; break;
602 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
603 s = "<AValid"; break;
604 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
605 s = "<VBusValid"; break;
606 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
607 default:
608 s = "VALID"; break;
609 }; s; }),
610 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
611 musb->port1_status);
612
613 /* go through A_WAIT_VFALL then start a new session */
614 if (!ignore)
615 musb_platform_set_vbus(musb, 0);
616 handled = IRQ_HANDLED;
617 }
618
619 if (int_usb & MUSB_INTR_SUSPEND) {
620 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
621 otg_state_string(musb->xceiv->state), devctl, power);
622 handled = IRQ_HANDLED;
623
624 switch (musb->xceiv->state) {
625 case OTG_STATE_A_PERIPHERAL:
626 /* We also come here if the cable is removed, since
627 * this silicon doesn't report ID-no-longer-grounded.
628 *
629 * We depend on T(a_wait_bcon) to shut us down, and
630 * hope users don't do anything dicey during this
631 * undesired detour through A_WAIT_BCON.
632 */
633 musb_hnp_stop(musb);
634 usb_hcd_resume_root_hub(musb_to_hcd(musb));
635 musb_root_disconnect(musb);
636 musb_platform_try_idle(musb, jiffies
637 + msecs_to_jiffies(musb->a_wait_bcon
638 ? : OTG_TIME_A_WAIT_BCON));
639
640 break;
641 case OTG_STATE_B_IDLE:
642 if (!musb->is_active)
643 break;
644 case OTG_STATE_B_PERIPHERAL:
645 musb_g_suspend(musb);
646 musb->is_active = is_otg_enabled(musb)
647 && otg->gadget->b_hnp_enable;
648 if (musb->is_active) {
649 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
650 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
651 mod_timer(&musb->otg_timer, jiffies
652 + msecs_to_jiffies(
653 OTG_TIME_B_ASE0_BRST));
654 }
655 break;
656 case OTG_STATE_A_WAIT_BCON:
657 if (musb->a_wait_bcon != 0)
658 musb_platform_try_idle(musb, jiffies
659 + msecs_to_jiffies(musb->a_wait_bcon));
660 break;
661 case OTG_STATE_A_HOST:
662 musb->xceiv->state = OTG_STATE_A_SUSPEND;
663 musb->is_active = is_otg_enabled(musb)
664 && otg->host->b_hnp_enable;
665 break;
666 case OTG_STATE_B_HOST:
667 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
668 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
669 break;
670 default:
671 /* "should not happen" */
672 musb->is_active = 0;
673 break;
674 }
675 }
676
677 if (int_usb & MUSB_INTR_CONNECT) {
678 struct usb_hcd *hcd = musb_to_hcd(musb);
679
680 handled = IRQ_HANDLED;
681 musb->is_active = 1;
682
683 musb->ep0_stage = MUSB_EP0_START;
684
685 /* flush endpoints when transitioning from Device Mode */
686 if (is_peripheral_active(musb)) {
687 /* REVISIT HNP; just force disconnect */
688 }
689 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
690 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
691 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
692 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
693 |USB_PORT_STAT_HIGH_SPEED
694 |USB_PORT_STAT_ENABLE
695 );
696 musb->port1_status |= USB_PORT_STAT_CONNECTION
697 |(USB_PORT_STAT_C_CONNECTION << 16);
698
699 /* high vs full speed is just a guess until after reset */
700 if (devctl & MUSB_DEVCTL_LSDEV)
701 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
702
703 /* indicate new connection to OTG machine */
704 switch (musb->xceiv->state) {
705 case OTG_STATE_B_PERIPHERAL:
706 if (int_usb & MUSB_INTR_SUSPEND) {
707 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
708 int_usb &= ~MUSB_INTR_SUSPEND;
709 goto b_host;
710 } else
711 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
712 break;
713 case OTG_STATE_B_WAIT_ACON:
714 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
715 b_host:
716 musb->xceiv->state = OTG_STATE_B_HOST;
717 hcd->self.is_b_host = 1;
718 musb->ignore_disconnect = 0;
719 del_timer(&musb->otg_timer);
720 break;
721 default:
722 if ((devctl & MUSB_DEVCTL_VBUS)
723 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
724 musb->xceiv->state = OTG_STATE_A_HOST;
725 hcd->self.is_b_host = 0;
726 }
727 break;
728 }
729
730 /* poke the root hub */
731 MUSB_HST_MODE(musb);
732 if (hcd->status_urb)
733 usb_hcd_poll_rh_status(hcd);
734 else
735 usb_hcd_resume_root_hub(hcd);
736
737 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
738 otg_state_string(musb->xceiv->state), devctl);
739 }
740
741 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
742 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
743 otg_state_string(musb->xceiv->state),
744 MUSB_MODE(musb), devctl);
745 handled = IRQ_HANDLED;
746
747 switch (musb->xceiv->state) {
748 case OTG_STATE_A_HOST:
749 case OTG_STATE_A_SUSPEND:
750 usb_hcd_resume_root_hub(musb_to_hcd(musb));
751 musb_root_disconnect(musb);
752 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
753 musb_platform_try_idle(musb, jiffies
754 + msecs_to_jiffies(musb->a_wait_bcon));
755 break;
756 case OTG_STATE_B_HOST:
757 /* REVISIT this behaves for "real disconnect"
758 * cases; make sure the other transitions from
759 * from B_HOST act right too. The B_HOST code
760 * in hnp_stop() is currently not used...
761 */
762 musb_root_disconnect(musb);
763 musb_to_hcd(musb)->self.is_b_host = 0;
764 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
765 MUSB_DEV_MODE(musb);
766 musb_g_disconnect(musb);
767 break;
768 case OTG_STATE_A_PERIPHERAL:
769 musb_hnp_stop(musb);
770 musb_root_disconnect(musb);
771 /* FALLTHROUGH */
772 case OTG_STATE_B_WAIT_ACON:
773 /* FALLTHROUGH */
774 case OTG_STATE_B_PERIPHERAL:
775 case OTG_STATE_B_IDLE:
776 musb_g_disconnect(musb);
777 break;
778 default:
779 WARNING("unhandled DISCONNECT transition (%s)\n",
780 otg_state_string(musb->xceiv->state));
781 break;
782 }
783 }
784
785 /* mentor saves a bit: bus reset and babble share the same irq.
786 * only host sees babble; only peripheral sees bus reset.
787 */
788 if (int_usb & MUSB_INTR_RESET) {
789 handled = IRQ_HANDLED;
790 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
791 /*
792 * Looks like non-HS BABBLE can be ignored, but
793 * HS BABBLE is an error condition. For HS the solution
794 * is to avoid babble in the first place and fix what
795 * caused BABBLE. When HS BABBLE happens we can only
796 * stop the session.
797 */
798 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
799 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
800 else {
801 ERR("Stopping host session -- babble\n");
802 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
803 }
804 } else if (is_peripheral_capable()) {
805 dev_dbg(musb->controller, "BUS RESET as %s\n",
806 otg_state_string(musb->xceiv->state));
807 switch (musb->xceiv->state) {
808 case OTG_STATE_A_SUSPEND:
809 /* We need to ignore disconnect on suspend
810 * otherwise tusb 2.0 won't reconnect after a
811 * power cycle, which breaks otg compliance.
812 */
813 musb->ignore_disconnect = 1;
814 musb_g_reset(musb);
815 /* FALLTHROUGH */
816 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
817 /* never use invalid T(a_wait_bcon) */
818 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
819 otg_state_string(musb->xceiv->state),
820 TA_WAIT_BCON(musb));
821 mod_timer(&musb->otg_timer, jiffies
822 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
823 break;
824 case OTG_STATE_A_PERIPHERAL:
825 musb->ignore_disconnect = 0;
826 del_timer(&musb->otg_timer);
827 musb_g_reset(musb);
828 break;
829 case OTG_STATE_B_WAIT_ACON:
830 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
831 otg_state_string(musb->xceiv->state));
832 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
833 musb_g_reset(musb);
834 break;
835 case OTG_STATE_B_IDLE:
836 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
837 /* FALLTHROUGH */
838 case OTG_STATE_B_PERIPHERAL:
839 musb_g_reset(musb);
840 break;
841 default:
842 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
843 otg_state_string(musb->xceiv->state));
844 }
845 }
846 }
847
848 #if 0
849 /* REVISIT ... this would be for multiplexing periodic endpoints, or
850 * supporting transfer phasing to prevent exceeding ISO bandwidth
851 * limits of a given frame or microframe.
852 *
853 * It's not needed for peripheral side, which dedicates endpoints;
854 * though it _might_ use SOF irqs for other purposes.
855 *
856 * And it's not currently needed for host side, which also dedicates
857 * endpoints, relies on TX/RX interval registers, and isn't claimed
858 * to support ISO transfers yet.
859 */
860 if (int_usb & MUSB_INTR_SOF) {
861 void __iomem *mbase = musb->mregs;
862 struct musb_hw_ep *ep;
863 u8 epnum;
864 u16 frame;
865
866 dev_dbg(musb->controller, "START_OF_FRAME\n");
867 handled = IRQ_HANDLED;
868
869 /* start any periodic Tx transfers waiting for current frame */
870 frame = musb_readw(mbase, MUSB_FRAME);
871 ep = musb->endpoints;
872 for (epnum = 1; (epnum < musb->nr_endpoints)
873 && (musb->epmask >= (1 << epnum));
874 epnum++, ep++) {
875 /*
876 * FIXME handle framecounter wraps (12 bits)
877 * eliminate duplicated StartUrb logic
878 */
879 if (ep->dwWaitFrame >= frame) {
880 ep->dwWaitFrame = 0;
881 pr_debug("SOF --> periodic TX%s on %d\n",
882 ep->tx_channel ? " DMA" : "",
883 epnum);
884 if (!ep->tx_channel)
885 musb_h_tx_start(musb, epnum);
886 else
887 cppi_hostdma_start(musb, epnum);
888 }
889 } /* end of for loop */
890 }
891 #endif
892
893 schedule_work(&musb->irq_work);
894
895 return handled;
896 }
897
898 /*-------------------------------------------------------------------------*/
899
900 /*
901 * Program the HDRC to start (enable interrupts, dma, etc.).
902 */
903 void musb_start(struct musb *musb)
904 {
905 void __iomem *regs = musb->mregs;
906 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
907
908 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
909
910 /* Set INT enable registers, enable interrupts */
911 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
912 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
913 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
914
915 musb_writeb(regs, MUSB_TESTMODE, 0);
916
917 /* put into basic highspeed mode and start session */
918 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
919 | MUSB_POWER_HSENAB
920 /* ENSUSPEND wedges tusb */
921 /* | MUSB_POWER_ENSUSPEND */
922 );
923
924 musb->is_active = 0;
925 devctl = musb_readb(regs, MUSB_DEVCTL);
926 devctl &= ~MUSB_DEVCTL_SESSION;
927
928 if (is_otg_enabled(musb)) {
929 /* session started after:
930 * (a) ID-grounded irq, host mode;
931 * (b) vbus present/connect IRQ, peripheral mode;
932 * (c) peripheral initiates, using SRP
933 */
934 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
935 musb->is_active = 1;
936 else
937 devctl |= MUSB_DEVCTL_SESSION;
938
939 } else if (is_host_enabled(musb)) {
940 /* assume ID pin is hard-wired to ground */
941 devctl |= MUSB_DEVCTL_SESSION;
942
943 } else /* peripheral is enabled */ {
944 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
945 musb->is_active = 1;
946 }
947 musb_platform_enable(musb);
948 musb_writeb(regs, MUSB_DEVCTL, devctl);
949 }
950
951
952 static void musb_generic_disable(struct musb *musb)
953 {
954 void __iomem *mbase = musb->mregs;
955 u16 temp;
956
957 /* disable interrupts */
958 musb_writeb(mbase, MUSB_INTRUSBE, 0);
959 musb_writew(mbase, MUSB_INTRTXE, 0);
960 musb_writew(mbase, MUSB_INTRRXE, 0);
961
962 /* off */
963 musb_writeb(mbase, MUSB_DEVCTL, 0);
964
965 /* flush pending interrupts */
966 temp = musb_readb(mbase, MUSB_INTRUSB);
967 temp = musb_readw(mbase, MUSB_INTRTX);
968 temp = musb_readw(mbase, MUSB_INTRRX);
969
970 }
971
972 /*
973 * Make the HDRC stop (disable interrupts, etc.);
974 * reversible by musb_start
975 * called on gadget driver unregister
976 * with controller locked, irqs blocked
977 * acts as a NOP unless some role activated the hardware
978 */
979 void musb_stop(struct musb *musb)
980 {
981 /* stop IRQs, timers, ... */
982 musb_platform_disable(musb);
983 musb_generic_disable(musb);
984 dev_dbg(musb->controller, "HDRC disabled\n");
985
986 /* FIXME
987 * - mark host and/or peripheral drivers unusable/inactive
988 * - disable DMA (and enable it in HdrcStart)
989 * - make sure we can musb_start() after musb_stop(); with
990 * OTG mode, gadget driver module rmmod/modprobe cycles that
991 * - ...
992 */
993 musb_platform_try_idle(musb, 0);
994 }
995
996 static void musb_shutdown(struct platform_device *pdev)
997 {
998 struct musb *musb = dev_to_musb(&pdev->dev);
999 unsigned long flags;
1000
1001 pm_runtime_get_sync(musb->controller);
1002
1003 musb_gadget_cleanup(musb);
1004
1005 spin_lock_irqsave(&musb->lock, flags);
1006 musb_platform_disable(musb);
1007 musb_generic_disable(musb);
1008 spin_unlock_irqrestore(&musb->lock, flags);
1009
1010 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1011 usb_remove_hcd(musb_to_hcd(musb));
1012 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1013 musb_platform_exit(musb);
1014
1015 pm_runtime_put(musb->controller);
1016 /* FIXME power down */
1017 }
1018
1019
1020 /*-------------------------------------------------------------------------*/
1021
1022 /*
1023 * The silicon either has hard-wired endpoint configurations, or else
1024 * "dynamic fifo" sizing. The driver has support for both, though at this
1025 * writing only the dynamic sizing is very well tested. Since we switched
1026 * away from compile-time hardware parameters, we can no longer rely on
1027 * dead code elimination to leave only the relevant one in the object file.
1028 *
1029 * We don't currently use dynamic fifo setup capability to do anything
1030 * more than selecting one of a bunch of predefined configurations.
1031 */
1032 #if defined(CONFIG_USB_MUSB_TUSB6010) \
1033 || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
1034 || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1035 || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
1036 || defined(CONFIG_USB_MUSB_AM35X) \
1037 || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
1038 || defined(CONFIG_USB_MUSB_DSPS) \
1039 || defined(CONFIG_USB_MUSB_DSPS_MODULE)
1040 static ushort __devinitdata fifo_mode = 4;
1041 #elif defined(CONFIG_USB_MUSB_UX500) \
1042 || defined(CONFIG_USB_MUSB_UX500_MODULE)
1043 static ushort __devinitdata fifo_mode = 5;
1044 #else
1045 static ushort __devinitdata fifo_mode = 2;
1046 #endif
1047
1048 /* "modprobe ... fifo_mode=1" etc */
1049 module_param(fifo_mode, ushort, 0);
1050 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1051
1052 /*
1053 * tables defining fifo_mode values. define more if you like.
1054 * for host side, make sure both halves of ep1 are set up.
1055 */
1056
1057 /* mode 0 - fits in 2KB */
1058 static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
1059 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1060 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1061 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1062 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1063 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1064 };
1065
1066 /* mode 1 - fits in 4KB */
1067 static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
1068 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1069 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1070 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1071 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1072 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1073 };
1074
1075 /* mode 2 - fits in 4KB */
1076 static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
1077 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1078 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1079 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1080 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1081 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1082 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1083 };
1084
1085 /* mode 3 - fits in 4KB */
1086 static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
1087 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1088 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1089 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1090 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1091 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1092 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1093 };
1094
1095 /* mode 4 - fits in 16KB */
1096 static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
1097 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1098 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1099 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1100 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1101 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1102 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1103 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1104 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1105 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1106 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1107 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1108 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1109 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1110 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1111 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1112 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1113 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1114 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1115 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1116 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1117 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1118 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1119 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1120 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1121 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1122 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1123 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1124 };
1125
1126 /* mode 5 - fits in 8KB */
1127 static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
1128 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1129 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1130 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1131 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1132 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1133 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1134 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1135 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1136 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1137 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1138 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1139 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1140 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1141 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1142 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1143 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1144 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1145 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1146 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1147 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1148 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1149 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1150 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1151 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1152 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1153 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1154 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1155 };
1156
1157 /*
1158 * configure a fifo; for non-shared endpoints, this may be called
1159 * once for a tx fifo and once for an rx fifo.
1160 *
1161 * returns negative errno or offset for next fifo.
1162 */
1163 static int __devinit
1164 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1165 const struct musb_fifo_cfg *cfg, u16 offset)
1166 {
1167 void __iomem *mbase = musb->mregs;
1168 int size = 0;
1169 u16 maxpacket = cfg->maxpacket;
1170 u16 c_off = offset >> 3;
1171 u8 c_size;
1172
1173 /* expect hw_ep has already been zero-initialized */
1174
1175 size = ffs(max(maxpacket, (u16) 8)) - 1;
1176 maxpacket = 1 << size;
1177
1178 c_size = size - 3;
1179 if (cfg->mode == BUF_DOUBLE) {
1180 if ((offset + (maxpacket << 1)) >
1181 (1 << (musb->config->ram_bits + 2)))
1182 return -EMSGSIZE;
1183 c_size |= MUSB_FIFOSZ_DPB;
1184 } else {
1185 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1186 return -EMSGSIZE;
1187 }
1188
1189 /* configure the FIFO */
1190 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1191
1192 /* EP0 reserved endpoint for control, bidirectional;
1193 * EP1 reserved for bulk, two unidirection halves.
1194 */
1195 if (hw_ep->epnum == 1)
1196 musb->bulk_ep = hw_ep;
1197 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1198 switch (cfg->style) {
1199 case FIFO_TX:
1200 musb_write_txfifosz(mbase, c_size);
1201 musb_write_txfifoadd(mbase, c_off);
1202 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1203 hw_ep->max_packet_sz_tx = maxpacket;
1204 break;
1205 case FIFO_RX:
1206 musb_write_rxfifosz(mbase, c_size);
1207 musb_write_rxfifoadd(mbase, c_off);
1208 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1209 hw_ep->max_packet_sz_rx = maxpacket;
1210 break;
1211 case FIFO_RXTX:
1212 musb_write_txfifosz(mbase, c_size);
1213 musb_write_txfifoadd(mbase, c_off);
1214 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1215 hw_ep->max_packet_sz_rx = maxpacket;
1216
1217 musb_write_rxfifosz(mbase, c_size);
1218 musb_write_rxfifoadd(mbase, c_off);
1219 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1220 hw_ep->max_packet_sz_tx = maxpacket;
1221
1222 hw_ep->is_shared_fifo = true;
1223 break;
1224 }
1225
1226 /* NOTE rx and tx endpoint irqs aren't managed separately,
1227 * which happens to be ok
1228 */
1229 musb->epmask |= (1 << hw_ep->epnum);
1230
1231 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1232 }
1233
1234 static struct musb_fifo_cfg __devinitdata ep0_cfg = {
1235 .style = FIFO_RXTX, .maxpacket = 64,
1236 };
1237
1238 static int __devinit ep_config_from_table(struct musb *musb)
1239 {
1240 const struct musb_fifo_cfg *cfg;
1241 unsigned i, n;
1242 int offset;
1243 struct musb_hw_ep *hw_ep = musb->endpoints;
1244
1245 if (musb->config->fifo_cfg) {
1246 cfg = musb->config->fifo_cfg;
1247 n = musb->config->fifo_cfg_size;
1248 goto done;
1249 }
1250
1251 switch (fifo_mode) {
1252 default:
1253 fifo_mode = 0;
1254 /* FALLTHROUGH */
1255 case 0:
1256 cfg = mode_0_cfg;
1257 n = ARRAY_SIZE(mode_0_cfg);
1258 break;
1259 case 1:
1260 cfg = mode_1_cfg;
1261 n = ARRAY_SIZE(mode_1_cfg);
1262 break;
1263 case 2:
1264 cfg = mode_2_cfg;
1265 n = ARRAY_SIZE(mode_2_cfg);
1266 break;
1267 case 3:
1268 cfg = mode_3_cfg;
1269 n = ARRAY_SIZE(mode_3_cfg);
1270 break;
1271 case 4:
1272 cfg = mode_4_cfg;
1273 n = ARRAY_SIZE(mode_4_cfg);
1274 break;
1275 case 5:
1276 cfg = mode_5_cfg;
1277 n = ARRAY_SIZE(mode_5_cfg);
1278 break;
1279 }
1280
1281 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1282 musb_driver_name, fifo_mode);
1283
1284
1285 done:
1286 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1287 /* assert(offset > 0) */
1288
1289 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1290 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1291 */
1292
1293 for (i = 0; i < n; i++) {
1294 u8 epn = cfg->hw_ep_num;
1295
1296 if (epn >= musb->config->num_eps) {
1297 pr_debug("%s: invalid ep %d\n",
1298 musb_driver_name, epn);
1299 return -EINVAL;
1300 }
1301 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1302 if (offset < 0) {
1303 pr_debug("%s: mem overrun, ep %d\n",
1304 musb_driver_name, epn);
1305 return -EINVAL;
1306 }
1307 epn++;
1308 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1309 }
1310
1311 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1312 musb_driver_name,
1313 n + 1, musb->config->num_eps * 2 - 1,
1314 offset, (1 << (musb->config->ram_bits + 2)));
1315
1316 if (!musb->bulk_ep) {
1317 pr_debug("%s: missing bulk\n", musb_driver_name);
1318 return -EINVAL;
1319 }
1320
1321 return 0;
1322 }
1323
1324
1325 /*
1326 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1327 * @param musb the controller
1328 */
1329 static int __devinit ep_config_from_hw(struct musb *musb)
1330 {
1331 u8 epnum = 0;
1332 struct musb_hw_ep *hw_ep;
1333 void *mbase = musb->mregs;
1334 int ret = 0;
1335
1336 dev_dbg(musb->controller, "<== static silicon ep config\n");
1337
1338 /* FIXME pick up ep0 maxpacket size */
1339
1340 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1341 musb_ep_select(mbase, epnum);
1342 hw_ep = musb->endpoints + epnum;
1343
1344 ret = musb_read_fifosize(musb, hw_ep, epnum);
1345 if (ret < 0)
1346 break;
1347
1348 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1349
1350 /* pick an RX/TX endpoint for bulk */
1351 if (hw_ep->max_packet_sz_tx < 512
1352 || hw_ep->max_packet_sz_rx < 512)
1353 continue;
1354
1355 /* REVISIT: this algorithm is lazy, we should at least
1356 * try to pick a double buffered endpoint.
1357 */
1358 if (musb->bulk_ep)
1359 continue;
1360 musb->bulk_ep = hw_ep;
1361 }
1362
1363 if (!musb->bulk_ep) {
1364 pr_debug("%s: missing bulk\n", musb_driver_name);
1365 return -EINVAL;
1366 }
1367
1368 return 0;
1369 }
1370
1371 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1372
1373 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1374 * configure endpoints, or take their config from silicon
1375 */
1376 static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
1377 {
1378 u8 reg;
1379 char *type;
1380 char aInfo[90], aRevision[32], aDate[12];
1381 void __iomem *mbase = musb->mregs;
1382 int status = 0;
1383 int i;
1384
1385 /* log core options (read using indexed model) */
1386 reg = musb_read_configdata(mbase);
1387
1388 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1389 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1390 strcat(aInfo, ", dyn FIFOs");
1391 musb->dyn_fifo = true;
1392 }
1393 if (reg & MUSB_CONFIGDATA_MPRXE) {
1394 strcat(aInfo, ", bulk combine");
1395 musb->bulk_combine = true;
1396 }
1397 if (reg & MUSB_CONFIGDATA_MPTXE) {
1398 strcat(aInfo, ", bulk split");
1399 musb->bulk_split = true;
1400 }
1401 if (reg & MUSB_CONFIGDATA_HBRXE) {
1402 strcat(aInfo, ", HB-ISO Rx");
1403 musb->hb_iso_rx = true;
1404 }
1405 if (reg & MUSB_CONFIGDATA_HBTXE) {
1406 strcat(aInfo, ", HB-ISO Tx");
1407 musb->hb_iso_tx = true;
1408 }
1409 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1410 strcat(aInfo, ", SoftConn");
1411
1412 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1413 musb_driver_name, reg, aInfo);
1414
1415 aDate[0] = 0;
1416 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1417 musb->is_multipoint = 1;
1418 type = "M";
1419 } else {
1420 musb->is_multipoint = 0;
1421 type = "";
1422 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1423 printk(KERN_ERR
1424 "%s: kernel must blacklist external hubs\n",
1425 musb_driver_name);
1426 #endif
1427 }
1428
1429 /* log release info */
1430 musb->hwvers = musb_read_hwvers(mbase);
1431 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1432 MUSB_HWVERS_MINOR(musb->hwvers),
1433 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1434 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1435 musb_driver_name, type, aRevision, aDate);
1436
1437 /* configure ep0 */
1438 musb_configure_ep0(musb);
1439
1440 /* discover endpoint configuration */
1441 musb->nr_endpoints = 1;
1442 musb->epmask = 1;
1443
1444 if (musb->dyn_fifo)
1445 status = ep_config_from_table(musb);
1446 else
1447 status = ep_config_from_hw(musb);
1448
1449 if (status < 0)
1450 return status;
1451
1452 /* finish init, and print endpoint config */
1453 for (i = 0; i < musb->nr_endpoints; i++) {
1454 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1455
1456 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1457 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
1458 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1459 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1460 hw_ep->fifo_sync_va =
1461 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1462
1463 if (i == 0)
1464 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1465 else
1466 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1467 #endif
1468
1469 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1470 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1471 hw_ep->rx_reinit = 1;
1472 hw_ep->tx_reinit = 1;
1473
1474 if (hw_ep->max_packet_sz_tx) {
1475 dev_dbg(musb->controller,
1476 "%s: hw_ep %d%s, %smax %d\n",
1477 musb_driver_name, i,
1478 hw_ep->is_shared_fifo ? "shared" : "tx",
1479 hw_ep->tx_double_buffered
1480 ? "doublebuffer, " : "",
1481 hw_ep->max_packet_sz_tx);
1482 }
1483 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1484 dev_dbg(musb->controller,
1485 "%s: hw_ep %d%s, %smax %d\n",
1486 musb_driver_name, i,
1487 "rx",
1488 hw_ep->rx_double_buffered
1489 ? "doublebuffer, " : "",
1490 hw_ep->max_packet_sz_rx);
1491 }
1492 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1493 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1494 }
1495
1496 return 0;
1497 }
1498
1499 /*-------------------------------------------------------------------------*/
1500
1501 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1502 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
1503
1504 static irqreturn_t generic_interrupt(int irq, void *__hci)
1505 {
1506 unsigned long flags;
1507 irqreturn_t retval = IRQ_NONE;
1508 struct musb *musb = __hci;
1509
1510 spin_lock_irqsave(&musb->lock, flags);
1511
1512 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1513 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1514 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1515
1516 if (musb->int_usb || musb->int_tx || musb->int_rx)
1517 retval = musb_interrupt(musb);
1518
1519 spin_unlock_irqrestore(&musb->lock, flags);
1520
1521 return retval;
1522 }
1523
1524 #else
1525 #define generic_interrupt NULL
1526 #endif
1527
1528 /*
1529 * handle all the irqs defined by the HDRC core. for now we expect: other
1530 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1531 * will be assigned, and the irq will already have been acked.
1532 *
1533 * called in irq context with spinlock held, irqs blocked
1534 */
1535 irqreturn_t musb_interrupt(struct musb *musb)
1536 {
1537 irqreturn_t retval = IRQ_NONE;
1538 u8 devctl, power;
1539 int ep_num;
1540 u32 reg;
1541
1542 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1543 power = musb_readb(musb->mregs, MUSB_POWER);
1544
1545 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1546 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1547 musb->int_usb, musb->int_tx, musb->int_rx);
1548
1549 /* the core can interrupt us for multiple reasons; docs have
1550 * a generic interrupt flowchart to follow
1551 */
1552 if (musb->int_usb)
1553 retval |= musb_stage0_irq(musb, musb->int_usb,
1554 devctl, power);
1555
1556 /* "stage 1" is handling endpoint irqs */
1557
1558 /* handle endpoint 0 first */
1559 if (musb->int_tx & 1) {
1560 if (devctl & MUSB_DEVCTL_HM)
1561 retval |= musb_h_ep0_irq(musb);
1562 else
1563 retval |= musb_g_ep0_irq(musb);
1564 }
1565
1566 /* RX on endpoints 1-15 */
1567 reg = musb->int_rx >> 1;
1568 ep_num = 1;
1569 while (reg) {
1570 if (reg & 1) {
1571 /* musb_ep_select(musb->mregs, ep_num); */
1572 /* REVISIT just retval = ep->rx_irq(...) */
1573 retval = IRQ_HANDLED;
1574 if (devctl & MUSB_DEVCTL_HM) {
1575 if (is_host_capable())
1576 musb_host_rx(musb, ep_num);
1577 } else {
1578 if (is_peripheral_capable())
1579 musb_g_rx(musb, ep_num);
1580 }
1581 }
1582
1583 reg >>= 1;
1584 ep_num++;
1585 }
1586
1587 /* TX on endpoints 1-15 */
1588 reg = musb->int_tx >> 1;
1589 ep_num = 1;
1590 while (reg) {
1591 if (reg & 1) {
1592 /* musb_ep_select(musb->mregs, ep_num); */
1593 /* REVISIT just retval |= ep->tx_irq(...) */
1594 retval = IRQ_HANDLED;
1595 if (devctl & MUSB_DEVCTL_HM) {
1596 if (is_host_capable())
1597 musb_host_tx(musb, ep_num);
1598 } else {
1599 if (is_peripheral_capable())
1600 musb_g_tx(musb, ep_num);
1601 }
1602 }
1603 reg >>= 1;
1604 ep_num++;
1605 }
1606
1607 return retval;
1608 }
1609 EXPORT_SYMBOL_GPL(musb_interrupt);
1610
1611 #ifndef CONFIG_MUSB_PIO_ONLY
1612 static bool __devinitdata use_dma = 1;
1613
1614 /* "modprobe ... use_dma=0" etc */
1615 module_param(use_dma, bool, 0);
1616 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1617
1618 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1619 {
1620 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1621
1622 /* called with controller lock already held */
1623
1624 if (!epnum) {
1625 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1626 if (!is_cppi_enabled()) {
1627 /* endpoint 0 */
1628 if (devctl & MUSB_DEVCTL_HM)
1629 musb_h_ep0_irq(musb);
1630 else
1631 musb_g_ep0_irq(musb);
1632 }
1633 #endif
1634 } else {
1635 /* endpoints 1..15 */
1636 if (transmit) {
1637 if (devctl & MUSB_DEVCTL_HM) {
1638 if (is_host_capable())
1639 musb_host_tx(musb, epnum);
1640 } else {
1641 if (is_peripheral_capable())
1642 musb_g_tx(musb, epnum);
1643 }
1644 } else {
1645 /* receive */
1646 if (devctl & MUSB_DEVCTL_HM) {
1647 if (is_host_capable())
1648 musb_host_rx(musb, epnum);
1649 } else {
1650 if (is_peripheral_capable())
1651 musb_g_rx(musb, epnum);
1652 }
1653 }
1654 }
1655 }
1656 EXPORT_SYMBOL_GPL(musb_dma_completion);
1657
1658 #else
1659 #define use_dma 0
1660 #endif
1661
1662 /*-------------------------------------------------------------------------*/
1663
1664 #ifdef CONFIG_SYSFS
1665
1666 static ssize_t
1667 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1668 {
1669 struct musb *musb = dev_to_musb(dev);
1670 unsigned long flags;
1671 int ret = -EINVAL;
1672
1673 spin_lock_irqsave(&musb->lock, flags);
1674 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1675 spin_unlock_irqrestore(&musb->lock, flags);
1676
1677 return ret;
1678 }
1679
1680 static ssize_t
1681 musb_mode_store(struct device *dev, struct device_attribute *attr,
1682 const char *buf, size_t n)
1683 {
1684 struct musb *musb = dev_to_musb(dev);
1685 unsigned long flags;
1686 int status;
1687
1688 spin_lock_irqsave(&musb->lock, flags);
1689 if (sysfs_streq(buf, "host"))
1690 status = musb_platform_set_mode(musb, MUSB_HOST);
1691 else if (sysfs_streq(buf, "peripheral"))
1692 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1693 else if (sysfs_streq(buf, "otg"))
1694 status = musb_platform_set_mode(musb, MUSB_OTG);
1695 else
1696 status = -EINVAL;
1697 spin_unlock_irqrestore(&musb->lock, flags);
1698
1699 return (status == 0) ? n : status;
1700 }
1701 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1702
1703 static ssize_t
1704 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1705 const char *buf, size_t n)
1706 {
1707 struct musb *musb = dev_to_musb(dev);
1708 unsigned long flags;
1709 unsigned long val;
1710
1711 if (sscanf(buf, "%lu", &val) < 1) {
1712 dev_err(dev, "Invalid VBUS timeout ms value\n");
1713 return -EINVAL;
1714 }
1715
1716 spin_lock_irqsave(&musb->lock, flags);
1717 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1718 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1719 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1720 musb->is_active = 0;
1721 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1722 spin_unlock_irqrestore(&musb->lock, flags);
1723
1724 return n;
1725 }
1726
1727 static ssize_t
1728 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1729 {
1730 struct musb *musb = dev_to_musb(dev);
1731 unsigned long flags;
1732 unsigned long val;
1733 int vbus;
1734
1735 spin_lock_irqsave(&musb->lock, flags);
1736 val = musb->a_wait_bcon;
1737 /* FIXME get_vbus_status() is normally #defined as false...
1738 * and is effectively TUSB-specific.
1739 */
1740 vbus = musb_platform_get_vbus_status(musb);
1741 spin_unlock_irqrestore(&musb->lock, flags);
1742
1743 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1744 vbus ? "on" : "off", val);
1745 }
1746 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1747
1748 /* Gadget drivers can't know that a host is connected so they might want
1749 * to start SRP, but users can. This allows userspace to trigger SRP.
1750 */
1751 static ssize_t
1752 musb_srp_store(struct device *dev, struct device_attribute *attr,
1753 const char *buf, size_t n)
1754 {
1755 struct musb *musb = dev_to_musb(dev);
1756 unsigned short srp;
1757
1758 if (sscanf(buf, "%hu", &srp) != 1
1759 || (srp != 1)) {
1760 dev_err(dev, "SRP: Value must be 1\n");
1761 return -EINVAL;
1762 }
1763
1764 if (srp == 1)
1765 musb_g_wakeup(musb);
1766
1767 return n;
1768 }
1769 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1770
1771 static struct attribute *musb_attributes[] = {
1772 &dev_attr_mode.attr,
1773 &dev_attr_vbus.attr,
1774 &dev_attr_srp.attr,
1775 NULL
1776 };
1777
1778 static const struct attribute_group musb_attr_group = {
1779 .attrs = musb_attributes,
1780 };
1781
1782 #endif /* sysfs */
1783
1784 /* Only used to provide driver mode change events */
1785 static void musb_irq_work(struct work_struct *data)
1786 {
1787 struct musb *musb = container_of(data, struct musb, irq_work);
1788 static int old_state;
1789
1790 if (musb->xceiv->state != old_state) {
1791 old_state = musb->xceiv->state;
1792 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1793 }
1794 }
1795
1796 /* --------------------------------------------------------------------------
1797 * Init support
1798 */
1799
1800 static struct musb *__devinit
1801 allocate_instance(struct device *dev,
1802 struct musb_hdrc_config *config, void __iomem *mbase)
1803 {
1804 struct musb *musb;
1805 struct musb_hw_ep *ep;
1806 int epnum;
1807 struct usb_hcd *hcd;
1808
1809 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1810 if (!hcd)
1811 return NULL;
1812 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1813
1814 musb = hcd_to_musb(hcd);
1815 INIT_LIST_HEAD(&musb->control);
1816 INIT_LIST_HEAD(&musb->in_bulk);
1817 INIT_LIST_HEAD(&musb->out_bulk);
1818
1819 hcd->uses_new_polling = 1;
1820 hcd->has_tt = 1;
1821
1822 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1823 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1824 dev_set_drvdata(dev, musb);
1825 musb->mregs = mbase;
1826 musb->ctrl_base = mbase;
1827 musb->nIrq = -ENODEV;
1828 musb->config = config;
1829 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1830 for (epnum = 0, ep = musb->endpoints;
1831 epnum < musb->config->num_eps;
1832 epnum++, ep++) {
1833 ep->musb = musb;
1834 ep->epnum = epnum;
1835 }
1836
1837 musb->controller = dev;
1838
1839 return musb;
1840 }
1841
1842 static void musb_free(struct musb *musb)
1843 {
1844 /* this has multiple entry modes. it handles fault cleanup after
1845 * probe(), where things may be partially set up, as well as rmmod
1846 * cleanup after everything's been de-activated.
1847 */
1848
1849 #ifdef CONFIG_SYSFS
1850 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1851 #endif
1852
1853 if (musb->nIrq >= 0) {
1854 if (musb->irq_wake)
1855 disable_irq_wake(musb->nIrq);
1856 free_irq(musb->nIrq, musb);
1857 }
1858 if (is_dma_capable() && musb->dma_controller) {
1859 struct dma_controller *c = musb->dma_controller;
1860
1861 (void) c->stop(c);
1862 dma_controller_destroy(c);
1863 }
1864
1865 kfree(musb);
1866 }
1867
1868 /*
1869 * Perform generic per-controller initialization.
1870 *
1871 * @pDevice: the controller (already clocked, etc)
1872 * @nIrq: irq
1873 * @mregs: virtual address of controller registers,
1874 * not yet corrected for platform-specific offsets
1875 */
1876 static int __devinit
1877 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1878 {
1879 int status;
1880 struct musb *musb;
1881 struct musb_hdrc_platform_data *plat = dev->platform_data;
1882
1883 /* The driver might handle more features than the board; OK.
1884 * Fail when the board needs a feature that's not enabled.
1885 */
1886 if (!plat) {
1887 dev_dbg(dev, "no platform_data?\n");
1888 status = -ENODEV;
1889 goto fail0;
1890 }
1891
1892 /* allocate */
1893 musb = allocate_instance(dev, plat->config, ctrl);
1894 if (!musb) {
1895 status = -ENOMEM;
1896 goto fail0;
1897 }
1898
1899 pm_runtime_use_autosuspend(musb->controller);
1900 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1901 pm_runtime_enable(musb->controller);
1902
1903 spin_lock_init(&musb->lock);
1904 musb->board_mode = plat->mode;
1905 musb->board_set_power = plat->set_power;
1906 musb->min_power = plat->min_power;
1907 musb->ops = plat->platform_ops;
1908
1909 /* The musb_platform_init() call:
1910 * - adjusts musb->mregs and musb->isr if needed,
1911 * - may initialize an integrated tranceiver
1912 * - initializes musb->xceiv, usually by otg_get_transceiver()
1913 * - stops powering VBUS
1914 *
1915 * There are various transceiver configurations. Blackfin,
1916 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1917 * external/discrete ones in various flavors (twl4030 family,
1918 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1919 */
1920 musb->isr = generic_interrupt;
1921 status = musb_platform_init(musb);
1922 if (status < 0)
1923 goto fail1;
1924
1925 if (!musb->isr) {
1926 status = -ENODEV;
1927 goto fail2;
1928 }
1929
1930 if (!musb->xceiv->io_ops) {
1931 musb->xceiv->io_dev = musb->controller;
1932 musb->xceiv->io_priv = musb->mregs;
1933 musb->xceiv->io_ops = &musb_ulpi_access;
1934 }
1935
1936 pm_runtime_get_sync(musb->controller);
1937
1938 #ifndef CONFIG_MUSB_PIO_ONLY
1939 if (use_dma && dev->dma_mask) {
1940 struct dma_controller *c;
1941
1942 c = dma_controller_create(musb, musb->mregs);
1943 musb->dma_controller = c;
1944 if (c)
1945 (void) c->start(c);
1946 }
1947 #endif
1948 /* ideally this would be abstracted in platform setup */
1949 if (!is_dma_capable() || !musb->dma_controller)
1950 dev->dma_mask = NULL;
1951
1952 /* be sure interrupts are disabled before connecting ISR */
1953 musb_platform_disable(musb);
1954 musb_generic_disable(musb);
1955
1956 /* setup musb parts of the core (especially endpoints) */
1957 status = musb_core_init(plat->config->multipoint
1958 ? MUSB_CONTROLLER_MHDRC
1959 : MUSB_CONTROLLER_HDRC, musb);
1960 if (status < 0)
1961 goto fail3;
1962
1963 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
1964
1965 /* Init IRQ workqueue before request_irq */
1966 INIT_WORK(&musb->irq_work, musb_irq_work);
1967
1968 /* attach to the IRQ */
1969 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
1970 dev_err(dev, "request_irq %d failed!\n", nIrq);
1971 status = -ENODEV;
1972 goto fail3;
1973 }
1974 musb->nIrq = nIrq;
1975 /* FIXME this handles wakeup irqs wrong */
1976 if (enable_irq_wake(nIrq) == 0) {
1977 musb->irq_wake = 1;
1978 device_init_wakeup(dev, 1);
1979 } else {
1980 musb->irq_wake = 0;
1981 }
1982
1983 /* host side needs more setup */
1984 if (is_host_enabled(musb)) {
1985 struct usb_hcd *hcd = musb_to_hcd(musb);
1986
1987 otg_set_host(musb->xceiv->otg, &hcd->self);
1988
1989 if (is_otg_enabled(musb))
1990 hcd->self.otg_port = 1;
1991 musb->xceiv->otg->host = &hcd->self;
1992 hcd->power_budget = 2 * (plat->power ? : 250);
1993
1994 /* program PHY to use external vBus if required */
1995 if (plat->extvbus) {
1996 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
1997 busctl |= MUSB_ULPI_USE_EXTVBUS;
1998 musb_write_ulpi_buscontrol(musb->mregs, busctl);
1999 }
2000 }
2001
2002 /* For the host-only role, we can activate right away.
2003 * (We expect the ID pin to be forcibly grounded!!)
2004 * Otherwise, wait till the gadget driver hooks up.
2005 */
2006 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2007 struct usb_hcd *hcd = musb_to_hcd(musb);
2008
2009 MUSB_HST_MODE(musb);
2010 musb->xceiv->otg->default_a = 1;
2011 musb->xceiv->state = OTG_STATE_A_IDLE;
2012
2013 status = usb_add_hcd(musb_to_hcd(musb), 0, 0);
2014
2015 hcd->self.uses_pio_for_control = 1;
2016 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2017 "HOST", status,
2018 musb_readb(musb->mregs, MUSB_DEVCTL),
2019 (musb_readb(musb->mregs, MUSB_DEVCTL)
2020 & MUSB_DEVCTL_BDEVICE
2021 ? 'B' : 'A'));
2022
2023 } else /* peripheral is enabled */ {
2024 MUSB_DEV_MODE(musb);
2025 musb->xceiv->otg->default_a = 0;
2026 musb->xceiv->state = OTG_STATE_B_IDLE;
2027
2028 status = musb_gadget_setup(musb);
2029
2030 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2031 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2032 status,
2033 musb_readb(musb->mregs, MUSB_DEVCTL));
2034
2035 }
2036 if (status < 0)
2037 goto fail3;
2038
2039 status = musb_init_debugfs(musb);
2040 if (status < 0)
2041 goto fail4;
2042
2043 #ifdef CONFIG_SYSFS
2044 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2045 if (status)
2046 goto fail5;
2047 #endif
2048
2049 pm_runtime_put(musb->controller);
2050
2051 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2052 ({char *s;
2053 switch (musb->board_mode) {
2054 case MUSB_HOST: s = "Host"; break;
2055 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2056 default: s = "OTG"; break;
2057 }; s; }),
2058 ctrl,
2059 (is_dma_capable() && musb->dma_controller)
2060 ? "DMA" : "PIO",
2061 musb->nIrq);
2062
2063 return 0;
2064
2065 fail5:
2066 musb_exit_debugfs(musb);
2067
2068 fail4:
2069 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2070 usb_remove_hcd(musb_to_hcd(musb));
2071 else
2072 musb_gadget_cleanup(musb);
2073
2074 fail3:
2075 pm_runtime_put_sync(musb->controller);
2076
2077 fail2:
2078 if (musb->irq_wake)
2079 device_init_wakeup(dev, 0);
2080 musb_platform_exit(musb);
2081
2082 fail1:
2083 dev_err(musb->controller,
2084 "musb_init_controller failed with status %d\n", status);
2085
2086 musb_free(musb);
2087
2088 fail0:
2089
2090 return status;
2091
2092 }
2093
2094 /*-------------------------------------------------------------------------*/
2095
2096 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2097 * bridge to a platform device; this driver then suffices.
2098 */
2099
2100 #ifndef CONFIG_MUSB_PIO_ONLY
2101 static u64 *orig_dma_mask;
2102 #endif
2103
2104 static int __devinit musb_probe(struct platform_device *pdev)
2105 {
2106 struct device *dev = &pdev->dev;
2107 int irq = platform_get_irq_byname(pdev, "mc");
2108 int status;
2109 struct resource *iomem;
2110 void __iomem *base;
2111
2112 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2113 if (!iomem || irq <= 0)
2114 return -ENODEV;
2115
2116 base = ioremap(iomem->start, resource_size(iomem));
2117 if (!base) {
2118 dev_err(dev, "ioremap failed\n");
2119 return -ENOMEM;
2120 }
2121
2122 #ifndef CONFIG_MUSB_PIO_ONLY
2123 /* clobbered by use_dma=n */
2124 orig_dma_mask = dev->dma_mask;
2125 #endif
2126 status = musb_init_controller(dev, irq, base);
2127 if (status < 0)
2128 iounmap(base);
2129
2130 return status;
2131 }
2132
2133 static int __devexit musb_remove(struct platform_device *pdev)
2134 {
2135 struct musb *musb = dev_to_musb(&pdev->dev);
2136 void __iomem *ctrl_base = musb->ctrl_base;
2137
2138 /* this gets called on rmmod.
2139 * - Host mode: host may still be active
2140 * - Peripheral mode: peripheral is deactivated (or never-activated)
2141 * - OTG mode: both roles are deactivated (or never-activated)
2142 */
2143 musb_exit_debugfs(musb);
2144 musb_shutdown(pdev);
2145
2146 musb_free(musb);
2147 iounmap(ctrl_base);
2148 device_init_wakeup(&pdev->dev, 0);
2149 #ifndef CONFIG_MUSB_PIO_ONLY
2150 pdev->dev.dma_mask = orig_dma_mask;
2151 #endif
2152 return 0;
2153 }
2154
2155 #ifdef CONFIG_PM
2156
2157 static void musb_save_context(struct musb *musb)
2158 {
2159 int i;
2160 void __iomem *musb_base = musb->mregs;
2161 void __iomem *epio;
2162
2163 if (is_host_enabled(musb)) {
2164 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2165 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2166 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2167 }
2168 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2169 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2170 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2171 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2172 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2173 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2174
2175 for (i = 0; i < musb->config->num_eps; ++i) {
2176 struct musb_hw_ep *hw_ep;
2177
2178 hw_ep = &musb->endpoints[i];
2179 if (!hw_ep)
2180 continue;
2181
2182 epio = hw_ep->regs;
2183 if (!epio)
2184 continue;
2185
2186 musb_writeb(musb_base, MUSB_INDEX, i);
2187 musb->context.index_regs[i].txmaxp =
2188 musb_readw(epio, MUSB_TXMAXP);
2189 musb->context.index_regs[i].txcsr =
2190 musb_readw(epio, MUSB_TXCSR);
2191 musb->context.index_regs[i].rxmaxp =
2192 musb_readw(epio, MUSB_RXMAXP);
2193 musb->context.index_regs[i].rxcsr =
2194 musb_readw(epio, MUSB_RXCSR);
2195
2196 if (musb->dyn_fifo) {
2197 musb->context.index_regs[i].txfifoadd =
2198 musb_read_txfifoadd(musb_base);
2199 musb->context.index_regs[i].rxfifoadd =
2200 musb_read_rxfifoadd(musb_base);
2201 musb->context.index_regs[i].txfifosz =
2202 musb_read_txfifosz(musb_base);
2203 musb->context.index_regs[i].rxfifosz =
2204 musb_read_rxfifosz(musb_base);
2205 }
2206 if (is_host_enabled(musb)) {
2207 musb->context.index_regs[i].txtype =
2208 musb_readb(epio, MUSB_TXTYPE);
2209 musb->context.index_regs[i].txinterval =
2210 musb_readb(epio, MUSB_TXINTERVAL);
2211 musb->context.index_regs[i].rxtype =
2212 musb_readb(epio, MUSB_RXTYPE);
2213 musb->context.index_regs[i].rxinterval =
2214 musb_readb(epio, MUSB_RXINTERVAL);
2215
2216 musb->context.index_regs[i].txfunaddr =
2217 musb_read_txfunaddr(musb_base, i);
2218 musb->context.index_regs[i].txhubaddr =
2219 musb_read_txhubaddr(musb_base, i);
2220 musb->context.index_regs[i].txhubport =
2221 musb_read_txhubport(musb_base, i);
2222
2223 musb->context.index_regs[i].rxfunaddr =
2224 musb_read_rxfunaddr(musb_base, i);
2225 musb->context.index_regs[i].rxhubaddr =
2226 musb_read_rxhubaddr(musb_base, i);
2227 musb->context.index_regs[i].rxhubport =
2228 musb_read_rxhubport(musb_base, i);
2229 }
2230 }
2231 }
2232
2233 static void musb_restore_context(struct musb *musb)
2234 {
2235 int i;
2236 void __iomem *musb_base = musb->mregs;
2237 void __iomem *ep_target_regs;
2238 void __iomem *epio;
2239
2240 if (is_host_enabled(musb)) {
2241 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2242 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2243 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2244 }
2245 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2246 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2247 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2248 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2249 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2250
2251 for (i = 0; i < musb->config->num_eps; ++i) {
2252 struct musb_hw_ep *hw_ep;
2253
2254 hw_ep = &musb->endpoints[i];
2255 if (!hw_ep)
2256 continue;
2257
2258 epio = hw_ep->regs;
2259 if (!epio)
2260 continue;
2261
2262 musb_writeb(musb_base, MUSB_INDEX, i);
2263 musb_writew(epio, MUSB_TXMAXP,
2264 musb->context.index_regs[i].txmaxp);
2265 musb_writew(epio, MUSB_TXCSR,
2266 musb->context.index_regs[i].txcsr);
2267 musb_writew(epio, MUSB_RXMAXP,
2268 musb->context.index_regs[i].rxmaxp);
2269 musb_writew(epio, MUSB_RXCSR,
2270 musb->context.index_regs[i].rxcsr);
2271
2272 if (musb->dyn_fifo) {
2273 musb_write_txfifosz(musb_base,
2274 musb->context.index_regs[i].txfifosz);
2275 musb_write_rxfifosz(musb_base,
2276 musb->context.index_regs[i].rxfifosz);
2277 musb_write_txfifoadd(musb_base,
2278 musb->context.index_regs[i].txfifoadd);
2279 musb_write_rxfifoadd(musb_base,
2280 musb->context.index_regs[i].rxfifoadd);
2281 }
2282
2283 if (is_host_enabled(musb)) {
2284 musb_writeb(epio, MUSB_TXTYPE,
2285 musb->context.index_regs[i].txtype);
2286 musb_writeb(epio, MUSB_TXINTERVAL,
2287 musb->context.index_regs[i].txinterval);
2288 musb_writeb(epio, MUSB_RXTYPE,
2289 musb->context.index_regs[i].rxtype);
2290 musb_writeb(epio, MUSB_RXINTERVAL,
2291
2292 musb->context.index_regs[i].rxinterval);
2293 musb_write_txfunaddr(musb_base, i,
2294 musb->context.index_regs[i].txfunaddr);
2295 musb_write_txhubaddr(musb_base, i,
2296 musb->context.index_regs[i].txhubaddr);
2297 musb_write_txhubport(musb_base, i,
2298 musb->context.index_regs[i].txhubport);
2299
2300 ep_target_regs =
2301 musb_read_target_reg_base(i, musb_base);
2302
2303 musb_write_rxfunaddr(ep_target_regs,
2304 musb->context.index_regs[i].rxfunaddr);
2305 musb_write_rxhubaddr(ep_target_regs,
2306 musb->context.index_regs[i].rxhubaddr);
2307 musb_write_rxhubport(ep_target_regs,
2308 musb->context.index_regs[i].rxhubport);
2309 }
2310 }
2311 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2312 }
2313
2314 static int musb_suspend(struct device *dev)
2315 {
2316 struct musb *musb = dev_to_musb(dev);
2317 unsigned long flags;
2318
2319 spin_lock_irqsave(&musb->lock, flags);
2320
2321 if (is_peripheral_active(musb)) {
2322 /* FIXME force disconnect unless we know USB will wake
2323 * the system up quickly enough to respond ...
2324 */
2325 } else if (is_host_active(musb)) {
2326 /* we know all the children are suspended; sometimes
2327 * they will even be wakeup-enabled.
2328 */
2329 }
2330
2331 spin_unlock_irqrestore(&musb->lock, flags);
2332 return 0;
2333 }
2334
2335 static int musb_resume_noirq(struct device *dev)
2336 {
2337 /* for static cmos like DaVinci, register values were preserved
2338 * unless for some reason the whole soc powered down or the USB
2339 * module got reset through the PSC (vs just being disabled).
2340 */
2341 return 0;
2342 }
2343
2344 static int musb_runtime_suspend(struct device *dev)
2345 {
2346 struct musb *musb = dev_to_musb(dev);
2347
2348 musb_save_context(musb);
2349
2350 return 0;
2351 }
2352
2353 static int musb_runtime_resume(struct device *dev)
2354 {
2355 struct musb *musb = dev_to_musb(dev);
2356 static int first = 1;
2357
2358 /*
2359 * When pm_runtime_get_sync called for the first time in driver
2360 * init, some of the structure is still not initialized which is
2361 * used in restore function. But clock needs to be
2362 * enabled before any register access, so
2363 * pm_runtime_get_sync has to be called.
2364 * Also context restore without save does not make
2365 * any sense
2366 */
2367 if (!first)
2368 musb_restore_context(musb);
2369 first = 0;
2370
2371 return 0;
2372 }
2373
2374 static const struct dev_pm_ops musb_dev_pm_ops = {
2375 .suspend = musb_suspend,
2376 .resume_noirq = musb_resume_noirq,
2377 .runtime_suspend = musb_runtime_suspend,
2378 .runtime_resume = musb_runtime_resume,
2379 };
2380
2381 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2382 #else
2383 #define MUSB_DEV_PM_OPS NULL
2384 #endif
2385
2386 static struct platform_driver musb_driver = {
2387 .driver = {
2388 .name = (char *)musb_driver_name,
2389 .bus = &platform_bus_type,
2390 .owner = THIS_MODULE,
2391 .pm = MUSB_DEV_PM_OPS,
2392 },
2393 .probe = musb_probe,
2394 .remove = __devexit_p(musb_remove),
2395 .shutdown = musb_shutdown,
2396 };
2397
2398 /*-------------------------------------------------------------------------*/
2399
2400 static int __init musb_init(void)
2401 {
2402 if (usb_disabled())
2403 return 0;
2404
2405 pr_info("%s: version " MUSB_VERSION ", "
2406 "?dma?"
2407 ", "
2408 "otg (peripheral+host)",
2409 musb_driver_name);
2410 return platform_driver_register(&musb_driver);
2411 }
2412 module_init(musb_init);
2413
2414 static void __exit musb_cleanup(void)
2415 {
2416 platform_driver_unregister(&musb_driver);
2417 }
2418 module_exit(musb_cleanup);
Linux kernel - Deliverables
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