2 * MUSB OTG driver peripheral support
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <linux/kernel.h>
37 #include <linux/list.h>
38 #include <linux/timer.h>
39 #include <linux/module.h>
40 #include <linux/smp.h>
41 #include <linux/spinlock.h>
42 #include <linux/delay.h>
43 #include <linux/moduleparam.h>
44 #include <linux/stat.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
48 #include "musb_core.h"
51 /* MUSB PERIPHERAL status 3-mar-2006:
53 * - EP0 seems solid. It passes both USBCV and usbtest control cases.
56 * + remote wakeup to Linux hosts work, but saw USBCV failures;
57 * in one test run (operator error?)
58 * + endpoint halt tests -- in both usbtest and usbcv -- seem
59 * to break when dma is enabled ... is something wrongly
62 * - Mass storage behaved ok when last tested. Network traffic patterns
63 * (with lots of short transfers etc) need retesting; they turn up the
64 * worst cases of the DMA, since short packets are typical but are not
68 * + both pio and dma behave in with network and g_zero tests
69 * + no cppi throughput issues other than no-hw-queueing
70 * + failed with FLAT_REG (DaVinci)
71 * + seems to behave with double buffering, PIO -and- CPPI
72 * + with gadgetfs + AIO, requests got lost?
75 * + both pio and dma behave in with network and g_zero tests
76 * + dma is slow in typical case (short_not_ok is clear)
77 * + double buffering ok with PIO
78 * + double buffering *FAILS* with CPPI, wrong data bytes sometimes
79 * + request lossage observed with gadgetfs
81 * - ISO not tested ... might work, but only weakly isochronous
83 * - Gadget driver disabling of softconnect during bind() is ignored; so
84 * drivers can't hold off host requests until userspace is ready.
85 * (Workaround: they can turn it off later.)
87 * - PORTABILITY (assumes PIO works):
88 * + DaVinci, basically works with cppi dma
89 * + OMAP 2430, ditto with mentor dma
90 * + TUSB 6010, platform-specific dma in the works
93 /* ----------------------------------------------------------------------- */
96 * Immediately complete a request.
98 * @param request the request to complete
99 * @param status the status to complete the request with
100 * Context: controller locked, IRQs blocked.
102 void musb_g_giveback(
104 struct usb_request
*request
,
106 __releases(ep
->musb
->lock
)
107 __acquires(ep
->musb
->lock
)
109 struct musb_request
*req
;
113 req
= to_musb_request(request
);
115 list_del(&request
->list
);
116 if (req
->request
.status
== -EINPROGRESS
)
117 req
->request
.status
= status
;
121 spin_unlock(&musb
->lock
);
122 if (is_dma_capable()) {
124 dma_unmap_single(musb
->controller
,
130 req
->request
.dma
= DMA_ADDR_INVALID
;
132 } else if (req
->request
.dma
!= DMA_ADDR_INVALID
)
133 dma_sync_single_for_cpu(musb
->controller
,
140 if (request
->status
== 0)
141 DBG(5, "%s done request %p, %d/%d\n",
142 ep
->end_point
.name
, request
,
143 req
->request
.actual
, req
->request
.length
);
145 DBG(2, "%s request %p, %d/%d fault %d\n",
146 ep
->end_point
.name
, request
,
147 req
->request
.actual
, req
->request
.length
,
149 req
->request
.complete(&req
->ep
->end_point
, &req
->request
);
150 spin_lock(&musb
->lock
);
154 /* ----------------------------------------------------------------------- */
157 * Abort requests queued to an endpoint using the status. Synchronous.
158 * caller locked controller and blocked irqs, and selected this ep.
160 static void nuke(struct musb_ep
*ep
, const int status
)
162 struct musb_request
*req
= NULL
;
163 void __iomem
*epio
= ep
->musb
->endpoints
[ep
->current_epnum
].regs
;
167 if (is_dma_capable() && ep
->dma
) {
168 struct dma_controller
*c
= ep
->musb
->dma_controller
;
173 * The programming guide says that we must not clear
174 * the DMAMODE bit before DMAENAB, so we only
175 * clear it in the second write...
177 musb_writew(epio
, MUSB_TXCSR
,
178 MUSB_TXCSR_DMAMODE
| MUSB_TXCSR_FLUSHFIFO
);
179 musb_writew(epio
, MUSB_TXCSR
,
180 0 | MUSB_TXCSR_FLUSHFIFO
);
182 musb_writew(epio
, MUSB_RXCSR
,
183 0 | MUSB_RXCSR_FLUSHFIFO
);
184 musb_writew(epio
, MUSB_RXCSR
,
185 0 | MUSB_RXCSR_FLUSHFIFO
);
188 value
= c
->channel_abort(ep
->dma
);
189 DBG(value
? 1 : 6, "%s: abort DMA --> %d\n", ep
->name
, value
);
190 c
->channel_release(ep
->dma
);
194 while (!list_empty(&(ep
->req_list
))) {
195 req
= container_of(ep
->req_list
.next
, struct musb_request
,
197 musb_g_giveback(ep
, &req
->request
, status
);
201 /* ----------------------------------------------------------------------- */
203 /* Data transfers - pure PIO, pure DMA, or mixed mode */
206 * This assumes the separate CPPI engine is responding to DMA requests
207 * from the usb core ... sequenced a bit differently from mentor dma.
210 static inline int max_ep_writesize(struct musb
*musb
, struct musb_ep
*ep
)
212 if (can_bulk_split(musb
, ep
->type
))
213 return ep
->hw_ep
->max_packet_sz_tx
;
215 return ep
->packet_sz
;
219 #ifdef CONFIG_USB_INVENTRA_DMA
221 /* Peripheral tx (IN) using Mentor DMA works as follows:
222 Only mode 0 is used for transfers <= wPktSize,
223 mode 1 is used for larger transfers,
225 One of the following happens:
226 - Host sends IN token which causes an endpoint interrupt
228 -> if DMA is currently busy, exit.
229 -> if queue is non-empty, txstate().
231 - Request is queued by the gadget driver.
232 -> if queue was previously empty, txstate()
237 | (data is transferred to the FIFO, then sent out when
238 | IN token(s) are recd from Host.
239 | -> DMA interrupt on completion
241 | -> stop DMA, ~DMAENAB,
242 | -> set TxPktRdy for last short pkt or zlp
243 | -> Complete Request
244 | -> Continue next request (call txstate)
245 |___________________________________|
247 * Non-Mentor DMA engines can of course work differently, such as by
248 * upleveling from irq-per-packet to irq-per-buffer.
254 * An endpoint is transmitting data. This can be called either from
255 * the IRQ routine or from ep.queue() to kickstart a request on an
258 * Context: controller locked, IRQs blocked, endpoint selected
260 static void txstate(struct musb
*musb
, struct musb_request
*req
)
262 u8 epnum
= req
->epnum
;
263 struct musb_ep
*musb_ep
;
264 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
265 struct usb_request
*request
;
266 u16 fifo_count
= 0, csr
;
271 /* we shouldn't get here while DMA is active ... but we do ... */
272 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
273 DBG(4, "dma pending...\n");
277 /* read TXCSR before */
278 csr
= musb_readw(epio
, MUSB_TXCSR
);
280 request
= &req
->request
;
281 fifo_count
= min(max_ep_writesize(musb
, musb_ep
),
282 (int)(request
->length
- request
->actual
));
284 if (csr
& MUSB_TXCSR_TXPKTRDY
) {
285 DBG(5, "%s old packet still ready , txcsr %03x\n",
286 musb_ep
->end_point
.name
, csr
);
290 if (csr
& MUSB_TXCSR_P_SENDSTALL
) {
291 DBG(5, "%s stalling, txcsr %03x\n",
292 musb_ep
->end_point
.name
, csr
);
296 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
297 epnum
, musb_ep
->packet_sz
, fifo_count
,
300 #ifndef CONFIG_MUSB_PIO_ONLY
301 if (is_dma_capable() && musb_ep
->dma
) {
302 struct dma_controller
*c
= musb
->dma_controller
;
305 /* setup DMA, then program endpoint CSR */
306 request_size
= min_t(size_t, request
->length
- request
->actual
,
307 musb_ep
->dma
->max_len
);
309 use_dma
= (request
->dma
!= DMA_ADDR_INVALID
);
311 /* MUSB_TXCSR_P_ISO is still set correctly */
313 #ifdef CONFIG_USB_INVENTRA_DMA
315 if (request_size
< musb_ep
->packet_sz
)
316 musb_ep
->dma
->desired_mode
= 0;
318 musb_ep
->dma
->desired_mode
= 1;
320 use_dma
= use_dma
&& c
->channel_program(
321 musb_ep
->dma
, musb_ep
->packet_sz
,
322 musb_ep
->dma
->desired_mode
,
323 request
->dma
+ request
->actual
, request_size
);
325 if (musb_ep
->dma
->desired_mode
== 0) {
327 * We must not clear the DMAMODE bit
328 * before the DMAENAB bit -- and the
329 * latter doesn't always get cleared
330 * before we get here...
332 csr
&= ~(MUSB_TXCSR_AUTOSET
333 | MUSB_TXCSR_DMAENAB
);
334 musb_writew(epio
, MUSB_TXCSR
, csr
335 | MUSB_TXCSR_P_WZC_BITS
);
336 csr
&= ~MUSB_TXCSR_DMAMODE
;
337 csr
|= (MUSB_TXCSR_DMAENAB
|
339 /* against programming guide */
341 csr
|= (MUSB_TXCSR_DMAENAB
344 if (!musb_ep
->hb_mult
)
345 csr
|= MUSB_TXCSR_AUTOSET
;
347 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
349 musb_writew(epio
, MUSB_TXCSR
, csr
);
353 #elif defined(CONFIG_USB_TI_CPPI_DMA)
354 /* program endpoint CSR first, then setup DMA */
355 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
356 csr
|= MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_DMAMODE
|
358 musb_writew(epio
, MUSB_TXCSR
,
359 (MUSB_TXCSR_P_WZC_BITS
& ~MUSB_TXCSR_P_UNDERRUN
)
362 /* ensure writebuffer is empty */
363 csr
= musb_readw(epio
, MUSB_TXCSR
);
365 /* NOTE host side sets DMAENAB later than this; both are
366 * OK since the transfer dma glue (between CPPI and Mentor
367 * fifos) just tells CPPI it could start. Data only moves
368 * to the USB TX fifo when both fifos are ready.
371 /* "mode" is irrelevant here; handle terminating ZLPs like
372 * PIO does, since the hardware RNDIS mode seems unreliable
373 * except for the last-packet-is-already-short case.
375 use_dma
= use_dma
&& c
->channel_program(
376 musb_ep
->dma
, musb_ep
->packet_sz
,
378 request
->dma
+ request
->actual
,
381 c
->channel_release(musb_ep
->dma
);
383 csr
&= ~MUSB_TXCSR_DMAENAB
;
384 musb_writew(epio
, MUSB_TXCSR
, csr
);
385 /* invariant: prequest->buf is non-null */
387 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
388 use_dma
= use_dma
&& c
->channel_program(
389 musb_ep
->dma
, musb_ep
->packet_sz
,
391 request
->dma
+ request
->actual
,
398 musb_write_fifo(musb_ep
->hw_ep
, fifo_count
,
399 (u8
*) (request
->buf
+ request
->actual
));
400 request
->actual
+= fifo_count
;
401 csr
|= MUSB_TXCSR_TXPKTRDY
;
402 csr
&= ~MUSB_TXCSR_P_UNDERRUN
;
403 musb_writew(epio
, MUSB_TXCSR
, csr
);
406 /* host may already have the data when this message shows... */
407 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
408 musb_ep
->end_point
.name
, use_dma
? "dma" : "pio",
409 request
->actual
, request
->length
,
410 musb_readw(epio
, MUSB_TXCSR
),
412 musb_readw(epio
, MUSB_TXMAXP
));
416 * FIFO state update (e.g. data ready).
417 * Called from IRQ, with controller locked.
419 void musb_g_tx(struct musb
*musb
, u8 epnum
)
422 struct usb_request
*request
;
423 u8 __iomem
*mbase
= musb
->mregs
;
424 struct musb_ep
*musb_ep
= &musb
->endpoints
[epnum
].ep_in
;
425 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
426 struct dma_channel
*dma
;
428 musb_ep_select(mbase
, epnum
);
429 request
= next_request(musb_ep
);
431 csr
= musb_readw(epio
, MUSB_TXCSR
);
432 DBG(4, "<== %s, txcsr %04x\n", musb_ep
->end_point
.name
, csr
);
434 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
437 * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX
438 * probably rates reporting as a host error.
440 if (csr
& MUSB_TXCSR_P_SENTSTALL
) {
441 csr
|= MUSB_TXCSR_P_WZC_BITS
;
442 csr
&= ~MUSB_TXCSR_P_SENTSTALL
;
443 musb_writew(epio
, MUSB_TXCSR
, csr
);
447 if (csr
& MUSB_TXCSR_P_UNDERRUN
) {
448 /* We NAKed, no big deal... little reason to care. */
449 csr
|= MUSB_TXCSR_P_WZC_BITS
;
450 csr
&= ~(MUSB_TXCSR_P_UNDERRUN
| MUSB_TXCSR_TXPKTRDY
);
451 musb_writew(epio
, MUSB_TXCSR
, csr
);
452 DBG(20, "underrun on ep%d, req %p\n", epnum
, request
);
455 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
457 * SHOULD NOT HAPPEN... has with CPPI though, after
458 * changing SENDSTALL (and other cases); harmless?
460 DBG(5, "%s dma still busy?\n", musb_ep
->end_point
.name
);
467 if (dma
&& (csr
& MUSB_TXCSR_DMAENAB
)) {
469 csr
|= MUSB_TXCSR_P_WZC_BITS
;
470 csr
&= ~(MUSB_TXCSR_DMAENAB
| MUSB_TXCSR_P_UNDERRUN
|
471 MUSB_TXCSR_TXPKTRDY
);
472 musb_writew(epio
, MUSB_TXCSR
, csr
);
473 /* Ensure writebuffer is empty. */
474 csr
= musb_readw(epio
, MUSB_TXCSR
);
475 request
->actual
+= musb_ep
->dma
->actual_len
;
476 DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
477 epnum
, csr
, musb_ep
->dma
->actual_len
, request
);
481 * First, maybe a terminating short packet. Some DMA
482 * engines might handle this by themselves.
484 if ((request
->zero
&& request
->length
485 && (request
->length
% musb_ep
->packet_sz
== 0)
486 && (request
->actual
== request
->length
))
487 #ifdef CONFIG_USB_INVENTRA_DMA
488 || (is_dma
&& (!dma
->desired_mode
||
490 (musb_ep
->packet_sz
- 1))))
494 * On DMA completion, FIFO may not be
497 if (csr
& MUSB_TXCSR_TXPKTRDY
)
500 DBG(4, "sending zero pkt\n");
501 musb_writew(epio
, MUSB_TXCSR
, MUSB_TXCSR_MODE
502 | MUSB_TXCSR_TXPKTRDY
);
506 if (request
->actual
== request
->length
) {
507 musb_g_giveback(musb_ep
, request
, 0);
508 request
= musb_ep
->desc
? next_request(musb_ep
) : NULL
;
510 DBG(4, "%s idle now\n",
511 musb_ep
->end_point
.name
);
516 txstate(musb
, to_musb_request(request
));
520 /* ------------------------------------------------------------ */
522 #ifdef CONFIG_USB_INVENTRA_DMA
524 /* Peripheral rx (OUT) using Mentor DMA works as follows:
525 - Only mode 0 is used.
527 - Request is queued by the gadget class driver.
528 -> if queue was previously empty, rxstate()
530 - Host sends OUT token which causes an endpoint interrupt
532 | -> if request queued, call rxstate
534 | | -> DMA interrupt on completion
538 | | -> if data recd = max expected
539 | | by the request, or host
540 | | sent a short packet,
541 | | complete the request,
542 | | and start the next one.
543 | |_____________________________________|
544 | else just wait for the host
545 | to send the next OUT token.
546 |__________________________________________________|
548 * Non-Mentor DMA engines can of course work differently.
554 * Context: controller locked, IRQs blocked, endpoint selected
556 static void rxstate(struct musb
*musb
, struct musb_request
*req
)
558 const u8 epnum
= req
->epnum
;
559 struct usb_request
*request
= &req
->request
;
560 struct musb_ep
*musb_ep
;
561 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
562 unsigned fifo_count
= 0;
564 u16 csr
= musb_readw(epio
, MUSB_RXCSR
);
565 struct musb_hw_ep
*hw_ep
= &musb
->endpoints
[epnum
];
567 if (hw_ep
->is_shared_fifo
)
568 musb_ep
= &hw_ep
->ep_in
;
570 musb_ep
= &hw_ep
->ep_out
;
572 len
= musb_ep
->packet_sz
;
574 /* We shouldn't get here while DMA is active, but we do... */
575 if (dma_channel_status(musb_ep
->dma
) == MUSB_DMA_STATUS_BUSY
) {
576 DBG(4, "DMA pending...\n");
580 if (csr
& MUSB_RXCSR_P_SENDSTALL
) {
581 DBG(5, "%s stalling, RXCSR %04x\n",
582 musb_ep
->end_point
.name
, csr
);
586 if (is_cppi_enabled() && musb_ep
->dma
) {
587 struct dma_controller
*c
= musb
->dma_controller
;
588 struct dma_channel
*channel
= musb_ep
->dma
;
590 /* NOTE: CPPI won't actually stop advancing the DMA
591 * queue after short packet transfers, so this is almost
592 * always going to run as IRQ-per-packet DMA so that
593 * faults will be handled correctly.
595 if (c
->channel_program(channel
,
597 !request
->short_not_ok
,
598 request
->dma
+ request
->actual
,
599 request
->length
- request
->actual
)) {
601 /* make sure that if an rxpkt arrived after the irq,
602 * the cppi engine will be ready to take it as soon
605 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
606 | MUSB_RXCSR_DMAMODE
);
607 csr
|= MUSB_RXCSR_DMAENAB
| MUSB_RXCSR_P_WZC_BITS
;
608 musb_writew(epio
, MUSB_RXCSR
, csr
);
613 if (csr
& MUSB_RXCSR_RXPKTRDY
) {
614 len
= musb_readw(epio
, MUSB_RXCOUNT
);
615 if (request
->actual
< request
->length
) {
616 #ifdef CONFIG_USB_INVENTRA_DMA
617 if (is_dma_capable() && musb_ep
->dma
) {
618 struct dma_controller
*c
;
619 struct dma_channel
*channel
;
622 c
= musb
->dma_controller
;
623 channel
= musb_ep
->dma
;
625 /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
626 * mode 0 only. So we do not get endpoint interrupts due to DMA
627 * completion. We only get interrupts from DMA controller.
629 * We could operate in DMA mode 1 if we knew the size of the tranfer
630 * in advance. For mass storage class, request->length = what the host
631 * sends, so that'd work. But for pretty much everything else,
632 * request->length is routinely more than what the host sends. For
633 * most these gadgets, end of is signified either by a short packet,
634 * or filling the last byte of the buffer. (Sending extra data in
635 * that last pckate should trigger an overflow fault.) But in mode 1,
636 * we don't get DMA completion interrrupt for short packets.
638 * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
639 * to get endpoint interrupt on every DMA req, but that didn't seem
642 * REVISIT an updated g_file_storage can set req->short_not_ok, which
643 * then becomes usable as a runtime "use mode 1" hint...
646 csr
|= MUSB_RXCSR_DMAENAB
;
648 csr
|= MUSB_RXCSR_AUTOCLEAR
;
649 /* csr |= MUSB_RXCSR_DMAMODE; */
651 /* this special sequence (enabling and then
652 * disabling MUSB_RXCSR_DMAMODE) is required
653 * to get DMAReq to activate
655 musb_writew(epio
, MUSB_RXCSR
,
656 csr
| MUSB_RXCSR_DMAMODE
);
658 if (!musb_ep
->hb_mult
&&
659 musb_ep
->hw_ep
->rx_double_buffered
)
660 csr
|= MUSB_RXCSR_AUTOCLEAR
;
662 musb_writew(epio
, MUSB_RXCSR
, csr
);
664 if (request
->actual
< request
->length
) {
665 int transfer_size
= 0;
667 transfer_size
= min(request
->length
- request
->actual
,
670 transfer_size
= min(request
->length
- request
->actual
,
673 if (transfer_size
<= musb_ep
->packet_sz
)
674 musb_ep
->dma
->desired_mode
= 0;
676 musb_ep
->dma
->desired_mode
= 1;
678 use_dma
= c
->channel_program(
681 channel
->desired_mode
,
690 #endif /* Mentor's DMA */
692 fifo_count
= request
->length
- request
->actual
;
693 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
694 musb_ep
->end_point
.name
,
698 fifo_count
= min_t(unsigned, len
, fifo_count
);
700 #ifdef CONFIG_USB_TUSB_OMAP_DMA
701 if (tusb_dma_omap() && musb_ep
->dma
) {
702 struct dma_controller
*c
= musb
->dma_controller
;
703 struct dma_channel
*channel
= musb_ep
->dma
;
704 u32 dma_addr
= request
->dma
+ request
->actual
;
707 ret
= c
->channel_program(channel
,
709 channel
->desired_mode
,
717 musb_read_fifo(musb_ep
->hw_ep
, fifo_count
, (u8
*)
718 (request
->buf
+ request
->actual
));
719 request
->actual
+= fifo_count
;
721 /* REVISIT if we left anything in the fifo, flush
722 * it and report -EOVERFLOW
726 csr
|= MUSB_RXCSR_P_WZC_BITS
;
727 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
728 musb_writew(epio
, MUSB_RXCSR
, csr
);
732 /* reach the end or short packet detected */
733 if (request
->actual
== request
->length
|| len
< musb_ep
->packet_sz
)
734 musb_g_giveback(musb_ep
, request
, 0);
738 * Data ready for a request; called from IRQ
740 void musb_g_rx(struct musb
*musb
, u8 epnum
)
743 struct usb_request
*request
;
744 void __iomem
*mbase
= musb
->mregs
;
745 struct musb_ep
*musb_ep
;
746 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
747 struct dma_channel
*dma
;
748 struct musb_hw_ep
*hw_ep
= &musb
->endpoints
[epnum
];
750 if (hw_ep
->is_shared_fifo
)
751 musb_ep
= &hw_ep
->ep_in
;
753 musb_ep
= &hw_ep
->ep_out
;
755 musb_ep_select(mbase
, epnum
);
757 request
= next_request(musb_ep
);
761 csr
= musb_readw(epio
, MUSB_RXCSR
);
762 dma
= is_dma_capable() ? musb_ep
->dma
: NULL
;
764 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep
->end_point
.name
,
765 csr
, dma
? " (dma)" : "", request
);
767 if (csr
& MUSB_RXCSR_P_SENTSTALL
) {
768 csr
|= MUSB_RXCSR_P_WZC_BITS
;
769 csr
&= ~MUSB_RXCSR_P_SENTSTALL
;
770 musb_writew(epio
, MUSB_RXCSR
, csr
);
774 if (csr
& MUSB_RXCSR_P_OVERRUN
) {
775 /* csr |= MUSB_RXCSR_P_WZC_BITS; */
776 csr
&= ~MUSB_RXCSR_P_OVERRUN
;
777 musb_writew(epio
, MUSB_RXCSR
, csr
);
779 DBG(3, "%s iso overrun on %p\n", musb_ep
->name
, request
);
780 if (request
->status
== -EINPROGRESS
)
781 request
->status
= -EOVERFLOW
;
783 if (csr
& MUSB_RXCSR_INCOMPRX
) {
784 /* REVISIT not necessarily an error */
785 DBG(4, "%s, incomprx\n", musb_ep
->end_point
.name
);
788 if (dma_channel_status(dma
) == MUSB_DMA_STATUS_BUSY
) {
789 /* "should not happen"; likely RXPKTRDY pending for DMA */
790 DBG((csr
& MUSB_RXCSR_DMAENAB
) ? 4 : 1,
791 "%s busy, csr %04x\n",
792 musb_ep
->end_point
.name
, csr
);
796 if (dma
&& (csr
& MUSB_RXCSR_DMAENAB
)) {
797 csr
&= ~(MUSB_RXCSR_AUTOCLEAR
799 | MUSB_RXCSR_DMAMODE
);
800 musb_writew(epio
, MUSB_RXCSR
,
801 MUSB_RXCSR_P_WZC_BITS
| csr
);
803 request
->actual
+= musb_ep
->dma
->actual_len
;
805 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
807 musb_readw(epio
, MUSB_RXCSR
),
808 musb_ep
->dma
->actual_len
, request
);
810 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
811 /* Autoclear doesn't clear RxPktRdy for short packets */
812 if ((dma
->desired_mode
== 0 && !hw_ep
->rx_double_buffered
)
814 & (musb_ep
->packet_sz
- 1))) {
816 csr
&= ~MUSB_RXCSR_RXPKTRDY
;
817 musb_writew(epio
, MUSB_RXCSR
, csr
);
820 /* incomplete, and not short? wait for next IN packet */
821 if ((request
->actual
< request
->length
)
822 && (musb_ep
->dma
->actual_len
823 == musb_ep
->packet_sz
)) {
824 /* In double buffer case, continue to unload fifo if
825 * there is Rx packet in FIFO.
827 csr
= musb_readw(epio
, MUSB_RXCSR
);
828 if ((csr
& MUSB_RXCSR_RXPKTRDY
) &&
829 hw_ep
->rx_double_buffered
)
834 musb_g_giveback(musb_ep
, request
, 0);
836 request
= next_request(musb_ep
);
841 /* Analyze request */
842 rxstate(musb
, to_musb_request(request
));
845 /* ------------------------------------------------------------ */
847 static int musb_gadget_enable(struct usb_ep
*ep
,
848 const struct usb_endpoint_descriptor
*desc
)
851 struct musb_ep
*musb_ep
;
852 struct musb_hw_ep
*hw_ep
;
859 int status
= -EINVAL
;
864 musb_ep
= to_musb_ep(ep
);
865 hw_ep
= musb_ep
->hw_ep
;
867 musb
= musb_ep
->musb
;
869 epnum
= musb_ep
->current_epnum
;
871 spin_lock_irqsave(&musb
->lock
, flags
);
877 musb_ep
->type
= usb_endpoint_type(desc
);
879 /* check direction and (later) maxpacket size against endpoint */
880 if (usb_endpoint_num(desc
) != epnum
)
883 /* REVISIT this rules out high bandwidth periodic transfers */
884 tmp
= le16_to_cpu(desc
->wMaxPacketSize
);
888 if (usb_endpoint_dir_in(desc
))
889 ok
= musb
->hb_iso_tx
;
891 ok
= musb
->hb_iso_rx
;
894 DBG(4, "%s: not support ISO high bandwidth\n", __func__
);
897 musb_ep
->hb_mult
= (tmp
>> 11) & 3;
899 musb_ep
->hb_mult
= 0;
902 musb_ep
->packet_sz
= tmp
& 0x7ff;
903 tmp
= musb_ep
->packet_sz
* (musb_ep
->hb_mult
+ 1);
905 /* enable the interrupts for the endpoint, set the endpoint
906 * packet size (or fail), set the mode, clear the fifo
908 musb_ep_select(mbase
, epnum
);
909 if (usb_endpoint_dir_in(desc
)) {
910 u16 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
912 if (hw_ep
->is_shared_fifo
)
917 if (tmp
> hw_ep
->max_packet_sz_tx
) {
918 DBG(4, "%s: packet size beyond hw fifo size\n", __func__
);
922 int_txe
|= (1 << epnum
);
923 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
925 /* REVISIT if can_bulk_split(), use by updating "tmp";
926 * likewise high bandwidth periodic tx
928 /* Set TXMAXP with the FIFO size of the endpoint
929 * to disable double buffering mode.
931 musb_writew(regs
, MUSB_TXMAXP
, musb_ep
->packet_sz
| (musb_ep
->hb_mult
<< 11));
933 csr
= MUSB_TXCSR_MODE
| MUSB_TXCSR_CLRDATATOG
;
934 if (musb_readw(regs
, MUSB_TXCSR
)
935 & MUSB_TXCSR_FIFONOTEMPTY
)
936 csr
|= MUSB_TXCSR_FLUSHFIFO
;
937 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
938 csr
|= MUSB_TXCSR_P_ISO
;
940 /* set twice in case of double buffering */
941 musb_writew(regs
, MUSB_TXCSR
, csr
);
942 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
943 musb_writew(regs
, MUSB_TXCSR
, csr
);
946 u16 int_rxe
= musb_readw(mbase
, MUSB_INTRRXE
);
948 if (hw_ep
->is_shared_fifo
)
953 if (tmp
> hw_ep
->max_packet_sz_rx
) {
954 DBG(4, "%s: packet size beyond hw fifo size\n", __func__
);
958 int_rxe
|= (1 << epnum
);
959 musb_writew(mbase
, MUSB_INTRRXE
, int_rxe
);
961 /* REVISIT if can_bulk_combine() use by updating "tmp"
962 * likewise high bandwidth periodic rx
964 /* Set RXMAXP with the FIFO size of the endpoint
965 * to disable double buffering mode.
967 musb_writew(regs
, MUSB_RXMAXP
, musb_ep
->packet_sz
| (musb_ep
->hb_mult
<< 11));
969 /* force shared fifo to OUT-only mode */
970 if (hw_ep
->is_shared_fifo
) {
971 csr
= musb_readw(regs
, MUSB_TXCSR
);
972 csr
&= ~(MUSB_TXCSR_MODE
| MUSB_TXCSR_TXPKTRDY
);
973 musb_writew(regs
, MUSB_TXCSR
, csr
);
976 csr
= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_CLRDATATOG
;
977 if (musb_ep
->type
== USB_ENDPOINT_XFER_ISOC
)
978 csr
|= MUSB_RXCSR_P_ISO
;
979 else if (musb_ep
->type
== USB_ENDPOINT_XFER_INT
)
980 csr
|= MUSB_RXCSR_DISNYET
;
982 /* set twice in case of double buffering */
983 musb_writew(regs
, MUSB_RXCSR
, csr
);
984 musb_writew(regs
, MUSB_RXCSR
, csr
);
987 /* NOTE: all the I/O code _should_ work fine without DMA, in case
988 * for some reason you run out of channels here.
990 if (is_dma_capable() && musb
->dma_controller
) {
991 struct dma_controller
*c
= musb
->dma_controller
;
993 musb_ep
->dma
= c
->channel_alloc(c
, hw_ep
,
994 (desc
->bEndpointAddress
& USB_DIR_IN
));
998 musb_ep
->desc
= desc
;
1000 musb_ep
->wedged
= 0;
1003 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
1004 musb_driver_name
, musb_ep
->end_point
.name
,
1005 ({ char *s
; switch (musb_ep
->type
) {
1006 case USB_ENDPOINT_XFER_BULK
: s
= "bulk"; break;
1007 case USB_ENDPOINT_XFER_INT
: s
= "int"; break;
1008 default: s
= "iso"; break;
1010 musb_ep
->is_in
? "IN" : "OUT",
1011 musb_ep
->dma
? "dma, " : "",
1012 musb_ep
->packet_sz
);
1014 schedule_work(&musb
->irq_work
);
1017 spin_unlock_irqrestore(&musb
->lock
, flags
);
1022 * Disable an endpoint flushing all requests queued.
1024 static int musb_gadget_disable(struct usb_ep
*ep
)
1026 unsigned long flags
;
1029 struct musb_ep
*musb_ep
;
1033 musb_ep
= to_musb_ep(ep
);
1034 musb
= musb_ep
->musb
;
1035 epnum
= musb_ep
->current_epnum
;
1036 epio
= musb
->endpoints
[epnum
].regs
;
1038 spin_lock_irqsave(&musb
->lock
, flags
);
1039 musb_ep_select(musb
->mregs
, epnum
);
1041 /* zero the endpoint sizes */
1042 if (musb_ep
->is_in
) {
1043 u16 int_txe
= musb_readw(musb
->mregs
, MUSB_INTRTXE
);
1044 int_txe
&= ~(1 << epnum
);
1045 musb_writew(musb
->mregs
, MUSB_INTRTXE
, int_txe
);
1046 musb_writew(epio
, MUSB_TXMAXP
, 0);
1048 u16 int_rxe
= musb_readw(musb
->mregs
, MUSB_INTRRXE
);
1049 int_rxe
&= ~(1 << epnum
);
1050 musb_writew(musb
->mregs
, MUSB_INTRRXE
, int_rxe
);
1051 musb_writew(epio
, MUSB_RXMAXP
, 0);
1054 musb_ep
->desc
= NULL
;
1056 /* abort all pending DMA and requests */
1057 nuke(musb_ep
, -ESHUTDOWN
);
1059 schedule_work(&musb
->irq_work
);
1061 spin_unlock_irqrestore(&(musb
->lock
), flags
);
1063 DBG(2, "%s\n", musb_ep
->end_point
.name
);
1069 * Allocate a request for an endpoint.
1070 * Reused by ep0 code.
1072 struct usb_request
*musb_alloc_request(struct usb_ep
*ep
, gfp_t gfp_flags
)
1074 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1075 struct musb_request
*request
= NULL
;
1077 request
= kzalloc(sizeof *request
, gfp_flags
);
1079 INIT_LIST_HEAD(&request
->request
.list
);
1080 request
->request
.dma
= DMA_ADDR_INVALID
;
1081 request
->epnum
= musb_ep
->current_epnum
;
1082 request
->ep
= musb_ep
;
1085 return &request
->request
;
1090 * Reused by ep0 code.
1092 void musb_free_request(struct usb_ep
*ep
, struct usb_request
*req
)
1094 kfree(to_musb_request(req
));
1097 static LIST_HEAD(buffers
);
1099 struct free_record
{
1100 struct list_head list
;
1107 * Context: controller locked, IRQs blocked.
1109 void musb_ep_restart(struct musb
*musb
, struct musb_request
*req
)
1111 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1112 req
->tx
? "TX/IN" : "RX/OUT",
1113 &req
->request
, req
->request
.length
, req
->epnum
);
1115 musb_ep_select(musb
->mregs
, req
->epnum
);
1122 static int musb_gadget_queue(struct usb_ep
*ep
, struct usb_request
*req
,
1125 struct musb_ep
*musb_ep
;
1126 struct musb_request
*request
;
1129 unsigned long lockflags
;
1136 musb_ep
= to_musb_ep(ep
);
1137 musb
= musb_ep
->musb
;
1139 request
= to_musb_request(req
);
1140 request
->musb
= musb
;
1142 if (request
->ep
!= musb_ep
)
1145 DBG(4, "<== to %s request=%p\n", ep
->name
, req
);
1147 /* request is mine now... */
1148 request
->request
.actual
= 0;
1149 request
->request
.status
= -EINPROGRESS
;
1150 request
->epnum
= musb_ep
->current_epnum
;
1151 request
->tx
= musb_ep
->is_in
;
1153 if (is_dma_capable() && musb_ep
->dma
) {
1154 if (request
->request
.dma
== DMA_ADDR_INVALID
) {
1155 request
->request
.dma
= dma_map_single(
1157 request
->request
.buf
,
1158 request
->request
.length
,
1162 request
->mapped
= 1;
1164 dma_sync_single_for_device(musb
->controller
,
1165 request
->request
.dma
,
1166 request
->request
.length
,
1170 request
->mapped
= 0;
1173 request
->mapped
= 0;
1175 spin_lock_irqsave(&musb
->lock
, lockflags
);
1177 /* don't queue if the ep is down */
1178 if (!musb_ep
->desc
) {
1179 DBG(4, "req %p queued to %s while ep %s\n",
1180 req
, ep
->name
, "disabled");
1181 status
= -ESHUTDOWN
;
1185 /* add request to the list */
1186 list_add_tail(&(request
->request
.list
), &(musb_ep
->req_list
));
1188 /* it this is the head of the queue, start i/o ... */
1189 if (!musb_ep
->busy
&& &request
->request
.list
== musb_ep
->req_list
.next
)
1190 musb_ep_restart(musb
, request
);
1193 spin_unlock_irqrestore(&musb
->lock
, lockflags
);
1197 static int musb_gadget_dequeue(struct usb_ep
*ep
, struct usb_request
*request
)
1199 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1200 struct usb_request
*r
;
1201 unsigned long flags
;
1203 struct musb
*musb
= musb_ep
->musb
;
1205 if (!ep
|| !request
|| to_musb_request(request
)->ep
!= musb_ep
)
1208 spin_lock_irqsave(&musb
->lock
, flags
);
1210 list_for_each_entry(r
, &musb_ep
->req_list
, list
) {
1215 DBG(3, "request %p not queued to %s\n", request
, ep
->name
);
1220 /* if the hardware doesn't have the request, easy ... */
1221 if (musb_ep
->req_list
.next
!= &request
->list
|| musb_ep
->busy
)
1222 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1224 /* ... else abort the dma transfer ... */
1225 else if (is_dma_capable() && musb_ep
->dma
) {
1226 struct dma_controller
*c
= musb
->dma_controller
;
1228 musb_ep_select(musb
->mregs
, musb_ep
->current_epnum
);
1229 if (c
->channel_abort
)
1230 status
= c
->channel_abort(musb_ep
->dma
);
1234 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1236 /* NOTE: by sticking to easily tested hardware/driver states,
1237 * we leave counting of in-flight packets imprecise.
1239 musb_g_giveback(musb_ep
, request
, -ECONNRESET
);
1243 spin_unlock_irqrestore(&musb
->lock
, flags
);
1248 * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any
1249 * data but will queue requests.
1251 * exported to ep0 code
1253 static int musb_gadget_set_halt(struct usb_ep
*ep
, int value
)
1255 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1256 u8 epnum
= musb_ep
->current_epnum
;
1257 struct musb
*musb
= musb_ep
->musb
;
1258 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1259 void __iomem
*mbase
;
1260 unsigned long flags
;
1262 struct musb_request
*request
;
1267 mbase
= musb
->mregs
;
1269 spin_lock_irqsave(&musb
->lock
, flags
);
1271 if ((USB_ENDPOINT_XFER_ISOC
== musb_ep
->type
)) {
1276 musb_ep_select(mbase
, epnum
);
1278 request
= to_musb_request(next_request(musb_ep
));
1281 DBG(3, "request in progress, cannot halt %s\n",
1286 /* Cannot portably stall with non-empty FIFO */
1287 if (musb_ep
->is_in
) {
1288 csr
= musb_readw(epio
, MUSB_TXCSR
);
1289 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1290 DBG(3, "FIFO busy, cannot halt %s\n", ep
->name
);
1296 musb_ep
->wedged
= 0;
1298 /* set/clear the stall and toggle bits */
1299 DBG(2, "%s: %s stall\n", ep
->name
, value
? "set" : "clear");
1300 if (musb_ep
->is_in
) {
1301 csr
= musb_readw(epio
, MUSB_TXCSR
);
1302 csr
|= MUSB_TXCSR_P_WZC_BITS
1303 | MUSB_TXCSR_CLRDATATOG
;
1305 csr
|= MUSB_TXCSR_P_SENDSTALL
;
1307 csr
&= ~(MUSB_TXCSR_P_SENDSTALL
1308 | MUSB_TXCSR_P_SENTSTALL
);
1309 csr
&= ~MUSB_TXCSR_TXPKTRDY
;
1310 musb_writew(epio
, MUSB_TXCSR
, csr
);
1312 csr
= musb_readw(epio
, MUSB_RXCSR
);
1313 csr
|= MUSB_RXCSR_P_WZC_BITS
1314 | MUSB_RXCSR_FLUSHFIFO
1315 | MUSB_RXCSR_CLRDATATOG
;
1317 csr
|= MUSB_RXCSR_P_SENDSTALL
;
1319 csr
&= ~(MUSB_RXCSR_P_SENDSTALL
1320 | MUSB_RXCSR_P_SENTSTALL
);
1321 musb_writew(epio
, MUSB_RXCSR
, csr
);
1324 /* maybe start the first request in the queue */
1325 if (!musb_ep
->busy
&& !value
&& request
) {
1326 DBG(3, "restarting the request\n");
1327 musb_ep_restart(musb
, request
);
1331 spin_unlock_irqrestore(&musb
->lock
, flags
);
1336 * Sets the halt feature with the clear requests ignored
1338 static int musb_gadget_set_wedge(struct usb_ep
*ep
)
1340 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1345 musb_ep
->wedged
= 1;
1347 return usb_ep_set_halt(ep
);
1350 static int musb_gadget_fifo_status(struct usb_ep
*ep
)
1352 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1353 void __iomem
*epio
= musb_ep
->hw_ep
->regs
;
1354 int retval
= -EINVAL
;
1356 if (musb_ep
->desc
&& !musb_ep
->is_in
) {
1357 struct musb
*musb
= musb_ep
->musb
;
1358 int epnum
= musb_ep
->current_epnum
;
1359 void __iomem
*mbase
= musb
->mregs
;
1360 unsigned long flags
;
1362 spin_lock_irqsave(&musb
->lock
, flags
);
1364 musb_ep_select(mbase
, epnum
);
1365 /* FIXME return zero unless RXPKTRDY is set */
1366 retval
= musb_readw(epio
, MUSB_RXCOUNT
);
1368 spin_unlock_irqrestore(&musb
->lock
, flags
);
1373 static void musb_gadget_fifo_flush(struct usb_ep
*ep
)
1375 struct musb_ep
*musb_ep
= to_musb_ep(ep
);
1376 struct musb
*musb
= musb_ep
->musb
;
1377 u8 epnum
= musb_ep
->current_epnum
;
1378 void __iomem
*epio
= musb
->endpoints
[epnum
].regs
;
1379 void __iomem
*mbase
;
1380 unsigned long flags
;
1383 mbase
= musb
->mregs
;
1385 spin_lock_irqsave(&musb
->lock
, flags
);
1386 musb_ep_select(mbase
, (u8
) epnum
);
1388 /* disable interrupts */
1389 int_txe
= musb_readw(mbase
, MUSB_INTRTXE
);
1390 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
& ~(1 << epnum
));
1392 if (musb_ep
->is_in
) {
1393 csr
= musb_readw(epio
, MUSB_TXCSR
);
1394 if (csr
& MUSB_TXCSR_FIFONOTEMPTY
) {
1395 csr
|= MUSB_TXCSR_FLUSHFIFO
| MUSB_TXCSR_P_WZC_BITS
;
1396 musb_writew(epio
, MUSB_TXCSR
, csr
);
1397 /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */
1398 musb_writew(epio
, MUSB_TXCSR
, csr
);
1401 csr
= musb_readw(epio
, MUSB_RXCSR
);
1402 csr
|= MUSB_RXCSR_FLUSHFIFO
| MUSB_RXCSR_P_WZC_BITS
;
1403 musb_writew(epio
, MUSB_RXCSR
, csr
);
1404 musb_writew(epio
, MUSB_RXCSR
, csr
);
1407 /* re-enable interrupt */
1408 musb_writew(mbase
, MUSB_INTRTXE
, int_txe
);
1409 spin_unlock_irqrestore(&musb
->lock
, flags
);
1412 static const struct usb_ep_ops musb_ep_ops
= {
1413 .enable
= musb_gadget_enable
,
1414 .disable
= musb_gadget_disable
,
1415 .alloc_request
= musb_alloc_request
,
1416 .free_request
= musb_free_request
,
1417 .queue
= musb_gadget_queue
,
1418 .dequeue
= musb_gadget_dequeue
,
1419 .set_halt
= musb_gadget_set_halt
,
1420 .set_wedge
= musb_gadget_set_wedge
,
1421 .fifo_status
= musb_gadget_fifo_status
,
1422 .fifo_flush
= musb_gadget_fifo_flush
1425 /* ----------------------------------------------------------------------- */
1427 static int musb_gadget_get_frame(struct usb_gadget
*gadget
)
1429 struct musb
*musb
= gadget_to_musb(gadget
);
1431 return (int)musb_readw(musb
->mregs
, MUSB_FRAME
);
1434 static int musb_gadget_wakeup(struct usb_gadget
*gadget
)
1436 struct musb
*musb
= gadget_to_musb(gadget
);
1437 void __iomem
*mregs
= musb
->mregs
;
1438 unsigned long flags
;
1439 int status
= -EINVAL
;
1443 spin_lock_irqsave(&musb
->lock
, flags
);
1445 switch (musb
->xceiv
->state
) {
1446 case OTG_STATE_B_PERIPHERAL
:
1447 /* NOTE: OTG state machine doesn't include B_SUSPENDED;
1448 * that's part of the standard usb 1.1 state machine, and
1449 * doesn't affect OTG transitions.
1451 if (musb
->may_wakeup
&& musb
->is_suspended
)
1454 case OTG_STATE_B_IDLE
:
1455 /* Start SRP ... OTG not required. */
1456 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1457 DBG(2, "Sending SRP: devctl: %02x\n", devctl
);
1458 devctl
|= MUSB_DEVCTL_SESSION
;
1459 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
);
1460 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1462 while (!(devctl
& MUSB_DEVCTL_SESSION
)) {
1463 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1468 while (devctl
& MUSB_DEVCTL_SESSION
) {
1469 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1474 /* Block idling for at least 1s */
1475 musb_platform_try_idle(musb
,
1476 jiffies
+ msecs_to_jiffies(1 * HZ
));
1481 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb
));
1487 power
= musb_readb(mregs
, MUSB_POWER
);
1488 power
|= MUSB_POWER_RESUME
;
1489 musb_writeb(mregs
, MUSB_POWER
, power
);
1490 DBG(2, "issue wakeup\n");
1492 /* FIXME do this next chunk in a timer callback, no udelay */
1495 power
= musb_readb(mregs
, MUSB_POWER
);
1496 power
&= ~MUSB_POWER_RESUME
;
1497 musb_writeb(mregs
, MUSB_POWER
, power
);
1499 spin_unlock_irqrestore(&musb
->lock
, flags
);
1504 musb_gadget_set_self_powered(struct usb_gadget
*gadget
, int is_selfpowered
)
1506 struct musb
*musb
= gadget_to_musb(gadget
);
1508 musb
->is_self_powered
= !!is_selfpowered
;
1512 static void musb_pullup(struct musb
*musb
, int is_on
)
1516 power
= musb_readb(musb
->mregs
, MUSB_POWER
);
1518 power
|= MUSB_POWER_SOFTCONN
;
1520 power
&= ~MUSB_POWER_SOFTCONN
;
1522 /* FIXME if on, HdrcStart; if off, HdrcStop */
1524 DBG(3, "gadget %s D+ pullup %s\n",
1525 musb
->gadget_driver
->function
, is_on
? "on" : "off");
1526 musb_writeb(musb
->mregs
, MUSB_POWER
, power
);
1530 static int musb_gadget_vbus_session(struct usb_gadget
*gadget
, int is_active
)
1532 DBG(2, "<= %s =>\n", __func__
);
1535 * FIXME iff driver's softconnect flag is set (as it is during probe,
1536 * though that can clear it), just musb_pullup().
1543 static int musb_gadget_vbus_draw(struct usb_gadget
*gadget
, unsigned mA
)
1545 struct musb
*musb
= gadget_to_musb(gadget
);
1547 if (!musb
->xceiv
->set_power
)
1549 return otg_set_power(musb
->xceiv
, mA
);
1552 static int musb_gadget_pullup(struct usb_gadget
*gadget
, int is_on
)
1554 struct musb
*musb
= gadget_to_musb(gadget
);
1555 unsigned long flags
;
1559 /* NOTE: this assumes we are sensing vbus; we'd rather
1560 * not pullup unless the B-session is active.
1562 spin_lock_irqsave(&musb
->lock
, flags
);
1563 if (is_on
!= musb
->softconnect
) {
1564 musb
->softconnect
= is_on
;
1565 musb_pullup(musb
, is_on
);
1567 spin_unlock_irqrestore(&musb
->lock
, flags
);
1571 static const struct usb_gadget_ops musb_gadget_operations
= {
1572 .get_frame
= musb_gadget_get_frame
,
1573 .wakeup
= musb_gadget_wakeup
,
1574 .set_selfpowered
= musb_gadget_set_self_powered
,
1575 /* .vbus_session = musb_gadget_vbus_session, */
1576 .vbus_draw
= musb_gadget_vbus_draw
,
1577 .pullup
= musb_gadget_pullup
,
1580 /* ----------------------------------------------------------------------- */
1584 /* Only this registration code "knows" the rule (from USB standards)
1585 * about there being only one external upstream port. It assumes
1586 * all peripheral ports are external...
1588 static struct musb
*the_gadget
;
1590 static void musb_gadget_release(struct device
*dev
)
1592 /* kref_put(WHAT) */
1593 dev_dbg(dev
, "%s\n", __func__
);
1598 init_peripheral_ep(struct musb
*musb
, struct musb_ep
*ep
, u8 epnum
, int is_in
)
1600 struct musb_hw_ep
*hw_ep
= musb
->endpoints
+ epnum
;
1602 memset(ep
, 0, sizeof *ep
);
1604 ep
->current_epnum
= epnum
;
1609 INIT_LIST_HEAD(&ep
->req_list
);
1611 sprintf(ep
->name
, "ep%d%s", epnum
,
1612 (!epnum
|| hw_ep
->is_shared_fifo
) ? "" : (
1613 is_in
? "in" : "out"));
1614 ep
->end_point
.name
= ep
->name
;
1615 INIT_LIST_HEAD(&ep
->end_point
.ep_list
);
1617 ep
->end_point
.maxpacket
= 64;
1618 ep
->end_point
.ops
= &musb_g_ep0_ops
;
1619 musb
->g
.ep0
= &ep
->end_point
;
1622 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_tx
;
1624 ep
->end_point
.maxpacket
= hw_ep
->max_packet_sz_rx
;
1625 ep
->end_point
.ops
= &musb_ep_ops
;
1626 list_add_tail(&ep
->end_point
.ep_list
, &musb
->g
.ep_list
);
1631 * Initialize the endpoints exposed to peripheral drivers, with backlinks
1632 * to the rest of the driver state.
1634 static inline void __init
musb_g_init_endpoints(struct musb
*musb
)
1637 struct musb_hw_ep
*hw_ep
;
1640 /* intialize endpoint list just once */
1641 INIT_LIST_HEAD(&(musb
->g
.ep_list
));
1643 for (epnum
= 0, hw_ep
= musb
->endpoints
;
1644 epnum
< musb
->nr_endpoints
;
1646 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1647 init_peripheral_ep(musb
, &hw_ep
->ep_in
, epnum
, 0);
1650 if (hw_ep
->max_packet_sz_tx
) {
1651 init_peripheral_ep(musb
, &hw_ep
->ep_in
,
1655 if (hw_ep
->max_packet_sz_rx
) {
1656 init_peripheral_ep(musb
, &hw_ep
->ep_out
,
1664 /* called once during driver setup to initialize and link into
1665 * the driver model; memory is zeroed.
1667 int __init
musb_gadget_setup(struct musb
*musb
)
1671 /* REVISIT minor race: if (erroneously) setting up two
1672 * musb peripherals at the same time, only the bus lock
1679 musb
->g
.ops
= &musb_gadget_operations
;
1680 musb
->g
.is_dualspeed
= 1;
1681 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1683 /* this "gadget" abstracts/virtualizes the controller */
1684 dev_set_name(&musb
->g
.dev
, "gadget");
1685 musb
->g
.dev
.parent
= musb
->controller
;
1686 musb
->g
.dev
.dma_mask
= musb
->controller
->dma_mask
;
1687 musb
->g
.dev
.release
= musb_gadget_release
;
1688 musb
->g
.name
= musb_driver_name
;
1690 if (is_otg_enabled(musb
))
1693 musb_g_init_endpoints(musb
);
1695 musb
->is_active
= 0;
1696 musb_platform_try_idle(musb
, 0);
1698 status
= device_register(&musb
->g
.dev
);
1700 put_device(&musb
->g
.dev
);
1706 void musb_gadget_cleanup(struct musb
*musb
)
1708 if (musb
!= the_gadget
)
1711 device_unregister(&musb
->g
.dev
);
1716 * Register the gadget driver. Used by gadget drivers when
1717 * registering themselves with the controller.
1719 * -EINVAL something went wrong (not driver)
1720 * -EBUSY another gadget is already using the controller
1721 * -ENOMEM no memeory to perform the operation
1723 * @param driver the gadget driver
1724 * @param bind the driver's bind function
1725 * @return <0 if error, 0 if everything is fine
1727 int usb_gadget_probe_driver(struct usb_gadget_driver
*driver
,
1728 int (*bind
)(struct usb_gadget
*))
1731 unsigned long flags
;
1732 struct musb
*musb
= the_gadget
;
1735 || driver
->speed
!= USB_SPEED_HIGH
1736 || !bind
|| !driver
->setup
)
1739 /* driver must be initialized to support peripheral mode */
1741 DBG(1, "%s, no dev??\n", __func__
);
1745 DBG(3, "registering driver %s\n", driver
->function
);
1746 spin_lock_irqsave(&musb
->lock
, flags
);
1748 if (musb
->gadget_driver
) {
1749 DBG(1, "%s is already bound to %s\n",
1751 musb
->gadget_driver
->driver
.name
);
1754 musb
->gadget_driver
= driver
;
1755 musb
->g
.dev
.driver
= &driver
->driver
;
1756 driver
->driver
.bus
= NULL
;
1757 musb
->softconnect
= 1;
1761 spin_unlock_irqrestore(&musb
->lock
, flags
);
1764 retval
= bind(&musb
->g
);
1766 DBG(3, "bind to driver %s failed --> %d\n",
1767 driver
->driver
.name
, retval
);
1768 musb
->gadget_driver
= NULL
;
1769 musb
->g
.dev
.driver
= NULL
;
1772 spin_lock_irqsave(&musb
->lock
, flags
);
1774 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1775 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
1776 musb
->is_active
= 1;
1778 /* FIXME this ignores the softconnect flag. Drivers are
1779 * allowed hold the peripheral inactive until for example
1780 * userspace hooks up printer hardware or DSP codecs, so
1781 * hosts only see fully functional devices.
1784 if (!is_otg_enabled(musb
))
1787 otg_set_peripheral(musb
->xceiv
, &musb
->g
);
1789 spin_unlock_irqrestore(&musb
->lock
, flags
);
1791 if (is_otg_enabled(musb
)) {
1792 DBG(3, "OTG startup...\n");
1794 /* REVISIT: funcall to other code, which also
1795 * handles power budgeting ... this way also
1796 * ensures HdrcStart is indirectly called.
1798 retval
= usb_add_hcd(musb_to_hcd(musb
), -1, 0);
1800 DBG(1, "add_hcd failed, %d\n", retval
);
1801 spin_lock_irqsave(&musb
->lock
, flags
);
1802 otg_set_peripheral(musb
->xceiv
, NULL
);
1803 musb
->gadget_driver
= NULL
;
1804 musb
->g
.dev
.driver
= NULL
;
1805 spin_unlock_irqrestore(&musb
->lock
, flags
);
1812 EXPORT_SYMBOL(usb_gadget_probe_driver
);
1814 static void stop_activity(struct musb
*musb
, struct usb_gadget_driver
*driver
)
1817 struct musb_hw_ep
*hw_ep
;
1819 /* don't disconnect if it's not connected */
1820 if (musb
->g
.speed
== USB_SPEED_UNKNOWN
)
1823 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1825 /* deactivate the hardware */
1826 if (musb
->softconnect
) {
1827 musb
->softconnect
= 0;
1828 musb_pullup(musb
, 0);
1832 /* killing any outstanding requests will quiesce the driver;
1833 * then report disconnect
1836 for (i
= 0, hw_ep
= musb
->endpoints
;
1837 i
< musb
->nr_endpoints
;
1839 musb_ep_select(musb
->mregs
, i
);
1840 if (hw_ep
->is_shared_fifo
/* || !epnum */) {
1841 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1843 if (hw_ep
->max_packet_sz_tx
)
1844 nuke(&hw_ep
->ep_in
, -ESHUTDOWN
);
1845 if (hw_ep
->max_packet_sz_rx
)
1846 nuke(&hw_ep
->ep_out
, -ESHUTDOWN
);
1850 spin_unlock(&musb
->lock
);
1851 driver
->disconnect(&musb
->g
);
1852 spin_lock(&musb
->lock
);
1857 * Unregister the gadget driver. Used by gadget drivers when
1858 * unregistering themselves from the controller.
1860 * @param driver the gadget driver to unregister
1862 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
1864 unsigned long flags
;
1866 struct musb
*musb
= the_gadget
;
1868 if (!driver
|| !driver
->unbind
|| !musb
)
1871 /* REVISIT always use otg_set_peripheral() here too;
1872 * this needs to shut down the OTG engine.
1875 spin_lock_irqsave(&musb
->lock
, flags
);
1877 #ifdef CONFIG_USB_MUSB_OTG
1878 musb_hnp_stop(musb
);
1881 if (musb
->gadget_driver
== driver
) {
1883 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
1885 musb
->xceiv
->state
= OTG_STATE_UNDEFINED
;
1886 stop_activity(musb
, driver
);
1887 otg_set_peripheral(musb
->xceiv
, NULL
);
1889 DBG(3, "unregistering driver %s\n", driver
->function
);
1890 spin_unlock_irqrestore(&musb
->lock
, flags
);
1891 driver
->unbind(&musb
->g
);
1892 spin_lock_irqsave(&musb
->lock
, flags
);
1894 musb
->gadget_driver
= NULL
;
1895 musb
->g
.dev
.driver
= NULL
;
1897 musb
->is_active
= 0;
1898 musb_platform_try_idle(musb
, 0);
1901 spin_unlock_irqrestore(&musb
->lock
, flags
);
1903 if (is_otg_enabled(musb
) && retval
== 0) {
1904 usb_remove_hcd(musb_to_hcd(musb
));
1905 /* FIXME we need to be able to register another
1906 * gadget driver here and have everything work;
1907 * that currently misbehaves.
1913 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
1916 /* ----------------------------------------------------------------------- */
1918 /* lifecycle operations called through plat_uds.c */
1920 void musb_g_resume(struct musb
*musb
)
1922 musb
->is_suspended
= 0;
1923 switch (musb
->xceiv
->state
) {
1924 case OTG_STATE_B_IDLE
:
1926 case OTG_STATE_B_WAIT_ACON
:
1927 case OTG_STATE_B_PERIPHERAL
:
1928 musb
->is_active
= 1;
1929 if (musb
->gadget_driver
&& musb
->gadget_driver
->resume
) {
1930 spin_unlock(&musb
->lock
);
1931 musb
->gadget_driver
->resume(&musb
->g
);
1932 spin_lock(&musb
->lock
);
1936 WARNING("unhandled RESUME transition (%s)\n",
1937 otg_state_string(musb
));
1941 /* called when SOF packets stop for 3+ msec */
1942 void musb_g_suspend(struct musb
*musb
)
1946 devctl
= musb_readb(musb
->mregs
, MUSB_DEVCTL
);
1947 DBG(3, "devctl %02x\n", devctl
);
1949 switch (musb
->xceiv
->state
) {
1950 case OTG_STATE_B_IDLE
:
1951 if ((devctl
& MUSB_DEVCTL_VBUS
) == MUSB_DEVCTL_VBUS
)
1952 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
1954 case OTG_STATE_B_PERIPHERAL
:
1955 musb
->is_suspended
= 1;
1956 if (musb
->gadget_driver
&& musb
->gadget_driver
->suspend
) {
1957 spin_unlock(&musb
->lock
);
1958 musb
->gadget_driver
->suspend(&musb
->g
);
1959 spin_lock(&musb
->lock
);
1963 /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ;
1964 * A_PERIPHERAL may need care too
1966 WARNING("unhandled SUSPEND transition (%s)\n",
1967 otg_state_string(musb
));
1971 /* Called during SRP */
1972 void musb_g_wakeup(struct musb
*musb
)
1974 musb_gadget_wakeup(&musb
->g
);
1977 /* called when VBUS drops below session threshold, and in other cases */
1978 void musb_g_disconnect(struct musb
*musb
)
1980 void __iomem
*mregs
= musb
->mregs
;
1981 u8 devctl
= musb_readb(mregs
, MUSB_DEVCTL
);
1983 DBG(3, "devctl %02x\n", devctl
);
1986 musb_writeb(mregs
, MUSB_DEVCTL
, devctl
& MUSB_DEVCTL_SESSION
);
1988 /* don't draw vbus until new b-default session */
1989 (void) musb_gadget_vbus_draw(&musb
->g
, 0);
1991 musb
->g
.speed
= USB_SPEED_UNKNOWN
;
1992 if (musb
->gadget_driver
&& musb
->gadget_driver
->disconnect
) {
1993 spin_unlock(&musb
->lock
);
1994 musb
->gadget_driver
->disconnect(&musb
->g
);
1995 spin_lock(&musb
->lock
);
1998 switch (musb
->xceiv
->state
) {
2000 #ifdef CONFIG_USB_MUSB_OTG
2001 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
2002 otg_state_string(musb
));
2003 musb
->xceiv
->state
= OTG_STATE_A_IDLE
;
2004 MUSB_HST_MODE(musb
);
2006 case OTG_STATE_A_PERIPHERAL
:
2007 musb
->xceiv
->state
= OTG_STATE_A_WAIT_BCON
;
2008 MUSB_HST_MODE(musb
);
2010 case OTG_STATE_B_WAIT_ACON
:
2011 case OTG_STATE_B_HOST
:
2013 case OTG_STATE_B_PERIPHERAL
:
2014 case OTG_STATE_B_IDLE
:
2015 musb
->xceiv
->state
= OTG_STATE_B_IDLE
;
2017 case OTG_STATE_B_SRP_INIT
:
2021 musb
->is_active
= 0;
2024 void musb_g_reset(struct musb
*musb
)
2025 __releases(musb
->lock
)
2026 __acquires(musb
->lock
)
2028 void __iomem
*mbase
= musb
->mregs
;
2029 u8 devctl
= musb_readb(mbase
, MUSB_DEVCTL
);
2032 DBG(3, "<== %s addr=%x driver '%s'\n",
2033 (devctl
& MUSB_DEVCTL_BDEVICE
)
2034 ? "B-Device" : "A-Device",
2035 musb_readb(mbase
, MUSB_FADDR
),
2037 ? musb
->gadget_driver
->driver
.name
2041 /* report disconnect, if we didn't already (flushing EP state) */
2042 if (musb
->g
.speed
!= USB_SPEED_UNKNOWN
)
2043 musb_g_disconnect(musb
);
2046 else if (devctl
& MUSB_DEVCTL_HR
)
2047 musb_writeb(mbase
, MUSB_DEVCTL
, MUSB_DEVCTL_SESSION
);
2050 /* what speed did we negotiate? */
2051 power
= musb_readb(mbase
, MUSB_POWER
);
2052 musb
->g
.speed
= (power
& MUSB_POWER_HSMODE
)
2053 ? USB_SPEED_HIGH
: USB_SPEED_FULL
;
2055 /* start in USB_STATE_DEFAULT */
2056 musb
->is_active
= 1;
2057 musb
->is_suspended
= 0;
2058 MUSB_DEV_MODE(musb
);
2060 musb
->ep0_state
= MUSB_EP0_STAGE_SETUP
;
2062 musb
->may_wakeup
= 0;
2063 musb
->g
.b_hnp_enable
= 0;
2064 musb
->g
.a_alt_hnp_support
= 0;
2065 musb
->g
.a_hnp_support
= 0;
2067 /* Normal reset, as B-Device;
2068 * or else after HNP, as A-Device
2070 if (devctl
& MUSB_DEVCTL_BDEVICE
) {
2071 musb
->xceiv
->state
= OTG_STATE_B_PERIPHERAL
;
2072 musb
->g
.is_a_peripheral
= 0;
2073 } else if (is_otg_enabled(musb
)) {
2074 musb
->xceiv
->state
= OTG_STATE_A_PERIPHERAL
;
2075 musb
->g
.is_a_peripheral
= 1;
2079 /* start with default limits on VBUS power draw */
2080 (void) musb_gadget_vbus_draw(&musb
->g
,
2081 is_otg_enabled(musb
) ? 8 : 100);