drivers/usb/phy/phy-omap-usb3.c

   1 /*
   2  * omap-usb3 - USB PHY, talking to dwc3 controller in OMAP.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/usb/omap_usb.h>
  23 #include <linux/of.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/delay.h>
  28 #include <linux/usb/omap_control_usb.h>
  29
  30 #define NUM_SYS_CLKS            6
  31 #define PLL_STATUS              0x00000004
  32 #define PLL_GO                  0x00000008
  33 #define PLL_CONFIGURATION1      0x0000000C
  34 #define PLL_CONFIGURATION2      0x00000010
  35 #define PLL_CONFIGURATION3      0x00000014
  36 #define PLL_CONFIGURATION4      0x00000020
  37
  38 #define PLL_REGM_MASK           0x001FFE00
  39 #define PLL_REGM_SHIFT          0x9
  40 #define PLL_REGM_F_MASK         0x0003FFFF
  41 #define PLL_REGM_F_SHIFT        0x0
  42 #define PLL_REGN_MASK           0x000001FE
  43 #define PLL_REGN_SHIFT          0x1
  44 #define PLL_SELFREQDCO_MASK     0x0000000E
  45 #define PLL_SELFREQDCO_SHIFT    0x1
  46 #define PLL_SD_MASK             0x0003FC00
  47 #define PLL_SD_SHIFT            0x9
  48 #define SET_PLL_GO              0x1
  49 #define PLL_TICOPWDN            0x10000
  50 #define PLL_LOCK                0x2
  51 #define PLL_IDLE                0x1
  52
  53 /*
  54  * This is an Empirical value that works, need to confirm the actual
  55  * value required for the USB3PHY_PLL_CONFIGURATION2.PLL_IDLE status
  56  * to be correctly reflected in the USB3PHY_PLL_STATUS register.
  57  */
  58 # define PLL_IDLE_TIME  100;
  59
  60 enum sys_clk_rate {
  61         CLK_RATE_UNDEFINED = -1,
  62         CLK_RATE_12MHZ,
  63         CLK_RATE_16MHZ,
  64         CLK_RATE_19MHZ,
  65         CLK_RATE_20MHZ,
  66         CLK_RATE_26MHZ,
  67         CLK_RATE_38MHZ
  68 };
  69
  70 static struct usb_dpll_params omap_usb3_dpll_params[NUM_SYS_CLKS] = {
  71         {1250, 5, 4, 20, 0},            /* 12 MHz */
  72         {3125, 20, 4, 20, 0},           /* 16.8 MHz */
  73         {1172, 8, 4, 20, 65537},        /* 19.2 MHz */
  74         {1250, 12, 4, 20, 0},           /* 26 MHz */
  75         {3125, 47, 4, 20, 92843},       /* 38.4 MHz */
  76         {1000, 7, 4, 10, 0},            /* 20 MHz */
  77
  78 };
  79
  80 static int omap_usb3_suspend(struct usb_phy *x, int suspend)
  81 {
  82         struct omap_usb *phy = phy_to_omapusb(x);
  83         int     val;
  84         int timeout = PLL_IDLE_TIME;
  85
  86         if (suspend && !phy->is_suspended) {
  87                 val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  88                 val |= PLL_IDLE;
  89                 omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  90
  91                 do {
  92                         val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
  93                         if (val & PLL_TICOPWDN)
  94                                 break;
  95                         udelay(1);
  96                 } while (--timeout);
  97
  98                 omap_control_usb3_phy_power(phy->control_dev, 0);
  99
 100                 phy->is_suspended       = 1;
 101         } else if (!suspend && phy->is_suspended) {
 102                 phy->is_suspended       = 0;
 103
 104                 val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 105                 val &= ~PLL_IDLE;
 106                 omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 107
 108                 do {
 109                         val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
 110                         if (!(val & PLL_TICOPWDN))
 111                                 break;
 112                         udelay(1);
 113                 } while (--timeout);
 114         }
 115
 116         return 0;
 117 }
 118
 119 static inline enum sys_clk_rate __get_sys_clk_index(unsigned long rate)
 120 {
 121         switch (rate) {
 122         case 12000000:
 123                 return CLK_RATE_12MHZ;
 124         case 16800000:
 125                 return CLK_RATE_16MHZ;
 126         case 19200000:
 127                 return CLK_RATE_19MHZ;
 128         case 20000000:
 129                 return CLK_RATE_20MHZ;
 130         case 26000000:
 131                 return CLK_RATE_26MHZ;
 132         case 38400000:
 133                 return CLK_RATE_38MHZ;
 134         default:
 135                 return CLK_RATE_UNDEFINED;
 136         }
 137 }
 138
 139 static void omap_usb_dpll_relock(struct omap_usb *phy)
 140 {
 141         u32             val;
 142         unsigned long   timeout;
 143
 144         omap_usb_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 145
 146         timeout = jiffies + msecs_to_jiffies(20);
 147         do {
 148                 val = omap_usb_readl(phy->pll_ctrl_base, PLL_STATUS);
 149                 if (val & PLL_LOCK)
 150                         break;
 151         } while (!WARN_ON(time_after(jiffies, timeout)));
 152 }
 153
 154 static int omap_usb_dpll_lock(struct omap_usb *phy)
 155 {
 156         u32                     val;
 157         unsigned long           rate;
 158         enum sys_clk_rate       clk_index;
 159
 160         rate            = clk_get_rate(phy->sys_clk);
 161         clk_index       = __get_sys_clk_index(rate);
 162
 163         if (clk_index == CLK_RATE_UNDEFINED) {
 164                 pr_err("dpll cannot be locked for sys clk freq:%luHz\n", rate);
 165                 return -EINVAL;
 166         }
 167
 168         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 169         val &= ~PLL_REGN_MASK;
 170         val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
 171         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 172
 173         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 174         val &= ~PLL_SELFREQDCO_MASK;
 175         val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
 176         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 177
 178         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 179         val &= ~PLL_REGM_MASK;
 180         val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
 181         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 182
 183         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 184         val &= ~PLL_REGM_F_MASK;
 185         val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
 186         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 187
 188         val = omap_usb_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 189         val &= ~PLL_SD_MASK;
 190         val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
 191         omap_usb_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 192
 193         omap_usb_dpll_relock(phy);
 194
 195         return 0;
 196 }
 197
 198 static int omap_usb3_init(struct usb_phy *x)
 199 {
 200         struct omap_usb *phy = phy_to_omapusb(x);
 201
 202         omap_usb_dpll_lock(phy);
 203         omap_control_usb3_phy_power(phy->control_dev, 1);
 204
 205         return 0;
 206 }
 207
 208 static int omap_usb3_probe(struct platform_device *pdev)
 209 {
 210         struct omap_usb                 *phy;
 211         struct resource                 *res;
 212
 213         phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
 214         if (!phy) {
 215                 dev_err(&pdev->dev, "unable to alloc mem for OMAP USB3 PHY\n");
 216                 return -ENOMEM;
 217         }
 218
 219         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl");
 220         phy->pll_ctrl_base = devm_ioremap_resource(&pdev->dev, res);
 221         if (IS_ERR(phy->pll_ctrl_base))
 222                 return PTR_ERR(phy->pll_ctrl_base);
 223
 224         phy->dev                = &pdev->dev;
 225
 226         phy->phy.dev            = phy->dev;
 227         phy->phy.label          = "omap-usb3";
 228         phy->phy.init           = omap_usb3_init;
 229         phy->phy.set_suspend    = omap_usb3_suspend;
 230         phy->phy.type           = USB_PHY_TYPE_USB3;
 231
 232         phy->is_suspended       = 1;
 233         phy->wkupclk = devm_clk_get(phy->dev, "usb_phy_cm_clk32k");
 234         if (IS_ERR(phy->wkupclk)) {
 235                 dev_err(&pdev->dev, "unable to get usb_phy_cm_clk32k\n");
 236                 return PTR_ERR(phy->wkupclk);
 237         }
 238         clk_prepare(phy->wkupclk);
 239
 240         phy->optclk = devm_clk_get(phy->dev, "usb_otg_ss_refclk960m");
 241         if (IS_ERR(phy->optclk)) {
 242                 dev_err(&pdev->dev, "unable to get usb_otg_ss_refclk960m\n");
 243                 return PTR_ERR(phy->optclk);
 244         }
 245         clk_prepare(phy->optclk);
 246
 247         phy->sys_clk = devm_clk_get(phy->dev, "sys_clkin");
 248         if (IS_ERR(phy->sys_clk)) {
 249                 pr_err("%s: unable to get sys_clkin\n", __func__);
 250                 return -EINVAL;
 251         }
 252
 253         phy->control_dev = omap_get_control_dev();
 254         if (IS_ERR(phy->control_dev)) {
 255                 dev_dbg(&pdev->dev, "Failed to get control device\n");
 256                 return -ENODEV;
 257         }
 258
 259         omap_control_usb3_phy_power(phy->control_dev, 0);
 260         usb_add_phy_dev(&phy->phy);
 261
 262         platform_set_drvdata(pdev, phy);
 263
 264         pm_runtime_enable(phy->dev);
 265         pm_runtime_get(&pdev->dev);
 266
 267         return 0;
 268 }
 269
 270 static int omap_usb3_remove(struct platform_device *pdev)
 271 {
 272         struct omap_usb *phy = platform_get_drvdata(pdev);
 273
 274         clk_unprepare(phy->wkupclk);
 275         clk_unprepare(phy->optclk);
 276         usb_remove_phy(&phy->phy);
 277         if (!pm_runtime_suspended(&pdev->dev))
 278                 pm_runtime_put(&pdev->dev);
 279         pm_runtime_disable(&pdev->dev);
 280
 281         return 0;
 282 }
 283
 284 #ifdef CONFIG_PM_RUNTIME
 285
 286 static int omap_usb3_runtime_suspend(struct device *dev)
 287 {
 288         struct platform_device  *pdev = to_platform_device(dev);
 289         struct omap_usb *phy = platform_get_drvdata(pdev);
 290
 291         clk_disable(phy->wkupclk);
 292         clk_disable(phy->optclk);
 293
 294         return 0;
 295 }
 296
 297 static int omap_usb3_runtime_resume(struct device *dev)
 298 {
 299         u32 ret = 0;
 300         struct platform_device  *pdev = to_platform_device(dev);
 301         struct omap_usb *phy = platform_get_drvdata(pdev);
 302
 303         ret = clk_enable(phy->optclk);
 304         if (ret) {
 305                 dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
 306                 goto err1;
 307         }
 308
 309         ret = clk_enable(phy->wkupclk);
 310         if (ret) {
 311                 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
 312                 goto err2;
 313         }
 314
 315         return 0;
 316
 317 err2:
 318         clk_disable(phy->optclk);
 319
 320 err1:
 321         return ret;
 322 }
 323
 324 static const struct dev_pm_ops omap_usb3_pm_ops = {
 325         SET_RUNTIME_PM_OPS(omap_usb3_runtime_suspend, omap_usb3_runtime_resume,
 326                 NULL)
 327 };
 328
 329 #define DEV_PM_OPS     (&omap_usb3_pm_ops)
 330 #else
 331 #define DEV_PM_OPS     NULL
 332 #endif
 333
 334 #ifdef CONFIG_OF
 335 static const struct of_device_id omap_usb3_id_table[] = {
 336         { .compatible = "ti,omap-usb3" },
 337         {}
 338 };
 339 MODULE_DEVICE_TABLE(of, omap_usb3_id_table);
 340 #endif
 341
 342 static struct platform_driver omap_usb3_driver = {
 343         .probe          = omap_usb3_probe,
 344         .remove         = omap_usb3_remove,
 345         .driver         = {
 346                 .name   = "omap-usb3",
 347                 .owner  = THIS_MODULE,
 348                 .pm     = DEV_PM_OPS,
 349                 .of_match_table = of_match_ptr(omap_usb3_id_table),
 350         },
 351 };
 352
 353 module_platform_driver(omap_usb3_driver);
 354
 355 MODULE_ALIAS("platform: omap_usb3");
 356 MODULE_AUTHOR("Texas Instruments Inc.");
 357 MODULE_DESCRIPTION("OMAP USB3 phy driver");
 358 MODULE_LICENSE("GPL v2");